Searched refs:RwReg16 (Results 1 – 25 of 545) sorted by relevance
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106 #define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */107 #define REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE0 Control B */109 #define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enab…110 #define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enab…111 #define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag…117 #define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */118 #define REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) /**< \brief (RTC) MODE1 Control B */120 #define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enab…121 #define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enab…122 #define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag…[all …]
87 #define REG_SDHC0_BSR (*(RwReg16*)0x45000004UL) /**< \brief (SDHC0) Block Size */88 #define REG_SDHC0_BCR (*(RwReg16*)0x45000006UL) /**< \brief (SDHC0) Block Count */90 #define REG_SDHC0_TMR (*(RwReg16*)0x4500000CUL) /**< \brief (SDHC0) Transfer Mode */91 #define REG_SDHC0_CR (*(RwReg16*)0x4500000EUL) /**< \brief (SDHC0) Command */102 #define REG_SDHC0_CCR (*(RwReg16*)0x4500002CUL) /**< \brief (SDHC0) Clock Control */105 #define REG_SDHC0_NISTR (*(RwReg16*)0x45000030UL) /**< \brief (SDHC0) Normal Interrupt S…106 #define REG_SDHC0_EISTR (*(RwReg16*)0x45000032UL) /**< \brief (SDHC0) Error Interrupt St…107 #define REG_SDHC0_NISTER (*(RwReg16*)0x45000034UL) /**< \brief (SDHC0) Normal Interrupt S…108 #define REG_SDHC0_EISTER (*(RwReg16*)0x45000036UL) /**< \brief (SDHC0) Error Interrupt St…109 #define REG_SDHC0_NISIER (*(RwReg16*)0x45000038UL) /**< \brief (SDHC0) Normal Interrupt S…[all …]
87 #define REG_SDHC1_BSR (*(RwReg16*)0x46000004UL) /**< \brief (SDHC1) Block Size */88 #define REG_SDHC1_BCR (*(RwReg16*)0x46000006UL) /**< \brief (SDHC1) Block Count */90 #define REG_SDHC1_TMR (*(RwReg16*)0x4600000CUL) /**< \brief (SDHC1) Transfer Mode */91 #define REG_SDHC1_CR (*(RwReg16*)0x4600000EUL) /**< \brief (SDHC1) Command */102 #define REG_SDHC1_CCR (*(RwReg16*)0x4600002CUL) /**< \brief (SDHC1) Clock Control */105 #define REG_SDHC1_NISTR (*(RwReg16*)0x46000030UL) /**< \brief (SDHC1) Normal Interrupt S…106 #define REG_SDHC1_EISTR (*(RwReg16*)0x46000032UL) /**< \brief (SDHC1) Error Interrupt St…107 #define REG_SDHC1_NISTER (*(RwReg16*)0x46000034UL) /**< \brief (SDHC1) Normal Interrupt S…108 #define REG_SDHC1_EISTER (*(RwReg16*)0x46000036UL) /**< \brief (SDHC1) Error Interrupt St…109 #define REG_SDHC1_NISIER (*(RwReg16*)0x46000038UL) /**< \brief (SDHC1) Normal Interrupt S…[all …]
60 #define REG_ADC0_CTRLA (*(RwReg16*)0x43001C00UL) /**< \brief (ADC0) Control A */63 #define REG_ADC0_INPUTCTRL (*(RwReg16*)0x43001C04UL) /**< \brief (ADC0) Input Control */64 #define REG_ADC0_CTRLB (*(RwReg16*)0x43001C06UL) /**< \brief (ADC0) Control B */68 #define REG_ADC0_WINLT (*(RwReg16*)0x43001C0CUL) /**< \brief (ADC0) Window Monitor Lowe…69 #define REG_ADC0_WINUT (*(RwReg16*)0x43001C0EUL) /**< \brief (ADC0) Window Monitor Uppe…70 #define REG_ADC0_GAINCORR (*(RwReg16*)0x43001C10UL) /**< \brief (ADC0) Gain Correction */71 #define REG_ADC0_OFFSETCORR (*(RwReg16*)0x43001C12UL) /**< \brief (ADC0) Offset Correction */83 #define REG_ADC0_CALIB (*(RwReg16*)0x43001C48UL) /**< \brief (ADC0) Calibration */
67 #define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */69 #define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enab…70 #define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enab…71 #define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag…75 #define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */77 #define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enab…78 #define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enab…79 #define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag…81 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value …82 #define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period…[all …]
75 #define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002000UL) /**< \brief (RTC) MODE0 Control A */77 #define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002008UL) /**< \brief (RTC) MODE0 Interrupt Enab…78 #define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000200AUL) /**< \brief (RTC) MODE0 Interrupt Enab…79 #define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000200CUL) /**< \brief (RTC) MODE0 Interrupt Flag…83 #define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002000UL) /**< \brief (RTC) MODE1 Control A */85 #define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002008UL) /**< \brief (RTC) MODE1 Interrupt Enab…86 #define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000200AUL) /**< \brief (RTC) MODE1 Interrupt Enab…87 #define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000200CUL) /**< \brief (RTC) MODE1 Interrupt Flag…89 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002018UL) /**< \brief (RTC) MODE1 Counter Value …90 #define REG_RTC_MODE1_PER (*(RwReg16*)0x4000201CUL) /**< \brief (RTC) MODE1 Counter Period…[all …]
64 #define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */68 #define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */69 #define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control …75 #define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */76 #define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control …80 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value …81 #define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period…82 #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Valu…83 #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Valu…84 #define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */[all …]
63 #define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */67 #define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */68 #define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control …74 #define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */75 #define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control …79 #define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value …80 #define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period…81 #define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Valu…82 #define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Valu…83 #define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */[all …]
