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Searched refs:REG_PIOA_IFER (Results 1 – 7 of 7) sorted by relevance

/hal_atmel-3.6.0/asf/sam/include/sam3x/instance/
Dpioa.h41 …#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enab… macro
85 …#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enab… macro
/hal_atmel-3.6.0/asf/sam/include/sam4e/instance/
Dpioa.h41 #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Reg… macro
102 #define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Reg… macro
/hal_atmel-3.6.0/asf/sam/include/samv71b/instance/
Dpioa.h43 #define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */ macro
102 #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enab… macro
/hal_atmel-3.6.0/asf/sam/include/same70b/instance/
Dpioa.h43 #define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */ macro
102 #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enab… macro
/hal_atmel-3.6.0/asf/sam/include/same70/instance/
Dpioa.h43 #define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */ macro
102 #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enab… macro
/hal_atmel-3.6.0/asf/sam/include/samv71/instance/
Dpioa.h43 #define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */ macro
103 #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enab… macro
/hal_atmel-3.6.0/asf/sam/include/sam4s/instance/
Dpioa.h41 …#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Ena… macro
101 …#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Ena… macro