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Searched refs:REG_ADC0_DSEQSTAT (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-3.6.0/asf/sam0/include/samd51/instance/
Dadc0.h55 #define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */ macro
80 #define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Stat… macro
/hal_atmel-3.6.0/asf/sam0/include/same53/instance/
Dadc0.h55 #define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */ macro
80 #define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Stat… macro
/hal_atmel-3.6.0/asf/sam0/include/same51/instance/
Dadc0.h55 #define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */ macro
80 #define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Stat… macro
/hal_atmel-3.6.0/asf/sam0/include/same54/instance/
Dadc0.h55 #define REG_ADC0_DSEQSTAT (0x43001C3C) /**< \brief (ADC0) DMA Sequencial Status */ macro
80 #define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) /**< \brief (ADC0) DMA Sequencial Stat… macro