1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_EMAC_COMPONENT_ 31 #define _SAM3XA_EMAC_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Ethernet MAC 10/100 */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM3XA_EMAC Ethernet MAC 10/100 */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief EmacSa hardware registers */ 41 typedef struct { 42 __IO uint32_t EMAC_SAxB; /**< \brief (EmacSa Offset: 0x0) Specific Address 1 Bottom Register */ 43 __IO uint32_t EMAC_SAxT; /**< \brief (EmacSa Offset: 0x4) Specific Address 1 Top Register */ 44 } EmacSa; 45 /** \brief Emac hardware registers */ 46 #define EMACSA_NUMBER 4 47 typedef struct { 48 __IO uint32_t EMAC_NCR; /**< \brief (Emac Offset: 0x00) Network Control Register */ 49 __IO uint32_t EMAC_NCFGR; /**< \brief (Emac Offset: 0x04) Network Configuration Register */ 50 __I uint32_t EMAC_NSR; /**< \brief (Emac Offset: 0x08) Network Status Register */ 51 __I uint32_t Reserved1[2]; 52 __IO uint32_t EMAC_TSR; /**< \brief (Emac Offset: 0x14) Transmit Status Register */ 53 __IO uint32_t EMAC_RBQP; /**< \brief (Emac Offset: 0x18) Receive Buffer Queue Pointer Register */ 54 __IO uint32_t EMAC_TBQP; /**< \brief (Emac Offset: 0x1C) Transmit Buffer Queue Pointer Register */ 55 __IO uint32_t EMAC_RSR; /**< \brief (Emac Offset: 0x20) Receive Status Register */ 56 __IO uint32_t EMAC_ISR; /**< \brief (Emac Offset: 0x24) Interrupt Status Register */ 57 __O uint32_t EMAC_IER; /**< \brief (Emac Offset: 0x28) Interrupt Enable Register */ 58 __O uint32_t EMAC_IDR; /**< \brief (Emac Offset: 0x2C) Interrupt Disable Register */ 59 __I uint32_t EMAC_IMR; /**< \brief (Emac Offset: 0x30) Interrupt Mask Register */ 60 __IO uint32_t EMAC_MAN; /**< \brief (Emac Offset: 0x34) Phy Maintenance Register */ 61 __IO uint32_t EMAC_PTR; /**< \brief (Emac Offset: 0x38) Pause Time Register */ 62 __IO uint32_t EMAC_PFR; /**< \brief (Emac Offset: 0x3C) Pause Frames Received Register */ 63 __IO uint32_t EMAC_FTO; /**< \brief (Emac Offset: 0x40) Frames Transmitted Ok Register */ 64 __IO uint32_t EMAC_SCF; /**< \brief (Emac Offset: 0x44) Single Collision Frames Register */ 65 __IO uint32_t EMAC_MCF; /**< \brief (Emac Offset: 0x48) Multiple Collision Frames Register */ 66 __IO uint32_t EMAC_FRO; /**< \brief (Emac Offset: 0x4C) Frames Received Ok Register */ 67 __IO uint32_t EMAC_FCSE; /**< \brief (Emac Offset: 0x50) Frame Check Sequence Errors Register */ 68 __IO uint32_t EMAC_ALE; /**< \brief (Emac Offset: 0x54) Alignment Errors Register */ 69 __IO uint32_t EMAC_DTF; /**< \brief (Emac Offset: 0x58) Deferred Transmission Frames Register */ 70 __IO uint32_t EMAC_LCOL; /**< \brief (Emac Offset: 0x5C) Late Collisions Register */ 71 __IO uint32_t EMAC_ECOL; /**< \brief (Emac Offset: 0x60) Excessive Collisions Register */ 72 __IO uint32_t EMAC_TUND; /**< \brief (Emac Offset: 0x64) Transmit Underrun Errors Register */ 73 __IO uint32_t EMAC_CSE; /**< \brief (Emac Offset: 0x68) Carrier Sense Errors Register */ 74 __IO uint32_t EMAC_RRE; /**< \brief (Emac Offset: 0x6C) Receive Resource Errors Register */ 75 __IO uint32_t EMAC_ROV; /**< \brief (Emac Offset: 0x70) Receive Overrun Errors Register */ 76 __IO uint32_t EMAC_RSE; /**< \brief (Emac Offset: 0x74) Receive Symbol Errors Register */ 77 __IO uint32_t EMAC_ELE; /**< \brief (Emac Offset: 0x78) Excessive Length Errors Register */ 78 __IO uint32_t EMAC_RJA; /**< \brief (Emac Offset: 0x7C) Receive Jabbers Register */ 79 __IO uint32_t EMAC_USF; /**< \brief (Emac Offset: 0x80) Undersize Frames Register */ 80 __IO uint32_t EMAC_STE; /**< \brief (Emac Offset: 0x84) SQE Test Errors Register */ 81 __IO uint32_t EMAC_RLE; /**< \brief (Emac Offset: 0x88) Received Length Field Mismatch Register */ 82 __I uint32_t Reserved2[1]; 83 __IO uint32_t EMAC_HRB; /**< \brief (Emac Offset: 0x90) Hash Register Bottom [31:0] Register */ 84 __IO uint32_t EMAC_HRT; /**< \brief (Emac Offset: 0x94) Hash Register Top [63:32] Register */ 85 EmacSa EMAC_SA[EMACSA_NUMBER]; /**< \brief (Emac Offset: 0x98) sa = 1 .. 4 */ 86 __IO uint32_t EMAC_TID; /**< \brief (Emac Offset: 0xB8) Type ID Checking Register */ 87 __I uint32_t Reserved3[1]; 88 __IO uint32_t EMAC_USRIO; /**< \brief (Emac Offset: 0xC0) User Input/Output Register */ 89 } Emac; 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 /* -------- EMAC_NCR : (EMAC Offset: 0x00) Network Control Register -------- */ 92 #define EMAC_NCR_LB (0x1u << 0) /**< \brief (EMAC_NCR) LoopBack */ 93 #define EMAC_NCR_LLB (0x1u << 1) /**< \brief (EMAC_NCR) Loopback local */ 94 #define EMAC_NCR_RE (0x1u << 2) /**< \brief (EMAC_NCR) Receive enable */ 95 #define EMAC_NCR_TE (0x1u << 3) /**< \brief (EMAC_NCR) Transmit enable */ 96 #define EMAC_NCR_MPE (0x1u << 4) /**< \brief (EMAC_NCR) Management port enable */ 97 #define EMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (EMAC_NCR) Clear statistics registers */ 98 #define EMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (EMAC_NCR) Increment statistics registers */ 99 #define EMAC_NCR_WESTAT (0x1u << 7) /**< \brief (EMAC_NCR) Write enable for statistics registers */ 100 #define EMAC_NCR_BP (0x1u << 8) /**< \brief (EMAC_NCR) Back pressure */ 101 #define EMAC_NCR_TSTART (0x1u << 9) /**< \brief (EMAC_NCR) Start transmission */ 102 #define EMAC_NCR_THALT (0x1u << 10) /**< \brief (EMAC_NCR) Transmit halt */ 103 /* -------- EMAC_NCFGR : (EMAC Offset: 0x04) Network Configuration Register -------- */ 104 #define EMAC_NCFGR_SPD (0x1u << 0) /**< \brief (EMAC_NCFGR) Speed */ 105 #define EMAC_NCFGR_FD (0x1u << 1) /**< \brief (EMAC_NCFGR) Full Duplex */ 106 #define EMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (EMAC_NCFGR) Jumbo Frames */ 107 #define EMAC_NCFGR_CAF (0x1u << 4) /**< \brief (EMAC_NCFGR) Copy All Frames */ 108 #define EMAC_NCFGR_NBC (0x1u << 5) /**< \brief (EMAC_NCFGR) No Broadcast */ 109 #define EMAC_NCFGR_MTI (0x1u << 6) /**< \brief (EMAC_NCFGR) Multicast Hash Enable */ 110 #define EMAC_NCFGR_UNI (0x1u << 7) /**< \brief (EMAC_NCFGR) Unicast Hash Enable */ 111 #define EMAC_NCFGR_BIG (0x1u << 8) /**< \brief (EMAC_NCFGR) Receive 1536 bytes frames */ 112 #define EMAC_NCFGR_CLK_Pos 10 113 #define EMAC_NCFGR_CLK_Msk (0x3u << EMAC_NCFGR_CLK_Pos) /**< \brief (EMAC_NCFGR) MDC clock divider */ 114 #define EMAC_NCFGR_CLK_MCK_8 (0x0u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz). */ 115 #define EMAC_NCFGR_CLK_MCK_16 (0x1u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz). */ 116 #define EMAC_NCFGR_CLK_MCK_32 (0x2u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz). */ 117 #define EMAC_NCFGR_CLK_MCK_64 (0x3u << 10) /**< \brief (EMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz). */ 118 #define EMAC_NCFGR_RTY (0x1u << 12) /**< \brief (EMAC_NCFGR) Retry test */ 119 #define EMAC_NCFGR_PAE (0x1u << 13) /**< \brief (EMAC_NCFGR) Pause Enable */ 120 #define EMAC_NCFGR_RBOF_Pos 14 121 #define EMAC_NCFGR_RBOF_Msk (0x3u << EMAC_NCFGR_RBOF_Pos) /**< \brief (EMAC_NCFGR) Receive Buffer Offset */ 122 #define EMAC_NCFGR_RBOF_OFFSET_0 (0x0u << 14) /**< \brief (EMAC_NCFGR) No offset from start of receive buffer. */ 123 #define EMAC_NCFGR_RBOF_OFFSET_1 (0x1u << 14) /**< \brief (EMAC_NCFGR) One-byte offset from start of receive buffer. */ 124 #define EMAC_NCFGR_RBOF_OFFSET_2 (0x2u << 14) /**< \brief (EMAC_NCFGR) Two-byte offset from start of receive buffer. */ 125 #define EMAC_NCFGR_RBOF_OFFSET_3 (0x3u << 14) /**< \brief (EMAC_NCFGR) Three-byte offset from start of receive buffer. */ 126 #define EMAC_NCFGR_RLCE (0x1u << 16) /**< \brief (EMAC_NCFGR) Receive Length field Checking Enable */ 127 #define EMAC_NCFGR_DRFCS (0x1u << 17) /**< \brief (EMAC_NCFGR) Discard Receive FCS */ 128 #define EMAC_NCFGR_EFRHD (0x1u << 18) /**< \brief (EMAC_NCFGR) */ 129 #define EMAC_NCFGR_IRXFCS (0x1u << 19) /**< \brief (EMAC_NCFGR) Ignore RX FCS */ 130 /* -------- EMAC_NSR : (EMAC Offset: 0x08) Network Status Register -------- */ 131 #define EMAC_NSR_MDIO (0x1u << 1) /**< \brief (EMAC_NSR) */ 132 #define EMAC_NSR_IDLE (0x1u << 2) /**< \brief (EMAC_NSR) */ 133 /* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- */ 134 #define EMAC_TSR_UBR (0x1u << 0) /**< \brief (EMAC_TSR) Used Bit Read */ 135 #define EMAC_TSR_COL (0x1u << 1) /**< \brief (EMAC_TSR) Collision Occurred */ 136 #define EMAC_TSR_RLES (0x1u << 2) /**< \brief (EMAC_TSR) Retry Limit exceeded */ 137 #define EMAC_TSR_TGO (0x1u << 3) /**< \brief (EMAC_TSR) Transmit Go */ 138 #define EMAC_TSR_BEX (0x1u << 4) /**< \brief (EMAC_TSR) Buffers exhausted mid frame */ 139 #define EMAC_TSR_COMP (0x1u << 5) /**< \brief (EMAC_TSR) Transmit Complete */ 140 #define EMAC_TSR_UND (0x1u << 6) /**< \brief (EMAC_TSR) Transmit Underrun */ 141 /* -------- EMAC_RBQP : (EMAC Offset: 0x18) Receive Buffer Queue Pointer Register -------- */ 142 #define EMAC_RBQP_ADDR_Pos 2 143 #define EMAC_RBQP_ADDR_Msk (0x3fffffffu << EMAC_RBQP_ADDR_Pos) /**< \brief (EMAC_RBQP) Receive buffer queue pointer address */ 144 #define EMAC_RBQP_ADDR(value) ((EMAC_RBQP_ADDR_Msk & ((value) << EMAC_RBQP_ADDR_Pos))) 145 /* -------- EMAC_TBQP : (EMAC Offset: 0x1C) Transmit Buffer Queue Pointer Register -------- */ 146 #define EMAC_TBQP_ADDR_Pos 2 147 #define EMAC_TBQP_ADDR_Msk (0x3fffffffu << EMAC_TBQP_ADDR_Pos) /**< \brief (EMAC_TBQP) Transmit buffer queue pointer address */ 148 #define EMAC_TBQP_ADDR(value) ((EMAC_TBQP_ADDR_Msk & ((value) << EMAC_TBQP_ADDR_Pos))) 149 /* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ 150 #define EMAC_RSR_BNA (0x1u << 0) /**< \brief (EMAC_RSR) Buffer Not Available */ 151 #define EMAC_RSR_REC (0x1u << 1) /**< \brief (EMAC_RSR) Frame Received */ 152 #define EMAC_RSR_OVR (0x1u << 2) /**< \brief (EMAC_RSR) Receive Overrun */ 153 /* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ 154 #define EMAC_ISR_MFD (0x1u << 0) /**< \brief (EMAC_ISR) Management Frame Done */ 155 #define EMAC_ISR_RCOMP (0x1u << 1) /**< \brief (EMAC_ISR) Receive Complete */ 156 #define EMAC_ISR_RXUBR (0x1u << 2) /**< \brief (EMAC_ISR) Receive Used Bit Read */ 157 #define EMAC_ISR_TXUBR (0x1u << 3) /**< \brief (EMAC_ISR) Transmit Used Bit Read */ 158 #define EMAC_ISR_TUND (0x1u << 4) /**< \brief (EMAC_ISR) Ethernet Transmit Buffer Underrun */ 159 #define EMAC_ISR_RLEX (0x1u << 5) /**< \brief (EMAC_ISR) Retry Limit Exceeded */ 160 #define EMAC_ISR_TXERR (0x1u << 6) /**< \brief (EMAC_ISR) Transmit Error */ 161 #define EMAC_ISR_TCOMP (0x1u << 7) /**< \brief (EMAC_ISR) Transmit Complete */ 162 #define EMAC_ISR_ROVR (0x1u << 10) /**< \brief (EMAC_ISR) Receive Overrun */ 163 #define EMAC_ISR_HRESP (0x1u << 11) /**< \brief (EMAC_ISR) Hresp not OK */ 164 #define EMAC_ISR_PFRE (0x1u << 12) /**< \brief (EMAC_ISR) Pause Frame Received */ 165 #define EMAC_ISR_PTZ (0x1u << 13) /**< \brief (EMAC_ISR) Pause Time Zero */ 166 /* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ 167 #define EMAC_IER_MFD (0x1u << 0) /**< \brief (EMAC_IER) Management Frame sent */ 168 #define EMAC_IER_RCOMP (0x1u << 1) /**< \brief (EMAC_IER) Receive Complete */ 169 #define EMAC_IER_RXUBR (0x1u << 2) /**< \brief (EMAC_IER) Receive Used Bit Read */ 170 #define EMAC_IER_TXUBR (0x1u << 3) /**< \brief (EMAC_IER) Transmit Used Bit Read */ 171 #define EMAC_IER_TUND (0x1u << 4) /**< \brief (EMAC_IER) Ethernet Transmit Buffer Underrun */ 172 #define EMAC_IER_RLE (0x1u << 5) /**< \brief (EMAC_IER) Retry Limit Exceeded */ 173 #define EMAC_IER_TXERR (0x1u << 6) /**< \brief (EMAC_IER) */ 174 #define EMAC_IER_TCOMP (0x1u << 7) /**< \brief (EMAC_IER) Transmit Complete */ 175 #define EMAC_IER_ROVR (0x1u << 10) /**< \brief (EMAC_IER) Receive Overrun */ 176 #define EMAC_IER_HRESP (0x1u << 11) /**< \brief (EMAC_IER) Hresp not OK */ 177 #define EMAC_IER_PFR (0x1u << 12) /**< \brief (EMAC_IER) Pause Frame Received */ 178 #define EMAC_IER_PTZ (0x1u << 13) /**< \brief (EMAC_IER) Pause Time Zero */ 179 /* -------- EMAC_IDR : (EMAC Offset: 0x2C) Interrupt Disable Register -------- */ 180 #define EMAC_IDR_MFD (0x1u << 0) /**< \brief (EMAC_IDR) Management Frame sent */ 181 #define EMAC_IDR_RCOMP (0x1u << 1) /**< \brief (EMAC_IDR) Receive Complete */ 182 #define EMAC_IDR_RXUBR (0x1u << 2) /**< \brief (EMAC_IDR) Receive Used Bit Read */ 183 #define EMAC_IDR_TXUBR (0x1u << 3) /**< \brief (EMAC_IDR) Transmit Used Bit Read */ 184 #define EMAC_IDR_TUND (0x1u << 4) /**< \brief (EMAC_IDR) Ethernet Transmit Buffer Underrun */ 185 #define EMAC_IDR_RLE (0x1u << 5) /**< \brief (EMAC_IDR) Retry Limit Exceeded */ 186 #define EMAC_IDR_TXERR (0x1u << 6) /**< \brief (EMAC_IDR) */ 187 #define EMAC_IDR_TCOMP (0x1u << 7) /**< \brief (EMAC_IDR) Transmit Complete */ 188 #define EMAC_IDR_ROVR (0x1u << 10) /**< \brief (EMAC_IDR) Receive Overrun */ 189 #define EMAC_IDR_HRESP (0x1u << 11) /**< \brief (EMAC_IDR) Hresp not OK */ 190 #define EMAC_IDR_PFR (0x1u << 12) /**< \brief (EMAC_IDR) Pause Frame Received */ 191 #define EMAC_IDR_PTZ (0x1u << 13) /**< \brief (EMAC_IDR) Pause Time Zero */ 192 /* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ 193 #define EMAC_IMR_MFD (0x1u << 0) /**< \brief (EMAC_IMR) Management Frame sent */ 194 #define EMAC_IMR_RCOMP (0x1u << 1) /**< \brief (EMAC_IMR) Receive Complete */ 195 #define EMAC_IMR_RXUBR (0x1u << 2) /**< \brief (EMAC_IMR) Receive Used Bit Read */ 196 #define EMAC_IMR_TXUBR (0x1u << 3) /**< \brief (EMAC_IMR) Transmit Used Bit Read */ 197 #define EMAC_IMR_TUND (0x1u << 4) /**< \brief (EMAC_IMR) Ethernet Transmit Buffer Underrun */ 198 #define EMAC_IMR_RLE (0x1u << 5) /**< \brief (EMAC_IMR) Retry Limit Exceeded */ 199 #define EMAC_IMR_TXERR (0x1u << 6) /**< \brief (EMAC_IMR) */ 200 #define EMAC_IMR_TCOMP (0x1u << 7) /**< \brief (EMAC_IMR) Transmit Complete */ 201 #define EMAC_IMR_ROVR (0x1u << 10) /**< \brief (EMAC_IMR) Receive Overrun */ 202 #define EMAC_IMR_HRESP (0x1u << 11) /**< \brief (EMAC_IMR) Hresp not OK */ 203 #define EMAC_IMR_PFR (0x1u << 12) /**< \brief (EMAC_IMR) Pause Frame Received */ 204 #define EMAC_IMR_PTZ (0x1u << 13) /**< \brief (EMAC_IMR) Pause Time Zero */ 205 /* -------- EMAC_MAN : (EMAC Offset: 0x34) Phy Maintenance Register -------- */ 206 #define EMAC_MAN_DATA_Pos 0 207 #define EMAC_MAN_DATA_Msk (0xffffu << EMAC_MAN_DATA_Pos) /**< \brief (EMAC_MAN) */ 208 #define EMAC_MAN_DATA(value) ((EMAC_MAN_DATA_Msk & ((value) << EMAC_MAN_DATA_Pos))) 209 #define EMAC_MAN_CODE_Pos 16 210 #define EMAC_MAN_CODE_Msk (0x3u << EMAC_MAN_CODE_Pos) /**< \brief (EMAC_MAN) */ 211 #define EMAC_MAN_CODE(value) ((EMAC_MAN_CODE_Msk & ((value) << EMAC_MAN_CODE_Pos))) 212 #define EMAC_MAN_REGA_Pos 18 213 #define EMAC_MAN_REGA_Msk (0x1fu << EMAC_MAN_REGA_Pos) /**< \brief (EMAC_MAN) Register Address */ 214 #define EMAC_MAN_REGA(value) ((EMAC_MAN_REGA_Msk & ((value) << EMAC_MAN_REGA_Pos))) 215 #define EMAC_MAN_PHYA_Pos 23 216 #define EMAC_MAN_PHYA_Msk (0x1fu << EMAC_MAN_PHYA_Pos) /**< \brief (EMAC_MAN) PHY Address */ 217 #define EMAC_MAN_PHYA(value) ((EMAC_MAN_PHYA_Msk & ((value) << EMAC_MAN_PHYA_Pos))) 218 #define EMAC_MAN_RW_Pos 28 219 #define EMAC_MAN_RW_Msk (0x3u << EMAC_MAN_RW_Pos) /**< \brief (EMAC_MAN) Read-write */ 220 #define EMAC_MAN_RW(value) ((EMAC_MAN_RW_Msk & ((value) << EMAC_MAN_RW_Pos))) 221 #define EMAC_MAN_SOF_Pos 30 222 #define EMAC_MAN_SOF_Msk (0x3u << EMAC_MAN_SOF_Pos) /**< \brief (EMAC_MAN) Start of frame */ 223 #define EMAC_MAN_SOF(value) ((EMAC_MAN_SOF_Msk & ((value) << EMAC_MAN_SOF_Pos))) 224 /* -------- EMAC_PTR : (EMAC Offset: 0x38) Pause Time Register -------- */ 225 #define EMAC_PTR_PTIME_Pos 0 226 #define EMAC_PTR_PTIME_Msk (0xffffu << EMAC_PTR_PTIME_Pos) /**< \brief (EMAC_PTR) Pause Time */ 227 #define EMAC_PTR_PTIME(value) ((EMAC_PTR_PTIME_Msk & ((value) << EMAC_PTR_PTIME_Pos))) 228 /* -------- EMAC_PFR : (EMAC Offset: 0x3C) Pause Frames Received Register -------- */ 229 #define EMAC_PFR_FROK_Pos 0 230 #define EMAC_PFR_FROK_Msk (0xffffu << EMAC_PFR_FROK_Pos) /**< \brief (EMAC_PFR) Pause Frames received OK */ 231 #define EMAC_PFR_FROK(value) ((EMAC_PFR_FROK_Msk & ((value) << EMAC_PFR_FROK_Pos))) 232 /* -------- EMAC_FTO : (EMAC Offset: 0x40) Frames Transmitted Ok Register -------- */ 233 #define EMAC_FTO_FTOK_Pos 0 234 #define EMAC_FTO_FTOK_Msk (0xffffffu << EMAC_FTO_FTOK_Pos) /**< \brief (EMAC_FTO) Frames Transmitted OK */ 235 #define EMAC_FTO_FTOK(value) ((EMAC_FTO_FTOK_Msk & ((value) << EMAC_FTO_FTOK_Pos))) 236 /* -------- EMAC_SCF : (EMAC Offset: 0x44) Single Collision Frames Register -------- */ 237 #define EMAC_SCF_SCF_Pos 0 238 #define EMAC_SCF_SCF_Msk (0xffffu << EMAC_SCF_SCF_Pos) /**< \brief (EMAC_SCF) Single Collision Frames */ 239 #define EMAC_SCF_SCF(value) ((EMAC_SCF_SCF_Msk & ((value) << EMAC_SCF_SCF_Pos))) 240 /* -------- EMAC_MCF : (EMAC Offset: 0x48) Multiple Collision Frames Register -------- */ 241 #define EMAC_MCF_MCF_Pos 0 242 #define EMAC_MCF_MCF_Msk (0xffffu << EMAC_MCF_MCF_Pos) /**< \brief (EMAC_MCF) Multicollision Frames */ 243 #define EMAC_MCF_MCF(value) ((EMAC_MCF_MCF_Msk & ((value) << EMAC_MCF_MCF_Pos))) 244 /* -------- EMAC_FRO : (EMAC Offset: 0x4C) Frames Received Ok Register -------- */ 245 #define EMAC_FRO_FROK_Pos 0 246 #define EMAC_FRO_FROK_Msk (0xffffffu << EMAC_FRO_FROK_Pos) /**< \brief (EMAC_FRO) Frames Received OK */ 247 #define EMAC_FRO_FROK(value) ((EMAC_FRO_FROK_Msk & ((value) << EMAC_FRO_FROK_Pos))) 248 /* -------- EMAC_FCSE : (EMAC Offset: 0x50) Frame Check Sequence Errors Register -------- */ 249 #define EMAC_FCSE_FCSE_Pos 0 250 #define EMAC_FCSE_FCSE_Msk (0xffu << EMAC_FCSE_FCSE_Pos) /**< \brief (EMAC_FCSE) Frame Check Sequence Errors */ 251 #define EMAC_FCSE_FCSE(value) ((EMAC_FCSE_FCSE_Msk & ((value) << EMAC_FCSE_FCSE_Pos))) 252 /* -------- EMAC_ALE : (EMAC Offset: 0x54) Alignment Errors Register -------- */ 253 #define EMAC_ALE_ALE_Pos 0 254 #define EMAC_ALE_ALE_Msk (0xffu << EMAC_ALE_ALE_Pos) /**< \brief (EMAC_ALE) Alignment Errors */ 255 #define EMAC_ALE_ALE(value) ((EMAC_ALE_ALE_Msk & ((value) << EMAC_ALE_ALE_Pos))) 256 /* -------- EMAC_DTF : (EMAC Offset: 0x58) Deferred Transmission Frames Register -------- */ 257 #define EMAC_DTF_DTF_Pos 0 258 #define EMAC_DTF_DTF_Msk (0xffffu << EMAC_DTF_DTF_Pos) /**< \brief (EMAC_DTF) Deferred Transmission Frames */ 259 #define EMAC_DTF_DTF(value) ((EMAC_DTF_DTF_Msk & ((value) << EMAC_DTF_DTF_Pos))) 260 /* -------- EMAC_LCOL : (EMAC Offset: 0x5C) Late Collisions Register -------- */ 261 #define EMAC_LCOL_LCOL_Pos 0 262 #define EMAC_LCOL_LCOL_Msk (0xffu << EMAC_LCOL_LCOL_Pos) /**< \brief (EMAC_LCOL) Late Collisions */ 263 #define EMAC_LCOL_LCOL(value) ((EMAC_LCOL_LCOL_Msk & ((value) << EMAC_LCOL_LCOL_Pos))) 264 /* -------- EMAC_ECOL : (EMAC Offset: 0x60) Excessive Collisions Register -------- */ 265 #define EMAC_ECOL_EXCOL_Pos 0 266 #define EMAC_ECOL_EXCOL_Msk (0xffu << EMAC_ECOL_EXCOL_Pos) /**< \brief (EMAC_ECOL) Excessive Collisions */ 267 #define EMAC_ECOL_EXCOL(value) ((EMAC_ECOL_EXCOL_Msk & ((value) << EMAC_ECOL_EXCOL_Pos))) 268 /* -------- EMAC_TUND : (EMAC Offset: 0x64) Transmit Underrun Errors Register -------- */ 269 #define EMAC_TUND_TUND_Pos 0 270 #define EMAC_TUND_TUND_Msk (0xffu << EMAC_TUND_TUND_Pos) /**< \brief (EMAC_TUND) Transmit Underruns */ 271 #define EMAC_TUND_TUND(value) ((EMAC_TUND_TUND_Msk & ((value) << EMAC_TUND_TUND_Pos))) 272 /* -------- EMAC_CSE : (EMAC Offset: 0x68) Carrier Sense Errors Register -------- */ 273 #define EMAC_CSE_CSE_Pos 0 274 #define EMAC_CSE_CSE_Msk (0xffu << EMAC_CSE_CSE_Pos) /**< \brief (EMAC_CSE) Carrier Sense Errors */ 275 #define EMAC_CSE_CSE(value) ((EMAC_CSE_CSE_Msk & ((value) << EMAC_CSE_CSE_Pos))) 276 /* -------- EMAC_RRE : (EMAC Offset: 0x6C) Receive Resource Errors Register -------- */ 277 #define EMAC_RRE_RRE_Pos 0 278 #define EMAC_RRE_RRE_Msk (0xffffu << EMAC_RRE_RRE_Pos) /**< \brief (EMAC_RRE) Receive Resource Errors */ 279 #define EMAC_RRE_RRE(value) ((EMAC_RRE_RRE_Msk & ((value) << EMAC_RRE_RRE_Pos))) 280 /* -------- EMAC_ROV : (EMAC Offset: 0x70) Receive Overrun Errors Register -------- */ 281 #define EMAC_ROV_ROVR_Pos 0 282 #define EMAC_ROV_ROVR_Msk (0xffu << EMAC_ROV_ROVR_Pos) /**< \brief (EMAC_ROV) Receive Overrun */ 283 #define EMAC_ROV_ROVR(value) ((EMAC_ROV_ROVR_Msk & ((value) << EMAC_ROV_ROVR_Pos))) 284 /* -------- EMAC_RSE : (EMAC Offset: 0x74) Receive Symbol Errors Register -------- */ 285 #define EMAC_RSE_RSE_Pos 0 286 #define EMAC_RSE_RSE_Msk (0xffu << EMAC_RSE_RSE_Pos) /**< \brief (EMAC_RSE) Receive Symbol Errors */ 287 #define EMAC_RSE_RSE(value) ((EMAC_RSE_RSE_Msk & ((value) << EMAC_RSE_RSE_Pos))) 288 /* -------- EMAC_ELE : (EMAC Offset: 0x78) Excessive Length Errors Register -------- */ 289 #define EMAC_ELE_EXL_Pos 0 290 #define EMAC_ELE_EXL_Msk (0xffu << EMAC_ELE_EXL_Pos) /**< \brief (EMAC_ELE) Excessive Length Errors */ 291 #define EMAC_ELE_EXL(value) ((EMAC_ELE_EXL_Msk & ((value) << EMAC_ELE_EXL_Pos))) 292 /* -------- EMAC_RJA : (EMAC Offset: 0x7C) Receive Jabbers Register -------- */ 293 #define EMAC_RJA_RJB_Pos 0 294 #define EMAC_RJA_RJB_Msk (0xffu << EMAC_RJA_RJB_Pos) /**< \brief (EMAC_RJA) Receive Jabbers */ 295 #define EMAC_RJA_RJB(value) ((EMAC_RJA_RJB_Msk & ((value) << EMAC_RJA_RJB_Pos))) 296 /* -------- EMAC_USF : (EMAC Offset: 0x80) Undersize Frames Register -------- */ 297 #define EMAC_USF_USF_Pos 0 298 #define EMAC_USF_USF_Msk (0xffu << EMAC_USF_USF_Pos) /**< \brief (EMAC_USF) Undersize frames */ 299 #define EMAC_USF_USF(value) ((EMAC_USF_USF_Msk & ((value) << EMAC_USF_USF_Pos))) 300 /* -------- EMAC_STE : (EMAC Offset: 0x84) SQE Test Errors Register -------- */ 301 #define EMAC_STE_SQER_Pos 0 302 #define EMAC_STE_SQER_Msk (0xffu << EMAC_STE_SQER_Pos) /**< \brief (EMAC_STE) SQE test errors */ 303 #define EMAC_STE_SQER(value) ((EMAC_STE_SQER_Msk & ((value) << EMAC_STE_SQER_Pos))) 304 /* -------- EMAC_RLE : (EMAC Offset: 0x88) Received Length Field Mismatch Register -------- */ 305 #define EMAC_RLE_RLFM_Pos 0 306 #define EMAC_RLE_RLFM_Msk (0xffu << EMAC_RLE_RLFM_Pos) /**< \brief (EMAC_RLE) Receive Length Field Mismatch */ 307 #define EMAC_RLE_RLFM(value) ((EMAC_RLE_RLFM_Msk & ((value) << EMAC_RLE_RLFM_Pos))) 308 /* -------- EMAC_HRB : (EMAC Offset: 0x90) Hash Register Bottom [31:0] Register -------- */ 309 #define EMAC_HRB_ADDR_Pos 0 310 #define EMAC_HRB_ADDR_Msk (0xffffffffu << EMAC_HRB_ADDR_Pos) /**< \brief (EMAC_HRB) */ 311 #define EMAC_HRB_ADDR(value) ((EMAC_HRB_ADDR_Msk & ((value) << EMAC_HRB_ADDR_Pos))) 312 /* -------- EMAC_HRT : (EMAC Offset: 0x94) Hash Register Top [63:32] Register -------- */ 313 #define EMAC_HRT_ADDR_Pos 0 314 #define EMAC_HRT_ADDR_Msk (0xffffffffu << EMAC_HRT_ADDR_Pos) /**< \brief (EMAC_HRT) */ 315 #define EMAC_HRT_ADDR(value) ((EMAC_HRT_ADDR_Msk & ((value) << EMAC_HRT_ADDR_Pos))) 316 /* -------- EMAC_SAxB : (EMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ 317 #define EMAC_SAxB_ADDR_Pos 0 318 #define EMAC_SAxB_ADDR_Msk (0xffffffffu << EMAC_SAxB_ADDR_Pos) /**< \brief (EMAC_SAxB) */ 319 #define EMAC_SAxB_ADDR(value) ((EMAC_SAxB_ADDR_Msk & ((value) << EMAC_SAxB_ADDR_Pos))) 320 /* -------- EMAC_SAxT : (EMAC Offset: N/A) Specific Address 1 Top Register -------- */ 321 #define EMAC_SAxT_ADDR_Pos 0 322 #define EMAC_SAxT_ADDR_Msk (0xffffu << EMAC_SAxT_ADDR_Pos) /**< \brief (EMAC_SAxT) */ 323 #define EMAC_SAxT_ADDR(value) ((EMAC_SAxT_ADDR_Msk & ((value) << EMAC_SAxT_ADDR_Pos))) 324 /* -------- EMAC_TID : (EMAC Offset: 0xB8) Type ID Checking Register -------- */ 325 #define EMAC_TID_TID_Pos 0 326 #define EMAC_TID_TID_Msk (0xffffu << EMAC_TID_TID_Pos) /**< \brief (EMAC_TID) Type ID checking */ 327 #define EMAC_TID_TID(value) ((EMAC_TID_TID_Msk & ((value) << EMAC_TID_TID_Pos))) 328 /* -------- EMAC_USRIO : (EMAC Offset: 0xC0) User Input/Output Register -------- */ 329 #define EMAC_USRIO_RMII (0x1u << 0) /**< \brief (EMAC_USRIO) Reduce MII */ 330 #define EMAC_USRIO_CLKEN (0x1u << 1) /**< \brief (EMAC_USRIO) Clock Enable */ 331 332 /*@}*/ 333 334 335 #endif /* _SAM3XA_EMAC_COMPONENT_ */ 336
