1 /**
2  * \file
3  *
4  * \brief Component description for USART
5  *
6  * Copyright (c) 2016 Atmel Corporation,
7  *                    a wholly owned subsidiary of Microchip Technology Inc.
8  *
9  * \asf_license_start
10  *
11  * \page License
12  *
13  * Licensed under the Apache License, Version 2.0 (the "License");
14  * you may not use this file except in compliance with the License.
15  * You may obtain a copy of the Licence at
16  *
17  *     http://www.apache.org/licenses/LICENSE-2.0
18  *
19  * Unless required by applicable law or agreed to in writing, software
20  * distributed under the License is distributed on an "AS IS" BASIS,
21  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22  * See the License for the specific language governing permissions and
23  * limitations under the License.
24  *
25  * \asf_license_stop
26  *
27  */
28 
29 #ifndef _SAM4L_USART_COMPONENT_
30 #define _SAM4L_USART_COMPONENT_
31 
32 /* ========================================================================== */
33 /**  SOFTWARE API DEFINITION FOR USART */
34 /* ========================================================================== */
35 /** \addtogroup SAM4L_USART Universal Synchronous Asynchronous Receiver Transmitter */
36 /*@{*/
37 
38 #define USART_I7601
39 #define REV_USART                   0x6021
40 
41 /* -------- US_CR : (USART Offset: 0x00) ( /W 32) Control Register -------- */
42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
43 typedef union {
44   struct { // LIN mode
45     uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
46     uint32_t RSTRX:1;          /*!< bit:      2  Reset Receiver                     */
47     uint32_t RSTTX:1;          /*!< bit:      3  Reset Transmitter                  */
48     uint32_t RXEN:1;           /*!< bit:      4  Receiver Enable                    */
49     uint32_t RXDIS:1;          /*!< bit:      5  Receiver Disable                   */
50     uint32_t TXEN:1;           /*!< bit:      6  Transmitter Enable                 */
51     uint32_t TXDIS:1;          /*!< bit:      7  Transmitter Disable                */
52     uint32_t RSTSTA:1;         /*!< bit:      8  Reset Status Bits                  */
53     uint32_t STTBRK:1;         /*!< bit:      9  Start Break                        */
54     uint32_t STPBRK:1;         /*!< bit:     10  Stop Break                         */
55     uint32_t STTTO:1;          /*!< bit:     11  Start Time-out                     */
56     uint32_t SENDA:1;          /*!< bit:     12  Send Address                       */
57     uint32_t RSTIT:1;          /*!< bit:     13  Reset Iterations                   */
58     uint32_t RSTNACK:1;        /*!< bit:     14  Reset Non Acknowledge              */
59     uint32_t RETTO:1;          /*!< bit:     15  Rearm Time-out                     */
60     uint32_t DTREN:1;          /*!< bit:     16  Data Terminal Ready Enable         */
61     uint32_t DTRDIS:1;         /*!< bit:     17  Data Terminal Ready Disable        */
62     uint32_t RTSEN:1;          /*!< bit:     18  Request to Send Enable             */
63     uint32_t RTSDIS:1;         /*!< bit:     19  Request to Send Disable            */
64     uint32_t LINABT:1;         /*!< bit:     20  Abort the current LIN transmission */
65     uint32_t LINWKUP:1;        /*!< bit:     21  Sends a wakeup signal on the LIN bus */
66     uint32_t :10;              /*!< bit: 22..31  Reserved                           */
67   } LIN;                       /*!< Structure used for LIN                          */
68   struct { // SPI_MASTER mode
69     uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
70     uint32_t RSTRX:1;          /*!< bit:      2  Reset Receiver                     */
71     uint32_t RSTTX:1;          /*!< bit:      3  Reset Transmitter                  */
72     uint32_t RXEN:1;           /*!< bit:      4  Receiver Enable                    */
73     uint32_t RXDIS:1;          /*!< bit:      5  Receiver Disable                   */
74     uint32_t TXEN:1;           /*!< bit:      6  Transmitter Enable                 */
75     uint32_t TXDIS:1;          /*!< bit:      7  Transmitter Disable                */
76     uint32_t RSTSTA:1;         /*!< bit:      8  Reset Status Bits                  */
77     uint32_t STTBRK:1;         /*!< bit:      9  Start Break                        */
78     uint32_t STPBRK:1;         /*!< bit:     10  Stop Break                         */
79     uint32_t STTTO:1;          /*!< bit:     11  Start Time-out                     */
80     uint32_t SENDA:1;          /*!< bit:     12  Send Address                       */
81     uint32_t RSTIT:1;          /*!< bit:     13  Reset Iterations                   */
82     uint32_t RSTNACK:1;        /*!< bit:     14  Reset Non Acknowledge              */
83     uint32_t RETTO:1;          /*!< bit:     15  Rearm Time-out                     */
84     uint32_t DTREN:1;          /*!< bit:     16  Data Terminal Ready Enable         */
85     uint32_t DTRDIS:1;         /*!< bit:     17  Data Terminal Ready Disable        */
86     uint32_t FCS:1;            /*!< bit:     18  Force SPI Chip Select              */
87     uint32_t RCS:1;            /*!< bit:     19  Release SPI Chip Select            */
88     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
89   } SPI_MASTER;                /*!< Structure used for SPI_MASTER                   */
90   struct { // USART mode
91     uint32_t :2;               /*!< bit:  0.. 1  Reserved                           */
92     uint32_t RSTRX:1;          /*!< bit:      2  Reset Receiver                     */
93     uint32_t RSTTX:1;          /*!< bit:      3  Reset Transmitter                  */
94     uint32_t RXEN:1;           /*!< bit:      4  Receiver Enable                    */
95     uint32_t RXDIS:1;          /*!< bit:      5  Receiver Disable                   */
96     uint32_t TXEN:1;           /*!< bit:      6  Transmitter Enable                 */
97     uint32_t TXDIS:1;          /*!< bit:      7  Transmitter Disable                */
98     uint32_t RSTSTA:1;         /*!< bit:      8  Reset Status Bits                  */
99     uint32_t STTBRK:1;         /*!< bit:      9  Start Break                        */
100     uint32_t STPBRK:1;         /*!< bit:     10  Stop Break                         */
101     uint32_t STTTO:1;          /*!< bit:     11  Start Time-out                     */
102     uint32_t SENDA:1;          /*!< bit:     12  Send Address                       */
103     uint32_t RSTIT:1;          /*!< bit:     13  Reset Iterations                   */
104     uint32_t RSTNACK:1;        /*!< bit:     14  Reset Non Acknowledge              */
105     uint32_t RETTO:1;          /*!< bit:     15  Rearm Time-out                     */
106     uint32_t DTREN:1;          /*!< bit:     16  Data Terminal Ready Enable         */
107     uint32_t DTRDIS:1;         /*!< bit:     17  Data Terminal Ready Disable        */
108     uint32_t RTSEN:1;          /*!< bit:     18  Request to Send Enable             */
109     uint32_t RTSDIS:1;         /*!< bit:     19  Request to Send Disable            */
110     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
111   } USART;                     /*!< Structure used for USART                        */
112   uint32_t reg;                /*!< Type      used for register access              */
113 } US_CR_Type;
114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
115 
116 #define US_CR_OFFSET                0x00         /**< \brief (US_CR offset) Control Register */
117 
118 // LIN mode
119 #define US_CR_LIN_RSTRX_Pos         2            /**< \brief (US_CR_LIN) Reset Receiver */
120 #define US_CR_LIN_RSTRX             (_U_(0x1) << US_CR_LIN_RSTRX_Pos)
121 #define   US_CR_LIN_RSTRX_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
122 #define   US_CR_LIN_RSTRX_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Resets the receiver */
123 #define US_CR_LIN_RSTRX_0           (US_CR_LIN_RSTRX_0_Val         << US_CR_LIN_RSTRX_Pos)
124 #define US_CR_LIN_RSTRX_1           (US_CR_LIN_RSTRX_1_Val         << US_CR_LIN_RSTRX_Pos)
125 #define US_CR_LIN_RSTTX_Pos         3            /**< \brief (US_CR_LIN) Reset Transmitter */
126 #define US_CR_LIN_RSTTX             (_U_(0x1) << US_CR_LIN_RSTTX_Pos)
127 #define   US_CR_LIN_RSTTX_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
128 #define   US_CR_LIN_RSTTX_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Resets the transmitter */
129 #define US_CR_LIN_RSTTX_0           (US_CR_LIN_RSTTX_0_Val         << US_CR_LIN_RSTTX_Pos)
130 #define US_CR_LIN_RSTTX_1           (US_CR_LIN_RSTTX_1_Val         << US_CR_LIN_RSTTX_Pos)
131 #define US_CR_LIN_RXEN_Pos          4            /**< \brief (US_CR_LIN) Receiver Enable */
132 #define US_CR_LIN_RXEN              (_U_(0x1) << US_CR_LIN_RXEN_Pos)
133 #define   US_CR_LIN_RXEN_0_Val            _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
134 #define   US_CR_LIN_RXEN_1_Val            _U_(0x1)   /**< \brief (US_CR_LIN) Enables the receiver, if RXDIS is 0 */
135 #define US_CR_LIN_RXEN_0            (US_CR_LIN_RXEN_0_Val          << US_CR_LIN_RXEN_Pos)
136 #define US_CR_LIN_RXEN_1            (US_CR_LIN_RXEN_1_Val          << US_CR_LIN_RXEN_Pos)
137 #define US_CR_LIN_RXDIS_Pos         5            /**< \brief (US_CR_LIN) Receiver Disable */
138 #define US_CR_LIN_RXDIS             (_U_(0x1) << US_CR_LIN_RXDIS_Pos)
139 #define   US_CR_LIN_RXDIS_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
140 #define   US_CR_LIN_RXDIS_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Disables the receiver */
141 #define US_CR_LIN_RXDIS_0           (US_CR_LIN_RXDIS_0_Val         << US_CR_LIN_RXDIS_Pos)
142 #define US_CR_LIN_RXDIS_1           (US_CR_LIN_RXDIS_1_Val         << US_CR_LIN_RXDIS_Pos)
143 #define US_CR_LIN_TXEN_Pos          6            /**< \brief (US_CR_LIN) Transmitter Enable */
144 #define US_CR_LIN_TXEN              (_U_(0x1) << US_CR_LIN_TXEN_Pos)
145 #define   US_CR_LIN_TXEN_0_Val            _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
146 #define   US_CR_LIN_TXEN_1_Val            _U_(0x1)   /**< \brief (US_CR_LIN) Enables the transmitter if TXDIS is 0 */
147 #define US_CR_LIN_TXEN_0            (US_CR_LIN_TXEN_0_Val          << US_CR_LIN_TXEN_Pos)
148 #define US_CR_LIN_TXEN_1            (US_CR_LIN_TXEN_1_Val          << US_CR_LIN_TXEN_Pos)
149 #define US_CR_LIN_TXDIS_Pos         7            /**< \brief (US_CR_LIN) Transmitter Disable */
150 #define US_CR_LIN_TXDIS             (_U_(0x1) << US_CR_LIN_TXDIS_Pos)
151 #define   US_CR_LIN_TXDIS_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
152 #define   US_CR_LIN_TXDIS_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Disables the transmitter */
153 #define US_CR_LIN_TXDIS_0           (US_CR_LIN_TXDIS_0_Val         << US_CR_LIN_TXDIS_Pos)
154 #define US_CR_LIN_TXDIS_1           (US_CR_LIN_TXDIS_1_Val         << US_CR_LIN_TXDIS_Pos)
155 #define US_CR_LIN_RSTSTA_Pos        8            /**< \brief (US_CR_LIN) Reset Status Bits */
156 #define US_CR_LIN_RSTSTA            (_U_(0x1) << US_CR_LIN_RSTSTA_Pos)
157 #define   US_CR_LIN_RSTSTA_0_Val          _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
158 #define   US_CR_LIN_RSTSTA_1_Val          _U_(0x1)   /**< \brief (US_CR_LIN) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */
159 #define US_CR_LIN_RSTSTA_0          (US_CR_LIN_RSTSTA_0_Val        << US_CR_LIN_RSTSTA_Pos)
160 #define US_CR_LIN_RSTSTA_1          (US_CR_LIN_RSTSTA_1_Val        << US_CR_LIN_RSTSTA_Pos)
161 #define US_CR_LIN_STTBRK_Pos        9            /**< \brief (US_CR_LIN) Start Break */
162 #define US_CR_LIN_STTBRK            (_U_(0x1) << US_CR_LIN_STTBRK_Pos)
163 #define   US_CR_LIN_STTBRK_0_Val          _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
164 #define   US_CR_LIN_STTBRK_1_Val          _U_(0x1)   /**< \brief (US_CR_LIN) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */
165 #define US_CR_LIN_STTBRK_0          (US_CR_LIN_STTBRK_0_Val        << US_CR_LIN_STTBRK_Pos)
166 #define US_CR_LIN_STTBRK_1          (US_CR_LIN_STTBRK_1_Val        << US_CR_LIN_STTBRK_Pos)
167 #define US_CR_LIN_STPBRK_Pos        10           /**< \brief (US_CR_LIN) Stop Break */
168 #define US_CR_LIN_STPBRK            (_U_(0x1) << US_CR_LIN_STPBRK_Pos)
169 #define   US_CR_LIN_STPBRK_0_Val          _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
170 #define   US_CR_LIN_STPBRK_1_Val          _U_(0x1)   /**< \brief (US_CR_LIN) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */
171 #define US_CR_LIN_STPBRK_0          (US_CR_LIN_STPBRK_0_Val        << US_CR_LIN_STPBRK_Pos)
172 #define US_CR_LIN_STPBRK_1          (US_CR_LIN_STPBRK_1_Val        << US_CR_LIN_STPBRK_Pos)
173 #define US_CR_LIN_STTTO_Pos         11           /**< \brief (US_CR_LIN) Start Time-out */
174 #define US_CR_LIN_STTTO             (_U_(0x1) << US_CR_LIN_STTTO_Pos)
175 #define   US_CR_LIN_STTTO_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
176 #define   US_CR_LIN_STTTO_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Starts waiting for a character before clocking the time-out counter */
177 #define US_CR_LIN_STTTO_0           (US_CR_LIN_STTTO_0_Val         << US_CR_LIN_STTTO_Pos)
178 #define US_CR_LIN_STTTO_1           (US_CR_LIN_STTTO_1_Val         << US_CR_LIN_STTTO_Pos)
179 #define US_CR_LIN_SENDA_Pos         12           /**< \brief (US_CR_LIN) Send Address */
180 #define US_CR_LIN_SENDA             (_U_(0x1) << US_CR_LIN_SENDA_Pos)
181 #define   US_CR_LIN_SENDA_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
182 #define   US_CR_LIN_SENDA_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */
183 #define US_CR_LIN_SENDA_0           (US_CR_LIN_SENDA_0_Val         << US_CR_LIN_SENDA_Pos)
184 #define US_CR_LIN_SENDA_1           (US_CR_LIN_SENDA_1_Val         << US_CR_LIN_SENDA_Pos)
185 #define US_CR_LIN_RSTIT_Pos         13           /**< \brief (US_CR_LIN) Reset Iterations */
186 #define US_CR_LIN_RSTIT             (_U_(0x1) << US_CR_LIN_RSTIT_Pos)
187 #define   US_CR_LIN_RSTIT_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
188 #define   US_CR_LIN_RSTIT_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */
189 #define US_CR_LIN_RSTIT_0           (US_CR_LIN_RSTIT_0_Val         << US_CR_LIN_RSTIT_Pos)
190 #define US_CR_LIN_RSTIT_1           (US_CR_LIN_RSTIT_1_Val         << US_CR_LIN_RSTIT_Pos)
191 #define US_CR_LIN_RSTNACK_Pos       14           /**< \brief (US_CR_LIN) Reset Non Acknowledge */
192 #define US_CR_LIN_RSTNACK           (_U_(0x1) << US_CR_LIN_RSTNACK_Pos)
193 #define   US_CR_LIN_RSTNACK_0_Val         _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
194 #define   US_CR_LIN_RSTNACK_1_Val         _U_(0x1)   /**< \brief (US_CR_LIN) Resets NACK in CSR */
195 #define US_CR_LIN_RSTNACK_0         (US_CR_LIN_RSTNACK_0_Val       << US_CR_LIN_RSTNACK_Pos)
196 #define US_CR_LIN_RSTNACK_1         (US_CR_LIN_RSTNACK_1_Val       << US_CR_LIN_RSTNACK_Pos)
197 #define US_CR_LIN_RETTO_Pos         15           /**< \brief (US_CR_LIN) Rearm Time-out */
198 #define US_CR_LIN_RETTO             (_U_(0x1) << US_CR_LIN_RETTO_Pos)
199 #define   US_CR_LIN_RETTO_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
200 #define   US_CR_LIN_RETTO_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Restart Time-out */
201 #define US_CR_LIN_RETTO_0           (US_CR_LIN_RETTO_0_Val         << US_CR_LIN_RETTO_Pos)
202 #define US_CR_LIN_RETTO_1           (US_CR_LIN_RETTO_1_Val         << US_CR_LIN_RETTO_Pos)
203 #define US_CR_LIN_DTREN_Pos         16           /**< \brief (US_CR_LIN) Data Terminal Ready Enable */
204 #define US_CR_LIN_DTREN             (_U_(0x1) << US_CR_LIN_DTREN_Pos)
205 #define   US_CR_LIN_DTREN_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
206 #define   US_CR_LIN_DTREN_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Drives the pin DTR at 0 */
207 #define US_CR_LIN_DTREN_0           (US_CR_LIN_DTREN_0_Val         << US_CR_LIN_DTREN_Pos)
208 #define US_CR_LIN_DTREN_1           (US_CR_LIN_DTREN_1_Val         << US_CR_LIN_DTREN_Pos)
209 #define US_CR_LIN_DTRDIS_Pos        17           /**< \brief (US_CR_LIN) Data Terminal Ready Disable */
210 #define US_CR_LIN_DTRDIS            (_U_(0x1) << US_CR_LIN_DTRDIS_Pos)
211 #define   US_CR_LIN_DTRDIS_0_Val          _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
212 #define   US_CR_LIN_DTRDIS_1_Val          _U_(0x1)   /**< \brief (US_CR_LIN) Drives the pin DTR to 1 */
213 #define US_CR_LIN_DTRDIS_0          (US_CR_LIN_DTRDIS_0_Val        << US_CR_LIN_DTRDIS_Pos)
214 #define US_CR_LIN_DTRDIS_1          (US_CR_LIN_DTRDIS_1_Val        << US_CR_LIN_DTRDIS_Pos)
215 #define US_CR_LIN_RTSEN_Pos         18           /**< \brief (US_CR_LIN) Request to Send Enable */
216 #define US_CR_LIN_RTSEN             (_U_(0x1) << US_CR_LIN_RTSEN_Pos)
217 #define   US_CR_LIN_RTSEN_0_Val           _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
218 #define   US_CR_LIN_RTSEN_1_Val           _U_(0x1)   /**< \brief (US_CR_LIN) Drives the pin RTS to 0 */
219 #define US_CR_LIN_RTSEN_0           (US_CR_LIN_RTSEN_0_Val         << US_CR_LIN_RTSEN_Pos)
220 #define US_CR_LIN_RTSEN_1           (US_CR_LIN_RTSEN_1_Val         << US_CR_LIN_RTSEN_Pos)
221 #define US_CR_LIN_RTSDIS_Pos        19           /**< \brief (US_CR_LIN) Request to Send Disable */
222 #define US_CR_LIN_RTSDIS            (_U_(0x1) << US_CR_LIN_RTSDIS_Pos)
223 #define   US_CR_LIN_RTSDIS_0_Val          _U_(0x0)   /**< \brief (US_CR_LIN) No effect */
224 #define   US_CR_LIN_RTSDIS_1_Val          _U_(0x1)   /**< \brief (US_CR_LIN) Drives the pin RTS to 1 */
225 #define US_CR_LIN_RTSDIS_0          (US_CR_LIN_RTSDIS_0_Val        << US_CR_LIN_RTSDIS_Pos)
226 #define US_CR_LIN_RTSDIS_1          (US_CR_LIN_RTSDIS_1_Val        << US_CR_LIN_RTSDIS_Pos)
227 #define US_CR_LIN_LINABT_Pos        20           /**< \brief (US_CR_LIN) Abort the current LIN transmission */
228 #define US_CR_LIN_LINABT            (_U_(0x1) << US_CR_LIN_LINABT_Pos)
229 #define US_CR_LIN_LINWKUP_Pos       21           /**< \brief (US_CR_LIN) Sends a wakeup signal on the LIN bus */
230 #define US_CR_LIN_LINWKUP           (_U_(0x1) << US_CR_LIN_LINWKUP_Pos)
231 #define US_CR_LIN_MASK              _U_(0x003FFFFC) /**< \brief (US_CR_LIN) MASK Register */
232 
233 // SPI_MASTER mode
234 #define US_CR_SPI_MASTER_RSTRX_Pos  2            /**< \brief (US_CR_SPI_MASTER) Reset Receiver */
235 #define US_CR_SPI_MASTER_RSTRX      (_U_(0x1) << US_CR_SPI_MASTER_RSTRX_Pos)
236 #define   US_CR_SPI_MASTER_RSTRX_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
237 #define   US_CR_SPI_MASTER_RSTRX_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Resets the receiver */
238 #define US_CR_SPI_MASTER_RSTRX_0    (US_CR_SPI_MASTER_RSTRX_0_Val  << US_CR_SPI_MASTER_RSTRX_Pos)
239 #define US_CR_SPI_MASTER_RSTRX_1    (US_CR_SPI_MASTER_RSTRX_1_Val  << US_CR_SPI_MASTER_RSTRX_Pos)
240 #define US_CR_SPI_MASTER_RSTTX_Pos  3            /**< \brief (US_CR_SPI_MASTER) Reset Transmitter */
241 #define US_CR_SPI_MASTER_RSTTX      (_U_(0x1) << US_CR_SPI_MASTER_RSTTX_Pos)
242 #define   US_CR_SPI_MASTER_RSTTX_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
243 #define   US_CR_SPI_MASTER_RSTTX_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Resets the transmitter */
244 #define US_CR_SPI_MASTER_RSTTX_0    (US_CR_SPI_MASTER_RSTTX_0_Val  << US_CR_SPI_MASTER_RSTTX_Pos)
245 #define US_CR_SPI_MASTER_RSTTX_1    (US_CR_SPI_MASTER_RSTTX_1_Val  << US_CR_SPI_MASTER_RSTTX_Pos)
246 #define US_CR_SPI_MASTER_RXEN_Pos   4            /**< \brief (US_CR_SPI_MASTER) Receiver Enable */
247 #define US_CR_SPI_MASTER_RXEN       (_U_(0x1) << US_CR_SPI_MASTER_RXEN_Pos)
248 #define   US_CR_SPI_MASTER_RXEN_0_Val     _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
249 #define   US_CR_SPI_MASTER_RXEN_1_Val     _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Enables the receiver, if RXDIS is 0 */
250 #define US_CR_SPI_MASTER_RXEN_0     (US_CR_SPI_MASTER_RXEN_0_Val   << US_CR_SPI_MASTER_RXEN_Pos)
251 #define US_CR_SPI_MASTER_RXEN_1     (US_CR_SPI_MASTER_RXEN_1_Val   << US_CR_SPI_MASTER_RXEN_Pos)
252 #define US_CR_SPI_MASTER_RXDIS_Pos  5            /**< \brief (US_CR_SPI_MASTER) Receiver Disable */
253 #define US_CR_SPI_MASTER_RXDIS      (_U_(0x1) << US_CR_SPI_MASTER_RXDIS_Pos)
254 #define   US_CR_SPI_MASTER_RXDIS_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
255 #define   US_CR_SPI_MASTER_RXDIS_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Disables the receiver */
256 #define US_CR_SPI_MASTER_RXDIS_0    (US_CR_SPI_MASTER_RXDIS_0_Val  << US_CR_SPI_MASTER_RXDIS_Pos)
257 #define US_CR_SPI_MASTER_RXDIS_1    (US_CR_SPI_MASTER_RXDIS_1_Val  << US_CR_SPI_MASTER_RXDIS_Pos)
258 #define US_CR_SPI_MASTER_TXEN_Pos   6            /**< \brief (US_CR_SPI_MASTER) Transmitter Enable */
259 #define US_CR_SPI_MASTER_TXEN       (_U_(0x1) << US_CR_SPI_MASTER_TXEN_Pos)
260 #define   US_CR_SPI_MASTER_TXEN_0_Val     _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
261 #define   US_CR_SPI_MASTER_TXEN_1_Val     _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Enables the transmitter if TXDIS is 0 */
262 #define US_CR_SPI_MASTER_TXEN_0     (US_CR_SPI_MASTER_TXEN_0_Val   << US_CR_SPI_MASTER_TXEN_Pos)
263 #define US_CR_SPI_MASTER_TXEN_1     (US_CR_SPI_MASTER_TXEN_1_Val   << US_CR_SPI_MASTER_TXEN_Pos)
264 #define US_CR_SPI_MASTER_TXDIS_Pos  7            /**< \brief (US_CR_SPI_MASTER) Transmitter Disable */
265 #define US_CR_SPI_MASTER_TXDIS      (_U_(0x1) << US_CR_SPI_MASTER_TXDIS_Pos)
266 #define   US_CR_SPI_MASTER_TXDIS_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
267 #define   US_CR_SPI_MASTER_TXDIS_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Disables the transmitter */
268 #define US_CR_SPI_MASTER_TXDIS_0    (US_CR_SPI_MASTER_TXDIS_0_Val  << US_CR_SPI_MASTER_TXDIS_Pos)
269 #define US_CR_SPI_MASTER_TXDIS_1    (US_CR_SPI_MASTER_TXDIS_1_Val  << US_CR_SPI_MASTER_TXDIS_Pos)
270 #define US_CR_SPI_MASTER_RSTSTA_Pos 8            /**< \brief (US_CR_SPI_MASTER) Reset Status Bits */
271 #define US_CR_SPI_MASTER_RSTSTA     (_U_(0x1) << US_CR_SPI_MASTER_RSTSTA_Pos)
272 #define   US_CR_SPI_MASTER_RSTSTA_0_Val   _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
273 #define   US_CR_SPI_MASTER_RSTSTA_1_Val   _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */
274 #define US_CR_SPI_MASTER_RSTSTA_0   (US_CR_SPI_MASTER_RSTSTA_0_Val << US_CR_SPI_MASTER_RSTSTA_Pos)
275 #define US_CR_SPI_MASTER_RSTSTA_1   (US_CR_SPI_MASTER_RSTSTA_1_Val << US_CR_SPI_MASTER_RSTSTA_Pos)
276 #define US_CR_SPI_MASTER_STTBRK_Pos 9            /**< \brief (US_CR_SPI_MASTER) Start Break */
277 #define US_CR_SPI_MASTER_STTBRK     (_U_(0x1) << US_CR_SPI_MASTER_STTBRK_Pos)
278 #define   US_CR_SPI_MASTER_STTBRK_0_Val   _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
279 #define   US_CR_SPI_MASTER_STTBRK_1_Val   _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */
280 #define US_CR_SPI_MASTER_STTBRK_0   (US_CR_SPI_MASTER_STTBRK_0_Val << US_CR_SPI_MASTER_STTBRK_Pos)
281 #define US_CR_SPI_MASTER_STTBRK_1   (US_CR_SPI_MASTER_STTBRK_1_Val << US_CR_SPI_MASTER_STTBRK_Pos)
282 #define US_CR_SPI_MASTER_STPBRK_Pos 10           /**< \brief (US_CR_SPI_MASTER) Stop Break */
283 #define US_CR_SPI_MASTER_STPBRK     (_U_(0x1) << US_CR_SPI_MASTER_STPBRK_Pos)
284 #define   US_CR_SPI_MASTER_STPBRK_0_Val   _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
285 #define   US_CR_SPI_MASTER_STPBRK_1_Val   _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */
286 #define US_CR_SPI_MASTER_STPBRK_0   (US_CR_SPI_MASTER_STPBRK_0_Val << US_CR_SPI_MASTER_STPBRK_Pos)
287 #define US_CR_SPI_MASTER_STPBRK_1   (US_CR_SPI_MASTER_STPBRK_1_Val << US_CR_SPI_MASTER_STPBRK_Pos)
288 #define US_CR_SPI_MASTER_STTTO_Pos  11           /**< \brief (US_CR_SPI_MASTER) Start Time-out */
289 #define US_CR_SPI_MASTER_STTTO      (_U_(0x1) << US_CR_SPI_MASTER_STTTO_Pos)
290 #define   US_CR_SPI_MASTER_STTTO_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
291 #define   US_CR_SPI_MASTER_STTTO_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Starts waiting for a character before clocking the time-out counter */
292 #define US_CR_SPI_MASTER_STTTO_0    (US_CR_SPI_MASTER_STTTO_0_Val  << US_CR_SPI_MASTER_STTTO_Pos)
293 #define US_CR_SPI_MASTER_STTTO_1    (US_CR_SPI_MASTER_STTTO_1_Val  << US_CR_SPI_MASTER_STTTO_Pos)
294 #define US_CR_SPI_MASTER_SENDA_Pos  12           /**< \brief (US_CR_SPI_MASTER) Send Address */
295 #define US_CR_SPI_MASTER_SENDA      (_U_(0x1) << US_CR_SPI_MASTER_SENDA_Pos)
296 #define   US_CR_SPI_MASTER_SENDA_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
297 #define   US_CR_SPI_MASTER_SENDA_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */
298 #define US_CR_SPI_MASTER_SENDA_0    (US_CR_SPI_MASTER_SENDA_0_Val  << US_CR_SPI_MASTER_SENDA_Pos)
299 #define US_CR_SPI_MASTER_SENDA_1    (US_CR_SPI_MASTER_SENDA_1_Val  << US_CR_SPI_MASTER_SENDA_Pos)
300 #define US_CR_SPI_MASTER_RSTIT_Pos  13           /**< \brief (US_CR_SPI_MASTER) Reset Iterations */
301 #define US_CR_SPI_MASTER_RSTIT      (_U_(0x1) << US_CR_SPI_MASTER_RSTIT_Pos)
302 #define   US_CR_SPI_MASTER_RSTIT_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
303 #define   US_CR_SPI_MASTER_RSTIT_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */
304 #define US_CR_SPI_MASTER_RSTIT_0    (US_CR_SPI_MASTER_RSTIT_0_Val  << US_CR_SPI_MASTER_RSTIT_Pos)
305 #define US_CR_SPI_MASTER_RSTIT_1    (US_CR_SPI_MASTER_RSTIT_1_Val  << US_CR_SPI_MASTER_RSTIT_Pos)
306 #define US_CR_SPI_MASTER_RSTNACK_Pos 14           /**< \brief (US_CR_SPI_MASTER) Reset Non Acknowledge */
307 #define US_CR_SPI_MASTER_RSTNACK    (_U_(0x1) << US_CR_SPI_MASTER_RSTNACK_Pos)
308 #define   US_CR_SPI_MASTER_RSTNACK_0_Val  _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
309 #define   US_CR_SPI_MASTER_RSTNACK_1_Val  _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Resets NACK in CSR */
310 #define US_CR_SPI_MASTER_RSTNACK_0  (US_CR_SPI_MASTER_RSTNACK_0_Val << US_CR_SPI_MASTER_RSTNACK_Pos)
311 #define US_CR_SPI_MASTER_RSTNACK_1  (US_CR_SPI_MASTER_RSTNACK_1_Val << US_CR_SPI_MASTER_RSTNACK_Pos)
312 #define US_CR_SPI_MASTER_RETTO_Pos  15           /**< \brief (US_CR_SPI_MASTER) Rearm Time-out */
313 #define US_CR_SPI_MASTER_RETTO      (_U_(0x1) << US_CR_SPI_MASTER_RETTO_Pos)
314 #define   US_CR_SPI_MASTER_RETTO_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
315 #define   US_CR_SPI_MASTER_RETTO_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Restart Time-out */
316 #define US_CR_SPI_MASTER_RETTO_0    (US_CR_SPI_MASTER_RETTO_0_Val  << US_CR_SPI_MASTER_RETTO_Pos)
317 #define US_CR_SPI_MASTER_RETTO_1    (US_CR_SPI_MASTER_RETTO_1_Val  << US_CR_SPI_MASTER_RETTO_Pos)
318 #define US_CR_SPI_MASTER_DTREN_Pos  16           /**< \brief (US_CR_SPI_MASTER) Data Terminal Ready Enable */
319 #define US_CR_SPI_MASTER_DTREN      (_U_(0x1) << US_CR_SPI_MASTER_DTREN_Pos)
320 #define   US_CR_SPI_MASTER_DTREN_0_Val    _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
321 #define   US_CR_SPI_MASTER_DTREN_1_Val    _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Drives the pin DTR at 0 */
322 #define US_CR_SPI_MASTER_DTREN_0    (US_CR_SPI_MASTER_DTREN_0_Val  << US_CR_SPI_MASTER_DTREN_Pos)
323 #define US_CR_SPI_MASTER_DTREN_1    (US_CR_SPI_MASTER_DTREN_1_Val  << US_CR_SPI_MASTER_DTREN_Pos)
324 #define US_CR_SPI_MASTER_DTRDIS_Pos 17           /**< \brief (US_CR_SPI_MASTER) Data Terminal Ready Disable */
325 #define US_CR_SPI_MASTER_DTRDIS     (_U_(0x1) << US_CR_SPI_MASTER_DTRDIS_Pos)
326 #define   US_CR_SPI_MASTER_DTRDIS_0_Val   _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
327 #define   US_CR_SPI_MASTER_DTRDIS_1_Val   _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Drives the pin DTR to 1 */
328 #define US_CR_SPI_MASTER_DTRDIS_0   (US_CR_SPI_MASTER_DTRDIS_0_Val << US_CR_SPI_MASTER_DTRDIS_Pos)
329 #define US_CR_SPI_MASTER_DTRDIS_1   (US_CR_SPI_MASTER_DTRDIS_1_Val << US_CR_SPI_MASTER_DTRDIS_Pos)
330 #define US_CR_SPI_MASTER_FCS_Pos    18           /**< \brief (US_CR_SPI_MASTER) Force SPI Chip Select */
331 #define US_CR_SPI_MASTER_FCS        (_U_(0x1) << US_CR_SPI_MASTER_FCS_Pos)
332 #define   US_CR_SPI_MASTER_FCS_0_Val      _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
333 #define   US_CR_SPI_MASTER_FCS_1_Val      _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) */
334 #define US_CR_SPI_MASTER_FCS_0      (US_CR_SPI_MASTER_FCS_0_Val    << US_CR_SPI_MASTER_FCS_Pos)
335 #define US_CR_SPI_MASTER_FCS_1      (US_CR_SPI_MASTER_FCS_1_Val    << US_CR_SPI_MASTER_FCS_Pos)
336 #define US_CR_SPI_MASTER_RCS_Pos    19           /**< \brief (US_CR_SPI_MASTER) Release SPI Chip Select */
337 #define US_CR_SPI_MASTER_RCS        (_U_(0x1) << US_CR_SPI_MASTER_RCS_Pos)
338 #define   US_CR_SPI_MASTER_RCS_0_Val      _U_(0x0)   /**< \brief (US_CR_SPI_MASTER) No effect */
339 #define   US_CR_SPI_MASTER_RCS_1_Val      _U_(0x1)   /**< \brief (US_CR_SPI_MASTER) Releases the Slave Select Line NSS (RTS pin) */
340 #define US_CR_SPI_MASTER_RCS_0      (US_CR_SPI_MASTER_RCS_0_Val    << US_CR_SPI_MASTER_RCS_Pos)
341 #define US_CR_SPI_MASTER_RCS_1      (US_CR_SPI_MASTER_RCS_1_Val    << US_CR_SPI_MASTER_RCS_Pos)
342 #define US_CR_SPI_MASTER_MASK       _U_(0x000FFFFC) /**< \brief (US_CR_SPI_MASTER) MASK Register */
343 
344 // USART mode
345 #define US_CR_USART_RSTRX_Pos       2            /**< \brief (US_CR_USART) Reset Receiver */
346 #define US_CR_USART_RSTRX           (_U_(0x1) << US_CR_USART_RSTRX_Pos)
347 #define   US_CR_USART_RSTRX_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
348 #define   US_CR_USART_RSTRX_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Resets the receiver */
349 #define US_CR_USART_RSTRX_0         (US_CR_USART_RSTRX_0_Val       << US_CR_USART_RSTRX_Pos)
350 #define US_CR_USART_RSTRX_1         (US_CR_USART_RSTRX_1_Val       << US_CR_USART_RSTRX_Pos)
351 #define US_CR_USART_RSTTX_Pos       3            /**< \brief (US_CR_USART) Reset Transmitter */
352 #define US_CR_USART_RSTTX           (_U_(0x1) << US_CR_USART_RSTTX_Pos)
353 #define   US_CR_USART_RSTTX_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
354 #define   US_CR_USART_RSTTX_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Resets the transmitter */
355 #define US_CR_USART_RSTTX_0         (US_CR_USART_RSTTX_0_Val       << US_CR_USART_RSTTX_Pos)
356 #define US_CR_USART_RSTTX_1         (US_CR_USART_RSTTX_1_Val       << US_CR_USART_RSTTX_Pos)
357 #define US_CR_USART_RXEN_Pos        4            /**< \brief (US_CR_USART) Receiver Enable */
358 #define US_CR_USART_RXEN            (_U_(0x1) << US_CR_USART_RXEN_Pos)
359 #define   US_CR_USART_RXEN_0_Val          _U_(0x0)   /**< \brief (US_CR_USART) No effect */
360 #define   US_CR_USART_RXEN_1_Val          _U_(0x1)   /**< \brief (US_CR_USART) Enables the receiver, if RXDIS is 0 */
361 #define US_CR_USART_RXEN_0          (US_CR_USART_RXEN_0_Val        << US_CR_USART_RXEN_Pos)
362 #define US_CR_USART_RXEN_1          (US_CR_USART_RXEN_1_Val        << US_CR_USART_RXEN_Pos)
363 #define US_CR_USART_RXDIS_Pos       5            /**< \brief (US_CR_USART) Receiver Disable */
364 #define US_CR_USART_RXDIS           (_U_(0x1) << US_CR_USART_RXDIS_Pos)
365 #define   US_CR_USART_RXDIS_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
366 #define   US_CR_USART_RXDIS_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Disables the receiver */
367 #define US_CR_USART_RXDIS_0         (US_CR_USART_RXDIS_0_Val       << US_CR_USART_RXDIS_Pos)
368 #define US_CR_USART_RXDIS_1         (US_CR_USART_RXDIS_1_Val       << US_CR_USART_RXDIS_Pos)
369 #define US_CR_USART_TXEN_Pos        6            /**< \brief (US_CR_USART) Transmitter Enable */
370 #define US_CR_USART_TXEN            (_U_(0x1) << US_CR_USART_TXEN_Pos)
371 #define   US_CR_USART_TXEN_0_Val          _U_(0x0)   /**< \brief (US_CR_USART) No effect */
372 #define   US_CR_USART_TXEN_1_Val          _U_(0x1)   /**< \brief (US_CR_USART) Enables the transmitter if TXDIS is 0 */
373 #define US_CR_USART_TXEN_0          (US_CR_USART_TXEN_0_Val        << US_CR_USART_TXEN_Pos)
374 #define US_CR_USART_TXEN_1          (US_CR_USART_TXEN_1_Val        << US_CR_USART_TXEN_Pos)
375 #define US_CR_USART_TXDIS_Pos       7            /**< \brief (US_CR_USART) Transmitter Disable */
376 #define US_CR_USART_TXDIS           (_U_(0x1) << US_CR_USART_TXDIS_Pos)
377 #define   US_CR_USART_TXDIS_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
378 #define   US_CR_USART_TXDIS_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Disables the transmitter */
379 #define US_CR_USART_TXDIS_0         (US_CR_USART_TXDIS_0_Val       << US_CR_USART_TXDIS_Pos)
380 #define US_CR_USART_TXDIS_1         (US_CR_USART_TXDIS_1_Val       << US_CR_USART_TXDIS_Pos)
381 #define US_CR_USART_RSTSTA_Pos      8            /**< \brief (US_CR_USART) Reset Status Bits */
382 #define US_CR_USART_RSTSTA          (_U_(0x1) << US_CR_USART_RSTSTA_Pos)
383 #define   US_CR_USART_RSTSTA_0_Val        _U_(0x0)   /**< \brief (US_CR_USART) No effect */
384 #define   US_CR_USART_RSTSTA_1_Val        _U_(0x1)   /**< \brief (US_CR_USART) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */
385 #define US_CR_USART_RSTSTA_0        (US_CR_USART_RSTSTA_0_Val      << US_CR_USART_RSTSTA_Pos)
386 #define US_CR_USART_RSTSTA_1        (US_CR_USART_RSTSTA_1_Val      << US_CR_USART_RSTSTA_Pos)
387 #define US_CR_USART_STTBRK_Pos      9            /**< \brief (US_CR_USART) Start Break */
388 #define US_CR_USART_STTBRK          (_U_(0x1) << US_CR_USART_STTBRK_Pos)
389 #define   US_CR_USART_STTBRK_0_Val        _U_(0x0)   /**< \brief (US_CR_USART) No effect */
390 #define   US_CR_USART_STTBRK_1_Val        _U_(0x1)   /**< \brief (US_CR_USART) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */
391 #define US_CR_USART_STTBRK_0        (US_CR_USART_STTBRK_0_Val      << US_CR_USART_STTBRK_Pos)
392 #define US_CR_USART_STTBRK_1        (US_CR_USART_STTBRK_1_Val      << US_CR_USART_STTBRK_Pos)
393 #define US_CR_USART_STPBRK_Pos      10           /**< \brief (US_CR_USART) Stop Break */
394 #define US_CR_USART_STPBRK          (_U_(0x1) << US_CR_USART_STPBRK_Pos)
395 #define   US_CR_USART_STPBRK_0_Val        _U_(0x0)   /**< \brief (US_CR_USART) No effect */
396 #define   US_CR_USART_STPBRK_1_Val        _U_(0x1)   /**< \brief (US_CR_USART) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */
397 #define US_CR_USART_STPBRK_0        (US_CR_USART_STPBRK_0_Val      << US_CR_USART_STPBRK_Pos)
398 #define US_CR_USART_STPBRK_1        (US_CR_USART_STPBRK_1_Val      << US_CR_USART_STPBRK_Pos)
399 #define US_CR_USART_STTTO_Pos       11           /**< \brief (US_CR_USART) Start Time-out */
400 #define US_CR_USART_STTTO           (_U_(0x1) << US_CR_USART_STTTO_Pos)
401 #define   US_CR_USART_STTTO_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
402 #define   US_CR_USART_STTTO_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Starts waiting for a character before clocking the time-out counter */
403 #define US_CR_USART_STTTO_0         (US_CR_USART_STTTO_0_Val       << US_CR_USART_STTTO_Pos)
404 #define US_CR_USART_STTTO_1         (US_CR_USART_STTTO_1_Val       << US_CR_USART_STTTO_Pos)
405 #define US_CR_USART_SENDA_Pos       12           /**< \brief (US_CR_USART) Send Address */
406 #define US_CR_USART_SENDA           (_U_(0x1) << US_CR_USART_SENDA_Pos)
407 #define   US_CR_USART_SENDA_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
408 #define   US_CR_USART_SENDA_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */
409 #define US_CR_USART_SENDA_0         (US_CR_USART_SENDA_0_Val       << US_CR_USART_SENDA_Pos)
410 #define US_CR_USART_SENDA_1         (US_CR_USART_SENDA_1_Val       << US_CR_USART_SENDA_Pos)
411 #define US_CR_USART_RSTIT_Pos       13           /**< \brief (US_CR_USART) Reset Iterations */
412 #define US_CR_USART_RSTIT           (_U_(0x1) << US_CR_USART_RSTIT_Pos)
413 #define   US_CR_USART_RSTIT_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
414 #define   US_CR_USART_RSTIT_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */
415 #define US_CR_USART_RSTIT_0         (US_CR_USART_RSTIT_0_Val       << US_CR_USART_RSTIT_Pos)
416 #define US_CR_USART_RSTIT_1         (US_CR_USART_RSTIT_1_Val       << US_CR_USART_RSTIT_Pos)
417 #define US_CR_USART_RSTNACK_Pos     14           /**< \brief (US_CR_USART) Reset Non Acknowledge */
418 #define US_CR_USART_RSTNACK         (_U_(0x1) << US_CR_USART_RSTNACK_Pos)
419 #define   US_CR_USART_RSTNACK_0_Val       _U_(0x0)   /**< \brief (US_CR_USART) No effect */
420 #define   US_CR_USART_RSTNACK_1_Val       _U_(0x1)   /**< \brief (US_CR_USART) Resets NACK in CSR */
421 #define US_CR_USART_RSTNACK_0       (US_CR_USART_RSTNACK_0_Val     << US_CR_USART_RSTNACK_Pos)
422 #define US_CR_USART_RSTNACK_1       (US_CR_USART_RSTNACK_1_Val     << US_CR_USART_RSTNACK_Pos)
423 #define US_CR_USART_RETTO_Pos       15           /**< \brief (US_CR_USART) Rearm Time-out */
424 #define US_CR_USART_RETTO           (_U_(0x1) << US_CR_USART_RETTO_Pos)
425 #define   US_CR_USART_RETTO_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
426 #define   US_CR_USART_RETTO_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Restart Time-out */
427 #define US_CR_USART_RETTO_0         (US_CR_USART_RETTO_0_Val       << US_CR_USART_RETTO_Pos)
428 #define US_CR_USART_RETTO_1         (US_CR_USART_RETTO_1_Val       << US_CR_USART_RETTO_Pos)
429 #define US_CR_USART_DTREN_Pos       16           /**< \brief (US_CR_USART) Data Terminal Ready Enable */
430 #define US_CR_USART_DTREN           (_U_(0x1) << US_CR_USART_DTREN_Pos)
431 #define   US_CR_USART_DTREN_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
432 #define   US_CR_USART_DTREN_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Drives the pin DTR at 0 */
433 #define US_CR_USART_DTREN_0         (US_CR_USART_DTREN_0_Val       << US_CR_USART_DTREN_Pos)
434 #define US_CR_USART_DTREN_1         (US_CR_USART_DTREN_1_Val       << US_CR_USART_DTREN_Pos)
435 #define US_CR_USART_DTRDIS_Pos      17           /**< \brief (US_CR_USART) Data Terminal Ready Disable */
436 #define US_CR_USART_DTRDIS          (_U_(0x1) << US_CR_USART_DTRDIS_Pos)
437 #define   US_CR_USART_DTRDIS_0_Val        _U_(0x0)   /**< \brief (US_CR_USART) No effect */
438 #define   US_CR_USART_DTRDIS_1_Val        _U_(0x1)   /**< \brief (US_CR_USART) Drives the pin DTR to 1 */
439 #define US_CR_USART_DTRDIS_0        (US_CR_USART_DTRDIS_0_Val      << US_CR_USART_DTRDIS_Pos)
440 #define US_CR_USART_DTRDIS_1        (US_CR_USART_DTRDIS_1_Val      << US_CR_USART_DTRDIS_Pos)
441 #define US_CR_USART_RTSEN_Pos       18           /**< \brief (US_CR_USART) Request to Send Enable */
442 #define US_CR_USART_RTSEN           (_U_(0x1) << US_CR_USART_RTSEN_Pos)
443 #define   US_CR_USART_RTSEN_0_Val         _U_(0x0)   /**< \brief (US_CR_USART) No effect */
444 #define   US_CR_USART_RTSEN_1_Val         _U_(0x1)   /**< \brief (US_CR_USART) Drives the pin RTS to 0 */
445 #define US_CR_USART_RTSEN_0         (US_CR_USART_RTSEN_0_Val       << US_CR_USART_RTSEN_Pos)
446 #define US_CR_USART_RTSEN_1         (US_CR_USART_RTSEN_1_Val       << US_CR_USART_RTSEN_Pos)
447 #define US_CR_USART_RTSDIS_Pos      19           /**< \brief (US_CR_USART) Request to Send Disable */
448 #define US_CR_USART_RTSDIS          (_U_(0x1) << US_CR_USART_RTSDIS_Pos)
449 #define   US_CR_USART_RTSDIS_0_Val        _U_(0x0)   /**< \brief (US_CR_USART) No effect */
450 #define   US_CR_USART_RTSDIS_1_Val        _U_(0x1)   /**< \brief (US_CR_USART) Drives the pin RTS to 1 */
451 #define US_CR_USART_RTSDIS_0        (US_CR_USART_RTSDIS_0_Val      << US_CR_USART_RTSDIS_Pos)
452 #define US_CR_USART_RTSDIS_1        (US_CR_USART_RTSDIS_1_Val      << US_CR_USART_RTSDIS_Pos)
453 #define US_CR_USART_MASK            _U_(0x000FFFFC) /**< \brief (US_CR_USART) MASK Register */
454 
455 // Any mode
456 #define US_CR_RSTRX_Pos             2            /**< \brief (US_CR) Reset Receiver */
457 #define US_CR_RSTRX                 (_U_(0x1) << US_CR_RSTRX_Pos)
458 #define   US_CR_RSTRX_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
459 #define   US_CR_RSTRX_1_Val               _U_(0x1)   /**< \brief (US_CR) Resets the receiver */
460 #define US_CR_RSTRX_0               (US_CR_RSTRX_0_Val             << US_CR_RSTRX_Pos)
461 #define US_CR_RSTRX_1               (US_CR_RSTRX_1_Val             << US_CR_RSTRX_Pos)
462 #define US_CR_RSTTX_Pos             3            /**< \brief (US_CR) Reset Transmitter */
463 #define US_CR_RSTTX                 (_U_(0x1) << US_CR_RSTTX_Pos)
464 #define   US_CR_RSTTX_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
465 #define   US_CR_RSTTX_1_Val               _U_(0x1)   /**< \brief (US_CR) Resets the transmitter */
466 #define US_CR_RSTTX_0               (US_CR_RSTTX_0_Val             << US_CR_RSTTX_Pos)
467 #define US_CR_RSTTX_1               (US_CR_RSTTX_1_Val             << US_CR_RSTTX_Pos)
468 #define US_CR_RXEN_Pos              4            /**< \brief (US_CR) Receiver Enable */
469 #define US_CR_RXEN                  (_U_(0x1) << US_CR_RXEN_Pos)
470 #define   US_CR_RXEN_0_Val                _U_(0x0)   /**< \brief (US_CR) No effect */
471 #define   US_CR_RXEN_1_Val                _U_(0x1)   /**< \brief (US_CR) Enables the receiver, if RXDIS is 0 */
472 #define US_CR_RXEN_0                (US_CR_RXEN_0_Val              << US_CR_RXEN_Pos)
473 #define US_CR_RXEN_1                (US_CR_RXEN_1_Val              << US_CR_RXEN_Pos)
474 #define US_CR_RXDIS_Pos             5            /**< \brief (US_CR) Receiver Disable */
475 #define US_CR_RXDIS                 (_U_(0x1) << US_CR_RXDIS_Pos)
476 #define   US_CR_RXDIS_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
477 #define   US_CR_RXDIS_1_Val               _U_(0x1)   /**< \brief (US_CR) Disables the receiver */
478 #define US_CR_RXDIS_0               (US_CR_RXDIS_0_Val             << US_CR_RXDIS_Pos)
479 #define US_CR_RXDIS_1               (US_CR_RXDIS_1_Val             << US_CR_RXDIS_Pos)
480 #define US_CR_TXEN_Pos              6            /**< \brief (US_CR) Transmitter Enable */
481 #define US_CR_TXEN                  (_U_(0x1) << US_CR_TXEN_Pos)
482 #define   US_CR_TXEN_0_Val                _U_(0x0)   /**< \brief (US_CR) No effect */
483 #define   US_CR_TXEN_1_Val                _U_(0x1)   /**< \brief (US_CR) Enables the transmitter if TXDIS is 0 */
484 #define US_CR_TXEN_0                (US_CR_TXEN_0_Val              << US_CR_TXEN_Pos)
485 #define US_CR_TXEN_1                (US_CR_TXEN_1_Val              << US_CR_TXEN_Pos)
486 #define US_CR_TXDIS_Pos             7            /**< \brief (US_CR) Transmitter Disable */
487 #define US_CR_TXDIS                 (_U_(0x1) << US_CR_TXDIS_Pos)
488 #define   US_CR_TXDIS_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
489 #define   US_CR_TXDIS_1_Val               _U_(0x1)   /**< \brief (US_CR) Disables the transmitter */
490 #define US_CR_TXDIS_0               (US_CR_TXDIS_0_Val             << US_CR_TXDIS_Pos)
491 #define US_CR_TXDIS_1               (US_CR_TXDIS_1_Val             << US_CR_TXDIS_Pos)
492 #define US_CR_RSTSTA_Pos            8            /**< \brief (US_CR) Reset Status Bits */
493 #define US_CR_RSTSTA                (_U_(0x1) << US_CR_RSTSTA_Pos)
494 #define   US_CR_RSTSTA_0_Val              _U_(0x0)   /**< \brief (US_CR) No effect */
495 #define   US_CR_RSTSTA_1_Val              _U_(0x1)   /**< \brief (US_CR) Resets the status bits PARE, FRAME, OVRE and RXBRK in the CSR */
496 #define US_CR_RSTSTA_0              (US_CR_RSTSTA_0_Val            << US_CR_RSTSTA_Pos)
497 #define US_CR_RSTSTA_1              (US_CR_RSTSTA_1_Val            << US_CR_RSTSTA_Pos)
498 #define US_CR_STTBRK_Pos            9            /**< \brief (US_CR) Start Break */
499 #define US_CR_STTBRK                (_U_(0x1) << US_CR_STTBRK_Pos)
500 #define   US_CR_STTBRK_0_Val              _U_(0x0)   /**< \brief (US_CR) No effect */
501 #define   US_CR_STTBRK_1_Val              _U_(0x1)   /**< \brief (US_CR) Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted */
502 #define US_CR_STTBRK_0              (US_CR_STTBRK_0_Val            << US_CR_STTBRK_Pos)
503 #define US_CR_STTBRK_1              (US_CR_STTBRK_1_Val            << US_CR_STTBRK_Pos)
504 #define US_CR_STPBRK_Pos            10           /**< \brief (US_CR) Stop Break */
505 #define US_CR_STPBRK                (_U_(0x1) << US_CR_STPBRK_Pos)
506 #define   US_CR_STPBRK_0_Val              _U_(0x0)   /**< \brief (US_CR) No effect */
507 #define   US_CR_STPBRK_1_Val              _U_(0x1)   /**< \brief (US_CR) Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods.No effect if no break is being transmitted */
508 #define US_CR_STPBRK_0              (US_CR_STPBRK_0_Val            << US_CR_STPBRK_Pos)
509 #define US_CR_STPBRK_1              (US_CR_STPBRK_1_Val            << US_CR_STPBRK_Pos)
510 #define US_CR_STTTO_Pos             11           /**< \brief (US_CR) Start Time-out */
511 #define US_CR_STTTO                 (_U_(0x1) << US_CR_STTTO_Pos)
512 #define   US_CR_STTTO_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
513 #define   US_CR_STTTO_1_Val               _U_(0x1)   /**< \brief (US_CR) Starts waiting for a character before clocking the time-out counter */
514 #define US_CR_STTTO_0               (US_CR_STTTO_0_Val             << US_CR_STTTO_Pos)
515 #define US_CR_STTTO_1               (US_CR_STTTO_1_Val             << US_CR_STTTO_Pos)
516 #define US_CR_SENDA_Pos             12           /**< \brief (US_CR) Send Address */
517 #define US_CR_SENDA                 (_U_(0x1) << US_CR_SENDA_Pos)
518 #define   US_CR_SENDA_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
519 #define   US_CR_SENDA_1_Val               _U_(0x1)   /**< \brief (US_CR) In Multi-drop Mode only, the next character written to the THR is sent with the address bit set */
520 #define US_CR_SENDA_0               (US_CR_SENDA_0_Val             << US_CR_SENDA_Pos)
521 #define US_CR_SENDA_1               (US_CR_SENDA_1_Val             << US_CR_SENDA_Pos)
522 #define US_CR_RSTIT_Pos             13           /**< \brief (US_CR) Reset Iterations */
523 #define US_CR_RSTIT                 (_U_(0x1) << US_CR_RSTIT_Pos)
524 #define   US_CR_RSTIT_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
525 #define   US_CR_RSTIT_1_Val               _U_(0x1)   /**< \brief (US_CR) Resets ITERATION in CSR. No effect if the ISO7816 is not enabled */
526 #define US_CR_RSTIT_0               (US_CR_RSTIT_0_Val             << US_CR_RSTIT_Pos)
527 #define US_CR_RSTIT_1               (US_CR_RSTIT_1_Val             << US_CR_RSTIT_Pos)
528 #define US_CR_RSTNACK_Pos           14           /**< \brief (US_CR) Reset Non Acknowledge */
529 #define US_CR_RSTNACK               (_U_(0x1) << US_CR_RSTNACK_Pos)
530 #define   US_CR_RSTNACK_0_Val             _U_(0x0)   /**< \brief (US_CR) No effect */
531 #define   US_CR_RSTNACK_1_Val             _U_(0x1)   /**< \brief (US_CR) Resets NACK in CSR */
532 #define US_CR_RSTNACK_0             (US_CR_RSTNACK_0_Val           << US_CR_RSTNACK_Pos)
533 #define US_CR_RSTNACK_1             (US_CR_RSTNACK_1_Val           << US_CR_RSTNACK_Pos)
534 #define US_CR_RETTO_Pos             15           /**< \brief (US_CR) Rearm Time-out */
535 #define US_CR_RETTO                 (_U_(0x1) << US_CR_RETTO_Pos)
536 #define   US_CR_RETTO_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
537 #define   US_CR_RETTO_1_Val               _U_(0x1)   /**< \brief (US_CR) Restart Time-out */
538 #define US_CR_RETTO_0               (US_CR_RETTO_0_Val             << US_CR_RETTO_Pos)
539 #define US_CR_RETTO_1               (US_CR_RETTO_1_Val             << US_CR_RETTO_Pos)
540 #define US_CR_DTREN_Pos             16           /**< \brief (US_CR) Data Terminal Ready Enable */
541 #define US_CR_DTREN                 (_U_(0x1) << US_CR_DTREN_Pos)
542 #define   US_CR_DTREN_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
543 #define   US_CR_DTREN_1_Val               _U_(0x1)   /**< \brief (US_CR) Drives the pin DTR at 0 */
544 #define US_CR_DTREN_0               (US_CR_DTREN_0_Val             << US_CR_DTREN_Pos)
545 #define US_CR_DTREN_1               (US_CR_DTREN_1_Val             << US_CR_DTREN_Pos)
546 #define US_CR_DTRDIS_Pos            17           /**< \brief (US_CR) Data Terminal Ready Disable */
547 #define US_CR_DTRDIS                (_U_(0x1) << US_CR_DTRDIS_Pos)
548 #define   US_CR_DTRDIS_0_Val              _U_(0x0)   /**< \brief (US_CR) No effect */
549 #define   US_CR_DTRDIS_1_Val              _U_(0x1)   /**< \brief (US_CR) Drives the pin DTR to 1 */
550 #define US_CR_DTRDIS_0              (US_CR_DTRDIS_0_Val            << US_CR_DTRDIS_Pos)
551 #define US_CR_DTRDIS_1              (US_CR_DTRDIS_1_Val            << US_CR_DTRDIS_Pos)
552 #define US_CR_RTSEN_Pos             18           /**< \brief (US_CR) Request to Send Enable */
553 #define US_CR_RTSEN                 (_U_(0x1) << US_CR_RTSEN_Pos)
554 #define   US_CR_RTSEN_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
555 #define   US_CR_RTSEN_1_Val               _U_(0x1)   /**< \brief (US_CR) Drives the pin RTS to 0 */
556 #define US_CR_RTSEN_0               (US_CR_RTSEN_0_Val             << US_CR_RTSEN_Pos)
557 #define US_CR_RTSEN_1               (US_CR_RTSEN_1_Val             << US_CR_RTSEN_Pos)
558 #define US_CR_FCS_Pos               18           /**< \brief (US_CR) Force SPI Chip Select */
559 #define US_CR_FCS                   (_U_(0x1) << US_CR_FCS_Pos)
560 #define   US_CR_FCS_0_Val                 _U_(0x0)   /**< \brief (US_CR) No effect */
561 #define   US_CR_FCS_1_Val                 _U_(0x1)   /**< \brief (US_CR) Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer) */
562 #define US_CR_FCS_0                 (US_CR_FCS_0_Val               << US_CR_FCS_Pos)
563 #define US_CR_FCS_1                 (US_CR_FCS_1_Val               << US_CR_FCS_Pos)
564 #define US_CR_RTSEN_Pos             18           /**< \brief (US_CR) Request to Send Enable */
565 #define US_CR_RTSEN                 (_U_(0x1) << US_CR_RTSEN_Pos)
566 #define   US_CR_RTSEN_0_Val               _U_(0x0)   /**< \brief (US_CR) No effect */
567 #define   US_CR_RTSEN_1_Val               _U_(0x1)   /**< \brief (US_CR) Drives the pin RTS to 0 */
568 #define US_CR_RTSEN_0               (US_CR_RTSEN_0_Val             << US_CR_RTSEN_Pos)
569 #define US_CR_RTSEN_1               (US_CR_RTSEN_1_Val             << US_CR_RTSEN_Pos)
570 #define US_CR_RTSDIS_Pos            19           /**< \brief (US_CR) Request to Send Disable */
571 #define US_CR_RTSDIS                (_U_(0x1) << US_CR_RTSDIS_Pos)
572 #define   US_CR_RTSDIS_0_Val              _U_(0x0)   /**< \brief (US_CR) No effect */
573 #define   US_CR_RTSDIS_1_Val              _U_(0x1)   /**< \brief (US_CR) Drives the pin RTS to 1 */
574 #define US_CR_RTSDIS_0              (US_CR_RTSDIS_0_Val            << US_CR_RTSDIS_Pos)
575 #define US_CR_RTSDIS_1              (US_CR_RTSDIS_1_Val            << US_CR_RTSDIS_Pos)
576 #define US_CR_RCS_Pos               19           /**< \brief (US_CR) Release SPI Chip Select */
577 #define US_CR_RCS                   (_U_(0x1) << US_CR_RCS_Pos)
578 #define   US_CR_RCS_0_Val                 _U_(0x0)   /**< \brief (US_CR) No effect */
579 #define   US_CR_RCS_1_Val                 _U_(0x1)   /**< \brief (US_CR) Releases the Slave Select Line NSS (RTS pin) */
580 #define US_CR_RCS_0                 (US_CR_RCS_0_Val               << US_CR_RCS_Pos)
581 #define US_CR_RCS_1                 (US_CR_RCS_1_Val               << US_CR_RCS_Pos)
582 #define US_CR_RTSDIS_Pos            19           /**< \brief (US_CR) Request to Send Disable */
583 #define US_CR_RTSDIS                (_U_(0x1) << US_CR_RTSDIS_Pos)
584 #define   US_CR_RTSDIS_0_Val              _U_(0x0)   /**< \brief (US_CR) No effect */
585 #define   US_CR_RTSDIS_1_Val              _U_(0x1)   /**< \brief (US_CR) Drives the pin RTS to 1 */
586 #define US_CR_RTSDIS_0              (US_CR_RTSDIS_0_Val            << US_CR_RTSDIS_Pos)
587 #define US_CR_RTSDIS_1              (US_CR_RTSDIS_1_Val            << US_CR_RTSDIS_Pos)
588 #define US_CR_LINABT_Pos            20           /**< \brief (US_CR) Abort the current LIN transmission */
589 #define US_CR_LINABT                (_U_(0x1) << US_CR_LINABT_Pos)
590 #define US_CR_LINWKUP_Pos           21           /**< \brief (US_CR) Sends a wakeup signal on the LIN bus */
591 #define US_CR_LINWKUP               (_U_(0x1) << US_CR_LINWKUP_Pos)
592 #define US_CR_MASK                  _U_(0x003FFFFC) /**< \brief (US_CR) MASK Register */
593 
594 /* -------- US_MR : (USART Offset: 0x04) (R/W 32) Mode Register -------- */
595 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
596 typedef union {
597   struct { // SPI mode
598     uint32_t MODE:4;           /*!< bit:  0.. 3  Usart Mode                         */
599     uint32_t USCLKS:2;         /*!< bit:  4.. 5  Clock Selection                    */
600     uint32_t CHRL:2;           /*!< bit:  6.. 7  Character Length.                  */
601     uint32_t CPHA:1;           /*!< bit:      8  SPI CLock Phase                    */
602     uint32_t PAR:3;            /*!< bit:  9..11  Parity Type                        */
603     uint32_t NBSTOP:2;         /*!< bit: 12..13  Number of Stop Bits                */
604     uint32_t CHMODE:2;         /*!< bit: 14..15  Channel Mode                       */
605     uint32_t CPOL:1;           /*!< bit:     16  SPI Clock Polarity                 */
606     uint32_t MODE9:1;          /*!< bit:     17  9-bit Character Length             */
607     uint32_t CLKO:1;           /*!< bit:     18  Clock Output Select                */
608     uint32_t OVER:1;           /*!< bit:     19  Oversampling Mode                  */
609     uint32_t INACK:1;          /*!< bit:     20  Inhibit Non Acknowledge            */
610     uint32_t DSNACK:1;         /*!< bit:     21  Disable Successive NACK            */
611     uint32_t :1;               /*!< bit:     22  Reserved                           */
612     uint32_t INVDATA:1;        /*!< bit:     23  Inverted data                      */
613     uint32_t MAX_ITERATION:3;  /*!< bit: 24..26  Max interation                     */
614     uint32_t :1;               /*!< bit:     27  Reserved                           */
615     uint32_t FILTER:1;         /*!< bit:     28  Infrared Receive Line Filter       */
616     uint32_t :3;               /*!< bit: 29..31  Reserved                           */
617   } SPI;                       /*!< Structure used for SPI                          */
618   struct { // USART mode
619     uint32_t MODE:4;           /*!< bit:  0.. 3  Usart Mode                         */
620     uint32_t USCLKS:2;         /*!< bit:  4.. 5  Clock Selection                    */
621     uint32_t CHRL:2;           /*!< bit:  6.. 7  Character Length.                  */
622     uint32_t SYNC:1;           /*!< bit:      8  Synchronous Mode Select            */
623     uint32_t PAR:3;            /*!< bit:  9..11  Parity Type                        */
624     uint32_t NBSTOP:2;         /*!< bit: 12..13  Number of Stop Bits                */
625     uint32_t CHMODE:2;         /*!< bit: 14..15  Channel Mode                       */
626     uint32_t MSBF:1;           /*!< bit:     16  Bit Order                          */
627     uint32_t MODE9:1;          /*!< bit:     17  9-bit Character Length             */
628     uint32_t CLKO:1;           /*!< bit:     18  Clock Output Select                */
629     uint32_t OVER:1;           /*!< bit:     19  Oversampling Mode                  */
630     uint32_t INACK:1;          /*!< bit:     20  Inhibit Non Acknowledge            */
631     uint32_t DSNACK:1;         /*!< bit:     21  Disable Successive NACK            */
632     uint32_t VAR_SYNC:1;       /*!< bit:     22  Variable synchronization of command/data sync Start Frame Delimiter */
633     uint32_t INVDATA:1;        /*!< bit:     23  Inverted data                      */
634     uint32_t MAX_ITERATION:3;  /*!< bit: 24..26  Max interation                     */
635     uint32_t :1;               /*!< bit:     27  Reserved                           */
636     uint32_t FILTER:1;         /*!< bit:     28  Infrared Receive Line Filter       */
637     uint32_t MAN:1;            /*!< bit:     29  Manchester Encoder/Decoder Enable  */
638     uint32_t MODSYNC:1;        /*!< bit:     30  Manchester Synchronization Mode    */
639     uint32_t ONEBIT:1;         /*!< bit:     31  Start Frame Delimiter selector     */
640   } USART;                     /*!< Structure used for USART                        */
641   uint32_t reg;                /*!< Type      used for register access              */
642 } US_MR_Type;
643 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
644 
645 #define US_MR_OFFSET                0x04         /**< \brief (US_MR offset) Mode Register */
646 #define US_MR_RESETVALUE            _U_(0x00000000); /**< \brief (US_MR reset_value) Mode Register */
647 
648 // SPI mode
649 #define US_MR_SPI_MODE_Pos          0            /**< \brief (US_MR_SPI) Usart Mode */
650 #define US_MR_SPI_MODE_Msk          (_U_(0xF) << US_MR_SPI_MODE_Pos)
651 #define US_MR_SPI_MODE(value)       (US_MR_SPI_MODE_Msk & ((value) << US_MR_SPI_MODE_Pos))
652 #define   US_MR_SPI_MODE_NORMAL_Val       _U_(0x0)   /**< \brief (US_MR_SPI) Normal */
653 #define   US_MR_SPI_MODE_RS485_Val        _U_(0x1)   /**< \brief (US_MR_SPI) RS485 */
654 #define   US_MR_SPI_MODE_HARDWARE_Val     _U_(0x2)   /**< \brief (US_MR_SPI) Hardware Handshaking */
655 #define   US_MR_SPI_MODE_MODEM_Val        _U_(0x3)   /**< \brief (US_MR_SPI) Modem */
656 #define   US_MR_SPI_MODE_ISO7816_T0_Val   _U_(0x4)   /**< \brief (US_MR_SPI) IS07816 Protocol: T = 0 */
657 #define   US_MR_SPI_MODE_ISO7816_T1_Val   _U_(0x6)   /**< \brief (US_MR_SPI) IS07816 Protocol: T = 1 */
658 #define   US_MR_SPI_MODE_IRDA_Val         _U_(0x8)   /**< \brief (US_MR_SPI) IrDA */
659 #define   US_MR_SPI_MODE_LIN_MASTER_Val   _U_(0xA)   /**< \brief (US_MR_SPI) LIN Master */
660 #define   US_MR_SPI_MODE_LIN_SLAVE_Val    _U_(0xB)   /**< \brief (US_MR_SPI) LIN Slave */
661 #define   US_MR_SPI_MODE_SPI_MASTER_Val   _U_(0xE)   /**< \brief (US_MR_SPI) SPI Master */
662 #define   US_MR_SPI_MODE_SPI_SLAVE_Val    _U_(0xF)   /**< \brief (US_MR_SPI) SPI Slave */
663 #define US_MR_SPI_MODE_NORMAL       (US_MR_SPI_MODE_NORMAL_Val     << US_MR_SPI_MODE_Pos)
664 #define US_MR_SPI_MODE_RS485        (US_MR_SPI_MODE_RS485_Val      << US_MR_SPI_MODE_Pos)
665 #define US_MR_SPI_MODE_HARDWARE     (US_MR_SPI_MODE_HARDWARE_Val   << US_MR_SPI_MODE_Pos)
666 #define US_MR_SPI_MODE_MODEM        (US_MR_SPI_MODE_MODEM_Val      << US_MR_SPI_MODE_Pos)
667 #define US_MR_SPI_MODE_ISO7816_T0   (US_MR_SPI_MODE_ISO7816_T0_Val << US_MR_SPI_MODE_Pos)
668 #define US_MR_SPI_MODE_ISO7816_T1   (US_MR_SPI_MODE_ISO7816_T1_Val << US_MR_SPI_MODE_Pos)
669 #define US_MR_SPI_MODE_IRDA         (US_MR_SPI_MODE_IRDA_Val       << US_MR_SPI_MODE_Pos)
670 #define US_MR_SPI_MODE_LIN_MASTER   (US_MR_SPI_MODE_LIN_MASTER_Val << US_MR_SPI_MODE_Pos)
671 #define US_MR_SPI_MODE_LIN_SLAVE    (US_MR_SPI_MODE_LIN_SLAVE_Val  << US_MR_SPI_MODE_Pos)
672 #define US_MR_SPI_MODE_SPI_MASTER   (US_MR_SPI_MODE_SPI_MASTER_Val << US_MR_SPI_MODE_Pos)
673 #define US_MR_SPI_MODE_SPI_SLAVE    (US_MR_SPI_MODE_SPI_SLAVE_Val  << US_MR_SPI_MODE_Pos)
674 #define US_MR_SPI_USCLKS_Pos        4            /**< \brief (US_MR_SPI) Clock Selection */
675 #define US_MR_SPI_USCLKS_Msk        (_U_(0x3) << US_MR_SPI_USCLKS_Pos)
676 #define US_MR_SPI_USCLKS(value)     (US_MR_SPI_USCLKS_Msk & ((value) << US_MR_SPI_USCLKS_Pos))
677 #define   US_MR_SPI_USCLKS_MCK_Val        _U_(0x0)   /**< \brief (US_MR_SPI) MCK */
678 #define   US_MR_SPI_USCLKS_MCK_DIV_Val    _U_(0x1)   /**< \brief (US_MR_SPI) MCK / DIV */
679 #define   US_MR_SPI_USCLKS_2_Val          _U_(0x2)   /**< \brief (US_MR_SPI) Reserved */
680 #define   US_MR_SPI_USCLKS_SCK_Val        _U_(0x3)   /**< \brief (US_MR_SPI) SCK */
681 #define US_MR_SPI_USCLKS_MCK        (US_MR_SPI_USCLKS_MCK_Val      << US_MR_SPI_USCLKS_Pos)
682 #define US_MR_SPI_USCLKS_MCK_DIV    (US_MR_SPI_USCLKS_MCK_DIV_Val  << US_MR_SPI_USCLKS_Pos)
683 #define US_MR_SPI_USCLKS_2          (US_MR_SPI_USCLKS_2_Val        << US_MR_SPI_USCLKS_Pos)
684 #define US_MR_SPI_USCLKS_SCK        (US_MR_SPI_USCLKS_SCK_Val      << US_MR_SPI_USCLKS_Pos)
685 #define US_MR_SPI_CHRL_Pos          6            /**< \brief (US_MR_SPI) Character Length. */
686 #define US_MR_SPI_CHRL_Msk          (_U_(0x3) << US_MR_SPI_CHRL_Pos)
687 #define US_MR_SPI_CHRL(value)       (US_MR_SPI_CHRL_Msk & ((value) << US_MR_SPI_CHRL_Pos))
688 #define   US_MR_SPI_CHRL_5_Val            _U_(0x0)   /**< \brief (US_MR_SPI) 5 bits */
689 #define   US_MR_SPI_CHRL_6_Val            _U_(0x1)   /**< \brief (US_MR_SPI) 6 bits */
690 #define   US_MR_SPI_CHRL_7_Val            _U_(0x2)   /**< \brief (US_MR_SPI) 7 bits */
691 #define   US_MR_SPI_CHRL_8_Val            _U_(0x3)   /**< \brief (US_MR_SPI) 8 bits */
692 #define US_MR_SPI_CHRL_5            (US_MR_SPI_CHRL_5_Val          << US_MR_SPI_CHRL_Pos)
693 #define US_MR_SPI_CHRL_6            (US_MR_SPI_CHRL_6_Val          << US_MR_SPI_CHRL_Pos)
694 #define US_MR_SPI_CHRL_7            (US_MR_SPI_CHRL_7_Val          << US_MR_SPI_CHRL_Pos)
695 #define US_MR_SPI_CHRL_8            (US_MR_SPI_CHRL_8_Val          << US_MR_SPI_CHRL_Pos)
696 #define US_MR_SPI_CPHA_Pos          8            /**< \brief (US_MR_SPI) SPI CLock Phase */
697 #define US_MR_SPI_CPHA              (_U_(0x1) << US_MR_SPI_CPHA_Pos)
698 #define   US_MR_SPI_CPHA_0_Val            _U_(0x0)   /**< \brief (US_MR_SPI) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK */
699 #define   US_MR_SPI_CPHA_1_Val            _U_(0x1)   /**< \brief (US_MR_SPI) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK */
700 #define US_MR_SPI_CPHA_0            (US_MR_SPI_CPHA_0_Val          << US_MR_SPI_CPHA_Pos)
701 #define US_MR_SPI_CPHA_1            (US_MR_SPI_CPHA_1_Val          << US_MR_SPI_CPHA_Pos)
702 #define US_MR_SPI_PAR_Pos           9            /**< \brief (US_MR_SPI) Parity Type */
703 #define US_MR_SPI_PAR_Msk           (_U_(0x7) << US_MR_SPI_PAR_Pos)
704 #define US_MR_SPI_PAR(value)        (US_MR_SPI_PAR_Msk & ((value) << US_MR_SPI_PAR_Pos))
705 #define   US_MR_SPI_PAR_EVEN_Val          _U_(0x0)   /**< \brief (US_MR_SPI) Even parity */
706 #define   US_MR_SPI_PAR_ODD_Val           _U_(0x1)   /**< \brief (US_MR_SPI) Odd parity */
707 #define   US_MR_SPI_PAR_SPACE_Val         _U_(0x2)   /**< \brief (US_MR_SPI) Parity forced to 0 (Space) */
708 #define   US_MR_SPI_PAR_MARK_Val          _U_(0x3)   /**< \brief (US_MR_SPI) Parity forced to 1 (Mark) */
709 #define   US_MR_SPI_PAR_NONE_Val          _U_(0x4)   /**< \brief (US_MR_SPI) No Parity */
710 #define   US_MR_SPI_PAR_5_Val             _U_(0x5)   /**< \brief (US_MR_SPI) No Parity */
711 #define   US_MR_SPI_PAR_MULTI_Val         _U_(0x6)   /**< \brief (US_MR_SPI) Multi-drop mode */
712 #define   US_MR_SPI_PAR_7_Val             _U_(0x7)   /**< \brief (US_MR_SPI) Multi-drop mode */
713 #define US_MR_SPI_PAR_EVEN          (US_MR_SPI_PAR_EVEN_Val        << US_MR_SPI_PAR_Pos)
714 #define US_MR_SPI_PAR_ODD           (US_MR_SPI_PAR_ODD_Val         << US_MR_SPI_PAR_Pos)
715 #define US_MR_SPI_PAR_SPACE         (US_MR_SPI_PAR_SPACE_Val       << US_MR_SPI_PAR_Pos)
716 #define US_MR_SPI_PAR_MARK          (US_MR_SPI_PAR_MARK_Val        << US_MR_SPI_PAR_Pos)
717 #define US_MR_SPI_PAR_NONE          (US_MR_SPI_PAR_NONE_Val        << US_MR_SPI_PAR_Pos)
718 #define US_MR_SPI_PAR_5             (US_MR_SPI_PAR_5_Val           << US_MR_SPI_PAR_Pos)
719 #define US_MR_SPI_PAR_MULTI         (US_MR_SPI_PAR_MULTI_Val       << US_MR_SPI_PAR_Pos)
720 #define US_MR_SPI_PAR_7             (US_MR_SPI_PAR_7_Val           << US_MR_SPI_PAR_Pos)
721 #define US_MR_SPI_NBSTOP_Pos        12           /**< \brief (US_MR_SPI) Number of Stop Bits */
722 #define US_MR_SPI_NBSTOP_Msk        (_U_(0x3) << US_MR_SPI_NBSTOP_Pos)
723 #define US_MR_SPI_NBSTOP(value)     (US_MR_SPI_NBSTOP_Msk & ((value) << US_MR_SPI_NBSTOP_Pos))
724 #define   US_MR_SPI_NBSTOP_1_Val          _U_(0x0)   /**< \brief (US_MR_SPI) 1 stop bit */
725 #define   US_MR_SPI_NBSTOP_1_5_Val        _U_(0x1)   /**< \brief (US_MR_SPI) 1.5 stop bits (Only valid if SYNC=0) */
726 #define   US_MR_SPI_NBSTOP_2_Val          _U_(0x2)   /**< \brief (US_MR_SPI) 2 stop bits */
727 #define   US_MR_SPI_NBSTOP_3_Val          _U_(0x3)   /**< \brief (US_MR_SPI) Reserved */
728 #define US_MR_SPI_NBSTOP_1          (US_MR_SPI_NBSTOP_1_Val        << US_MR_SPI_NBSTOP_Pos)
729 #define US_MR_SPI_NBSTOP_1_5        (US_MR_SPI_NBSTOP_1_5_Val      << US_MR_SPI_NBSTOP_Pos)
730 #define US_MR_SPI_NBSTOP_2          (US_MR_SPI_NBSTOP_2_Val        << US_MR_SPI_NBSTOP_Pos)
731 #define US_MR_SPI_NBSTOP_3          (US_MR_SPI_NBSTOP_3_Val        << US_MR_SPI_NBSTOP_Pos)
732 #define US_MR_SPI_CHMODE_Pos        14           /**< \brief (US_MR_SPI) Channel Mode */
733 #define US_MR_SPI_CHMODE_Msk        (_U_(0x3) << US_MR_SPI_CHMODE_Pos)
734 #define US_MR_SPI_CHMODE(value)     (US_MR_SPI_CHMODE_Msk & ((value) << US_MR_SPI_CHMODE_Pos))
735 #define   US_MR_SPI_CHMODE_NORMAL_Val     _U_(0x0)   /**< \brief (US_MR_SPI) Normal Mode */
736 #define   US_MR_SPI_CHMODE_ECHO_Val       _U_(0x1)   /**< \brief (US_MR_SPI) Automatic Echo. Receiver input is connected to the TXD pin */
737 #define   US_MR_SPI_CHMODE_LOCAL_LOOP_Val _U_(0x2)   /**< \brief (US_MR_SPI) Local Loopback. Transmitter output is connected to the Receiver Input */
738 #define   US_MR_SPI_CHMODE_REMOTE_LOOP_Val _U_(0x3)   /**< \brief (US_MR_SPI) Remote Loopback. RXD pin is internally connected to the TXD pin */
739 #define US_MR_SPI_CHMODE_NORMAL     (US_MR_SPI_CHMODE_NORMAL_Val   << US_MR_SPI_CHMODE_Pos)
740 #define US_MR_SPI_CHMODE_ECHO       (US_MR_SPI_CHMODE_ECHO_Val     << US_MR_SPI_CHMODE_Pos)
741 #define US_MR_SPI_CHMODE_LOCAL_LOOP (US_MR_SPI_CHMODE_LOCAL_LOOP_Val << US_MR_SPI_CHMODE_Pos)
742 #define US_MR_SPI_CHMODE_REMOTE_LOOP (US_MR_SPI_CHMODE_REMOTE_LOOP_Val << US_MR_SPI_CHMODE_Pos)
743 #define US_MR_SPI_CPOL_Pos          16           /**< \brief (US_MR_SPI) SPI Clock Polarity */
744 #define US_MR_SPI_CPOL              (_U_(0x1) << US_MR_SPI_CPOL_Pos)
745 #define   US_MR_SPI_CPOL_ZERO_Val         _U_(0x0)   /**< \brief (US_MR_SPI) The inactive state value of SPCK is logic level zero */
746 #define   US_MR_SPI_CPOL_ONE_Val          _U_(0x1)   /**< \brief (US_MR_SPI) The inactive state value of SPCK is logic level one */
747 #define US_MR_SPI_CPOL_ZERO         (US_MR_SPI_CPOL_ZERO_Val       << US_MR_SPI_CPOL_Pos)
748 #define US_MR_SPI_CPOL_ONE          (US_MR_SPI_CPOL_ONE_Val        << US_MR_SPI_CPOL_Pos)
749 #define US_MR_SPI_MODE9_Pos         17           /**< \brief (US_MR_SPI) 9-bit Character Length */
750 #define US_MR_SPI_MODE9             (_U_(0x1) << US_MR_SPI_MODE9_Pos)
751 #define   US_MR_SPI_MODE9_0_Val           _U_(0x0)   /**< \brief (US_MR_SPI) CHRL defines character length */
752 #define   US_MR_SPI_MODE9_1_Val           _U_(0x1)   /**< \brief (US_MR_SPI) 9-bit character length */
753 #define US_MR_SPI_MODE9_0           (US_MR_SPI_MODE9_0_Val         << US_MR_SPI_MODE9_Pos)
754 #define US_MR_SPI_MODE9_1           (US_MR_SPI_MODE9_1_Val         << US_MR_SPI_MODE9_Pos)
755 #define US_MR_SPI_CLKO_Pos          18           /**< \brief (US_MR_SPI) Clock Output Select */
756 #define US_MR_SPI_CLKO              (_U_(0x1) << US_MR_SPI_CLKO_Pos)
757 #define   US_MR_SPI_CLKO_0_Val            _U_(0x0)   /**< \brief (US_MR_SPI) The USART does not drive the SCK pin */
758 #define   US_MR_SPI_CLKO_1_Val            _U_(0x1)   /**< \brief (US_MR_SPI) The USART drives the SCK pin if USCLKS does not select the external clock SCK */
759 #define US_MR_SPI_CLKO_0            (US_MR_SPI_CLKO_0_Val          << US_MR_SPI_CLKO_Pos)
760 #define US_MR_SPI_CLKO_1            (US_MR_SPI_CLKO_1_Val          << US_MR_SPI_CLKO_Pos)
761 #define US_MR_SPI_OVER_Pos          19           /**< \brief (US_MR_SPI) Oversampling Mode */
762 #define US_MR_SPI_OVER              (_U_(0x1) << US_MR_SPI_OVER_Pos)
763 #define   US_MR_SPI_OVER_X16_Val          _U_(0x0)   /**< \brief (US_MR_SPI) 16x Oversampling */
764 #define   US_MR_SPI_OVER_X8_Val           _U_(0x1)   /**< \brief (US_MR_SPI) 8x Oversampling */
765 #define US_MR_SPI_OVER_X16          (US_MR_SPI_OVER_X16_Val        << US_MR_SPI_OVER_Pos)
766 #define US_MR_SPI_OVER_X8           (US_MR_SPI_OVER_X8_Val         << US_MR_SPI_OVER_Pos)
767 #define US_MR_SPI_INACK_Pos         20           /**< \brief (US_MR_SPI) Inhibit Non Acknowledge */
768 #define US_MR_SPI_INACK             (_U_(0x1) << US_MR_SPI_INACK_Pos)
769 #define   US_MR_SPI_INACK_0_Val           _U_(0x0)   /**< \brief (US_MR_SPI) The NACK is generated */
770 #define   US_MR_SPI_INACK_1_Val           _U_(0x1)   /**< \brief (US_MR_SPI) The NACK is not generated */
771 #define US_MR_SPI_INACK_0           (US_MR_SPI_INACK_0_Val         << US_MR_SPI_INACK_Pos)
772 #define US_MR_SPI_INACK_1           (US_MR_SPI_INACK_1_Val         << US_MR_SPI_INACK_Pos)
773 #define US_MR_SPI_DSNACK_Pos        21           /**< \brief (US_MR_SPI) Disable Successive NACK */
774 #define US_MR_SPI_DSNACK            (_U_(0x1) << US_MR_SPI_DSNACK_Pos)
775 #define   US_MR_SPI_DSNACK_0_Val          _U_(0x0)   /**< \brief (US_MR_SPI) NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) */
776 #define   US_MR_SPI_DSNACK_1_Val          _U_(0x1)   /**< \brief (US_MR_SPI) Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted */
777 #define US_MR_SPI_DSNACK_0          (US_MR_SPI_DSNACK_0_Val        << US_MR_SPI_DSNACK_Pos)
778 #define US_MR_SPI_DSNACK_1          (US_MR_SPI_DSNACK_1_Val        << US_MR_SPI_DSNACK_Pos)
779 #define US_MR_SPI_INVDATA_Pos       23           /**< \brief (US_MR_SPI) Inverted data */
780 #define US_MR_SPI_INVDATA           (_U_(0x1) << US_MR_SPI_INVDATA_Pos)
781 #define US_MR_SPI_MAX_ITERATION_Pos 24           /**< \brief (US_MR_SPI) Max interation */
782 #define US_MR_SPI_MAX_ITERATION_Msk (_U_(0x7) << US_MR_SPI_MAX_ITERATION_Pos)
783 #define US_MR_SPI_MAX_ITERATION(value) (US_MR_SPI_MAX_ITERATION_Msk & ((value) << US_MR_SPI_MAX_ITERATION_Pos))
784 #define US_MR_SPI_FILTER_Pos        28           /**< \brief (US_MR_SPI) Infrared Receive Line Filter */
785 #define US_MR_SPI_FILTER            (_U_(0x1) << US_MR_SPI_FILTER_Pos)
786 #define   US_MR_SPI_FILTER_0_Val          _U_(0x0)   /**< \brief (US_MR_SPI) The USART does not filter the receive line */
787 #define   US_MR_SPI_FILTER_1_Val          _U_(0x1)   /**< \brief (US_MR_SPI) The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) */
788 #define US_MR_SPI_FILTER_0          (US_MR_SPI_FILTER_0_Val        << US_MR_SPI_FILTER_Pos)
789 #define US_MR_SPI_FILTER_1          (US_MR_SPI_FILTER_1_Val        << US_MR_SPI_FILTER_Pos)
790 #define US_MR_SPI_MASK              _U_(0x17BFFFFF) /**< \brief (US_MR_SPI) MASK Register */
791 
792 // USART mode
793 #define US_MR_USART_MODE_Pos        0            /**< \brief (US_MR_USART) Usart Mode */
794 #define US_MR_USART_MODE_Msk        (_U_(0xF) << US_MR_USART_MODE_Pos)
795 #define US_MR_USART_MODE(value)     (US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))
796 #define   US_MR_USART_MODE_NORMAL_Val     _U_(0x0)   /**< \brief (US_MR_USART) Normal */
797 #define   US_MR_USART_MODE_RS485_Val      _U_(0x1)   /**< \brief (US_MR_USART) RS485 */
798 #define   US_MR_USART_MODE_HARDWARE_Val   _U_(0x2)   /**< \brief (US_MR_USART) Hardware Handshaking */
799 #define   US_MR_USART_MODE_MODEM_Val      _U_(0x3)   /**< \brief (US_MR_USART) Modem */
800 #define   US_MR_USART_MODE_ISO7816_T0_Val _U_(0x4)   /**< \brief (US_MR_USART) IS07816 Protocol: T = 0 */
801 #define   US_MR_USART_MODE_ISO7816_T1_Val _U_(0x6)   /**< \brief (US_MR_USART) IS07816 Protocol: T = 1 */
802 #define   US_MR_USART_MODE_IRDA_Val       _U_(0x8)   /**< \brief (US_MR_USART) IrDA */
803 #define   US_MR_USART_MODE_LIN_MASTER_Val _U_(0xA)   /**< \brief (US_MR_USART) LIN Master */
804 #define   US_MR_USART_MODE_LIN_SLAVE_Val  _U_(0xB)   /**< \brief (US_MR_USART) LIN Slave */
805 #define   US_MR_USART_MODE_SPI_MASTER_Val _U_(0xE)   /**< \brief (US_MR_USART) SPI Master */
806 #define   US_MR_USART_MODE_SPI_SLAVE_Val  _U_(0xF)   /**< \brief (US_MR_USART) SPI Slave */
807 #define US_MR_USART_MODE_NORMAL     (US_MR_USART_MODE_NORMAL_Val   << US_MR_USART_MODE_Pos)
808 #define US_MR_USART_MODE_RS485      (US_MR_USART_MODE_RS485_Val    << US_MR_USART_MODE_Pos)
809 #define US_MR_USART_MODE_HARDWARE   (US_MR_USART_MODE_HARDWARE_Val << US_MR_USART_MODE_Pos)
810 #define US_MR_USART_MODE_MODEM      (US_MR_USART_MODE_MODEM_Val    << US_MR_USART_MODE_Pos)
811 #define US_MR_USART_MODE_ISO7816_T0 (US_MR_USART_MODE_ISO7816_T0_Val << US_MR_USART_MODE_Pos)
812 #define US_MR_USART_MODE_ISO7816_T1 (US_MR_USART_MODE_ISO7816_T1_Val << US_MR_USART_MODE_Pos)
813 #define US_MR_USART_MODE_IRDA       (US_MR_USART_MODE_IRDA_Val     << US_MR_USART_MODE_Pos)
814 #define US_MR_USART_MODE_LIN_MASTER (US_MR_USART_MODE_LIN_MASTER_Val << US_MR_USART_MODE_Pos)
815 #define US_MR_USART_MODE_LIN_SLAVE  (US_MR_USART_MODE_LIN_SLAVE_Val << US_MR_USART_MODE_Pos)
816 #define US_MR_USART_MODE_SPI_MASTER (US_MR_USART_MODE_SPI_MASTER_Val << US_MR_USART_MODE_Pos)
817 #define US_MR_USART_MODE_SPI_SLAVE  (US_MR_USART_MODE_SPI_SLAVE_Val << US_MR_USART_MODE_Pos)
818 #define US_MR_USART_USCLKS_Pos      4            /**< \brief (US_MR_USART) Clock Selection */
819 #define US_MR_USART_USCLKS_Msk      (_U_(0x3) << US_MR_USART_USCLKS_Pos)
820 #define US_MR_USART_USCLKS(value)   (US_MR_USART_USCLKS_Msk & ((value) << US_MR_USART_USCLKS_Pos))
821 #define   US_MR_USART_USCLKS_MCK_Val      _U_(0x0)   /**< \brief (US_MR_USART) MCK */
822 #define   US_MR_USART_USCLKS_MCK_DIV_Val  _U_(0x1)   /**< \brief (US_MR_USART) MCK / DIV */
823 #define   US_MR_USART_USCLKS_2_Val        _U_(0x2)   /**< \brief (US_MR_USART) Reserved */
824 #define   US_MR_USART_USCLKS_SCK_Val      _U_(0x3)   /**< \brief (US_MR_USART) SCK */
825 #define US_MR_USART_USCLKS_MCK      (US_MR_USART_USCLKS_MCK_Val    << US_MR_USART_USCLKS_Pos)
826 #define US_MR_USART_USCLKS_MCK_DIV  (US_MR_USART_USCLKS_MCK_DIV_Val << US_MR_USART_USCLKS_Pos)
827 #define US_MR_USART_USCLKS_2        (US_MR_USART_USCLKS_2_Val      << US_MR_USART_USCLKS_Pos)
828 #define US_MR_USART_USCLKS_SCK      (US_MR_USART_USCLKS_SCK_Val    << US_MR_USART_USCLKS_Pos)
829 #define US_MR_USART_CHRL_Pos        6            /**< \brief (US_MR_USART) Character Length. */
830 #define US_MR_USART_CHRL_Msk        (_U_(0x3) << US_MR_USART_CHRL_Pos)
831 #define US_MR_USART_CHRL(value)     (US_MR_USART_CHRL_Msk & ((value) << US_MR_USART_CHRL_Pos))
832 #define   US_MR_USART_CHRL_5_Val          _U_(0x0)   /**< \brief (US_MR_USART) 5 bits */
833 #define   US_MR_USART_CHRL_6_Val          _U_(0x1)   /**< \brief (US_MR_USART) 6 bits */
834 #define   US_MR_USART_CHRL_7_Val          _U_(0x2)   /**< \brief (US_MR_USART) 7 bits */
835 #define   US_MR_USART_CHRL_8_Val          _U_(0x3)   /**< \brief (US_MR_USART) 8 bits */
836 #define US_MR_USART_CHRL_5          (US_MR_USART_CHRL_5_Val        << US_MR_USART_CHRL_Pos)
837 #define US_MR_USART_CHRL_6          (US_MR_USART_CHRL_6_Val        << US_MR_USART_CHRL_Pos)
838 #define US_MR_USART_CHRL_7          (US_MR_USART_CHRL_7_Val        << US_MR_USART_CHRL_Pos)
839 #define US_MR_USART_CHRL_8          (US_MR_USART_CHRL_8_Val        << US_MR_USART_CHRL_Pos)
840 #define US_MR_USART_SYNC_Pos        8            /**< \brief (US_MR_USART) Synchronous Mode Select */
841 #define US_MR_USART_SYNC            (_U_(0x1) << US_MR_USART_SYNC_Pos)
842 #define   US_MR_USART_SYNC_0_Val          _U_(0x0)   /**< \brief (US_MR_USART) USART operates in Synchronous Mode */
843 #define   US_MR_USART_SYNC_1_Val          _U_(0x1)   /**< \brief (US_MR_USART) USART operates in Asynchronous Mode */
844 #define US_MR_USART_SYNC_0          (US_MR_USART_SYNC_0_Val        << US_MR_USART_SYNC_Pos)
845 #define US_MR_USART_SYNC_1          (US_MR_USART_SYNC_1_Val        << US_MR_USART_SYNC_Pos)
846 #define US_MR_USART_PAR_Pos         9            /**< \brief (US_MR_USART) Parity Type */
847 #define US_MR_USART_PAR_Msk         (_U_(0x7) << US_MR_USART_PAR_Pos)
848 #define US_MR_USART_PAR(value)      (US_MR_USART_PAR_Msk & ((value) << US_MR_USART_PAR_Pos))
849 #define   US_MR_USART_PAR_EVEN_Val        _U_(0x0)   /**< \brief (US_MR_USART) Even parity */
850 #define   US_MR_USART_PAR_ODD_Val         _U_(0x1)   /**< \brief (US_MR_USART) Odd parity */
851 #define   US_MR_USART_PAR_SPACE_Val       _U_(0x2)   /**< \brief (US_MR_USART) Parity forced to 0 (Space) */
852 #define   US_MR_USART_PAR_MARK_Val        _U_(0x3)   /**< \brief (US_MR_USART) Parity forced to 1 (Mark) */
853 #define   US_MR_USART_PAR_NONE_Val        _U_(0x4)   /**< \brief (US_MR_USART) No Parity */
854 #define   US_MR_USART_PAR_5_Val           _U_(0x5)   /**< \brief (US_MR_USART) No Parity */
855 #define   US_MR_USART_PAR_MULTI_Val       _U_(0x6)   /**< \brief (US_MR_USART) Multi-drop mode */
856 #define   US_MR_USART_PAR_7_Val           _U_(0x7)   /**< \brief (US_MR_USART) Multi-drop mode */
857 #define US_MR_USART_PAR_EVEN        (US_MR_USART_PAR_EVEN_Val      << US_MR_USART_PAR_Pos)
858 #define US_MR_USART_PAR_ODD         (US_MR_USART_PAR_ODD_Val       << US_MR_USART_PAR_Pos)
859 #define US_MR_USART_PAR_SPACE       (US_MR_USART_PAR_SPACE_Val     << US_MR_USART_PAR_Pos)
860 #define US_MR_USART_PAR_MARK        (US_MR_USART_PAR_MARK_Val      << US_MR_USART_PAR_Pos)
861 #define US_MR_USART_PAR_NONE        (US_MR_USART_PAR_NONE_Val      << US_MR_USART_PAR_Pos)
862 #define US_MR_USART_PAR_5           (US_MR_USART_PAR_5_Val         << US_MR_USART_PAR_Pos)
863 #define US_MR_USART_PAR_MULTI       (US_MR_USART_PAR_MULTI_Val     << US_MR_USART_PAR_Pos)
864 #define US_MR_USART_PAR_7           (US_MR_USART_PAR_7_Val         << US_MR_USART_PAR_Pos)
865 #define US_MR_USART_NBSTOP_Pos      12           /**< \brief (US_MR_USART) Number of Stop Bits */
866 #define US_MR_USART_NBSTOP_Msk      (_U_(0x3) << US_MR_USART_NBSTOP_Pos)
867 #define US_MR_USART_NBSTOP(value)   (US_MR_USART_NBSTOP_Msk & ((value) << US_MR_USART_NBSTOP_Pos))
868 #define   US_MR_USART_NBSTOP_1_Val        _U_(0x0)   /**< \brief (US_MR_USART) 1 stop bit */
869 #define   US_MR_USART_NBSTOP_1_5_Val      _U_(0x1)   /**< \brief (US_MR_USART) 1.5 stop bits (Only valid if SYNC=0) */
870 #define   US_MR_USART_NBSTOP_2_Val        _U_(0x2)   /**< \brief (US_MR_USART) 2 stop bits */
871 #define   US_MR_USART_NBSTOP_3_Val        _U_(0x3)   /**< \brief (US_MR_USART) Reserved */
872 #define US_MR_USART_NBSTOP_1        (US_MR_USART_NBSTOP_1_Val      << US_MR_USART_NBSTOP_Pos)
873 #define US_MR_USART_NBSTOP_1_5      (US_MR_USART_NBSTOP_1_5_Val    << US_MR_USART_NBSTOP_Pos)
874 #define US_MR_USART_NBSTOP_2        (US_MR_USART_NBSTOP_2_Val      << US_MR_USART_NBSTOP_Pos)
875 #define US_MR_USART_NBSTOP_3        (US_MR_USART_NBSTOP_3_Val      << US_MR_USART_NBSTOP_Pos)
876 #define US_MR_USART_CHMODE_Pos      14           /**< \brief (US_MR_USART) Channel Mode */
877 #define US_MR_USART_CHMODE_Msk      (_U_(0x3) << US_MR_USART_CHMODE_Pos)
878 #define US_MR_USART_CHMODE(value)   (US_MR_USART_CHMODE_Msk & ((value) << US_MR_USART_CHMODE_Pos))
879 #define   US_MR_USART_CHMODE_NORMAL_Val   _U_(0x0)   /**< \brief (US_MR_USART) Normal Mode */
880 #define   US_MR_USART_CHMODE_ECHO_Val     _U_(0x1)   /**< \brief (US_MR_USART) Automatic Echo. Receiver input is connected to the TXD pin */
881 #define   US_MR_USART_CHMODE_LOCAL_LOOP_Val _U_(0x2)   /**< \brief (US_MR_USART) Local Loopback. Transmitter output is connected to the Receiver Input */
882 #define   US_MR_USART_CHMODE_REMOTE_LOOP_Val _U_(0x3)   /**< \brief (US_MR_USART) Remote Loopback. RXD pin is internally connected to the TXD pin */
883 #define US_MR_USART_CHMODE_NORMAL   (US_MR_USART_CHMODE_NORMAL_Val << US_MR_USART_CHMODE_Pos)
884 #define US_MR_USART_CHMODE_ECHO     (US_MR_USART_CHMODE_ECHO_Val   << US_MR_USART_CHMODE_Pos)
885 #define US_MR_USART_CHMODE_LOCAL_LOOP (US_MR_USART_CHMODE_LOCAL_LOOP_Val << US_MR_USART_CHMODE_Pos)
886 #define US_MR_USART_CHMODE_REMOTE_LOOP (US_MR_USART_CHMODE_REMOTE_LOOP_Val << US_MR_USART_CHMODE_Pos)
887 #define US_MR_USART_MSBF_Pos        16           /**< \brief (US_MR_USART) Bit Order */
888 #define US_MR_USART_MSBF            (_U_(0x1) << US_MR_USART_MSBF_Pos)
889 #define   US_MR_USART_MSBF_LSBF_Val       _U_(0x0)   /**< \brief (US_MR_USART) Least Significant Bit first */
890 #define   US_MR_USART_MSBF_MSBF_Val       _U_(0x1)   /**< \brief (US_MR_USART) Most Significant Bit first */
891 #define US_MR_USART_MSBF_LSBF       (US_MR_USART_MSBF_LSBF_Val     << US_MR_USART_MSBF_Pos)
892 #define US_MR_USART_MSBF_MSBF       (US_MR_USART_MSBF_MSBF_Val     << US_MR_USART_MSBF_Pos)
893 #define US_MR_USART_MODE9_Pos       17           /**< \brief (US_MR_USART) 9-bit Character Length */
894 #define US_MR_USART_MODE9           (_U_(0x1) << US_MR_USART_MODE9_Pos)
895 #define   US_MR_USART_MODE9_0_Val         _U_(0x0)   /**< \brief (US_MR_USART) CHRL defines character length */
896 #define   US_MR_USART_MODE9_1_Val         _U_(0x1)   /**< \brief (US_MR_USART) 9-bit character length */
897 #define US_MR_USART_MODE9_0         (US_MR_USART_MODE9_0_Val       << US_MR_USART_MODE9_Pos)
898 #define US_MR_USART_MODE9_1         (US_MR_USART_MODE9_1_Val       << US_MR_USART_MODE9_Pos)
899 #define US_MR_USART_CLKO_Pos        18           /**< \brief (US_MR_USART) Clock Output Select */
900 #define US_MR_USART_CLKO            (_U_(0x1) << US_MR_USART_CLKO_Pos)
901 #define   US_MR_USART_CLKO_0_Val          _U_(0x0)   /**< \brief (US_MR_USART) The USART does not drive the SCK pin */
902 #define   US_MR_USART_CLKO_1_Val          _U_(0x1)   /**< \brief (US_MR_USART) The USART drives the SCK pin if USCLKS does not select the external clock SCK */
903 #define US_MR_USART_CLKO_0          (US_MR_USART_CLKO_0_Val        << US_MR_USART_CLKO_Pos)
904 #define US_MR_USART_CLKO_1          (US_MR_USART_CLKO_1_Val        << US_MR_USART_CLKO_Pos)
905 #define US_MR_USART_OVER_Pos        19           /**< \brief (US_MR_USART) Oversampling Mode */
906 #define US_MR_USART_OVER            (_U_(0x1) << US_MR_USART_OVER_Pos)
907 #define   US_MR_USART_OVER_X16_Val        _U_(0x0)   /**< \brief (US_MR_USART) 16x Oversampling */
908 #define   US_MR_USART_OVER_X8_Val         _U_(0x1)   /**< \brief (US_MR_USART) 8x Oversampling */
909 #define US_MR_USART_OVER_X16        (US_MR_USART_OVER_X16_Val      << US_MR_USART_OVER_Pos)
910 #define US_MR_USART_OVER_X8         (US_MR_USART_OVER_X8_Val       << US_MR_USART_OVER_Pos)
911 #define US_MR_USART_INACK_Pos       20           /**< \brief (US_MR_USART) Inhibit Non Acknowledge */
912 #define US_MR_USART_INACK           (_U_(0x1) << US_MR_USART_INACK_Pos)
913 #define   US_MR_USART_INACK_0_Val         _U_(0x0)   /**< \brief (US_MR_USART) The NACK is generated */
914 #define   US_MR_USART_INACK_1_Val         _U_(0x1)   /**< \brief (US_MR_USART) The NACK is not generated */
915 #define US_MR_USART_INACK_0         (US_MR_USART_INACK_0_Val       << US_MR_USART_INACK_Pos)
916 #define US_MR_USART_INACK_1         (US_MR_USART_INACK_1_Val       << US_MR_USART_INACK_Pos)
917 #define US_MR_USART_DSNACK_Pos      21           /**< \brief (US_MR_USART) Disable Successive NACK */
918 #define US_MR_USART_DSNACK          (_U_(0x1) << US_MR_USART_DSNACK_Pos)
919 #define   US_MR_USART_DSNACK_0_Val        _U_(0x0)   /**< \brief (US_MR_USART) NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) */
920 #define   US_MR_USART_DSNACK_1_Val        _U_(0x1)   /**< \brief (US_MR_USART) Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted */
921 #define US_MR_USART_DSNACK_0        (US_MR_USART_DSNACK_0_Val      << US_MR_USART_DSNACK_Pos)
922 #define US_MR_USART_DSNACK_1        (US_MR_USART_DSNACK_1_Val      << US_MR_USART_DSNACK_Pos)
923 #define US_MR_USART_VAR_SYNC_Pos    22           /**< \brief (US_MR_USART) Variable synchronization of command/data sync Start Frame Delimiter */
924 #define US_MR_USART_VAR_SYNC        (_U_(0x1) << US_MR_USART_VAR_SYNC_Pos)
925 #define   US_MR_USART_VAR_SYNC_0_Val      _U_(0x0)   /**< \brief (US_MR_USART) User defined configuration of command or data sync field depending on SYNC value */
926 #define   US_MR_USART_VAR_SYNC_1_Val      _U_(0x1)   /**< \brief (US_MR_USART) The sync field is updated when a character is written into THR register */
927 #define US_MR_USART_VAR_SYNC_0      (US_MR_USART_VAR_SYNC_0_Val    << US_MR_USART_VAR_SYNC_Pos)
928 #define US_MR_USART_VAR_SYNC_1      (US_MR_USART_VAR_SYNC_1_Val    << US_MR_USART_VAR_SYNC_Pos)
929 #define US_MR_USART_INVDATA_Pos     23           /**< \brief (US_MR_USART) Inverted data */
930 #define US_MR_USART_INVDATA         (_U_(0x1) << US_MR_USART_INVDATA_Pos)
931 #define US_MR_USART_MAX_ITERATION_Pos 24           /**< \brief (US_MR_USART) Max interation */
932 #define US_MR_USART_MAX_ITERATION_Msk (_U_(0x7) << US_MR_USART_MAX_ITERATION_Pos)
933 #define US_MR_USART_MAX_ITERATION(value) (US_MR_USART_MAX_ITERATION_Msk & ((value) << US_MR_USART_MAX_ITERATION_Pos))
934 #define US_MR_USART_FILTER_Pos      28           /**< \brief (US_MR_USART) Infrared Receive Line Filter */
935 #define US_MR_USART_FILTER          (_U_(0x1) << US_MR_USART_FILTER_Pos)
936 #define   US_MR_USART_FILTER_0_Val        _U_(0x0)   /**< \brief (US_MR_USART) The USART does not filter the receive line */
937 #define   US_MR_USART_FILTER_1_Val        _U_(0x1)   /**< \brief (US_MR_USART) The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) */
938 #define US_MR_USART_FILTER_0        (US_MR_USART_FILTER_0_Val      << US_MR_USART_FILTER_Pos)
939 #define US_MR_USART_FILTER_1        (US_MR_USART_FILTER_1_Val      << US_MR_USART_FILTER_Pos)
940 #define US_MR_USART_MAN_Pos         29           /**< \brief (US_MR_USART) Manchester Encoder/Decoder Enable */
941 #define US_MR_USART_MAN             (_U_(0x1) << US_MR_USART_MAN_Pos)
942 #define   US_MR_USART_MAN_0_Val           _U_(0x0)   /**< \brief (US_MR_USART) Manchester Encoder/Decoder is disabled */
943 #define   US_MR_USART_MAN_1_Val           _U_(0x1)   /**< \brief (US_MR_USART) Manchester Encoder/Decoder is enabled */
944 #define US_MR_USART_MAN_0           (US_MR_USART_MAN_0_Val         << US_MR_USART_MAN_Pos)
945 #define US_MR_USART_MAN_1           (US_MR_USART_MAN_1_Val         << US_MR_USART_MAN_Pos)
946 #define US_MR_USART_MODSYNC_Pos     30           /**< \brief (US_MR_USART) Manchester Synchronization Mode */
947 #define US_MR_USART_MODSYNC         (_U_(0x1) << US_MR_USART_MODSYNC_Pos)
948 #define   US_MR_USART_MODSYNC_0_Val       _U_(0x0)   /**< \brief (US_MR_USART) The Manchester Start bit is a 0 to 1 transition */
949 #define   US_MR_USART_MODSYNC_1_Val       _U_(0x1)   /**< \brief (US_MR_USART) The Manchester Start bit is a 1 to 0 transition */
950 #define US_MR_USART_MODSYNC_0       (US_MR_USART_MODSYNC_0_Val     << US_MR_USART_MODSYNC_Pos)
951 #define US_MR_USART_MODSYNC_1       (US_MR_USART_MODSYNC_1_Val     << US_MR_USART_MODSYNC_Pos)
952 #define US_MR_USART_ONEBIT_Pos      31           /**< \brief (US_MR_USART) Start Frame Delimiter selector */
953 #define US_MR_USART_ONEBIT          (_U_(0x1) << US_MR_USART_ONEBIT_Pos)
954 #define   US_MR_USART_ONEBIT_0_Val        _U_(0x0)   /**< \brief (US_MR_USART) Start Frame delimiter is COMMAND or DATA SYNC */
955 #define   US_MR_USART_ONEBIT_1_Val        _U_(0x1)   /**< \brief (US_MR_USART) Start Frame delimiter is One Bit */
956 #define US_MR_USART_ONEBIT_0        (US_MR_USART_ONEBIT_0_Val      << US_MR_USART_ONEBIT_Pos)
957 #define US_MR_USART_ONEBIT_1        (US_MR_USART_ONEBIT_1_Val      << US_MR_USART_ONEBIT_Pos)
958 #define US_MR_USART_MASK            _U_(0xF7FFFFFF) /**< \brief (US_MR_USART) MASK Register */
959 
960 // Any mode
961 #define US_MR_MODE_Pos              0            /**< \brief (US_MR) Usart Mode */
962 #define US_MR_MODE_Msk              (_U_(0xF) << US_MR_MODE_Pos)
963 #define US_MR_MODE(value)           (US_MR_MODE_Msk & ((value) << US_MR_MODE_Pos))
964 #define   US_MR_MODE_NORMAL_Val           _U_(0x0)   /**< \brief (US_MR) Normal */
965 #define   US_MR_MODE_RS485_Val            _U_(0x1)   /**< \brief (US_MR) RS485 */
966 #define   US_MR_MODE_HARDWARE_Val         _U_(0x2)   /**< \brief (US_MR) Hardware Handshaking */
967 #define   US_MR_MODE_MODEM_Val            _U_(0x3)   /**< \brief (US_MR) Modem */
968 #define   US_MR_MODE_ISO7816_T0_Val       _U_(0x4)   /**< \brief (US_MR) IS07816 Protocol: T = 0 */
969 #define   US_MR_MODE_ISO7816_T1_Val       _U_(0x6)   /**< \brief (US_MR) IS07816 Protocol: T = 1 */
970 #define   US_MR_MODE_IRDA_Val             _U_(0x8)   /**< \brief (US_MR) IrDA */
971 #define   US_MR_MODE_LIN_MASTER_Val       _U_(0xA)   /**< \brief (US_MR) LIN Master */
972 #define   US_MR_MODE_LIN_SLAVE_Val        _U_(0xB)   /**< \brief (US_MR) LIN Slave */
973 #define   US_MR_MODE_SPI_MASTER_Val       _U_(0xE)   /**< \brief (US_MR) SPI Master */
974 #define   US_MR_MODE_SPI_SLAVE_Val        _U_(0xF)   /**< \brief (US_MR) SPI Slave */
975 #define US_MR_MODE_NORMAL           (US_MR_MODE_NORMAL_Val         << US_MR_MODE_Pos)
976 #define US_MR_MODE_RS485            (US_MR_MODE_RS485_Val          << US_MR_MODE_Pos)
977 #define US_MR_MODE_HARDWARE         (US_MR_MODE_HARDWARE_Val       << US_MR_MODE_Pos)
978 #define US_MR_MODE_MODEM            (US_MR_MODE_MODEM_Val          << US_MR_MODE_Pos)
979 #define US_MR_MODE_ISO7816_T0       (US_MR_MODE_ISO7816_T0_Val     << US_MR_MODE_Pos)
980 #define US_MR_MODE_ISO7816_T1       (US_MR_MODE_ISO7816_T1_Val     << US_MR_MODE_Pos)
981 #define US_MR_MODE_IRDA             (US_MR_MODE_IRDA_Val           << US_MR_MODE_Pos)
982 #define US_MR_MODE_LIN_MASTER       (US_MR_MODE_LIN_MASTER_Val     << US_MR_MODE_Pos)
983 #define US_MR_MODE_LIN_SLAVE        (US_MR_MODE_LIN_SLAVE_Val      << US_MR_MODE_Pos)
984 #define US_MR_MODE_SPI_MASTER       (US_MR_MODE_SPI_MASTER_Val     << US_MR_MODE_Pos)
985 #define US_MR_MODE_SPI_SLAVE        (US_MR_MODE_SPI_SLAVE_Val      << US_MR_MODE_Pos)
986 #define US_MR_USCLKS_Pos            4            /**< \brief (US_MR) Clock Selection */
987 #define US_MR_USCLKS_Msk            (_U_(0x3) << US_MR_USCLKS_Pos)
988 #define US_MR_USCLKS(value)         (US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))
989 #define   US_MR_USCLKS_MCK_Val            _U_(0x0)   /**< \brief (US_MR) MCK */
990 #define   US_MR_USCLKS_MCK_DIV_Val        _U_(0x1)   /**< \brief (US_MR) MCK / DIV */
991 #define   US_MR_USCLKS_2_Val              _U_(0x2)   /**< \brief (US_MR) Reserved */
992 #define   US_MR_USCLKS_SCK_Val            _U_(0x3)   /**< \brief (US_MR) SCK */
993 #define US_MR_USCLKS_MCK            (US_MR_USCLKS_MCK_Val          << US_MR_USCLKS_Pos)
994 #define US_MR_USCLKS_MCK_DIV        (US_MR_USCLKS_MCK_DIV_Val      << US_MR_USCLKS_Pos)
995 #define US_MR_USCLKS_2              (US_MR_USCLKS_2_Val            << US_MR_USCLKS_Pos)
996 #define US_MR_USCLKS_SCK            (US_MR_USCLKS_SCK_Val          << US_MR_USCLKS_Pos)
997 #define US_MR_CHRL_Pos              6            /**< \brief (US_MR) Character Length. */
998 #define US_MR_CHRL_Msk              (_U_(0x3) << US_MR_CHRL_Pos)
999 #define US_MR_CHRL(value)           (US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))
1000 #define   US_MR_CHRL_5_Val                _U_(0x0)   /**< \brief (US_MR) 5 bits */
1001 #define   US_MR_CHRL_6_Val                _U_(0x1)   /**< \brief (US_MR) 6 bits */
1002 #define   US_MR_CHRL_7_Val                _U_(0x2)   /**< \brief (US_MR) 7 bits */
1003 #define   US_MR_CHRL_8_Val                _U_(0x3)   /**< \brief (US_MR) 8 bits */
1004 #define US_MR_CHRL_5                (US_MR_CHRL_5_Val              << US_MR_CHRL_Pos)
1005 #define US_MR_CHRL_6                (US_MR_CHRL_6_Val              << US_MR_CHRL_Pos)
1006 #define US_MR_CHRL_7                (US_MR_CHRL_7_Val              << US_MR_CHRL_Pos)
1007 #define US_MR_CHRL_8                (US_MR_CHRL_8_Val              << US_MR_CHRL_Pos)
1008 #define US_MR_CPHA_Pos              8            /**< \brief (US_MR) SPI CLock Phase */
1009 #define US_MR_CPHA                  (_U_(0x1) << US_MR_CPHA_Pos)
1010 #define   US_MR_CPHA_0_Val                _U_(0x0)   /**< \brief (US_MR) Data is changed on the leading edge of SPCK and captured on the following edge of SPCK */
1011 #define   US_MR_CPHA_1_Val                _U_(0x1)   /**< \brief (US_MR) Data is captured on the leading edge of SPCK and changed on the following edge of SPCK */
1012 #define US_MR_CPHA_0                (US_MR_CPHA_0_Val              << US_MR_CPHA_Pos)
1013 #define US_MR_CPHA_1                (US_MR_CPHA_1_Val              << US_MR_CPHA_Pos)
1014 #define US_MR_SYNC_Pos              8            /**< \brief (US_MR) Synchronous Mode Select */
1015 #define US_MR_SYNC                  (_U_(0x1) << US_MR_SYNC_Pos)
1016 #define   US_MR_SYNC_0_Val                _U_(0x0)   /**< \brief (US_MR) USART operates in Synchronous Mode */
1017 #define   US_MR_SYNC_1_Val                _U_(0x1)   /**< \brief (US_MR) USART operates in Asynchronous Mode */
1018 #define US_MR_SYNC_0                (US_MR_SYNC_0_Val              << US_MR_SYNC_Pos)
1019 #define US_MR_SYNC_1                (US_MR_SYNC_1_Val              << US_MR_SYNC_Pos)
1020 #define US_MR_PAR_Pos               9            /**< \brief (US_MR) Parity Type */
1021 #define US_MR_PAR_Msk               (_U_(0x7) << US_MR_PAR_Pos)
1022 #define US_MR_PAR(value)            (US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))
1023 #define   US_MR_PAR_EVEN_Val              _U_(0x0)   /**< \brief (US_MR) Even parity */
1024 #define   US_MR_PAR_ODD_Val               _U_(0x1)   /**< \brief (US_MR) Odd parity */
1025 #define   US_MR_PAR_SPACE_Val             _U_(0x2)   /**< \brief (US_MR) Parity forced to 0 (Space) */
1026 #define   US_MR_PAR_MARK_Val              _U_(0x3)   /**< \brief (US_MR) Parity forced to 1 (Mark) */
1027 #define   US_MR_PAR_NONE_Val              _U_(0x4)   /**< \brief (US_MR) No Parity */
1028 #define   US_MR_PAR_5_Val                 _U_(0x5)   /**< \brief (US_MR) No Parity */
1029 #define   US_MR_PAR_MULTI_Val             _U_(0x6)   /**< \brief (US_MR) Multi-drop mode */
1030 #define   US_MR_PAR_7_Val                 _U_(0x7)   /**< \brief (US_MR) Multi-drop mode */
1031 #define US_MR_PAR_EVEN              (US_MR_PAR_EVEN_Val            << US_MR_PAR_Pos)
1032 #define US_MR_PAR_ODD               (US_MR_PAR_ODD_Val             << US_MR_PAR_Pos)
1033 #define US_MR_PAR_SPACE             (US_MR_PAR_SPACE_Val           << US_MR_PAR_Pos)
1034 #define US_MR_PAR_MARK              (US_MR_PAR_MARK_Val            << US_MR_PAR_Pos)
1035 #define US_MR_PAR_NONE              (US_MR_PAR_NONE_Val            << US_MR_PAR_Pos)
1036 #define US_MR_PAR_5                 (US_MR_PAR_5_Val               << US_MR_PAR_Pos)
1037 #define US_MR_PAR_MULTI             (US_MR_PAR_MULTI_Val           << US_MR_PAR_Pos)
1038 #define US_MR_PAR_7                 (US_MR_PAR_7_Val               << US_MR_PAR_Pos)
1039 #define US_MR_NBSTOP_Pos            12           /**< \brief (US_MR) Number of Stop Bits */
1040 #define US_MR_NBSTOP_Msk            (_U_(0x3) << US_MR_NBSTOP_Pos)
1041 #define US_MR_NBSTOP(value)         (US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))
1042 #define   US_MR_NBSTOP_1_Val              _U_(0x0)   /**< \brief (US_MR) 1 stop bit */
1043 #define   US_MR_NBSTOP_1_5_Val            _U_(0x1)   /**< \brief (US_MR) 1.5 stop bits (Only valid if SYNC=0) */
1044 #define   US_MR_NBSTOP_2_Val              _U_(0x2)   /**< \brief (US_MR) 2 stop bits */
1045 #define   US_MR_NBSTOP_3_Val              _U_(0x3)   /**< \brief (US_MR) Reserved */
1046 #define US_MR_NBSTOP_1              (US_MR_NBSTOP_1_Val            << US_MR_NBSTOP_Pos)
1047 #define US_MR_NBSTOP_1_5            (US_MR_NBSTOP_1_5_Val          << US_MR_NBSTOP_Pos)
1048 #define US_MR_NBSTOP_2              (US_MR_NBSTOP_2_Val            << US_MR_NBSTOP_Pos)
1049 #define US_MR_NBSTOP_3              (US_MR_NBSTOP_3_Val            << US_MR_NBSTOP_Pos)
1050 #define US_MR_CHMODE_Pos            14           /**< \brief (US_MR) Channel Mode */
1051 #define US_MR_CHMODE_Msk            (_U_(0x3) << US_MR_CHMODE_Pos)
1052 #define US_MR_CHMODE(value)         (US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))
1053 #define   US_MR_CHMODE_NORMAL_Val         _U_(0x0)   /**< \brief (US_MR) Normal Mode */
1054 #define   US_MR_CHMODE_ECHO_Val           _U_(0x1)   /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin */
1055 #define   US_MR_CHMODE_LOCAL_LOOP_Val     _U_(0x2)   /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input */
1056 #define   US_MR_CHMODE_REMOTE_LOOP_Val    _U_(0x3)   /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin */
1057 #define US_MR_CHMODE_NORMAL         (US_MR_CHMODE_NORMAL_Val       << US_MR_CHMODE_Pos)
1058 #define US_MR_CHMODE_ECHO           (US_MR_CHMODE_ECHO_Val         << US_MR_CHMODE_Pos)
1059 #define US_MR_CHMODE_LOCAL_LOOP     (US_MR_CHMODE_LOCAL_LOOP_Val   << US_MR_CHMODE_Pos)
1060 #define US_MR_CHMODE_REMOTE_LOOP    (US_MR_CHMODE_REMOTE_LOOP_Val  << US_MR_CHMODE_Pos)
1061 #define US_MR_CPOL_Pos              16           /**< \brief (US_MR) SPI Clock Polarity */
1062 #define US_MR_CPOL                  (_U_(0x1) << US_MR_CPOL_Pos)
1063 #define   US_MR_CPOL_ZERO_Val             _U_(0x0)   /**< \brief (US_MR) The inactive state value of SPCK is logic level zero */
1064 #define   US_MR_CPOL_ONE_Val              _U_(0x1)   /**< \brief (US_MR) The inactive state value of SPCK is logic level one */
1065 #define US_MR_CPOL_ZERO             (US_MR_CPOL_ZERO_Val           << US_MR_CPOL_Pos)
1066 #define US_MR_CPOL_ONE              (US_MR_CPOL_ONE_Val            << US_MR_CPOL_Pos)
1067 #define US_MR_MSBF_Pos              16           /**< \brief (US_MR) Bit Order */
1068 #define US_MR_MSBF                  (_U_(0x1) << US_MR_MSBF_Pos)
1069 #define   US_MR_MSBF_LSBF_Val             _U_(0x0)   /**< \brief (US_MR) Least Significant Bit first */
1070 #define   US_MR_MSBF_MSBF_Val             _U_(0x1)   /**< \brief (US_MR) Most Significant Bit first */
1071 #define US_MR_MSBF_LSBF             (US_MR_MSBF_LSBF_Val           << US_MR_MSBF_Pos)
1072 #define US_MR_MSBF_MSBF             (US_MR_MSBF_MSBF_Val           << US_MR_MSBF_Pos)
1073 #define US_MR_MODE9_Pos             17           /**< \brief (US_MR) 9-bit Character Length */
1074 #define US_MR_MODE9                 (_U_(0x1) << US_MR_MODE9_Pos)
1075 #define   US_MR_MODE9_0_Val               _U_(0x0)   /**< \brief (US_MR) CHRL defines character length */
1076 #define   US_MR_MODE9_1_Val               _U_(0x1)   /**< \brief (US_MR) 9-bit character length */
1077 #define US_MR_MODE9_0               (US_MR_MODE9_0_Val             << US_MR_MODE9_Pos)
1078 #define US_MR_MODE9_1               (US_MR_MODE9_1_Val             << US_MR_MODE9_Pos)
1079 #define US_MR_CLKO_Pos              18           /**< \brief (US_MR) Clock Output Select */
1080 #define US_MR_CLKO                  (_U_(0x1) << US_MR_CLKO_Pos)
1081 #define   US_MR_CLKO_0_Val                _U_(0x0)   /**< \brief (US_MR) The USART does not drive the SCK pin */
1082 #define   US_MR_CLKO_1_Val                _U_(0x1)   /**< \brief (US_MR) The USART drives the SCK pin if USCLKS does not select the external clock SCK */
1083 #define US_MR_CLKO_0                (US_MR_CLKO_0_Val              << US_MR_CLKO_Pos)
1084 #define US_MR_CLKO_1                (US_MR_CLKO_1_Val              << US_MR_CLKO_Pos)
1085 #define US_MR_OVER_Pos              19           /**< \brief (US_MR) Oversampling Mode */
1086 #define US_MR_OVER                  (_U_(0x1) << US_MR_OVER_Pos)
1087 #define   US_MR_OVER_X16_Val              _U_(0x0)   /**< \brief (US_MR) 16x Oversampling */
1088 #define   US_MR_OVER_X8_Val               _U_(0x1)   /**< \brief (US_MR) 8x Oversampling */
1089 #define US_MR_OVER_X16              (US_MR_OVER_X16_Val            << US_MR_OVER_Pos)
1090 #define US_MR_OVER_X8               (US_MR_OVER_X8_Val             << US_MR_OVER_Pos)
1091 #define US_MR_INACK_Pos             20           /**< \brief (US_MR) Inhibit Non Acknowledge */
1092 #define US_MR_INACK                 (_U_(0x1) << US_MR_INACK_Pos)
1093 #define   US_MR_INACK_0_Val               _U_(0x0)   /**< \brief (US_MR) The NACK is generated */
1094 #define   US_MR_INACK_1_Val               _U_(0x1)   /**< \brief (US_MR) The NACK is not generated */
1095 #define US_MR_INACK_0               (US_MR_INACK_0_Val             << US_MR_INACK_Pos)
1096 #define US_MR_INACK_1               (US_MR_INACK_1_Val             << US_MR_INACK_Pos)
1097 #define US_MR_DSNACK_Pos            21           /**< \brief (US_MR) Disable Successive NACK */
1098 #define US_MR_DSNACK                (_U_(0x1) << US_MR_DSNACK_Pos)
1099 #define   US_MR_DSNACK_0_Val              _U_(0x0)   /**< \brief (US_MR) NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set) */
1100 #define   US_MR_DSNACK_1_Val              _U_(0x1)   /**< \brief (US_MR) Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generatea NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted */
1101 #define US_MR_DSNACK_0              (US_MR_DSNACK_0_Val            << US_MR_DSNACK_Pos)
1102 #define US_MR_DSNACK_1              (US_MR_DSNACK_1_Val            << US_MR_DSNACK_Pos)
1103 #define US_MR_VAR_SYNC_Pos          22           /**< \brief (US_MR) Variable synchronization of command/data sync Start Frame Delimiter */
1104 #define US_MR_VAR_SYNC              (_U_(0x1) << US_MR_VAR_SYNC_Pos)
1105 #define   US_MR_VAR_SYNC_0_Val            _U_(0x0)   /**< \brief (US_MR) User defined configuration of command or data sync field depending on SYNC value */
1106 #define   US_MR_VAR_SYNC_1_Val            _U_(0x1)   /**< \brief (US_MR) The sync field is updated when a character is written into THR register */
1107 #define US_MR_VAR_SYNC_0            (US_MR_VAR_SYNC_0_Val          << US_MR_VAR_SYNC_Pos)
1108 #define US_MR_VAR_SYNC_1            (US_MR_VAR_SYNC_1_Val          << US_MR_VAR_SYNC_Pos)
1109 #define US_MR_INVDATA_Pos           23           /**< \brief (US_MR) Inverted data */
1110 #define US_MR_INVDATA               (_U_(0x1) << US_MR_INVDATA_Pos)
1111 #define US_MR_MAX_ITERATION_Pos     24           /**< \brief (US_MR) Max interation */
1112 #define US_MR_MAX_ITERATION_Msk     (_U_(0x7) << US_MR_MAX_ITERATION_Pos)
1113 #define US_MR_MAX_ITERATION(value)  (US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))
1114 #define US_MR_FILTER_Pos            28           /**< \brief (US_MR) Infrared Receive Line Filter */
1115 #define US_MR_FILTER                (_U_(0x1) << US_MR_FILTER_Pos)
1116 #define   US_MR_FILTER_0_Val              _U_(0x0)   /**< \brief (US_MR) The USART does not filter the receive line */
1117 #define   US_MR_FILTER_1_Val              _U_(0x1)   /**< \brief (US_MR) The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority) */
1118 #define US_MR_FILTER_0              (US_MR_FILTER_0_Val            << US_MR_FILTER_Pos)
1119 #define US_MR_FILTER_1              (US_MR_FILTER_1_Val            << US_MR_FILTER_Pos)
1120 #define US_MR_MAN_Pos               29           /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
1121 #define US_MR_MAN                   (_U_(0x1) << US_MR_MAN_Pos)
1122 #define   US_MR_MAN_0_Val                 _U_(0x0)   /**< \brief (US_MR) Manchester Encoder/Decoder is disabled */
1123 #define   US_MR_MAN_1_Val                 _U_(0x1)   /**< \brief (US_MR) Manchester Encoder/Decoder is enabled */
1124 #define US_MR_MAN_0                 (US_MR_MAN_0_Val               << US_MR_MAN_Pos)
1125 #define US_MR_MAN_1                 (US_MR_MAN_1_Val               << US_MR_MAN_Pos)
1126 #define US_MR_MODSYNC_Pos           30           /**< \brief (US_MR) Manchester Synchronization Mode */
1127 #define US_MR_MODSYNC               (_U_(0x1) << US_MR_MODSYNC_Pos)
1128 #define   US_MR_MODSYNC_0_Val             _U_(0x0)   /**< \brief (US_MR) The Manchester Start bit is a 0 to 1 transition */
1129 #define   US_MR_MODSYNC_1_Val             _U_(0x1)   /**< \brief (US_MR) The Manchester Start bit is a 1 to 0 transition */
1130 #define US_MR_MODSYNC_0             (US_MR_MODSYNC_0_Val           << US_MR_MODSYNC_Pos)
1131 #define US_MR_MODSYNC_1             (US_MR_MODSYNC_1_Val           << US_MR_MODSYNC_Pos)
1132 #define US_MR_ONEBIT_Pos            31           /**< \brief (US_MR) Start Frame Delimiter selector */
1133 #define US_MR_ONEBIT                (_U_(0x1) << US_MR_ONEBIT_Pos)
1134 #define   US_MR_ONEBIT_0_Val              _U_(0x0)   /**< \brief (US_MR) Start Frame delimiter is COMMAND or DATA SYNC */
1135 #define   US_MR_ONEBIT_1_Val              _U_(0x1)   /**< \brief (US_MR) Start Frame delimiter is One Bit */
1136 #define US_MR_ONEBIT_0              (US_MR_ONEBIT_0_Val            << US_MR_ONEBIT_Pos)
1137 #define US_MR_ONEBIT_1              (US_MR_ONEBIT_1_Val            << US_MR_ONEBIT_Pos)
1138 #define US_MR_MASK                  _U_(0xF7FFFFFF) /**< \brief (US_MR) MASK Register */
1139 
1140 /* -------- US_IER : (USART Offset: 0x08) ( /W 32) Interrupt Enable Register -------- */
1141 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1142 typedef union {
1143   struct { // LIN mode
1144     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready Interrupt Enable    */
1145     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready Interrupt Enable */
1146     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Enable    */
1147     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
1148     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Enable     */
1149     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Enable     */
1150     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Enable      */
1151     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Enable          */
1152     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty Interrupt Enable */
1153     uint32_t ITER:1;           /*!< bit:     10  Iteration Interrupt Enable         */
1154     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Enable      */
1155     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Enable       */
1156     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Enable */
1157     uint32_t LINID:1;          /*!< bit:     14  LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
1158     uint32_t LINTC:1;          /*!< bit:     15  LIN Transfer Conpleted Interrupt Enable */
1159     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Enable */
1160     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Enable */
1161     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Enable */
1162     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Enable */
1163     uint32_t :5;               /*!< bit: 20..24  Reserved                           */
1164     uint32_t LINBE:1;          /*!< bit:     25  LIN Bus Error Interrupt Enable     */
1165     uint32_t LINISFE:1;        /*!< bit:     26  LIN Inconsistent Synch Field Error Interrupt Enable */
1166     uint32_t LINIPE:1;         /*!< bit:     27  LIN Identifier Parity Interrupt Enable */
1167     uint32_t LINCE:1;          /*!< bit:     28  LIN Checksum Error Interrupt Enable */
1168     uint32_t LINSNRE:1;        /*!< bit:     29  LIN Slave Not Responding Error Interrupt Enable */
1169     uint32_t LINSTE:1;         /*!< bit:     30  LIN Synch Tolerance Error Interrupt Enable */
1170     uint32_t LINHTE:1;         /*!< bit:     31  LIN Header Timeout Error Interrupt Enable */
1171   } LIN;                       /*!< Structure used for LIN                          */
1172   struct { // SPI_SLAVE mode
1173     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready Interrupt Enable    */
1174     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready Interrupt Enable */
1175     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Enable    */
1176     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
1177     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Enable     */
1178     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Enable     */
1179     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Enable      */
1180     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Enable          */
1181     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty Interrupt Enable */
1182     uint32_t UNRE:1;           /*!< bit:     10  SPI Underrun Error Interrupt Enable */
1183     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Enable      */
1184     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Enable       */
1185     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge Interrupt Enable   */
1186     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
1187     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Enable */
1188     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Enable */
1189     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Enable */
1190     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Enable */
1191     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
1192   } SPI_SLAVE;                 /*!< Structure used for SPI_SLAVE                    */
1193   struct { // USART mode
1194     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready Interrupt Enable    */
1195     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready Interrupt Enable */
1196     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Enable    */
1197     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
1198     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Enable     */
1199     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Enable     */
1200     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Enable      */
1201     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Enable          */
1202     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty Interrupt Enable */
1203     uint32_t ITER:1;           /*!< bit:     10  Iteration Interrupt Enable         */
1204     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Enable      */
1205     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Enable       */
1206     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge Interrupt Enable   */
1207     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
1208     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Enable */
1209     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Enable */
1210     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Enable */
1211     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Enable */
1212     uint32_t MANE:1;           /*!< bit:     20  Manchester Error Interrupt Enable  */
1213     uint32_t :3;               /*!< bit: 21..23  Reserved                           */
1214     uint32_t MANEA:1;          /*!< bit:     24  Manchester Error Interrupt Enable  */
1215     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
1216   } USART;                     /*!< Structure used for USART                        */
1217   uint32_t reg;                /*!< Type      used for register access              */
1218 } US_IER_Type;
1219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1220 
1221 #define US_IER_OFFSET               0x08         /**< \brief (US_IER offset) Interrupt Enable Register */
1222 #define US_IER_RESETVALUE           _U_(0x00000000); /**< \brief (US_IER reset_value) Interrupt Enable Register */
1223 
1224 // LIN mode
1225 #define US_IER_LIN_RXRDY_Pos        0            /**< \brief (US_IER_LIN) Receiver Ready Interrupt Enable */
1226 #define US_IER_LIN_RXRDY            (_U_(0x1) << US_IER_LIN_RXRDY_Pos)
1227 #define   US_IER_LIN_RXRDY_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1228 #define   US_IER_LIN_RXRDY_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1229 #define US_IER_LIN_RXRDY_0          (US_IER_LIN_RXRDY_0_Val        << US_IER_LIN_RXRDY_Pos)
1230 #define US_IER_LIN_RXRDY_1          (US_IER_LIN_RXRDY_1_Val        << US_IER_LIN_RXRDY_Pos)
1231 #define US_IER_LIN_TXRDY_Pos        1            /**< \brief (US_IER_LIN) Transmitter Ready Interrupt Enable */
1232 #define US_IER_LIN_TXRDY            (_U_(0x1) << US_IER_LIN_TXRDY_Pos)
1233 #define   US_IER_LIN_TXRDY_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1234 #define   US_IER_LIN_TXRDY_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1235 #define US_IER_LIN_TXRDY_0          (US_IER_LIN_TXRDY_0_Val        << US_IER_LIN_TXRDY_Pos)
1236 #define US_IER_LIN_TXRDY_1          (US_IER_LIN_TXRDY_1_Val        << US_IER_LIN_TXRDY_Pos)
1237 #define US_IER_LIN_RXBRK_Pos        2            /**< \brief (US_IER_LIN) Receiver Break Interrupt Enable */
1238 #define US_IER_LIN_RXBRK            (_U_(0x1) << US_IER_LIN_RXBRK_Pos)
1239 #define   US_IER_LIN_RXBRK_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1240 #define   US_IER_LIN_RXBRK_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1241 #define US_IER_LIN_RXBRK_0          (US_IER_LIN_RXBRK_0_Val        << US_IER_LIN_RXBRK_Pos)
1242 #define US_IER_LIN_RXBRK_1          (US_IER_LIN_RXBRK_1_Val        << US_IER_LIN_RXBRK_Pos)
1243 #define US_IER_LIN_OVRE_Pos         5            /**< \brief (US_IER_LIN) Overrun Error Interrupt Enable */
1244 #define US_IER_LIN_OVRE             (_U_(0x1) << US_IER_LIN_OVRE_Pos)
1245 #define   US_IER_LIN_OVRE_0_Val           _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1246 #define   US_IER_LIN_OVRE_1_Val           _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1247 #define US_IER_LIN_OVRE_0           (US_IER_LIN_OVRE_0_Val         << US_IER_LIN_OVRE_Pos)
1248 #define US_IER_LIN_OVRE_1           (US_IER_LIN_OVRE_1_Val         << US_IER_LIN_OVRE_Pos)
1249 #define US_IER_LIN_FRAME_Pos        6            /**< \brief (US_IER_LIN) Framing Error Interrupt Enable */
1250 #define US_IER_LIN_FRAME            (_U_(0x1) << US_IER_LIN_FRAME_Pos)
1251 #define   US_IER_LIN_FRAME_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1252 #define   US_IER_LIN_FRAME_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1253 #define US_IER_LIN_FRAME_0          (US_IER_LIN_FRAME_0_Val        << US_IER_LIN_FRAME_Pos)
1254 #define US_IER_LIN_FRAME_1          (US_IER_LIN_FRAME_1_Val        << US_IER_LIN_FRAME_Pos)
1255 #define US_IER_LIN_PARE_Pos         7            /**< \brief (US_IER_LIN) Parity Error Interrupt Enable */
1256 #define US_IER_LIN_PARE             (_U_(0x1) << US_IER_LIN_PARE_Pos)
1257 #define   US_IER_LIN_PARE_0_Val           _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1258 #define   US_IER_LIN_PARE_1_Val           _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1259 #define US_IER_LIN_PARE_0           (US_IER_LIN_PARE_0_Val         << US_IER_LIN_PARE_Pos)
1260 #define US_IER_LIN_PARE_1           (US_IER_LIN_PARE_1_Val         << US_IER_LIN_PARE_Pos)
1261 #define US_IER_LIN_TIMEOUT_Pos      8            /**< \brief (US_IER_LIN) Time-out Interrupt Enable */
1262 #define US_IER_LIN_TIMEOUT          (_U_(0x1) << US_IER_LIN_TIMEOUT_Pos)
1263 #define   US_IER_LIN_TIMEOUT_0_Val        _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1264 #define   US_IER_LIN_TIMEOUT_1_Val        _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1265 #define US_IER_LIN_TIMEOUT_0        (US_IER_LIN_TIMEOUT_0_Val      << US_IER_LIN_TIMEOUT_Pos)
1266 #define US_IER_LIN_TIMEOUT_1        (US_IER_LIN_TIMEOUT_1_Val      << US_IER_LIN_TIMEOUT_Pos)
1267 #define US_IER_LIN_TXEMPTY_Pos      9            /**< \brief (US_IER_LIN) Transmitter Empty Interrupt Enable */
1268 #define US_IER_LIN_TXEMPTY          (_U_(0x1) << US_IER_LIN_TXEMPTY_Pos)
1269 #define   US_IER_LIN_TXEMPTY_0_Val        _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1270 #define   US_IER_LIN_TXEMPTY_1_Val        _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1271 #define US_IER_LIN_TXEMPTY_0        (US_IER_LIN_TXEMPTY_0_Val      << US_IER_LIN_TXEMPTY_Pos)
1272 #define US_IER_LIN_TXEMPTY_1        (US_IER_LIN_TXEMPTY_1_Val      << US_IER_LIN_TXEMPTY_Pos)
1273 #define US_IER_LIN_ITER_Pos         10           /**< \brief (US_IER_LIN) Iteration Interrupt Enable */
1274 #define US_IER_LIN_ITER             (_U_(0x1) << US_IER_LIN_ITER_Pos)
1275 #define   US_IER_LIN_ITER_0_Val           _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1276 #define   US_IER_LIN_ITER_1_Val           _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1277 #define US_IER_LIN_ITER_0           (US_IER_LIN_ITER_0_Val         << US_IER_LIN_ITER_Pos)
1278 #define US_IER_LIN_ITER_1           (US_IER_LIN_ITER_1_Val         << US_IER_LIN_ITER_Pos)
1279 #define US_IER_LIN_TXBUFE_Pos       11           /**< \brief (US_IER_LIN) Buffer Empty Interrupt Enable */
1280 #define US_IER_LIN_TXBUFE           (_U_(0x1) << US_IER_LIN_TXBUFE_Pos)
1281 #define   US_IER_LIN_TXBUFE_0_Val         _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1282 #define   US_IER_LIN_TXBUFE_1_Val         _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1283 #define US_IER_LIN_TXBUFE_0         (US_IER_LIN_TXBUFE_0_Val       << US_IER_LIN_TXBUFE_Pos)
1284 #define US_IER_LIN_TXBUFE_1         (US_IER_LIN_TXBUFE_1_Val       << US_IER_LIN_TXBUFE_Pos)
1285 #define US_IER_LIN_RXBUFF_Pos       12           /**< \brief (US_IER_LIN) Buffer Full Interrupt Enable */
1286 #define US_IER_LIN_RXBUFF           (_U_(0x1) << US_IER_LIN_RXBUFF_Pos)
1287 #define   US_IER_LIN_RXBUFF_0_Val         _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1288 #define   US_IER_LIN_RXBUFF_1_Val         _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1289 #define US_IER_LIN_RXBUFF_0         (US_IER_LIN_RXBUFF_0_Val       << US_IER_LIN_RXBUFF_Pos)
1290 #define US_IER_LIN_RXBUFF_1         (US_IER_LIN_RXBUFF_1_Val       << US_IER_LIN_RXBUFF_Pos)
1291 #define US_IER_LIN_NACK_Pos         13           /**< \brief (US_IER_LIN) Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Enable */
1292 #define US_IER_LIN_NACK             (_U_(0x1) << US_IER_LIN_NACK_Pos)
1293 #define   US_IER_LIN_NACK_0_Val           _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1294 #define   US_IER_LIN_NACK_1_Val           _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1295 #define US_IER_LIN_NACK_0           (US_IER_LIN_NACK_0_Val         << US_IER_LIN_NACK_Pos)
1296 #define US_IER_LIN_NACK_1           (US_IER_LIN_NACK_1_Val         << US_IER_LIN_NACK_Pos)
1297 #define US_IER_LIN_LINID_Pos        14           /**< \brief (US_IER_LIN) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
1298 #define US_IER_LIN_LINID            (_U_(0x1) << US_IER_LIN_LINID_Pos)
1299 #define US_IER_LIN_LINTC_Pos        15           /**< \brief (US_IER_LIN) LIN Transfer Conpleted Interrupt Enable */
1300 #define US_IER_LIN_LINTC            (_U_(0x1) << US_IER_LIN_LINTC_Pos)
1301 #define US_IER_LIN_RIIC_Pos         16           /**< \brief (US_IER_LIN) Ring Indicator Input Change Enable */
1302 #define US_IER_LIN_RIIC             (_U_(0x1) << US_IER_LIN_RIIC_Pos)
1303 #define   US_IER_LIN_RIIC_0_Val           _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1304 #define   US_IER_LIN_RIIC_1_Val           _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1305 #define US_IER_LIN_RIIC_0           (US_IER_LIN_RIIC_0_Val         << US_IER_LIN_RIIC_Pos)
1306 #define US_IER_LIN_RIIC_1           (US_IER_LIN_RIIC_1_Val         << US_IER_LIN_RIIC_Pos)
1307 #define US_IER_LIN_DSRIC_Pos        17           /**< \brief (US_IER_LIN) Data Set Ready Input Change Enable */
1308 #define US_IER_LIN_DSRIC            (_U_(0x1) << US_IER_LIN_DSRIC_Pos)
1309 #define   US_IER_LIN_DSRIC_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1310 #define   US_IER_LIN_DSRIC_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1311 #define US_IER_LIN_DSRIC_0          (US_IER_LIN_DSRIC_0_Val        << US_IER_LIN_DSRIC_Pos)
1312 #define US_IER_LIN_DSRIC_1          (US_IER_LIN_DSRIC_1_Val        << US_IER_LIN_DSRIC_Pos)
1313 #define US_IER_LIN_DCDIC_Pos        18           /**< \brief (US_IER_LIN) Data Carrier Detect Input Change Interrupt Enable */
1314 #define US_IER_LIN_DCDIC            (_U_(0x1) << US_IER_LIN_DCDIC_Pos)
1315 #define   US_IER_LIN_DCDIC_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1316 #define   US_IER_LIN_DCDIC_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1317 #define US_IER_LIN_DCDIC_0          (US_IER_LIN_DCDIC_0_Val        << US_IER_LIN_DCDIC_Pos)
1318 #define US_IER_LIN_DCDIC_1          (US_IER_LIN_DCDIC_1_Val        << US_IER_LIN_DCDIC_Pos)
1319 #define US_IER_LIN_CTSIC_Pos        19           /**< \brief (US_IER_LIN) Clear to Send Input Change Interrupt Enable */
1320 #define US_IER_LIN_CTSIC            (_U_(0x1) << US_IER_LIN_CTSIC_Pos)
1321 #define   US_IER_LIN_CTSIC_0_Val          _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1322 #define   US_IER_LIN_CTSIC_1_Val          _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1323 #define US_IER_LIN_CTSIC_0          (US_IER_LIN_CTSIC_0_Val        << US_IER_LIN_CTSIC_Pos)
1324 #define US_IER_LIN_CTSIC_1          (US_IER_LIN_CTSIC_1_Val        << US_IER_LIN_CTSIC_Pos)
1325 #define US_IER_LIN_LINBE_Pos        25           /**< \brief (US_IER_LIN) LIN Bus Error Interrupt Enable */
1326 #define US_IER_LIN_LINBE            (_U_(0x1) << US_IER_LIN_LINBE_Pos)
1327 #define US_IER_LIN_LINISFE_Pos      26           /**< \brief (US_IER_LIN) LIN Inconsistent Synch Field Error Interrupt Enable */
1328 #define US_IER_LIN_LINISFE          (_U_(0x1) << US_IER_LIN_LINISFE_Pos)
1329 #define US_IER_LIN_LINIPE_Pos       27           /**< \brief (US_IER_LIN) LIN Identifier Parity Interrupt Enable */
1330 #define US_IER_LIN_LINIPE           (_U_(0x1) << US_IER_LIN_LINIPE_Pos)
1331 #define US_IER_LIN_LINCE_Pos        28           /**< \brief (US_IER_LIN) LIN Checksum Error Interrupt Enable */
1332 #define US_IER_LIN_LINCE            (_U_(0x1) << US_IER_LIN_LINCE_Pos)
1333 #define US_IER_LIN_LINSNRE_Pos      29           /**< \brief (US_IER_LIN) LIN Slave Not Responding Error Interrupt Enable */
1334 #define US_IER_LIN_LINSNRE          (_U_(0x1) << US_IER_LIN_LINSNRE_Pos)
1335 #define US_IER_LIN_LINSTE_Pos       30           /**< \brief (US_IER_LIN) LIN Synch Tolerance Error Interrupt Enable */
1336 #define US_IER_LIN_LINSTE           (_U_(0x1) << US_IER_LIN_LINSTE_Pos)
1337 #define   US_IER_LIN_LINSTE_0_Val         _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1338 #define   US_IER_LIN_LINSTE_1_Val         _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1339 #define US_IER_LIN_LINSTE_0         (US_IER_LIN_LINSTE_0_Val       << US_IER_LIN_LINSTE_Pos)
1340 #define US_IER_LIN_LINSTE_1         (US_IER_LIN_LINSTE_1_Val       << US_IER_LIN_LINSTE_Pos)
1341 #define US_IER_LIN_LINHTE_Pos       31           /**< \brief (US_IER_LIN) LIN Header Timeout Error Interrupt Enable */
1342 #define US_IER_LIN_LINHTE           (_U_(0x1) << US_IER_LIN_LINHTE_Pos)
1343 #define   US_IER_LIN_LINHTE_0_Val         _U_(0x0)   /**< \brief (US_IER_LIN) No Effect */
1344 #define   US_IER_LIN_LINHTE_1_Val         _U_(0x1)   /**< \brief (US_IER_LIN) Enables the interrupt */
1345 #define US_IER_LIN_LINHTE_0         (US_IER_LIN_LINHTE_0_Val       << US_IER_LIN_LINHTE_Pos)
1346 #define US_IER_LIN_LINHTE_1         (US_IER_LIN_LINHTE_1_Val       << US_IER_LIN_LINHTE_Pos)
1347 #define US_IER_LIN_MASK             _U_(0xFE0FFFE7) /**< \brief (US_IER_LIN) MASK Register */
1348 
1349 // SPI_SLAVE mode
1350 #define US_IER_SPI_SLAVE_RXRDY_Pos  0            /**< \brief (US_IER_SPI_SLAVE) Receiver Ready Interrupt Enable */
1351 #define US_IER_SPI_SLAVE_RXRDY      (_U_(0x1) << US_IER_SPI_SLAVE_RXRDY_Pos)
1352 #define   US_IER_SPI_SLAVE_RXRDY_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1353 #define   US_IER_SPI_SLAVE_RXRDY_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1354 #define US_IER_SPI_SLAVE_RXRDY_0    (US_IER_SPI_SLAVE_RXRDY_0_Val  << US_IER_SPI_SLAVE_RXRDY_Pos)
1355 #define US_IER_SPI_SLAVE_RXRDY_1    (US_IER_SPI_SLAVE_RXRDY_1_Val  << US_IER_SPI_SLAVE_RXRDY_Pos)
1356 #define US_IER_SPI_SLAVE_TXRDY_Pos  1            /**< \brief (US_IER_SPI_SLAVE) Transmitter Ready Interrupt Enable */
1357 #define US_IER_SPI_SLAVE_TXRDY      (_U_(0x1) << US_IER_SPI_SLAVE_TXRDY_Pos)
1358 #define   US_IER_SPI_SLAVE_TXRDY_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1359 #define   US_IER_SPI_SLAVE_TXRDY_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1360 #define US_IER_SPI_SLAVE_TXRDY_0    (US_IER_SPI_SLAVE_TXRDY_0_Val  << US_IER_SPI_SLAVE_TXRDY_Pos)
1361 #define US_IER_SPI_SLAVE_TXRDY_1    (US_IER_SPI_SLAVE_TXRDY_1_Val  << US_IER_SPI_SLAVE_TXRDY_Pos)
1362 #define US_IER_SPI_SLAVE_RXBRK_Pos  2            /**< \brief (US_IER_SPI_SLAVE) Receiver Break Interrupt Enable */
1363 #define US_IER_SPI_SLAVE_RXBRK      (_U_(0x1) << US_IER_SPI_SLAVE_RXBRK_Pos)
1364 #define   US_IER_SPI_SLAVE_RXBRK_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1365 #define   US_IER_SPI_SLAVE_RXBRK_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1366 #define US_IER_SPI_SLAVE_RXBRK_0    (US_IER_SPI_SLAVE_RXBRK_0_Val  << US_IER_SPI_SLAVE_RXBRK_Pos)
1367 #define US_IER_SPI_SLAVE_RXBRK_1    (US_IER_SPI_SLAVE_RXBRK_1_Val  << US_IER_SPI_SLAVE_RXBRK_Pos)
1368 #define US_IER_SPI_SLAVE_OVRE_Pos   5            /**< \brief (US_IER_SPI_SLAVE) Overrun Error Interrupt Enable */
1369 #define US_IER_SPI_SLAVE_OVRE       (_U_(0x1) << US_IER_SPI_SLAVE_OVRE_Pos)
1370 #define   US_IER_SPI_SLAVE_OVRE_0_Val     _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1371 #define   US_IER_SPI_SLAVE_OVRE_1_Val     _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1372 #define US_IER_SPI_SLAVE_OVRE_0     (US_IER_SPI_SLAVE_OVRE_0_Val   << US_IER_SPI_SLAVE_OVRE_Pos)
1373 #define US_IER_SPI_SLAVE_OVRE_1     (US_IER_SPI_SLAVE_OVRE_1_Val   << US_IER_SPI_SLAVE_OVRE_Pos)
1374 #define US_IER_SPI_SLAVE_FRAME_Pos  6            /**< \brief (US_IER_SPI_SLAVE) Framing Error Interrupt Enable */
1375 #define US_IER_SPI_SLAVE_FRAME      (_U_(0x1) << US_IER_SPI_SLAVE_FRAME_Pos)
1376 #define   US_IER_SPI_SLAVE_FRAME_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1377 #define   US_IER_SPI_SLAVE_FRAME_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1378 #define US_IER_SPI_SLAVE_FRAME_0    (US_IER_SPI_SLAVE_FRAME_0_Val  << US_IER_SPI_SLAVE_FRAME_Pos)
1379 #define US_IER_SPI_SLAVE_FRAME_1    (US_IER_SPI_SLAVE_FRAME_1_Val  << US_IER_SPI_SLAVE_FRAME_Pos)
1380 #define US_IER_SPI_SLAVE_PARE_Pos   7            /**< \brief (US_IER_SPI_SLAVE) Parity Error Interrupt Enable */
1381 #define US_IER_SPI_SLAVE_PARE       (_U_(0x1) << US_IER_SPI_SLAVE_PARE_Pos)
1382 #define   US_IER_SPI_SLAVE_PARE_0_Val     _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1383 #define   US_IER_SPI_SLAVE_PARE_1_Val     _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1384 #define US_IER_SPI_SLAVE_PARE_0     (US_IER_SPI_SLAVE_PARE_0_Val   << US_IER_SPI_SLAVE_PARE_Pos)
1385 #define US_IER_SPI_SLAVE_PARE_1     (US_IER_SPI_SLAVE_PARE_1_Val   << US_IER_SPI_SLAVE_PARE_Pos)
1386 #define US_IER_SPI_SLAVE_TIMEOUT_Pos 8            /**< \brief (US_IER_SPI_SLAVE) Time-out Interrupt Enable */
1387 #define US_IER_SPI_SLAVE_TIMEOUT    (_U_(0x1) << US_IER_SPI_SLAVE_TIMEOUT_Pos)
1388 #define   US_IER_SPI_SLAVE_TIMEOUT_0_Val  _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1389 #define   US_IER_SPI_SLAVE_TIMEOUT_1_Val  _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1390 #define US_IER_SPI_SLAVE_TIMEOUT_0  (US_IER_SPI_SLAVE_TIMEOUT_0_Val << US_IER_SPI_SLAVE_TIMEOUT_Pos)
1391 #define US_IER_SPI_SLAVE_TIMEOUT_1  (US_IER_SPI_SLAVE_TIMEOUT_1_Val << US_IER_SPI_SLAVE_TIMEOUT_Pos)
1392 #define US_IER_SPI_SLAVE_TXEMPTY_Pos 9            /**< \brief (US_IER_SPI_SLAVE) Transmitter Empty Interrupt Enable */
1393 #define US_IER_SPI_SLAVE_TXEMPTY    (_U_(0x1) << US_IER_SPI_SLAVE_TXEMPTY_Pos)
1394 #define   US_IER_SPI_SLAVE_TXEMPTY_0_Val  _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1395 #define   US_IER_SPI_SLAVE_TXEMPTY_1_Val  _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1396 #define US_IER_SPI_SLAVE_TXEMPTY_0  (US_IER_SPI_SLAVE_TXEMPTY_0_Val << US_IER_SPI_SLAVE_TXEMPTY_Pos)
1397 #define US_IER_SPI_SLAVE_TXEMPTY_1  (US_IER_SPI_SLAVE_TXEMPTY_1_Val << US_IER_SPI_SLAVE_TXEMPTY_Pos)
1398 #define US_IER_SPI_SLAVE_UNRE_Pos   10           /**< \brief (US_IER_SPI_SLAVE) SPI Underrun Error Interrupt Enable */
1399 #define US_IER_SPI_SLAVE_UNRE       (_U_(0x1) << US_IER_SPI_SLAVE_UNRE_Pos)
1400 #define   US_IER_SPI_SLAVE_UNRE_0_Val     _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1401 #define   US_IER_SPI_SLAVE_UNRE_1_Val     _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1402 #define US_IER_SPI_SLAVE_UNRE_0     (US_IER_SPI_SLAVE_UNRE_0_Val   << US_IER_SPI_SLAVE_UNRE_Pos)
1403 #define US_IER_SPI_SLAVE_UNRE_1     (US_IER_SPI_SLAVE_UNRE_1_Val   << US_IER_SPI_SLAVE_UNRE_Pos)
1404 #define US_IER_SPI_SLAVE_TXBUFE_Pos 11           /**< \brief (US_IER_SPI_SLAVE) Buffer Empty Interrupt Enable */
1405 #define US_IER_SPI_SLAVE_TXBUFE     (_U_(0x1) << US_IER_SPI_SLAVE_TXBUFE_Pos)
1406 #define   US_IER_SPI_SLAVE_TXBUFE_0_Val   _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1407 #define   US_IER_SPI_SLAVE_TXBUFE_1_Val   _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1408 #define US_IER_SPI_SLAVE_TXBUFE_0   (US_IER_SPI_SLAVE_TXBUFE_0_Val << US_IER_SPI_SLAVE_TXBUFE_Pos)
1409 #define US_IER_SPI_SLAVE_TXBUFE_1   (US_IER_SPI_SLAVE_TXBUFE_1_Val << US_IER_SPI_SLAVE_TXBUFE_Pos)
1410 #define US_IER_SPI_SLAVE_RXBUFF_Pos 12           /**< \brief (US_IER_SPI_SLAVE) Buffer Full Interrupt Enable */
1411 #define US_IER_SPI_SLAVE_RXBUFF     (_U_(0x1) << US_IER_SPI_SLAVE_RXBUFF_Pos)
1412 #define   US_IER_SPI_SLAVE_RXBUFF_0_Val   _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1413 #define   US_IER_SPI_SLAVE_RXBUFF_1_Val   _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1414 #define US_IER_SPI_SLAVE_RXBUFF_0   (US_IER_SPI_SLAVE_RXBUFF_0_Val << US_IER_SPI_SLAVE_RXBUFF_Pos)
1415 #define US_IER_SPI_SLAVE_RXBUFF_1   (US_IER_SPI_SLAVE_RXBUFF_1_Val << US_IER_SPI_SLAVE_RXBUFF_Pos)
1416 #define US_IER_SPI_SLAVE_NACK_Pos   13           /**< \brief (US_IER_SPI_SLAVE) Non Acknowledge Interrupt Enable */
1417 #define US_IER_SPI_SLAVE_NACK       (_U_(0x1) << US_IER_SPI_SLAVE_NACK_Pos)
1418 #define   US_IER_SPI_SLAVE_NACK_0_Val     _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1419 #define   US_IER_SPI_SLAVE_NACK_1_Val     _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1420 #define US_IER_SPI_SLAVE_NACK_0     (US_IER_SPI_SLAVE_NACK_0_Val   << US_IER_SPI_SLAVE_NACK_Pos)
1421 #define US_IER_SPI_SLAVE_NACK_1     (US_IER_SPI_SLAVE_NACK_1_Val   << US_IER_SPI_SLAVE_NACK_Pos)
1422 #define US_IER_SPI_SLAVE_RIIC_Pos   16           /**< \brief (US_IER_SPI_SLAVE) Ring Indicator Input Change Enable */
1423 #define US_IER_SPI_SLAVE_RIIC       (_U_(0x1) << US_IER_SPI_SLAVE_RIIC_Pos)
1424 #define   US_IER_SPI_SLAVE_RIIC_0_Val     _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1425 #define   US_IER_SPI_SLAVE_RIIC_1_Val     _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1426 #define US_IER_SPI_SLAVE_RIIC_0     (US_IER_SPI_SLAVE_RIIC_0_Val   << US_IER_SPI_SLAVE_RIIC_Pos)
1427 #define US_IER_SPI_SLAVE_RIIC_1     (US_IER_SPI_SLAVE_RIIC_1_Val   << US_IER_SPI_SLAVE_RIIC_Pos)
1428 #define US_IER_SPI_SLAVE_DSRIC_Pos  17           /**< \brief (US_IER_SPI_SLAVE) Data Set Ready Input Change Enable */
1429 #define US_IER_SPI_SLAVE_DSRIC      (_U_(0x1) << US_IER_SPI_SLAVE_DSRIC_Pos)
1430 #define   US_IER_SPI_SLAVE_DSRIC_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1431 #define   US_IER_SPI_SLAVE_DSRIC_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1432 #define US_IER_SPI_SLAVE_DSRIC_0    (US_IER_SPI_SLAVE_DSRIC_0_Val  << US_IER_SPI_SLAVE_DSRIC_Pos)
1433 #define US_IER_SPI_SLAVE_DSRIC_1    (US_IER_SPI_SLAVE_DSRIC_1_Val  << US_IER_SPI_SLAVE_DSRIC_Pos)
1434 #define US_IER_SPI_SLAVE_DCDIC_Pos  18           /**< \brief (US_IER_SPI_SLAVE) Data Carrier Detect Input Change Interrupt Enable */
1435 #define US_IER_SPI_SLAVE_DCDIC      (_U_(0x1) << US_IER_SPI_SLAVE_DCDIC_Pos)
1436 #define   US_IER_SPI_SLAVE_DCDIC_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1437 #define   US_IER_SPI_SLAVE_DCDIC_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1438 #define US_IER_SPI_SLAVE_DCDIC_0    (US_IER_SPI_SLAVE_DCDIC_0_Val  << US_IER_SPI_SLAVE_DCDIC_Pos)
1439 #define US_IER_SPI_SLAVE_DCDIC_1    (US_IER_SPI_SLAVE_DCDIC_1_Val  << US_IER_SPI_SLAVE_DCDIC_Pos)
1440 #define US_IER_SPI_SLAVE_CTSIC_Pos  19           /**< \brief (US_IER_SPI_SLAVE) Clear to Send Input Change Interrupt Enable */
1441 #define US_IER_SPI_SLAVE_CTSIC      (_U_(0x1) << US_IER_SPI_SLAVE_CTSIC_Pos)
1442 #define   US_IER_SPI_SLAVE_CTSIC_0_Val    _U_(0x0)   /**< \brief (US_IER_SPI_SLAVE) No Effect */
1443 #define   US_IER_SPI_SLAVE_CTSIC_1_Val    _U_(0x1)   /**< \brief (US_IER_SPI_SLAVE) Enables the interrupt */
1444 #define US_IER_SPI_SLAVE_CTSIC_0    (US_IER_SPI_SLAVE_CTSIC_0_Val  << US_IER_SPI_SLAVE_CTSIC_Pos)
1445 #define US_IER_SPI_SLAVE_CTSIC_1    (US_IER_SPI_SLAVE_CTSIC_1_Val  << US_IER_SPI_SLAVE_CTSIC_Pos)
1446 #define US_IER_SPI_SLAVE_MASK       _U_(0x000F3FE7) /**< \brief (US_IER_SPI_SLAVE) MASK Register */
1447 
1448 // USART mode
1449 #define US_IER_USART_RXRDY_Pos      0            /**< \brief (US_IER_USART) Receiver Ready Interrupt Enable */
1450 #define US_IER_USART_RXRDY          (_U_(0x1) << US_IER_USART_RXRDY_Pos)
1451 #define   US_IER_USART_RXRDY_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1452 #define   US_IER_USART_RXRDY_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1453 #define US_IER_USART_RXRDY_0        (US_IER_USART_RXRDY_0_Val      << US_IER_USART_RXRDY_Pos)
1454 #define US_IER_USART_RXRDY_1        (US_IER_USART_RXRDY_1_Val      << US_IER_USART_RXRDY_Pos)
1455 #define US_IER_USART_TXRDY_Pos      1            /**< \brief (US_IER_USART) Transmitter Ready Interrupt Enable */
1456 #define US_IER_USART_TXRDY          (_U_(0x1) << US_IER_USART_TXRDY_Pos)
1457 #define   US_IER_USART_TXRDY_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1458 #define   US_IER_USART_TXRDY_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1459 #define US_IER_USART_TXRDY_0        (US_IER_USART_TXRDY_0_Val      << US_IER_USART_TXRDY_Pos)
1460 #define US_IER_USART_TXRDY_1        (US_IER_USART_TXRDY_1_Val      << US_IER_USART_TXRDY_Pos)
1461 #define US_IER_USART_RXBRK_Pos      2            /**< \brief (US_IER_USART) Receiver Break Interrupt Enable */
1462 #define US_IER_USART_RXBRK          (_U_(0x1) << US_IER_USART_RXBRK_Pos)
1463 #define   US_IER_USART_RXBRK_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1464 #define   US_IER_USART_RXBRK_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1465 #define US_IER_USART_RXBRK_0        (US_IER_USART_RXBRK_0_Val      << US_IER_USART_RXBRK_Pos)
1466 #define US_IER_USART_RXBRK_1        (US_IER_USART_RXBRK_1_Val      << US_IER_USART_RXBRK_Pos)
1467 #define US_IER_USART_OVRE_Pos       5            /**< \brief (US_IER_USART) Overrun Error Interrupt Enable */
1468 #define US_IER_USART_OVRE           (_U_(0x1) << US_IER_USART_OVRE_Pos)
1469 #define   US_IER_USART_OVRE_0_Val         _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1470 #define   US_IER_USART_OVRE_1_Val         _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1471 #define US_IER_USART_OVRE_0         (US_IER_USART_OVRE_0_Val       << US_IER_USART_OVRE_Pos)
1472 #define US_IER_USART_OVRE_1         (US_IER_USART_OVRE_1_Val       << US_IER_USART_OVRE_Pos)
1473 #define US_IER_USART_FRAME_Pos      6            /**< \brief (US_IER_USART) Framing Error Interrupt Enable */
1474 #define US_IER_USART_FRAME          (_U_(0x1) << US_IER_USART_FRAME_Pos)
1475 #define   US_IER_USART_FRAME_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1476 #define   US_IER_USART_FRAME_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1477 #define US_IER_USART_FRAME_0        (US_IER_USART_FRAME_0_Val      << US_IER_USART_FRAME_Pos)
1478 #define US_IER_USART_FRAME_1        (US_IER_USART_FRAME_1_Val      << US_IER_USART_FRAME_Pos)
1479 #define US_IER_USART_PARE_Pos       7            /**< \brief (US_IER_USART) Parity Error Interrupt Enable */
1480 #define US_IER_USART_PARE           (_U_(0x1) << US_IER_USART_PARE_Pos)
1481 #define   US_IER_USART_PARE_0_Val         _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1482 #define   US_IER_USART_PARE_1_Val         _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1483 #define US_IER_USART_PARE_0         (US_IER_USART_PARE_0_Val       << US_IER_USART_PARE_Pos)
1484 #define US_IER_USART_PARE_1         (US_IER_USART_PARE_1_Val       << US_IER_USART_PARE_Pos)
1485 #define US_IER_USART_TIMEOUT_Pos    8            /**< \brief (US_IER_USART) Time-out Interrupt Enable */
1486 #define US_IER_USART_TIMEOUT        (_U_(0x1) << US_IER_USART_TIMEOUT_Pos)
1487 #define   US_IER_USART_TIMEOUT_0_Val      _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1488 #define   US_IER_USART_TIMEOUT_1_Val      _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1489 #define US_IER_USART_TIMEOUT_0      (US_IER_USART_TIMEOUT_0_Val    << US_IER_USART_TIMEOUT_Pos)
1490 #define US_IER_USART_TIMEOUT_1      (US_IER_USART_TIMEOUT_1_Val    << US_IER_USART_TIMEOUT_Pos)
1491 #define US_IER_USART_TXEMPTY_Pos    9            /**< \brief (US_IER_USART) Transmitter Empty Interrupt Enable */
1492 #define US_IER_USART_TXEMPTY        (_U_(0x1) << US_IER_USART_TXEMPTY_Pos)
1493 #define   US_IER_USART_TXEMPTY_0_Val      _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1494 #define   US_IER_USART_TXEMPTY_1_Val      _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1495 #define US_IER_USART_TXEMPTY_0      (US_IER_USART_TXEMPTY_0_Val    << US_IER_USART_TXEMPTY_Pos)
1496 #define US_IER_USART_TXEMPTY_1      (US_IER_USART_TXEMPTY_1_Val    << US_IER_USART_TXEMPTY_Pos)
1497 #define US_IER_USART_ITER_Pos       10           /**< \brief (US_IER_USART) Iteration Interrupt Enable */
1498 #define US_IER_USART_ITER           (_U_(0x1) << US_IER_USART_ITER_Pos)
1499 #define   US_IER_USART_ITER_0_Val         _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1500 #define   US_IER_USART_ITER_1_Val         _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1501 #define US_IER_USART_ITER_0         (US_IER_USART_ITER_0_Val       << US_IER_USART_ITER_Pos)
1502 #define US_IER_USART_ITER_1         (US_IER_USART_ITER_1_Val       << US_IER_USART_ITER_Pos)
1503 #define US_IER_USART_TXBUFE_Pos     11           /**< \brief (US_IER_USART) Buffer Empty Interrupt Enable */
1504 #define US_IER_USART_TXBUFE         (_U_(0x1) << US_IER_USART_TXBUFE_Pos)
1505 #define   US_IER_USART_TXBUFE_0_Val       _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1506 #define   US_IER_USART_TXBUFE_1_Val       _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1507 #define US_IER_USART_TXBUFE_0       (US_IER_USART_TXBUFE_0_Val     << US_IER_USART_TXBUFE_Pos)
1508 #define US_IER_USART_TXBUFE_1       (US_IER_USART_TXBUFE_1_Val     << US_IER_USART_TXBUFE_Pos)
1509 #define US_IER_USART_RXBUFF_Pos     12           /**< \brief (US_IER_USART) Buffer Full Interrupt Enable */
1510 #define US_IER_USART_RXBUFF         (_U_(0x1) << US_IER_USART_RXBUFF_Pos)
1511 #define   US_IER_USART_RXBUFF_0_Val       _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1512 #define   US_IER_USART_RXBUFF_1_Val       _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1513 #define US_IER_USART_RXBUFF_0       (US_IER_USART_RXBUFF_0_Val     << US_IER_USART_RXBUFF_Pos)
1514 #define US_IER_USART_RXBUFF_1       (US_IER_USART_RXBUFF_1_Val     << US_IER_USART_RXBUFF_Pos)
1515 #define US_IER_USART_NACK_Pos       13           /**< \brief (US_IER_USART) Non Acknowledge Interrupt Enable */
1516 #define US_IER_USART_NACK           (_U_(0x1) << US_IER_USART_NACK_Pos)
1517 #define   US_IER_USART_NACK_0_Val         _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1518 #define   US_IER_USART_NACK_1_Val         _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1519 #define US_IER_USART_NACK_0         (US_IER_USART_NACK_0_Val       << US_IER_USART_NACK_Pos)
1520 #define US_IER_USART_NACK_1         (US_IER_USART_NACK_1_Val       << US_IER_USART_NACK_Pos)
1521 #define US_IER_USART_RIIC_Pos       16           /**< \brief (US_IER_USART) Ring Indicator Input Change Enable */
1522 #define US_IER_USART_RIIC           (_U_(0x1) << US_IER_USART_RIIC_Pos)
1523 #define   US_IER_USART_RIIC_0_Val         _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1524 #define   US_IER_USART_RIIC_1_Val         _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1525 #define US_IER_USART_RIIC_0         (US_IER_USART_RIIC_0_Val       << US_IER_USART_RIIC_Pos)
1526 #define US_IER_USART_RIIC_1         (US_IER_USART_RIIC_1_Val       << US_IER_USART_RIIC_Pos)
1527 #define US_IER_USART_DSRIC_Pos      17           /**< \brief (US_IER_USART) Data Set Ready Input Change Enable */
1528 #define US_IER_USART_DSRIC          (_U_(0x1) << US_IER_USART_DSRIC_Pos)
1529 #define   US_IER_USART_DSRIC_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1530 #define   US_IER_USART_DSRIC_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1531 #define US_IER_USART_DSRIC_0        (US_IER_USART_DSRIC_0_Val      << US_IER_USART_DSRIC_Pos)
1532 #define US_IER_USART_DSRIC_1        (US_IER_USART_DSRIC_1_Val      << US_IER_USART_DSRIC_Pos)
1533 #define US_IER_USART_DCDIC_Pos      18           /**< \brief (US_IER_USART) Data Carrier Detect Input Change Interrupt Enable */
1534 #define US_IER_USART_DCDIC          (_U_(0x1) << US_IER_USART_DCDIC_Pos)
1535 #define   US_IER_USART_DCDIC_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1536 #define   US_IER_USART_DCDIC_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1537 #define US_IER_USART_DCDIC_0        (US_IER_USART_DCDIC_0_Val      << US_IER_USART_DCDIC_Pos)
1538 #define US_IER_USART_DCDIC_1        (US_IER_USART_DCDIC_1_Val      << US_IER_USART_DCDIC_Pos)
1539 #define US_IER_USART_CTSIC_Pos      19           /**< \brief (US_IER_USART) Clear to Send Input Change Interrupt Enable */
1540 #define US_IER_USART_CTSIC          (_U_(0x1) << US_IER_USART_CTSIC_Pos)
1541 #define   US_IER_USART_CTSIC_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No Effect */
1542 #define   US_IER_USART_CTSIC_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1543 #define US_IER_USART_CTSIC_0        (US_IER_USART_CTSIC_0_Val      << US_IER_USART_CTSIC_Pos)
1544 #define US_IER_USART_CTSIC_1        (US_IER_USART_CTSIC_1_Val      << US_IER_USART_CTSIC_Pos)
1545 #define US_IER_USART_MANE_Pos       20           /**< \brief (US_IER_USART) Manchester Error Interrupt Enable */
1546 #define US_IER_USART_MANE           (_U_(0x1) << US_IER_USART_MANE_Pos)
1547 #define US_IER_USART_MANEA_Pos      24           /**< \brief (US_IER_USART) Manchester Error Interrupt Enable */
1548 #define US_IER_USART_MANEA          (_U_(0x1) << US_IER_USART_MANEA_Pos)
1549 #define   US_IER_USART_MANEA_0_Val        _U_(0x0)   /**< \brief (US_IER_USART) No effect */
1550 #define   US_IER_USART_MANEA_1_Val        _U_(0x1)   /**< \brief (US_IER_USART) Enables the interrupt */
1551 #define US_IER_USART_MANEA_0        (US_IER_USART_MANEA_0_Val      << US_IER_USART_MANEA_Pos)
1552 #define US_IER_USART_MANEA_1        (US_IER_USART_MANEA_1_Val      << US_IER_USART_MANEA_Pos)
1553 #define US_IER_USART_MASK           _U_(0x011F3FE7) /**< \brief (US_IER_USART) MASK Register */
1554 
1555 // Any mode
1556 #define US_IER_RXRDY_Pos            0            /**< \brief (US_IER) Receiver Ready Interrupt Enable */
1557 #define US_IER_RXRDY                (_U_(0x1) << US_IER_RXRDY_Pos)
1558 #define   US_IER_RXRDY_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1559 #define   US_IER_RXRDY_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1560 #define US_IER_RXRDY_0              (US_IER_RXRDY_0_Val            << US_IER_RXRDY_Pos)
1561 #define US_IER_RXRDY_1              (US_IER_RXRDY_1_Val            << US_IER_RXRDY_Pos)
1562 #define US_IER_TXRDY_Pos            1            /**< \brief (US_IER) Transmitter Ready Interrupt Enable */
1563 #define US_IER_TXRDY                (_U_(0x1) << US_IER_TXRDY_Pos)
1564 #define   US_IER_TXRDY_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1565 #define   US_IER_TXRDY_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1566 #define US_IER_TXRDY_0              (US_IER_TXRDY_0_Val            << US_IER_TXRDY_Pos)
1567 #define US_IER_TXRDY_1              (US_IER_TXRDY_1_Val            << US_IER_TXRDY_Pos)
1568 #define US_IER_RXBRK_Pos            2            /**< \brief (US_IER) Receiver Break Interrupt Enable */
1569 #define US_IER_RXBRK                (_U_(0x1) << US_IER_RXBRK_Pos)
1570 #define   US_IER_RXBRK_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1571 #define   US_IER_RXBRK_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1572 #define US_IER_RXBRK_0              (US_IER_RXBRK_0_Val            << US_IER_RXBRK_Pos)
1573 #define US_IER_RXBRK_1              (US_IER_RXBRK_1_Val            << US_IER_RXBRK_Pos)
1574 #define US_IER_OVRE_Pos             5            /**< \brief (US_IER) Overrun Error Interrupt Enable */
1575 #define US_IER_OVRE                 (_U_(0x1) << US_IER_OVRE_Pos)
1576 #define   US_IER_OVRE_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1577 #define   US_IER_OVRE_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1578 #define US_IER_OVRE_0               (US_IER_OVRE_0_Val             << US_IER_OVRE_Pos)
1579 #define US_IER_OVRE_1               (US_IER_OVRE_1_Val             << US_IER_OVRE_Pos)
1580 #define US_IER_FRAME_Pos            6            /**< \brief (US_IER) Framing Error Interrupt Enable */
1581 #define US_IER_FRAME                (_U_(0x1) << US_IER_FRAME_Pos)
1582 #define   US_IER_FRAME_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1583 #define   US_IER_FRAME_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1584 #define US_IER_FRAME_0              (US_IER_FRAME_0_Val            << US_IER_FRAME_Pos)
1585 #define US_IER_FRAME_1              (US_IER_FRAME_1_Val            << US_IER_FRAME_Pos)
1586 #define US_IER_PARE_Pos             7            /**< \brief (US_IER) Parity Error Interrupt Enable */
1587 #define US_IER_PARE                 (_U_(0x1) << US_IER_PARE_Pos)
1588 #define   US_IER_PARE_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1589 #define   US_IER_PARE_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1590 #define US_IER_PARE_0               (US_IER_PARE_0_Val             << US_IER_PARE_Pos)
1591 #define US_IER_PARE_1               (US_IER_PARE_1_Val             << US_IER_PARE_Pos)
1592 #define US_IER_TIMEOUT_Pos          8            /**< \brief (US_IER) Time-out Interrupt Enable */
1593 #define US_IER_TIMEOUT              (_U_(0x1) << US_IER_TIMEOUT_Pos)
1594 #define   US_IER_TIMEOUT_0_Val            _U_(0x0)   /**< \brief (US_IER) No Effect */
1595 #define   US_IER_TIMEOUT_1_Val            _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1596 #define US_IER_TIMEOUT_0            (US_IER_TIMEOUT_0_Val          << US_IER_TIMEOUT_Pos)
1597 #define US_IER_TIMEOUT_1            (US_IER_TIMEOUT_1_Val          << US_IER_TIMEOUT_Pos)
1598 #define US_IER_TXEMPTY_Pos          9            /**< \brief (US_IER) Transmitter Empty Interrupt Enable */
1599 #define US_IER_TXEMPTY              (_U_(0x1) << US_IER_TXEMPTY_Pos)
1600 #define   US_IER_TXEMPTY_0_Val            _U_(0x0)   /**< \brief (US_IER) No Effect */
1601 #define   US_IER_TXEMPTY_1_Val            _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1602 #define US_IER_TXEMPTY_0            (US_IER_TXEMPTY_0_Val          << US_IER_TXEMPTY_Pos)
1603 #define US_IER_TXEMPTY_1            (US_IER_TXEMPTY_1_Val          << US_IER_TXEMPTY_Pos)
1604 #define US_IER_ITER_Pos             10           /**< \brief (US_IER) Iteration Interrupt Enable */
1605 #define US_IER_ITER                 (_U_(0x1) << US_IER_ITER_Pos)
1606 #define   US_IER_ITER_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1607 #define   US_IER_ITER_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1608 #define US_IER_ITER_0               (US_IER_ITER_0_Val             << US_IER_ITER_Pos)
1609 #define US_IER_ITER_1               (US_IER_ITER_1_Val             << US_IER_ITER_Pos)
1610 #define US_IER_UNRE_Pos             10           /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */
1611 #define US_IER_UNRE                 (_U_(0x1) << US_IER_UNRE_Pos)
1612 #define   US_IER_UNRE_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1613 #define   US_IER_UNRE_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1614 #define US_IER_UNRE_0               (US_IER_UNRE_0_Val             << US_IER_UNRE_Pos)
1615 #define US_IER_UNRE_1               (US_IER_UNRE_1_Val             << US_IER_UNRE_Pos)
1616 #define US_IER_ITER_Pos             10           /**< \brief (US_IER) Iteration Interrupt Enable */
1617 #define US_IER_ITER                 (_U_(0x1) << US_IER_ITER_Pos)
1618 #define   US_IER_ITER_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1619 #define   US_IER_ITER_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1620 #define US_IER_ITER_0               (US_IER_ITER_0_Val             << US_IER_ITER_Pos)
1621 #define US_IER_ITER_1               (US_IER_ITER_1_Val             << US_IER_ITER_Pos)
1622 #define US_IER_TXBUFE_Pos           11           /**< \brief (US_IER) Buffer Empty Interrupt Enable */
1623 #define US_IER_TXBUFE               (_U_(0x1) << US_IER_TXBUFE_Pos)
1624 #define   US_IER_TXBUFE_0_Val             _U_(0x0)   /**< \brief (US_IER) No Effect */
1625 #define   US_IER_TXBUFE_1_Val             _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1626 #define US_IER_TXBUFE_0             (US_IER_TXBUFE_0_Val           << US_IER_TXBUFE_Pos)
1627 #define US_IER_TXBUFE_1             (US_IER_TXBUFE_1_Val           << US_IER_TXBUFE_Pos)
1628 #define US_IER_RXBUFF_Pos           12           /**< \brief (US_IER) Buffer Full Interrupt Enable */
1629 #define US_IER_RXBUFF               (_U_(0x1) << US_IER_RXBUFF_Pos)
1630 #define   US_IER_RXBUFF_0_Val             _U_(0x0)   /**< \brief (US_IER) No Effect */
1631 #define   US_IER_RXBUFF_1_Val             _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1632 #define US_IER_RXBUFF_0             (US_IER_RXBUFF_0_Val           << US_IER_RXBUFF_Pos)
1633 #define US_IER_RXBUFF_1             (US_IER_RXBUFF_1_Val           << US_IER_RXBUFF_Pos)
1634 #define US_IER_NACK_Pos             13           /**< \brief (US_IER) Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Enable */
1635 #define US_IER_NACK                 (_U_(0x1) << US_IER_NACK_Pos)
1636 #define   US_IER_NACK_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1637 #define   US_IER_NACK_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1638 #define US_IER_NACK_0               (US_IER_NACK_0_Val             << US_IER_NACK_Pos)
1639 #define US_IER_NACK_1               (US_IER_NACK_1_Val             << US_IER_NACK_Pos)
1640 #define US_IER_LINID_Pos            14           /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */
1641 #define US_IER_LINID                (_U_(0x1) << US_IER_LINID_Pos)
1642 #define US_IER_LINTC_Pos            15           /**< \brief (US_IER) LIN Transfer Conpleted Interrupt Enable */
1643 #define US_IER_LINTC                (_U_(0x1) << US_IER_LINTC_Pos)
1644 #define US_IER_RIIC_Pos             16           /**< \brief (US_IER) Ring Indicator Input Change Enable */
1645 #define US_IER_RIIC                 (_U_(0x1) << US_IER_RIIC_Pos)
1646 #define   US_IER_RIIC_0_Val               _U_(0x0)   /**< \brief (US_IER) No Effect */
1647 #define   US_IER_RIIC_1_Val               _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1648 #define US_IER_RIIC_0               (US_IER_RIIC_0_Val             << US_IER_RIIC_Pos)
1649 #define US_IER_RIIC_1               (US_IER_RIIC_1_Val             << US_IER_RIIC_Pos)
1650 #define US_IER_DSRIC_Pos            17           /**< \brief (US_IER) Data Set Ready Input Change Enable */
1651 #define US_IER_DSRIC                (_U_(0x1) << US_IER_DSRIC_Pos)
1652 #define   US_IER_DSRIC_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1653 #define   US_IER_DSRIC_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1654 #define US_IER_DSRIC_0              (US_IER_DSRIC_0_Val            << US_IER_DSRIC_Pos)
1655 #define US_IER_DSRIC_1              (US_IER_DSRIC_1_Val            << US_IER_DSRIC_Pos)
1656 #define US_IER_DCDIC_Pos            18           /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
1657 #define US_IER_DCDIC                (_U_(0x1) << US_IER_DCDIC_Pos)
1658 #define   US_IER_DCDIC_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1659 #define   US_IER_DCDIC_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1660 #define US_IER_DCDIC_0              (US_IER_DCDIC_0_Val            << US_IER_DCDIC_Pos)
1661 #define US_IER_DCDIC_1              (US_IER_DCDIC_1_Val            << US_IER_DCDIC_Pos)
1662 #define US_IER_CTSIC_Pos            19           /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
1663 #define US_IER_CTSIC                (_U_(0x1) << US_IER_CTSIC_Pos)
1664 #define   US_IER_CTSIC_0_Val              _U_(0x0)   /**< \brief (US_IER) No Effect */
1665 #define   US_IER_CTSIC_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1666 #define US_IER_CTSIC_0              (US_IER_CTSIC_0_Val            << US_IER_CTSIC_Pos)
1667 #define US_IER_CTSIC_1              (US_IER_CTSIC_1_Val            << US_IER_CTSIC_Pos)
1668 #define US_IER_MANE_Pos             20           /**< \brief (US_IER) Manchester Error Interrupt Enable */
1669 #define US_IER_MANE                 (_U_(0x1) << US_IER_MANE_Pos)
1670 #define US_IER_MANEA_Pos            24           /**< \brief (US_IER) Manchester Error Interrupt Enable */
1671 #define US_IER_MANEA                (_U_(0x1) << US_IER_MANEA_Pos)
1672 #define   US_IER_MANEA_0_Val              _U_(0x0)   /**< \brief (US_IER) No effect */
1673 #define   US_IER_MANEA_1_Val              _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1674 #define US_IER_MANEA_0              (US_IER_MANEA_0_Val            << US_IER_MANEA_Pos)
1675 #define US_IER_MANEA_1              (US_IER_MANEA_1_Val            << US_IER_MANEA_Pos)
1676 #define US_IER_LINBE_Pos            25           /**< \brief (US_IER) LIN Bus Error Interrupt Enable */
1677 #define US_IER_LINBE                (_U_(0x1) << US_IER_LINBE_Pos)
1678 #define US_IER_LINISFE_Pos          26           /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */
1679 #define US_IER_LINISFE              (_U_(0x1) << US_IER_LINISFE_Pos)
1680 #define US_IER_LINIPE_Pos           27           /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */
1681 #define US_IER_LINIPE               (_U_(0x1) << US_IER_LINIPE_Pos)
1682 #define US_IER_LINCE_Pos            28           /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */
1683 #define US_IER_LINCE                (_U_(0x1) << US_IER_LINCE_Pos)
1684 #define US_IER_LINSNRE_Pos          29           /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */
1685 #define US_IER_LINSNRE              (_U_(0x1) << US_IER_LINSNRE_Pos)
1686 #define US_IER_LINSTE_Pos           30           /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */
1687 #define US_IER_LINSTE               (_U_(0x1) << US_IER_LINSTE_Pos)
1688 #define   US_IER_LINSTE_0_Val             _U_(0x0)   /**< \brief (US_IER) No Effect */
1689 #define   US_IER_LINSTE_1_Val             _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1690 #define US_IER_LINSTE_0             (US_IER_LINSTE_0_Val           << US_IER_LINSTE_Pos)
1691 #define US_IER_LINSTE_1             (US_IER_LINSTE_1_Val           << US_IER_LINSTE_Pos)
1692 #define US_IER_LINHTE_Pos           31           /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */
1693 #define US_IER_LINHTE               (_U_(0x1) << US_IER_LINHTE_Pos)
1694 #define   US_IER_LINHTE_0_Val             _U_(0x0)   /**< \brief (US_IER) No Effect */
1695 #define   US_IER_LINHTE_1_Val             _U_(0x1)   /**< \brief (US_IER) Enables the interrupt */
1696 #define US_IER_LINHTE_0             (US_IER_LINHTE_0_Val           << US_IER_LINHTE_Pos)
1697 #define US_IER_LINHTE_1             (US_IER_LINHTE_1_Val           << US_IER_LINHTE_Pos)
1698 #define US_IER_MASK                 _U_(0xFF1FFFE7) /**< \brief (US_IER) MASK Register */
1699 
1700 /* -------- US_IDR : (USART Offset: 0x0C) ( /W 32) Interrupt Disable Register -------- */
1701 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
1702 typedef union {
1703   struct { // LIN mode
1704     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready Interrupt Disable   */
1705     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready Interrupt Disable */
1706     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Disable   */
1707     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
1708     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Disable    */
1709     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Disable    */
1710     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Disable     */
1711     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Disable         */
1712     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty Interrupt Disable */
1713     uint32_t ITER:1;           /*!< bit:     10  Iteration Interrupt Disable        */
1714     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Disable     */
1715     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Disable      */
1716     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Disable */
1717     uint32_t LINID:1;          /*!< bit:     14  LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
1718     uint32_t LINTC:1;          /*!< bit:     15  LIN Transfer Conpleted Interrupt Disable */
1719     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Disable */
1720     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Disable */
1721     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Disable */
1722     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Disable */
1723     uint32_t :5;               /*!< bit: 20..24  Reserved                           */
1724     uint32_t LINBE:1;          /*!< bit:     25  LIN Bus Error Interrupt Disable    */
1725     uint32_t LINISFE:1;        /*!< bit:     26  LIN Inconsistent Synch Field Error Interrupt Disable */
1726     uint32_t LINIPE:1;         /*!< bit:     27  LIN Identifier Parity Interrupt Disable */
1727     uint32_t LINCE:1;          /*!< bit:     28  LIN Checksum Error Interrupt Disable */
1728     uint32_t LINSNRE:1;        /*!< bit:     29  LIN Slave Not Responding Error Interrupt Disable */
1729     uint32_t LINSTE:1;         /*!< bit:     30  LIN Synch Tolerance Error Interrupt Disable */
1730     uint32_t LINHTE:1;         /*!< bit:     31  LIN Header Timeout Error Interrupt Disable */
1731   } LIN;                       /*!< Structure used for LIN                          */
1732   struct { // SPI_SLAVE mode
1733     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready Interrupt Disable   */
1734     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready Interrupt Disable */
1735     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Disable   */
1736     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
1737     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Disable    */
1738     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Disable    */
1739     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Disable     */
1740     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Disable         */
1741     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty Interrupt Disable */
1742     uint32_t UNRE:1;           /*!< bit:     10  SPI Underrun Error Interrupt Disable */
1743     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Disable     */
1744     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Disable      */
1745     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge Interrupt Disable  */
1746     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
1747     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Disable */
1748     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Disable */
1749     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Disable */
1750     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Disable */
1751     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
1752   } SPI_SLAVE;                 /*!< Structure used for SPI_SLAVE                    */
1753   struct { // USART mode
1754     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready Interrupt Disable   */
1755     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready Interrupt Disable */
1756     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Disable   */
1757     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
1758     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Disable    */
1759     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Disable    */
1760     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Disable     */
1761     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Disable         */
1762     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty Interrupt Disable */
1763     uint32_t ITER:1;           /*!< bit:     10  Iteration Interrupt Disable        */
1764     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Disable     */
1765     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Disable      */
1766     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge Interrupt Disable  */
1767     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
1768     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Disable */
1769     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Disable */
1770     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Disable */
1771     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Disable */
1772     uint32_t MANE:1;           /*!< bit:     20  Manchester Error Interrupt Disable */
1773     uint32_t :3;               /*!< bit: 21..23  Reserved                           */
1774     uint32_t MANEA:1;          /*!< bit:     24  Manchester Error Interrupt Disable */
1775     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
1776   } USART;                     /*!< Structure used for USART                        */
1777   uint32_t reg;                /*!< Type      used for register access              */
1778 } US_IDR_Type;
1779 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1780 
1781 #define US_IDR_OFFSET               0x0C         /**< \brief (US_IDR offset) Interrupt Disable Register */
1782 #define US_IDR_RESETVALUE           _U_(0x00000000); /**< \brief (US_IDR reset_value) Interrupt Disable Register */
1783 
1784 // LIN mode
1785 #define US_IDR_LIN_RXRDY_Pos        0            /**< \brief (US_IDR_LIN) Receiver Ready Interrupt Disable */
1786 #define US_IDR_LIN_RXRDY            (_U_(0x1) << US_IDR_LIN_RXRDY_Pos)
1787 #define   US_IDR_LIN_RXRDY_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1788 #define   US_IDR_LIN_RXRDY_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1789 #define US_IDR_LIN_RXRDY_0          (US_IDR_LIN_RXRDY_0_Val        << US_IDR_LIN_RXRDY_Pos)
1790 #define US_IDR_LIN_RXRDY_1          (US_IDR_LIN_RXRDY_1_Val        << US_IDR_LIN_RXRDY_Pos)
1791 #define US_IDR_LIN_TXRDY_Pos        1            /**< \brief (US_IDR_LIN) Transmitter Ready Interrupt Disable */
1792 #define US_IDR_LIN_TXRDY            (_U_(0x1) << US_IDR_LIN_TXRDY_Pos)
1793 #define   US_IDR_LIN_TXRDY_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1794 #define   US_IDR_LIN_TXRDY_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1795 #define US_IDR_LIN_TXRDY_0          (US_IDR_LIN_TXRDY_0_Val        << US_IDR_LIN_TXRDY_Pos)
1796 #define US_IDR_LIN_TXRDY_1          (US_IDR_LIN_TXRDY_1_Val        << US_IDR_LIN_TXRDY_Pos)
1797 #define US_IDR_LIN_RXBRK_Pos        2            /**< \brief (US_IDR_LIN) Receiver Break Interrupt Disable */
1798 #define US_IDR_LIN_RXBRK            (_U_(0x1) << US_IDR_LIN_RXBRK_Pos)
1799 #define   US_IDR_LIN_RXBRK_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1800 #define   US_IDR_LIN_RXBRK_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1801 #define US_IDR_LIN_RXBRK_0          (US_IDR_LIN_RXBRK_0_Val        << US_IDR_LIN_RXBRK_Pos)
1802 #define US_IDR_LIN_RXBRK_1          (US_IDR_LIN_RXBRK_1_Val        << US_IDR_LIN_RXBRK_Pos)
1803 #define US_IDR_LIN_OVRE_Pos         5            /**< \brief (US_IDR_LIN) Overrun Error Interrupt Disable */
1804 #define US_IDR_LIN_OVRE             (_U_(0x1) << US_IDR_LIN_OVRE_Pos)
1805 #define   US_IDR_LIN_OVRE_0_Val           _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1806 #define   US_IDR_LIN_OVRE_1_Val           _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1807 #define US_IDR_LIN_OVRE_0           (US_IDR_LIN_OVRE_0_Val         << US_IDR_LIN_OVRE_Pos)
1808 #define US_IDR_LIN_OVRE_1           (US_IDR_LIN_OVRE_1_Val         << US_IDR_LIN_OVRE_Pos)
1809 #define US_IDR_LIN_FRAME_Pos        6            /**< \brief (US_IDR_LIN) Framing Error Interrupt Disable */
1810 #define US_IDR_LIN_FRAME            (_U_(0x1) << US_IDR_LIN_FRAME_Pos)
1811 #define   US_IDR_LIN_FRAME_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1812 #define   US_IDR_LIN_FRAME_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1813 #define US_IDR_LIN_FRAME_0          (US_IDR_LIN_FRAME_0_Val        << US_IDR_LIN_FRAME_Pos)
1814 #define US_IDR_LIN_FRAME_1          (US_IDR_LIN_FRAME_1_Val        << US_IDR_LIN_FRAME_Pos)
1815 #define US_IDR_LIN_PARE_Pos         7            /**< \brief (US_IDR_LIN) Parity Error Interrupt Disable */
1816 #define US_IDR_LIN_PARE             (_U_(0x1) << US_IDR_LIN_PARE_Pos)
1817 #define   US_IDR_LIN_PARE_0_Val           _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1818 #define   US_IDR_LIN_PARE_1_Val           _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1819 #define US_IDR_LIN_PARE_0           (US_IDR_LIN_PARE_0_Val         << US_IDR_LIN_PARE_Pos)
1820 #define US_IDR_LIN_PARE_1           (US_IDR_LIN_PARE_1_Val         << US_IDR_LIN_PARE_Pos)
1821 #define US_IDR_LIN_TIMEOUT_Pos      8            /**< \brief (US_IDR_LIN) Time-out Interrupt Disable */
1822 #define US_IDR_LIN_TIMEOUT          (_U_(0x1) << US_IDR_LIN_TIMEOUT_Pos)
1823 #define   US_IDR_LIN_TIMEOUT_0_Val        _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1824 #define   US_IDR_LIN_TIMEOUT_1_Val        _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1825 #define US_IDR_LIN_TIMEOUT_0        (US_IDR_LIN_TIMEOUT_0_Val      << US_IDR_LIN_TIMEOUT_Pos)
1826 #define US_IDR_LIN_TIMEOUT_1        (US_IDR_LIN_TIMEOUT_1_Val      << US_IDR_LIN_TIMEOUT_Pos)
1827 #define US_IDR_LIN_TXEMPTY_Pos      9            /**< \brief (US_IDR_LIN) Transmitter Empty Interrupt Disable */
1828 #define US_IDR_LIN_TXEMPTY          (_U_(0x1) << US_IDR_LIN_TXEMPTY_Pos)
1829 #define   US_IDR_LIN_TXEMPTY_0_Val        _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1830 #define   US_IDR_LIN_TXEMPTY_1_Val        _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1831 #define US_IDR_LIN_TXEMPTY_0        (US_IDR_LIN_TXEMPTY_0_Val      << US_IDR_LIN_TXEMPTY_Pos)
1832 #define US_IDR_LIN_TXEMPTY_1        (US_IDR_LIN_TXEMPTY_1_Val      << US_IDR_LIN_TXEMPTY_Pos)
1833 #define US_IDR_LIN_ITER_Pos         10           /**< \brief (US_IDR_LIN) Iteration Interrupt Disable */
1834 #define US_IDR_LIN_ITER             (_U_(0x1) << US_IDR_LIN_ITER_Pos)
1835 #define   US_IDR_LIN_ITER_0_Val           _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1836 #define   US_IDR_LIN_ITER_1_Val           _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1837 #define US_IDR_LIN_ITER_0           (US_IDR_LIN_ITER_0_Val         << US_IDR_LIN_ITER_Pos)
1838 #define US_IDR_LIN_ITER_1           (US_IDR_LIN_ITER_1_Val         << US_IDR_LIN_ITER_Pos)
1839 #define US_IDR_LIN_TXBUFE_Pos       11           /**< \brief (US_IDR_LIN) Buffer Empty Interrupt Disable */
1840 #define US_IDR_LIN_TXBUFE           (_U_(0x1) << US_IDR_LIN_TXBUFE_Pos)
1841 #define   US_IDR_LIN_TXBUFE_0_Val         _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1842 #define   US_IDR_LIN_TXBUFE_1_Val         _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1843 #define US_IDR_LIN_TXBUFE_0         (US_IDR_LIN_TXBUFE_0_Val       << US_IDR_LIN_TXBUFE_Pos)
1844 #define US_IDR_LIN_TXBUFE_1         (US_IDR_LIN_TXBUFE_1_Val       << US_IDR_LIN_TXBUFE_Pos)
1845 #define US_IDR_LIN_RXBUFF_Pos       12           /**< \brief (US_IDR_LIN) Buffer Full Interrupt Disable */
1846 #define US_IDR_LIN_RXBUFF           (_U_(0x1) << US_IDR_LIN_RXBUFF_Pos)
1847 #define   US_IDR_LIN_RXBUFF_0_Val         _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1848 #define   US_IDR_LIN_RXBUFF_1_Val         _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1849 #define US_IDR_LIN_RXBUFF_0         (US_IDR_LIN_RXBUFF_0_Val       << US_IDR_LIN_RXBUFF_Pos)
1850 #define US_IDR_LIN_RXBUFF_1         (US_IDR_LIN_RXBUFF_1_Val       << US_IDR_LIN_RXBUFF_Pos)
1851 #define US_IDR_LIN_NACK_Pos         13           /**< \brief (US_IDR_LIN) Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Disable */
1852 #define US_IDR_LIN_NACK             (_U_(0x1) << US_IDR_LIN_NACK_Pos)
1853 #define   US_IDR_LIN_NACK_0_Val           _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1854 #define   US_IDR_LIN_NACK_1_Val           _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1855 #define US_IDR_LIN_NACK_0           (US_IDR_LIN_NACK_0_Val         << US_IDR_LIN_NACK_Pos)
1856 #define US_IDR_LIN_NACK_1           (US_IDR_LIN_NACK_1_Val         << US_IDR_LIN_NACK_Pos)
1857 #define US_IDR_LIN_LINID_Pos        14           /**< \brief (US_IDR_LIN) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
1858 #define US_IDR_LIN_LINID            (_U_(0x1) << US_IDR_LIN_LINID_Pos)
1859 #define US_IDR_LIN_LINTC_Pos        15           /**< \brief (US_IDR_LIN) LIN Transfer Conpleted Interrupt Disable */
1860 #define US_IDR_LIN_LINTC            (_U_(0x1) << US_IDR_LIN_LINTC_Pos)
1861 #define US_IDR_LIN_RIIC_Pos         16           /**< \brief (US_IDR_LIN) Ring Indicator Input Change Disable */
1862 #define US_IDR_LIN_RIIC             (_U_(0x1) << US_IDR_LIN_RIIC_Pos)
1863 #define   US_IDR_LIN_RIIC_0_Val           _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1864 #define   US_IDR_LIN_RIIC_1_Val           _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1865 #define US_IDR_LIN_RIIC_0           (US_IDR_LIN_RIIC_0_Val         << US_IDR_LIN_RIIC_Pos)
1866 #define US_IDR_LIN_RIIC_1           (US_IDR_LIN_RIIC_1_Val         << US_IDR_LIN_RIIC_Pos)
1867 #define US_IDR_LIN_DSRIC_Pos        17           /**< \brief (US_IDR_LIN) Data Set Ready Input Change Disable */
1868 #define US_IDR_LIN_DSRIC            (_U_(0x1) << US_IDR_LIN_DSRIC_Pos)
1869 #define   US_IDR_LIN_DSRIC_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1870 #define   US_IDR_LIN_DSRIC_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1871 #define US_IDR_LIN_DSRIC_0          (US_IDR_LIN_DSRIC_0_Val        << US_IDR_LIN_DSRIC_Pos)
1872 #define US_IDR_LIN_DSRIC_1          (US_IDR_LIN_DSRIC_1_Val        << US_IDR_LIN_DSRIC_Pos)
1873 #define US_IDR_LIN_DCDIC_Pos        18           /**< \brief (US_IDR_LIN) Data Carrier Detect Input Change Interrupt Disable */
1874 #define US_IDR_LIN_DCDIC            (_U_(0x1) << US_IDR_LIN_DCDIC_Pos)
1875 #define   US_IDR_LIN_DCDIC_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1876 #define   US_IDR_LIN_DCDIC_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1877 #define US_IDR_LIN_DCDIC_0          (US_IDR_LIN_DCDIC_0_Val        << US_IDR_LIN_DCDIC_Pos)
1878 #define US_IDR_LIN_DCDIC_1          (US_IDR_LIN_DCDIC_1_Val        << US_IDR_LIN_DCDIC_Pos)
1879 #define US_IDR_LIN_CTSIC_Pos        19           /**< \brief (US_IDR_LIN) Clear to Send Input Change Interrupt Disable */
1880 #define US_IDR_LIN_CTSIC            (_U_(0x1) << US_IDR_LIN_CTSIC_Pos)
1881 #define   US_IDR_LIN_CTSIC_0_Val          _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1882 #define   US_IDR_LIN_CTSIC_1_Val          _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1883 #define US_IDR_LIN_CTSIC_0          (US_IDR_LIN_CTSIC_0_Val        << US_IDR_LIN_CTSIC_Pos)
1884 #define US_IDR_LIN_CTSIC_1          (US_IDR_LIN_CTSIC_1_Val        << US_IDR_LIN_CTSIC_Pos)
1885 #define US_IDR_LIN_LINBE_Pos        25           /**< \brief (US_IDR_LIN) LIN Bus Error Interrupt Disable */
1886 #define US_IDR_LIN_LINBE            (_U_(0x1) << US_IDR_LIN_LINBE_Pos)
1887 #define US_IDR_LIN_LINISFE_Pos      26           /**< \brief (US_IDR_LIN) LIN Inconsistent Synch Field Error Interrupt Disable */
1888 #define US_IDR_LIN_LINISFE          (_U_(0x1) << US_IDR_LIN_LINISFE_Pos)
1889 #define US_IDR_LIN_LINIPE_Pos       27           /**< \brief (US_IDR_LIN) LIN Identifier Parity Interrupt Disable */
1890 #define US_IDR_LIN_LINIPE           (_U_(0x1) << US_IDR_LIN_LINIPE_Pos)
1891 #define US_IDR_LIN_LINCE_Pos        28           /**< \brief (US_IDR_LIN) LIN Checksum Error Interrupt Disable */
1892 #define US_IDR_LIN_LINCE            (_U_(0x1) << US_IDR_LIN_LINCE_Pos)
1893 #define US_IDR_LIN_LINSNRE_Pos      29           /**< \brief (US_IDR_LIN) LIN Slave Not Responding Error Interrupt Disable */
1894 #define US_IDR_LIN_LINSNRE          (_U_(0x1) << US_IDR_LIN_LINSNRE_Pos)
1895 #define US_IDR_LIN_LINSTE_Pos       30           /**< \brief (US_IDR_LIN) LIN Synch Tolerance Error Interrupt Disable */
1896 #define US_IDR_LIN_LINSTE           (_U_(0x1) << US_IDR_LIN_LINSTE_Pos)
1897 #define   US_IDR_LIN_LINSTE_0_Val         _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1898 #define   US_IDR_LIN_LINSTE_1_Val         _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1899 #define US_IDR_LIN_LINSTE_0         (US_IDR_LIN_LINSTE_0_Val       << US_IDR_LIN_LINSTE_Pos)
1900 #define US_IDR_LIN_LINSTE_1         (US_IDR_LIN_LINSTE_1_Val       << US_IDR_LIN_LINSTE_Pos)
1901 #define US_IDR_LIN_LINHTE_Pos       31           /**< \brief (US_IDR_LIN) LIN Header Timeout Error Interrupt Disable */
1902 #define US_IDR_LIN_LINHTE           (_U_(0x1) << US_IDR_LIN_LINHTE_Pos)
1903 #define   US_IDR_LIN_LINHTE_0_Val         _U_(0x0)   /**< \brief (US_IDR_LIN) No Effect */
1904 #define   US_IDR_LIN_LINHTE_1_Val         _U_(0x1)   /**< \brief (US_IDR_LIN) Disables the interrupt */
1905 #define US_IDR_LIN_LINHTE_0         (US_IDR_LIN_LINHTE_0_Val       << US_IDR_LIN_LINHTE_Pos)
1906 #define US_IDR_LIN_LINHTE_1         (US_IDR_LIN_LINHTE_1_Val       << US_IDR_LIN_LINHTE_Pos)
1907 #define US_IDR_LIN_MASK             _U_(0xFE0FFFE7) /**< \brief (US_IDR_LIN) MASK Register */
1908 
1909 // SPI_SLAVE mode
1910 #define US_IDR_SPI_SLAVE_RXRDY_Pos  0            /**< \brief (US_IDR_SPI_SLAVE) Receiver Ready Interrupt Disable */
1911 #define US_IDR_SPI_SLAVE_RXRDY      (_U_(0x1) << US_IDR_SPI_SLAVE_RXRDY_Pos)
1912 #define   US_IDR_SPI_SLAVE_RXRDY_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1913 #define   US_IDR_SPI_SLAVE_RXRDY_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1914 #define US_IDR_SPI_SLAVE_RXRDY_0    (US_IDR_SPI_SLAVE_RXRDY_0_Val  << US_IDR_SPI_SLAVE_RXRDY_Pos)
1915 #define US_IDR_SPI_SLAVE_RXRDY_1    (US_IDR_SPI_SLAVE_RXRDY_1_Val  << US_IDR_SPI_SLAVE_RXRDY_Pos)
1916 #define US_IDR_SPI_SLAVE_TXRDY_Pos  1            /**< \brief (US_IDR_SPI_SLAVE) Transmitter Ready Interrupt Disable */
1917 #define US_IDR_SPI_SLAVE_TXRDY      (_U_(0x1) << US_IDR_SPI_SLAVE_TXRDY_Pos)
1918 #define   US_IDR_SPI_SLAVE_TXRDY_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1919 #define   US_IDR_SPI_SLAVE_TXRDY_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1920 #define US_IDR_SPI_SLAVE_TXRDY_0    (US_IDR_SPI_SLAVE_TXRDY_0_Val  << US_IDR_SPI_SLAVE_TXRDY_Pos)
1921 #define US_IDR_SPI_SLAVE_TXRDY_1    (US_IDR_SPI_SLAVE_TXRDY_1_Val  << US_IDR_SPI_SLAVE_TXRDY_Pos)
1922 #define US_IDR_SPI_SLAVE_RXBRK_Pos  2            /**< \brief (US_IDR_SPI_SLAVE) Receiver Break Interrupt Disable */
1923 #define US_IDR_SPI_SLAVE_RXBRK      (_U_(0x1) << US_IDR_SPI_SLAVE_RXBRK_Pos)
1924 #define   US_IDR_SPI_SLAVE_RXBRK_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1925 #define   US_IDR_SPI_SLAVE_RXBRK_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1926 #define US_IDR_SPI_SLAVE_RXBRK_0    (US_IDR_SPI_SLAVE_RXBRK_0_Val  << US_IDR_SPI_SLAVE_RXBRK_Pos)
1927 #define US_IDR_SPI_SLAVE_RXBRK_1    (US_IDR_SPI_SLAVE_RXBRK_1_Val  << US_IDR_SPI_SLAVE_RXBRK_Pos)
1928 #define US_IDR_SPI_SLAVE_OVRE_Pos   5            /**< \brief (US_IDR_SPI_SLAVE) Overrun Error Interrupt Disable */
1929 #define US_IDR_SPI_SLAVE_OVRE       (_U_(0x1) << US_IDR_SPI_SLAVE_OVRE_Pos)
1930 #define   US_IDR_SPI_SLAVE_OVRE_0_Val     _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1931 #define   US_IDR_SPI_SLAVE_OVRE_1_Val     _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1932 #define US_IDR_SPI_SLAVE_OVRE_0     (US_IDR_SPI_SLAVE_OVRE_0_Val   << US_IDR_SPI_SLAVE_OVRE_Pos)
1933 #define US_IDR_SPI_SLAVE_OVRE_1     (US_IDR_SPI_SLAVE_OVRE_1_Val   << US_IDR_SPI_SLAVE_OVRE_Pos)
1934 #define US_IDR_SPI_SLAVE_FRAME_Pos  6            /**< \brief (US_IDR_SPI_SLAVE) Framing Error Interrupt Disable */
1935 #define US_IDR_SPI_SLAVE_FRAME      (_U_(0x1) << US_IDR_SPI_SLAVE_FRAME_Pos)
1936 #define   US_IDR_SPI_SLAVE_FRAME_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1937 #define   US_IDR_SPI_SLAVE_FRAME_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1938 #define US_IDR_SPI_SLAVE_FRAME_0    (US_IDR_SPI_SLAVE_FRAME_0_Val  << US_IDR_SPI_SLAVE_FRAME_Pos)
1939 #define US_IDR_SPI_SLAVE_FRAME_1    (US_IDR_SPI_SLAVE_FRAME_1_Val  << US_IDR_SPI_SLAVE_FRAME_Pos)
1940 #define US_IDR_SPI_SLAVE_PARE_Pos   7            /**< \brief (US_IDR_SPI_SLAVE) Parity Error Interrupt Disable */
1941 #define US_IDR_SPI_SLAVE_PARE       (_U_(0x1) << US_IDR_SPI_SLAVE_PARE_Pos)
1942 #define   US_IDR_SPI_SLAVE_PARE_0_Val     _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1943 #define   US_IDR_SPI_SLAVE_PARE_1_Val     _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1944 #define US_IDR_SPI_SLAVE_PARE_0     (US_IDR_SPI_SLAVE_PARE_0_Val   << US_IDR_SPI_SLAVE_PARE_Pos)
1945 #define US_IDR_SPI_SLAVE_PARE_1     (US_IDR_SPI_SLAVE_PARE_1_Val   << US_IDR_SPI_SLAVE_PARE_Pos)
1946 #define US_IDR_SPI_SLAVE_TIMEOUT_Pos 8            /**< \brief (US_IDR_SPI_SLAVE) Time-out Interrupt Disable */
1947 #define US_IDR_SPI_SLAVE_TIMEOUT    (_U_(0x1) << US_IDR_SPI_SLAVE_TIMEOUT_Pos)
1948 #define   US_IDR_SPI_SLAVE_TIMEOUT_0_Val  _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1949 #define   US_IDR_SPI_SLAVE_TIMEOUT_1_Val  _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1950 #define US_IDR_SPI_SLAVE_TIMEOUT_0  (US_IDR_SPI_SLAVE_TIMEOUT_0_Val << US_IDR_SPI_SLAVE_TIMEOUT_Pos)
1951 #define US_IDR_SPI_SLAVE_TIMEOUT_1  (US_IDR_SPI_SLAVE_TIMEOUT_1_Val << US_IDR_SPI_SLAVE_TIMEOUT_Pos)
1952 #define US_IDR_SPI_SLAVE_TXEMPTY_Pos 9            /**< \brief (US_IDR_SPI_SLAVE) Transmitter Empty Interrupt Disable */
1953 #define US_IDR_SPI_SLAVE_TXEMPTY    (_U_(0x1) << US_IDR_SPI_SLAVE_TXEMPTY_Pos)
1954 #define   US_IDR_SPI_SLAVE_TXEMPTY_0_Val  _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1955 #define   US_IDR_SPI_SLAVE_TXEMPTY_1_Val  _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1956 #define US_IDR_SPI_SLAVE_TXEMPTY_0  (US_IDR_SPI_SLAVE_TXEMPTY_0_Val << US_IDR_SPI_SLAVE_TXEMPTY_Pos)
1957 #define US_IDR_SPI_SLAVE_TXEMPTY_1  (US_IDR_SPI_SLAVE_TXEMPTY_1_Val << US_IDR_SPI_SLAVE_TXEMPTY_Pos)
1958 #define US_IDR_SPI_SLAVE_UNRE_Pos   10           /**< \brief (US_IDR_SPI_SLAVE) SPI Underrun Error Interrupt Disable */
1959 #define US_IDR_SPI_SLAVE_UNRE       (_U_(0x1) << US_IDR_SPI_SLAVE_UNRE_Pos)
1960 #define   US_IDR_SPI_SLAVE_UNRE_0_Val     _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1961 #define   US_IDR_SPI_SLAVE_UNRE_1_Val     _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1962 #define US_IDR_SPI_SLAVE_UNRE_0     (US_IDR_SPI_SLAVE_UNRE_0_Val   << US_IDR_SPI_SLAVE_UNRE_Pos)
1963 #define US_IDR_SPI_SLAVE_UNRE_1     (US_IDR_SPI_SLAVE_UNRE_1_Val   << US_IDR_SPI_SLAVE_UNRE_Pos)
1964 #define US_IDR_SPI_SLAVE_TXBUFE_Pos 11           /**< \brief (US_IDR_SPI_SLAVE) Buffer Empty Interrupt Disable */
1965 #define US_IDR_SPI_SLAVE_TXBUFE     (_U_(0x1) << US_IDR_SPI_SLAVE_TXBUFE_Pos)
1966 #define   US_IDR_SPI_SLAVE_TXBUFE_0_Val   _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1967 #define   US_IDR_SPI_SLAVE_TXBUFE_1_Val   _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1968 #define US_IDR_SPI_SLAVE_TXBUFE_0   (US_IDR_SPI_SLAVE_TXBUFE_0_Val << US_IDR_SPI_SLAVE_TXBUFE_Pos)
1969 #define US_IDR_SPI_SLAVE_TXBUFE_1   (US_IDR_SPI_SLAVE_TXBUFE_1_Val << US_IDR_SPI_SLAVE_TXBUFE_Pos)
1970 #define US_IDR_SPI_SLAVE_RXBUFF_Pos 12           /**< \brief (US_IDR_SPI_SLAVE) Buffer Full Interrupt Disable */
1971 #define US_IDR_SPI_SLAVE_RXBUFF     (_U_(0x1) << US_IDR_SPI_SLAVE_RXBUFF_Pos)
1972 #define   US_IDR_SPI_SLAVE_RXBUFF_0_Val   _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1973 #define   US_IDR_SPI_SLAVE_RXBUFF_1_Val   _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1974 #define US_IDR_SPI_SLAVE_RXBUFF_0   (US_IDR_SPI_SLAVE_RXBUFF_0_Val << US_IDR_SPI_SLAVE_RXBUFF_Pos)
1975 #define US_IDR_SPI_SLAVE_RXBUFF_1   (US_IDR_SPI_SLAVE_RXBUFF_1_Val << US_IDR_SPI_SLAVE_RXBUFF_Pos)
1976 #define US_IDR_SPI_SLAVE_NACK_Pos   13           /**< \brief (US_IDR_SPI_SLAVE) Non Acknowledge Interrupt Disable */
1977 #define US_IDR_SPI_SLAVE_NACK       (_U_(0x1) << US_IDR_SPI_SLAVE_NACK_Pos)
1978 #define   US_IDR_SPI_SLAVE_NACK_0_Val     _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1979 #define   US_IDR_SPI_SLAVE_NACK_1_Val     _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1980 #define US_IDR_SPI_SLAVE_NACK_0     (US_IDR_SPI_SLAVE_NACK_0_Val   << US_IDR_SPI_SLAVE_NACK_Pos)
1981 #define US_IDR_SPI_SLAVE_NACK_1     (US_IDR_SPI_SLAVE_NACK_1_Val   << US_IDR_SPI_SLAVE_NACK_Pos)
1982 #define US_IDR_SPI_SLAVE_RIIC_Pos   16           /**< \brief (US_IDR_SPI_SLAVE) Ring Indicator Input Change Disable */
1983 #define US_IDR_SPI_SLAVE_RIIC       (_U_(0x1) << US_IDR_SPI_SLAVE_RIIC_Pos)
1984 #define   US_IDR_SPI_SLAVE_RIIC_0_Val     _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1985 #define   US_IDR_SPI_SLAVE_RIIC_1_Val     _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1986 #define US_IDR_SPI_SLAVE_RIIC_0     (US_IDR_SPI_SLAVE_RIIC_0_Val   << US_IDR_SPI_SLAVE_RIIC_Pos)
1987 #define US_IDR_SPI_SLAVE_RIIC_1     (US_IDR_SPI_SLAVE_RIIC_1_Val   << US_IDR_SPI_SLAVE_RIIC_Pos)
1988 #define US_IDR_SPI_SLAVE_DSRIC_Pos  17           /**< \brief (US_IDR_SPI_SLAVE) Data Set Ready Input Change Disable */
1989 #define US_IDR_SPI_SLAVE_DSRIC      (_U_(0x1) << US_IDR_SPI_SLAVE_DSRIC_Pos)
1990 #define   US_IDR_SPI_SLAVE_DSRIC_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1991 #define   US_IDR_SPI_SLAVE_DSRIC_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1992 #define US_IDR_SPI_SLAVE_DSRIC_0    (US_IDR_SPI_SLAVE_DSRIC_0_Val  << US_IDR_SPI_SLAVE_DSRIC_Pos)
1993 #define US_IDR_SPI_SLAVE_DSRIC_1    (US_IDR_SPI_SLAVE_DSRIC_1_Val  << US_IDR_SPI_SLAVE_DSRIC_Pos)
1994 #define US_IDR_SPI_SLAVE_DCDIC_Pos  18           /**< \brief (US_IDR_SPI_SLAVE) Data Carrier Detect Input Change Interrupt Disable */
1995 #define US_IDR_SPI_SLAVE_DCDIC      (_U_(0x1) << US_IDR_SPI_SLAVE_DCDIC_Pos)
1996 #define   US_IDR_SPI_SLAVE_DCDIC_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
1997 #define   US_IDR_SPI_SLAVE_DCDIC_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
1998 #define US_IDR_SPI_SLAVE_DCDIC_0    (US_IDR_SPI_SLAVE_DCDIC_0_Val  << US_IDR_SPI_SLAVE_DCDIC_Pos)
1999 #define US_IDR_SPI_SLAVE_DCDIC_1    (US_IDR_SPI_SLAVE_DCDIC_1_Val  << US_IDR_SPI_SLAVE_DCDIC_Pos)
2000 #define US_IDR_SPI_SLAVE_CTSIC_Pos  19           /**< \brief (US_IDR_SPI_SLAVE) Clear to Send Input Change Interrupt Disable */
2001 #define US_IDR_SPI_SLAVE_CTSIC      (_U_(0x1) << US_IDR_SPI_SLAVE_CTSIC_Pos)
2002 #define   US_IDR_SPI_SLAVE_CTSIC_0_Val    _U_(0x0)   /**< \brief (US_IDR_SPI_SLAVE) No Effect */
2003 #define   US_IDR_SPI_SLAVE_CTSIC_1_Val    _U_(0x1)   /**< \brief (US_IDR_SPI_SLAVE) Disables the interrupt */
2004 #define US_IDR_SPI_SLAVE_CTSIC_0    (US_IDR_SPI_SLAVE_CTSIC_0_Val  << US_IDR_SPI_SLAVE_CTSIC_Pos)
2005 #define US_IDR_SPI_SLAVE_CTSIC_1    (US_IDR_SPI_SLAVE_CTSIC_1_Val  << US_IDR_SPI_SLAVE_CTSIC_Pos)
2006 #define US_IDR_SPI_SLAVE_MASK       _U_(0x000F3FE7) /**< \brief (US_IDR_SPI_SLAVE) MASK Register */
2007 
2008 // USART mode
2009 #define US_IDR_USART_RXRDY_Pos      0            /**< \brief (US_IDR_USART) Receiver Ready Interrupt Disable */
2010 #define US_IDR_USART_RXRDY          (_U_(0x1) << US_IDR_USART_RXRDY_Pos)
2011 #define   US_IDR_USART_RXRDY_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2012 #define   US_IDR_USART_RXRDY_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2013 #define US_IDR_USART_RXRDY_0        (US_IDR_USART_RXRDY_0_Val      << US_IDR_USART_RXRDY_Pos)
2014 #define US_IDR_USART_RXRDY_1        (US_IDR_USART_RXRDY_1_Val      << US_IDR_USART_RXRDY_Pos)
2015 #define US_IDR_USART_TXRDY_Pos      1            /**< \brief (US_IDR_USART) Transmitter Ready Interrupt Disable */
2016 #define US_IDR_USART_TXRDY          (_U_(0x1) << US_IDR_USART_TXRDY_Pos)
2017 #define   US_IDR_USART_TXRDY_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2018 #define   US_IDR_USART_TXRDY_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2019 #define US_IDR_USART_TXRDY_0        (US_IDR_USART_TXRDY_0_Val      << US_IDR_USART_TXRDY_Pos)
2020 #define US_IDR_USART_TXRDY_1        (US_IDR_USART_TXRDY_1_Val      << US_IDR_USART_TXRDY_Pos)
2021 #define US_IDR_USART_RXBRK_Pos      2            /**< \brief (US_IDR_USART) Receiver Break Interrupt Disable */
2022 #define US_IDR_USART_RXBRK          (_U_(0x1) << US_IDR_USART_RXBRK_Pos)
2023 #define   US_IDR_USART_RXBRK_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2024 #define   US_IDR_USART_RXBRK_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2025 #define US_IDR_USART_RXBRK_0        (US_IDR_USART_RXBRK_0_Val      << US_IDR_USART_RXBRK_Pos)
2026 #define US_IDR_USART_RXBRK_1        (US_IDR_USART_RXBRK_1_Val      << US_IDR_USART_RXBRK_Pos)
2027 #define US_IDR_USART_OVRE_Pos       5            /**< \brief (US_IDR_USART) Overrun Error Interrupt Disable */
2028 #define US_IDR_USART_OVRE           (_U_(0x1) << US_IDR_USART_OVRE_Pos)
2029 #define   US_IDR_USART_OVRE_0_Val         _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2030 #define   US_IDR_USART_OVRE_1_Val         _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2031 #define US_IDR_USART_OVRE_0         (US_IDR_USART_OVRE_0_Val       << US_IDR_USART_OVRE_Pos)
2032 #define US_IDR_USART_OVRE_1         (US_IDR_USART_OVRE_1_Val       << US_IDR_USART_OVRE_Pos)
2033 #define US_IDR_USART_FRAME_Pos      6            /**< \brief (US_IDR_USART) Framing Error Interrupt Disable */
2034 #define US_IDR_USART_FRAME          (_U_(0x1) << US_IDR_USART_FRAME_Pos)
2035 #define   US_IDR_USART_FRAME_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2036 #define   US_IDR_USART_FRAME_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2037 #define US_IDR_USART_FRAME_0        (US_IDR_USART_FRAME_0_Val      << US_IDR_USART_FRAME_Pos)
2038 #define US_IDR_USART_FRAME_1        (US_IDR_USART_FRAME_1_Val      << US_IDR_USART_FRAME_Pos)
2039 #define US_IDR_USART_PARE_Pos       7            /**< \brief (US_IDR_USART) Parity Error Interrupt Disable */
2040 #define US_IDR_USART_PARE           (_U_(0x1) << US_IDR_USART_PARE_Pos)
2041 #define   US_IDR_USART_PARE_0_Val         _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2042 #define   US_IDR_USART_PARE_1_Val         _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2043 #define US_IDR_USART_PARE_0         (US_IDR_USART_PARE_0_Val       << US_IDR_USART_PARE_Pos)
2044 #define US_IDR_USART_PARE_1         (US_IDR_USART_PARE_1_Val       << US_IDR_USART_PARE_Pos)
2045 #define US_IDR_USART_TIMEOUT_Pos    8            /**< \brief (US_IDR_USART) Time-out Interrupt Disable */
2046 #define US_IDR_USART_TIMEOUT        (_U_(0x1) << US_IDR_USART_TIMEOUT_Pos)
2047 #define   US_IDR_USART_TIMEOUT_0_Val      _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2048 #define   US_IDR_USART_TIMEOUT_1_Val      _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2049 #define US_IDR_USART_TIMEOUT_0      (US_IDR_USART_TIMEOUT_0_Val    << US_IDR_USART_TIMEOUT_Pos)
2050 #define US_IDR_USART_TIMEOUT_1      (US_IDR_USART_TIMEOUT_1_Val    << US_IDR_USART_TIMEOUT_Pos)
2051 #define US_IDR_USART_TXEMPTY_Pos    9            /**< \brief (US_IDR_USART) Transmitter Empty Interrupt Disable */
2052 #define US_IDR_USART_TXEMPTY        (_U_(0x1) << US_IDR_USART_TXEMPTY_Pos)
2053 #define   US_IDR_USART_TXEMPTY_0_Val      _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2054 #define   US_IDR_USART_TXEMPTY_1_Val      _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2055 #define US_IDR_USART_TXEMPTY_0      (US_IDR_USART_TXEMPTY_0_Val    << US_IDR_USART_TXEMPTY_Pos)
2056 #define US_IDR_USART_TXEMPTY_1      (US_IDR_USART_TXEMPTY_1_Val    << US_IDR_USART_TXEMPTY_Pos)
2057 #define US_IDR_USART_ITER_Pos       10           /**< \brief (US_IDR_USART) Iteration Interrupt Disable */
2058 #define US_IDR_USART_ITER           (_U_(0x1) << US_IDR_USART_ITER_Pos)
2059 #define   US_IDR_USART_ITER_0_Val         _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2060 #define   US_IDR_USART_ITER_1_Val         _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2061 #define US_IDR_USART_ITER_0         (US_IDR_USART_ITER_0_Val       << US_IDR_USART_ITER_Pos)
2062 #define US_IDR_USART_ITER_1         (US_IDR_USART_ITER_1_Val       << US_IDR_USART_ITER_Pos)
2063 #define US_IDR_USART_TXBUFE_Pos     11           /**< \brief (US_IDR_USART) Buffer Empty Interrupt Disable */
2064 #define US_IDR_USART_TXBUFE         (_U_(0x1) << US_IDR_USART_TXBUFE_Pos)
2065 #define   US_IDR_USART_TXBUFE_0_Val       _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2066 #define   US_IDR_USART_TXBUFE_1_Val       _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2067 #define US_IDR_USART_TXBUFE_0       (US_IDR_USART_TXBUFE_0_Val     << US_IDR_USART_TXBUFE_Pos)
2068 #define US_IDR_USART_TXBUFE_1       (US_IDR_USART_TXBUFE_1_Val     << US_IDR_USART_TXBUFE_Pos)
2069 #define US_IDR_USART_RXBUFF_Pos     12           /**< \brief (US_IDR_USART) Buffer Full Interrupt Disable */
2070 #define US_IDR_USART_RXBUFF         (_U_(0x1) << US_IDR_USART_RXBUFF_Pos)
2071 #define   US_IDR_USART_RXBUFF_0_Val       _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2072 #define   US_IDR_USART_RXBUFF_1_Val       _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2073 #define US_IDR_USART_RXBUFF_0       (US_IDR_USART_RXBUFF_0_Val     << US_IDR_USART_RXBUFF_Pos)
2074 #define US_IDR_USART_RXBUFF_1       (US_IDR_USART_RXBUFF_1_Val     << US_IDR_USART_RXBUFF_Pos)
2075 #define US_IDR_USART_NACK_Pos       13           /**< \brief (US_IDR_USART) Non Acknowledge Interrupt Disable */
2076 #define US_IDR_USART_NACK           (_U_(0x1) << US_IDR_USART_NACK_Pos)
2077 #define   US_IDR_USART_NACK_0_Val         _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2078 #define   US_IDR_USART_NACK_1_Val         _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2079 #define US_IDR_USART_NACK_0         (US_IDR_USART_NACK_0_Val       << US_IDR_USART_NACK_Pos)
2080 #define US_IDR_USART_NACK_1         (US_IDR_USART_NACK_1_Val       << US_IDR_USART_NACK_Pos)
2081 #define US_IDR_USART_RIIC_Pos       16           /**< \brief (US_IDR_USART) Ring Indicator Input Change Disable */
2082 #define US_IDR_USART_RIIC           (_U_(0x1) << US_IDR_USART_RIIC_Pos)
2083 #define   US_IDR_USART_RIIC_0_Val         _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2084 #define   US_IDR_USART_RIIC_1_Val         _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2085 #define US_IDR_USART_RIIC_0         (US_IDR_USART_RIIC_0_Val       << US_IDR_USART_RIIC_Pos)
2086 #define US_IDR_USART_RIIC_1         (US_IDR_USART_RIIC_1_Val       << US_IDR_USART_RIIC_Pos)
2087 #define US_IDR_USART_DSRIC_Pos      17           /**< \brief (US_IDR_USART) Data Set Ready Input Change Disable */
2088 #define US_IDR_USART_DSRIC          (_U_(0x1) << US_IDR_USART_DSRIC_Pos)
2089 #define   US_IDR_USART_DSRIC_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2090 #define   US_IDR_USART_DSRIC_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2091 #define US_IDR_USART_DSRIC_0        (US_IDR_USART_DSRIC_0_Val      << US_IDR_USART_DSRIC_Pos)
2092 #define US_IDR_USART_DSRIC_1        (US_IDR_USART_DSRIC_1_Val      << US_IDR_USART_DSRIC_Pos)
2093 #define US_IDR_USART_DCDIC_Pos      18           /**< \brief (US_IDR_USART) Data Carrier Detect Input Change Interrupt Disable */
2094 #define US_IDR_USART_DCDIC          (_U_(0x1) << US_IDR_USART_DCDIC_Pos)
2095 #define   US_IDR_USART_DCDIC_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2096 #define   US_IDR_USART_DCDIC_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2097 #define US_IDR_USART_DCDIC_0        (US_IDR_USART_DCDIC_0_Val      << US_IDR_USART_DCDIC_Pos)
2098 #define US_IDR_USART_DCDIC_1        (US_IDR_USART_DCDIC_1_Val      << US_IDR_USART_DCDIC_Pos)
2099 #define US_IDR_USART_CTSIC_Pos      19           /**< \brief (US_IDR_USART) Clear to Send Input Change Interrupt Disable */
2100 #define US_IDR_USART_CTSIC          (_U_(0x1) << US_IDR_USART_CTSIC_Pos)
2101 #define   US_IDR_USART_CTSIC_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No Effect */
2102 #define   US_IDR_USART_CTSIC_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the interrupt */
2103 #define US_IDR_USART_CTSIC_0        (US_IDR_USART_CTSIC_0_Val      << US_IDR_USART_CTSIC_Pos)
2104 #define US_IDR_USART_CTSIC_1        (US_IDR_USART_CTSIC_1_Val      << US_IDR_USART_CTSIC_Pos)
2105 #define US_IDR_USART_MANE_Pos       20           /**< \brief (US_IDR_USART) Manchester Error Interrupt Disable */
2106 #define US_IDR_USART_MANE           (_U_(0x1) << US_IDR_USART_MANE_Pos)
2107 #define US_IDR_USART_MANEA_Pos      24           /**< \brief (US_IDR_USART) Manchester Error Interrupt Disable */
2108 #define US_IDR_USART_MANEA          (_U_(0x1) << US_IDR_USART_MANEA_Pos)
2109 #define   US_IDR_USART_MANEA_0_Val        _U_(0x0)   /**< \brief (US_IDR_USART) No effect */
2110 #define   US_IDR_USART_MANEA_1_Val        _U_(0x1)   /**< \brief (US_IDR_USART) Disables the corresponding interrupt */
2111 #define US_IDR_USART_MANEA_0        (US_IDR_USART_MANEA_0_Val      << US_IDR_USART_MANEA_Pos)
2112 #define US_IDR_USART_MANEA_1        (US_IDR_USART_MANEA_1_Val      << US_IDR_USART_MANEA_Pos)
2113 #define US_IDR_USART_MASK           _U_(0x011F3FE7) /**< \brief (US_IDR_USART) MASK Register */
2114 
2115 // Any mode
2116 #define US_IDR_RXRDY_Pos            0            /**< \brief (US_IDR) Receiver Ready Interrupt Disable */
2117 #define US_IDR_RXRDY                (_U_(0x1) << US_IDR_RXRDY_Pos)
2118 #define   US_IDR_RXRDY_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2119 #define   US_IDR_RXRDY_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2120 #define US_IDR_RXRDY_0              (US_IDR_RXRDY_0_Val            << US_IDR_RXRDY_Pos)
2121 #define US_IDR_RXRDY_1              (US_IDR_RXRDY_1_Val            << US_IDR_RXRDY_Pos)
2122 #define US_IDR_TXRDY_Pos            1            /**< \brief (US_IDR) Transmitter Ready Interrupt Disable */
2123 #define US_IDR_TXRDY                (_U_(0x1) << US_IDR_TXRDY_Pos)
2124 #define   US_IDR_TXRDY_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2125 #define   US_IDR_TXRDY_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2126 #define US_IDR_TXRDY_0              (US_IDR_TXRDY_0_Val            << US_IDR_TXRDY_Pos)
2127 #define US_IDR_TXRDY_1              (US_IDR_TXRDY_1_Val            << US_IDR_TXRDY_Pos)
2128 #define US_IDR_RXBRK_Pos            2            /**< \brief (US_IDR) Receiver Break Interrupt Disable */
2129 #define US_IDR_RXBRK                (_U_(0x1) << US_IDR_RXBRK_Pos)
2130 #define   US_IDR_RXBRK_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2131 #define   US_IDR_RXBRK_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2132 #define US_IDR_RXBRK_0              (US_IDR_RXBRK_0_Val            << US_IDR_RXBRK_Pos)
2133 #define US_IDR_RXBRK_1              (US_IDR_RXBRK_1_Val            << US_IDR_RXBRK_Pos)
2134 #define US_IDR_OVRE_Pos             5            /**< \brief (US_IDR) Overrun Error Interrupt Disable */
2135 #define US_IDR_OVRE                 (_U_(0x1) << US_IDR_OVRE_Pos)
2136 #define   US_IDR_OVRE_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2137 #define   US_IDR_OVRE_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2138 #define US_IDR_OVRE_0               (US_IDR_OVRE_0_Val             << US_IDR_OVRE_Pos)
2139 #define US_IDR_OVRE_1               (US_IDR_OVRE_1_Val             << US_IDR_OVRE_Pos)
2140 #define US_IDR_FRAME_Pos            6            /**< \brief (US_IDR) Framing Error Interrupt Disable */
2141 #define US_IDR_FRAME                (_U_(0x1) << US_IDR_FRAME_Pos)
2142 #define   US_IDR_FRAME_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2143 #define   US_IDR_FRAME_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2144 #define US_IDR_FRAME_0              (US_IDR_FRAME_0_Val            << US_IDR_FRAME_Pos)
2145 #define US_IDR_FRAME_1              (US_IDR_FRAME_1_Val            << US_IDR_FRAME_Pos)
2146 #define US_IDR_PARE_Pos             7            /**< \brief (US_IDR) Parity Error Interrupt Disable */
2147 #define US_IDR_PARE                 (_U_(0x1) << US_IDR_PARE_Pos)
2148 #define   US_IDR_PARE_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2149 #define   US_IDR_PARE_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2150 #define US_IDR_PARE_0               (US_IDR_PARE_0_Val             << US_IDR_PARE_Pos)
2151 #define US_IDR_PARE_1               (US_IDR_PARE_1_Val             << US_IDR_PARE_Pos)
2152 #define US_IDR_TIMEOUT_Pos          8            /**< \brief (US_IDR) Time-out Interrupt Disable */
2153 #define US_IDR_TIMEOUT              (_U_(0x1) << US_IDR_TIMEOUT_Pos)
2154 #define   US_IDR_TIMEOUT_0_Val            _U_(0x0)   /**< \brief (US_IDR) No Effect */
2155 #define   US_IDR_TIMEOUT_1_Val            _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2156 #define US_IDR_TIMEOUT_0            (US_IDR_TIMEOUT_0_Val          << US_IDR_TIMEOUT_Pos)
2157 #define US_IDR_TIMEOUT_1            (US_IDR_TIMEOUT_1_Val          << US_IDR_TIMEOUT_Pos)
2158 #define US_IDR_TXEMPTY_Pos          9            /**< \brief (US_IDR) Transmitter Empty Interrupt Disable */
2159 #define US_IDR_TXEMPTY              (_U_(0x1) << US_IDR_TXEMPTY_Pos)
2160 #define   US_IDR_TXEMPTY_0_Val            _U_(0x0)   /**< \brief (US_IDR) No Effect */
2161 #define   US_IDR_TXEMPTY_1_Val            _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2162 #define US_IDR_TXEMPTY_0            (US_IDR_TXEMPTY_0_Val          << US_IDR_TXEMPTY_Pos)
2163 #define US_IDR_TXEMPTY_1            (US_IDR_TXEMPTY_1_Val          << US_IDR_TXEMPTY_Pos)
2164 #define US_IDR_ITER_Pos             10           /**< \brief (US_IDR) Iteration Interrupt Disable */
2165 #define US_IDR_ITER                 (_U_(0x1) << US_IDR_ITER_Pos)
2166 #define   US_IDR_ITER_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2167 #define   US_IDR_ITER_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2168 #define US_IDR_ITER_0               (US_IDR_ITER_0_Val             << US_IDR_ITER_Pos)
2169 #define US_IDR_ITER_1               (US_IDR_ITER_1_Val             << US_IDR_ITER_Pos)
2170 #define US_IDR_UNRE_Pos             10           /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */
2171 #define US_IDR_UNRE                 (_U_(0x1) << US_IDR_UNRE_Pos)
2172 #define   US_IDR_UNRE_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2173 #define   US_IDR_UNRE_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2174 #define US_IDR_UNRE_0               (US_IDR_UNRE_0_Val             << US_IDR_UNRE_Pos)
2175 #define US_IDR_UNRE_1               (US_IDR_UNRE_1_Val             << US_IDR_UNRE_Pos)
2176 #define US_IDR_ITER_Pos             10           /**< \brief (US_IDR) Iteration Interrupt Disable */
2177 #define US_IDR_ITER                 (_U_(0x1) << US_IDR_ITER_Pos)
2178 #define   US_IDR_ITER_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2179 #define   US_IDR_ITER_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2180 #define US_IDR_ITER_0               (US_IDR_ITER_0_Val             << US_IDR_ITER_Pos)
2181 #define US_IDR_ITER_1               (US_IDR_ITER_1_Val             << US_IDR_ITER_Pos)
2182 #define US_IDR_TXBUFE_Pos           11           /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
2183 #define US_IDR_TXBUFE               (_U_(0x1) << US_IDR_TXBUFE_Pos)
2184 #define   US_IDR_TXBUFE_0_Val             _U_(0x0)   /**< \brief (US_IDR) No Effect */
2185 #define   US_IDR_TXBUFE_1_Val             _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2186 #define US_IDR_TXBUFE_0             (US_IDR_TXBUFE_0_Val           << US_IDR_TXBUFE_Pos)
2187 #define US_IDR_TXBUFE_1             (US_IDR_TXBUFE_1_Val           << US_IDR_TXBUFE_Pos)
2188 #define US_IDR_RXBUFF_Pos           12           /**< \brief (US_IDR) Buffer Full Interrupt Disable */
2189 #define US_IDR_RXBUFF               (_U_(0x1) << US_IDR_RXBUFF_Pos)
2190 #define   US_IDR_RXBUFF_0_Val             _U_(0x0)   /**< \brief (US_IDR) No Effect */
2191 #define   US_IDR_RXBUFF_1_Val             _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2192 #define US_IDR_RXBUFF_0             (US_IDR_RXBUFF_0_Val           << US_IDR_RXBUFF_Pos)
2193 #define US_IDR_RXBUFF_1             (US_IDR_RXBUFF_1_Val           << US_IDR_RXBUFF_Pos)
2194 #define US_IDR_NACK_Pos             13           /**< \brief (US_IDR) Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Disable */
2195 #define US_IDR_NACK                 (_U_(0x1) << US_IDR_NACK_Pos)
2196 #define   US_IDR_NACK_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2197 #define   US_IDR_NACK_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2198 #define US_IDR_NACK_0               (US_IDR_NACK_0_Val             << US_IDR_NACK_Pos)
2199 #define US_IDR_NACK_1               (US_IDR_NACK_1_Val             << US_IDR_NACK_Pos)
2200 #define US_IDR_LINID_Pos            14           /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */
2201 #define US_IDR_LINID                (_U_(0x1) << US_IDR_LINID_Pos)
2202 #define US_IDR_LINTC_Pos            15           /**< \brief (US_IDR) LIN Transfer Conpleted Interrupt Disable */
2203 #define US_IDR_LINTC                (_U_(0x1) << US_IDR_LINTC_Pos)
2204 #define US_IDR_RIIC_Pos             16           /**< \brief (US_IDR) Ring Indicator Input Change Disable */
2205 #define US_IDR_RIIC                 (_U_(0x1) << US_IDR_RIIC_Pos)
2206 #define   US_IDR_RIIC_0_Val               _U_(0x0)   /**< \brief (US_IDR) No Effect */
2207 #define   US_IDR_RIIC_1_Val               _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2208 #define US_IDR_RIIC_0               (US_IDR_RIIC_0_Val             << US_IDR_RIIC_Pos)
2209 #define US_IDR_RIIC_1               (US_IDR_RIIC_1_Val             << US_IDR_RIIC_Pos)
2210 #define US_IDR_DSRIC_Pos            17           /**< \brief (US_IDR) Data Set Ready Input Change Disable */
2211 #define US_IDR_DSRIC                (_U_(0x1) << US_IDR_DSRIC_Pos)
2212 #define   US_IDR_DSRIC_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2213 #define   US_IDR_DSRIC_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2214 #define US_IDR_DSRIC_0              (US_IDR_DSRIC_0_Val            << US_IDR_DSRIC_Pos)
2215 #define US_IDR_DSRIC_1              (US_IDR_DSRIC_1_Val            << US_IDR_DSRIC_Pos)
2216 #define US_IDR_DCDIC_Pos            18           /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
2217 #define US_IDR_DCDIC                (_U_(0x1) << US_IDR_DCDIC_Pos)
2218 #define   US_IDR_DCDIC_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2219 #define   US_IDR_DCDIC_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2220 #define US_IDR_DCDIC_0              (US_IDR_DCDIC_0_Val            << US_IDR_DCDIC_Pos)
2221 #define US_IDR_DCDIC_1              (US_IDR_DCDIC_1_Val            << US_IDR_DCDIC_Pos)
2222 #define US_IDR_CTSIC_Pos            19           /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
2223 #define US_IDR_CTSIC                (_U_(0x1) << US_IDR_CTSIC_Pos)
2224 #define   US_IDR_CTSIC_0_Val              _U_(0x0)   /**< \brief (US_IDR) No Effect */
2225 #define   US_IDR_CTSIC_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2226 #define US_IDR_CTSIC_0              (US_IDR_CTSIC_0_Val            << US_IDR_CTSIC_Pos)
2227 #define US_IDR_CTSIC_1              (US_IDR_CTSIC_1_Val            << US_IDR_CTSIC_Pos)
2228 #define US_IDR_MANE_Pos             20           /**< \brief (US_IDR) Manchester Error Interrupt Disable */
2229 #define US_IDR_MANE                 (_U_(0x1) << US_IDR_MANE_Pos)
2230 #define US_IDR_MANEA_Pos            24           /**< \brief (US_IDR) Manchester Error Interrupt Disable */
2231 #define US_IDR_MANEA                (_U_(0x1) << US_IDR_MANEA_Pos)
2232 #define   US_IDR_MANEA_0_Val              _U_(0x0)   /**< \brief (US_IDR) No effect */
2233 #define   US_IDR_MANEA_1_Val              _U_(0x1)   /**< \brief (US_IDR) Disables the corresponding interrupt */
2234 #define US_IDR_MANEA_0              (US_IDR_MANEA_0_Val            << US_IDR_MANEA_Pos)
2235 #define US_IDR_MANEA_1              (US_IDR_MANEA_1_Val            << US_IDR_MANEA_Pos)
2236 #define US_IDR_LINBE_Pos            25           /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */
2237 #define US_IDR_LINBE                (_U_(0x1) << US_IDR_LINBE_Pos)
2238 #define US_IDR_LINISFE_Pos          26           /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */
2239 #define US_IDR_LINISFE              (_U_(0x1) << US_IDR_LINISFE_Pos)
2240 #define US_IDR_LINIPE_Pos           27           /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */
2241 #define US_IDR_LINIPE               (_U_(0x1) << US_IDR_LINIPE_Pos)
2242 #define US_IDR_LINCE_Pos            28           /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */
2243 #define US_IDR_LINCE                (_U_(0x1) << US_IDR_LINCE_Pos)
2244 #define US_IDR_LINSNRE_Pos          29           /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */
2245 #define US_IDR_LINSNRE              (_U_(0x1) << US_IDR_LINSNRE_Pos)
2246 #define US_IDR_LINSTE_Pos           30           /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */
2247 #define US_IDR_LINSTE               (_U_(0x1) << US_IDR_LINSTE_Pos)
2248 #define   US_IDR_LINSTE_0_Val             _U_(0x0)   /**< \brief (US_IDR) No Effect */
2249 #define   US_IDR_LINSTE_1_Val             _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2250 #define US_IDR_LINSTE_0             (US_IDR_LINSTE_0_Val           << US_IDR_LINSTE_Pos)
2251 #define US_IDR_LINSTE_1             (US_IDR_LINSTE_1_Val           << US_IDR_LINSTE_Pos)
2252 #define US_IDR_LINHTE_Pos           31           /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */
2253 #define US_IDR_LINHTE               (_U_(0x1) << US_IDR_LINHTE_Pos)
2254 #define   US_IDR_LINHTE_0_Val             _U_(0x0)   /**< \brief (US_IDR) No Effect */
2255 #define   US_IDR_LINHTE_1_Val             _U_(0x1)   /**< \brief (US_IDR) Disables the interrupt */
2256 #define US_IDR_LINHTE_0             (US_IDR_LINHTE_0_Val           << US_IDR_LINHTE_Pos)
2257 #define US_IDR_LINHTE_1             (US_IDR_LINHTE_1_Val           << US_IDR_LINHTE_Pos)
2258 #define US_IDR_MASK                 _U_(0xFF1FFFE7) /**< \brief (US_IDR) MASK Register */
2259 
2260 /* -------- US_IMR : (USART Offset: 0x10) (R/  32) Interrupt Mask Register -------- */
2261 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
2262 typedef union {
2263   struct { // LIN mode
2264     uint32_t RXRDY:1;          /*!< bit:      0  RXRDY Interrupt Mask               */
2265     uint32_t TXRDY:1;          /*!< bit:      1  TXRDY Interrupt Mask               */
2266     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Mask      */
2267     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
2268     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Mask       */
2269     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Mask       */
2270     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Mask        */
2271     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Mask            */
2272     uint32_t TXEMPTY:1;        /*!< bit:      9  TXEMPTY Interrupt Mask             */
2273     uint32_t ITER:1;           /*!< bit:     10  Iteration Interrupt Mask           */
2274     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Mask        */
2275     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Mask         */
2276     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Mask */
2277     uint32_t LINID:1;          /*!< bit:     14  LIN Identifier Sent or LIN Received Interrupt Mask */
2278     uint32_t LINTC:1;          /*!< bit:     15  LIN Transfer Conpleted Interrupt Mask */
2279     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Mask   */
2280     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Mask   */
2281     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Mask */
2282     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Mask */
2283     uint32_t :5;               /*!< bit: 20..24  Reserved                           */
2284     uint32_t LINBE:1;          /*!< bit:     25  LIN Bus Error Interrupt Mask       */
2285     uint32_t LINISFE:1;        /*!< bit:     26  LIN Inconsistent Synch Field Error Interrupt Mask */
2286     uint32_t LINIPE:1;         /*!< bit:     27  LIN Identifier Parity Interrupt Mask */
2287     uint32_t LINCE:1;          /*!< bit:     28  LIN Checksum Error Interrupt Mask  */
2288     uint32_t LINSNRE:1;        /*!< bit:     29  LIN Slave Not Responding Error Interrupt Mask */
2289     uint32_t LINSTE:1;         /*!< bit:     30  LIN Synch Tolerance Error Interrupt Mask */
2290     uint32_t LINHTE:1;         /*!< bit:     31  LIN Header Timeout Error Interrupt Mask */
2291   } LIN;                       /*!< Structure used for LIN                          */
2292   struct { // SPI_SLAVE mode
2293     uint32_t RXRDY:1;          /*!< bit:      0  RXRDY Interrupt Mask               */
2294     uint32_t TXRDY:1;          /*!< bit:      1  TXRDY Interrupt Mask               */
2295     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Mask      */
2296     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
2297     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Mask       */
2298     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Mask       */
2299     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Mask        */
2300     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Mask            */
2301     uint32_t TXEMPTY:1;        /*!< bit:      9  TXEMPTY Interrupt Mask             */
2302     uint32_t UNRE:1;           /*!< bit:     10  SPI Underrun Error Interrupt Mask  */
2303     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Mask        */
2304     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Mask         */
2305     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge Interrupt Mask     */
2306     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
2307     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Mask   */
2308     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Mask   */
2309     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Mask */
2310     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Mask */
2311     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
2312   } SPI_SLAVE;                 /*!< Structure used for SPI_SLAVE                    */
2313   struct { // USART mode
2314     uint32_t RXRDY:1;          /*!< bit:      0  RXRDY Interrupt Mask               */
2315     uint32_t TXRDY:1;          /*!< bit:      1  TXRDY Interrupt Mask               */
2316     uint32_t RXBRK:1;          /*!< bit:      2  Receiver Break Interrupt Mask      */
2317     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
2318     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error Interrupt Mask       */
2319     uint32_t FRAME:1;          /*!< bit:      6  Framing Error Interrupt Mask       */
2320     uint32_t PARE:1;           /*!< bit:      7  Parity Error Interrupt Mask        */
2321     uint32_t TIMEOUT:1;        /*!< bit:      8  Time-out Interrupt Mask            */
2322     uint32_t TXEMPTY:1;        /*!< bit:      9  TXEMPTY Interrupt Mask             */
2323     uint32_t ITER:1;           /*!< bit:     10  Iteration Interrupt Mask           */
2324     uint32_t TXBUFE:1;         /*!< bit:     11  Buffer Empty Interrupt Mask        */
2325     uint32_t RXBUFF:1;         /*!< bit:     12  Buffer Full Interrupt Mask         */
2326     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge Interrupt Mask     */
2327     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
2328     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Mask   */
2329     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Mask   */
2330     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Interrupt Mask */
2331     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Interrupt Mask */
2332     uint32_t MANE:1;           /*!< bit:     20  Manchester Error Interrupt Mask    */
2333     uint32_t :3;               /*!< bit: 21..23  Reserved                           */
2334     uint32_t MANEA:1;          /*!< bit:     24  Manchester Error Interrupt Mask    */
2335     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
2336   } USART;                     /*!< Structure used for USART                        */
2337   uint32_t reg;                /*!< Type      used for register access              */
2338 } US_IMR_Type;
2339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
2340 
2341 #define US_IMR_OFFSET               0x10         /**< \brief (US_IMR offset) Interrupt Mask Register */
2342 #define US_IMR_RESETVALUE           _U_(0x00000000); /**< \brief (US_IMR reset_value) Interrupt Mask Register */
2343 
2344 // LIN mode
2345 #define US_IMR_LIN_RXRDY_Pos        0            /**< \brief (US_IMR_LIN) RXRDY Interrupt Mask */
2346 #define US_IMR_LIN_RXRDY            (_U_(0x1) << US_IMR_LIN_RXRDY_Pos)
2347 #define   US_IMR_LIN_RXRDY_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2348 #define   US_IMR_LIN_RXRDY_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2349 #define US_IMR_LIN_RXRDY_0          (US_IMR_LIN_RXRDY_0_Val        << US_IMR_LIN_RXRDY_Pos)
2350 #define US_IMR_LIN_RXRDY_1          (US_IMR_LIN_RXRDY_1_Val        << US_IMR_LIN_RXRDY_Pos)
2351 #define US_IMR_LIN_TXRDY_Pos        1            /**< \brief (US_IMR_LIN) TXRDY Interrupt Mask */
2352 #define US_IMR_LIN_TXRDY            (_U_(0x1) << US_IMR_LIN_TXRDY_Pos)
2353 #define   US_IMR_LIN_TXRDY_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2354 #define   US_IMR_LIN_TXRDY_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2355 #define US_IMR_LIN_TXRDY_0          (US_IMR_LIN_TXRDY_0_Val        << US_IMR_LIN_TXRDY_Pos)
2356 #define US_IMR_LIN_TXRDY_1          (US_IMR_LIN_TXRDY_1_Val        << US_IMR_LIN_TXRDY_Pos)
2357 #define US_IMR_LIN_RXBRK_Pos        2            /**< \brief (US_IMR_LIN) Receiver Break Interrupt Mask */
2358 #define US_IMR_LIN_RXBRK            (_U_(0x1) << US_IMR_LIN_RXBRK_Pos)
2359 #define   US_IMR_LIN_RXBRK_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2360 #define   US_IMR_LIN_RXBRK_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2361 #define US_IMR_LIN_RXBRK_0          (US_IMR_LIN_RXBRK_0_Val        << US_IMR_LIN_RXBRK_Pos)
2362 #define US_IMR_LIN_RXBRK_1          (US_IMR_LIN_RXBRK_1_Val        << US_IMR_LIN_RXBRK_Pos)
2363 #define US_IMR_LIN_OVRE_Pos         5            /**< \brief (US_IMR_LIN) Overrun Error Interrupt Mask */
2364 #define US_IMR_LIN_OVRE             (_U_(0x1) << US_IMR_LIN_OVRE_Pos)
2365 #define   US_IMR_LIN_OVRE_0_Val           _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2366 #define   US_IMR_LIN_OVRE_1_Val           _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2367 #define US_IMR_LIN_OVRE_0           (US_IMR_LIN_OVRE_0_Val         << US_IMR_LIN_OVRE_Pos)
2368 #define US_IMR_LIN_OVRE_1           (US_IMR_LIN_OVRE_1_Val         << US_IMR_LIN_OVRE_Pos)
2369 #define US_IMR_LIN_FRAME_Pos        6            /**< \brief (US_IMR_LIN) Framing Error Interrupt Mask */
2370 #define US_IMR_LIN_FRAME            (_U_(0x1) << US_IMR_LIN_FRAME_Pos)
2371 #define   US_IMR_LIN_FRAME_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2372 #define   US_IMR_LIN_FRAME_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2373 #define US_IMR_LIN_FRAME_0          (US_IMR_LIN_FRAME_0_Val        << US_IMR_LIN_FRAME_Pos)
2374 #define US_IMR_LIN_FRAME_1          (US_IMR_LIN_FRAME_1_Val        << US_IMR_LIN_FRAME_Pos)
2375 #define US_IMR_LIN_PARE_Pos         7            /**< \brief (US_IMR_LIN) Parity Error Interrupt Mask */
2376 #define US_IMR_LIN_PARE             (_U_(0x1) << US_IMR_LIN_PARE_Pos)
2377 #define   US_IMR_LIN_PARE_0_Val           _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2378 #define   US_IMR_LIN_PARE_1_Val           _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2379 #define US_IMR_LIN_PARE_0           (US_IMR_LIN_PARE_0_Val         << US_IMR_LIN_PARE_Pos)
2380 #define US_IMR_LIN_PARE_1           (US_IMR_LIN_PARE_1_Val         << US_IMR_LIN_PARE_Pos)
2381 #define US_IMR_LIN_TIMEOUT_Pos      8            /**< \brief (US_IMR_LIN) Time-out Interrupt Mask */
2382 #define US_IMR_LIN_TIMEOUT          (_U_(0x1) << US_IMR_LIN_TIMEOUT_Pos)
2383 #define   US_IMR_LIN_TIMEOUT_0_Val        _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2384 #define   US_IMR_LIN_TIMEOUT_1_Val        _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2385 #define US_IMR_LIN_TIMEOUT_0        (US_IMR_LIN_TIMEOUT_0_Val      << US_IMR_LIN_TIMEOUT_Pos)
2386 #define US_IMR_LIN_TIMEOUT_1        (US_IMR_LIN_TIMEOUT_1_Val      << US_IMR_LIN_TIMEOUT_Pos)
2387 #define US_IMR_LIN_TXEMPTY_Pos      9            /**< \brief (US_IMR_LIN) TXEMPTY Interrupt Mask */
2388 #define US_IMR_LIN_TXEMPTY          (_U_(0x1) << US_IMR_LIN_TXEMPTY_Pos)
2389 #define   US_IMR_LIN_TXEMPTY_0_Val        _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2390 #define   US_IMR_LIN_TXEMPTY_1_Val        _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2391 #define US_IMR_LIN_TXEMPTY_0        (US_IMR_LIN_TXEMPTY_0_Val      << US_IMR_LIN_TXEMPTY_Pos)
2392 #define US_IMR_LIN_TXEMPTY_1        (US_IMR_LIN_TXEMPTY_1_Val      << US_IMR_LIN_TXEMPTY_Pos)
2393 #define US_IMR_LIN_ITER_Pos         10           /**< \brief (US_IMR_LIN) Iteration Interrupt Mask */
2394 #define US_IMR_LIN_ITER             (_U_(0x1) << US_IMR_LIN_ITER_Pos)
2395 #define   US_IMR_LIN_ITER_0_Val           _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2396 #define   US_IMR_LIN_ITER_1_Val           _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2397 #define US_IMR_LIN_ITER_0           (US_IMR_LIN_ITER_0_Val         << US_IMR_LIN_ITER_Pos)
2398 #define US_IMR_LIN_ITER_1           (US_IMR_LIN_ITER_1_Val         << US_IMR_LIN_ITER_Pos)
2399 #define US_IMR_LIN_TXBUFE_Pos       11           /**< \brief (US_IMR_LIN) Buffer Empty Interrupt Mask */
2400 #define US_IMR_LIN_TXBUFE           (_U_(0x1) << US_IMR_LIN_TXBUFE_Pos)
2401 #define   US_IMR_LIN_TXBUFE_0_Val         _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2402 #define   US_IMR_LIN_TXBUFE_1_Val         _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2403 #define US_IMR_LIN_TXBUFE_0         (US_IMR_LIN_TXBUFE_0_Val       << US_IMR_LIN_TXBUFE_Pos)
2404 #define US_IMR_LIN_TXBUFE_1         (US_IMR_LIN_TXBUFE_1_Val       << US_IMR_LIN_TXBUFE_Pos)
2405 #define US_IMR_LIN_RXBUFF_Pos       12           /**< \brief (US_IMR_LIN) Buffer Full Interrupt Mask */
2406 #define US_IMR_LIN_RXBUFF           (_U_(0x1) << US_IMR_LIN_RXBUFF_Pos)
2407 #define   US_IMR_LIN_RXBUFF_0_Val         _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2408 #define   US_IMR_LIN_RXBUFF_1_Val         _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2409 #define US_IMR_LIN_RXBUFF_0         (US_IMR_LIN_RXBUFF_0_Val       << US_IMR_LIN_RXBUFF_Pos)
2410 #define US_IMR_LIN_RXBUFF_1         (US_IMR_LIN_RXBUFF_1_Val       << US_IMR_LIN_RXBUFF_Pos)
2411 #define US_IMR_LIN_NACK_Pos         13           /**< \brief (US_IMR_LIN) Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Mask */
2412 #define US_IMR_LIN_NACK             (_U_(0x1) << US_IMR_LIN_NACK_Pos)
2413 #define   US_IMR_LIN_NACK_0_Val           _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2414 #define   US_IMR_LIN_NACK_1_Val           _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2415 #define US_IMR_LIN_NACK_0           (US_IMR_LIN_NACK_0_Val         << US_IMR_LIN_NACK_Pos)
2416 #define US_IMR_LIN_NACK_1           (US_IMR_LIN_NACK_1_Val         << US_IMR_LIN_NACK_Pos)
2417 #define US_IMR_LIN_LINID_Pos        14           /**< \brief (US_IMR_LIN) LIN Identifier Sent or LIN Received Interrupt Mask */
2418 #define US_IMR_LIN_LINID            (_U_(0x1) << US_IMR_LIN_LINID_Pos)
2419 #define US_IMR_LIN_LINTC_Pos        15           /**< \brief (US_IMR_LIN) LIN Transfer Conpleted Interrupt Mask */
2420 #define US_IMR_LIN_LINTC            (_U_(0x1) << US_IMR_LIN_LINTC_Pos)
2421 #define US_IMR_LIN_RIIC_Pos         16           /**< \brief (US_IMR_LIN) Ring Indicator Input Change Mask */
2422 #define US_IMR_LIN_RIIC             (_U_(0x1) << US_IMR_LIN_RIIC_Pos)
2423 #define   US_IMR_LIN_RIIC_0_Val           _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2424 #define   US_IMR_LIN_RIIC_1_Val           _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2425 #define US_IMR_LIN_RIIC_0           (US_IMR_LIN_RIIC_0_Val         << US_IMR_LIN_RIIC_Pos)
2426 #define US_IMR_LIN_RIIC_1           (US_IMR_LIN_RIIC_1_Val         << US_IMR_LIN_RIIC_Pos)
2427 #define US_IMR_LIN_DSRIC_Pos        17           /**< \brief (US_IMR_LIN) Data Set Ready Input Change Mask */
2428 #define US_IMR_LIN_DSRIC            (_U_(0x1) << US_IMR_LIN_DSRIC_Pos)
2429 #define   US_IMR_LIN_DSRIC_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2430 #define   US_IMR_LIN_DSRIC_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2431 #define US_IMR_LIN_DSRIC_0          (US_IMR_LIN_DSRIC_0_Val        << US_IMR_LIN_DSRIC_Pos)
2432 #define US_IMR_LIN_DSRIC_1          (US_IMR_LIN_DSRIC_1_Val        << US_IMR_LIN_DSRIC_Pos)
2433 #define US_IMR_LIN_DCDIC_Pos        18           /**< \brief (US_IMR_LIN) Data Carrier Detect Input Change Interrupt Mask */
2434 #define US_IMR_LIN_DCDIC            (_U_(0x1) << US_IMR_LIN_DCDIC_Pos)
2435 #define   US_IMR_LIN_DCDIC_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2436 #define   US_IMR_LIN_DCDIC_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2437 #define US_IMR_LIN_DCDIC_0          (US_IMR_LIN_DCDIC_0_Val        << US_IMR_LIN_DCDIC_Pos)
2438 #define US_IMR_LIN_DCDIC_1          (US_IMR_LIN_DCDIC_1_Val        << US_IMR_LIN_DCDIC_Pos)
2439 #define US_IMR_LIN_CTSIC_Pos        19           /**< \brief (US_IMR_LIN) Clear to Send Input Change Interrupt Mask */
2440 #define US_IMR_LIN_CTSIC            (_U_(0x1) << US_IMR_LIN_CTSIC_Pos)
2441 #define   US_IMR_LIN_CTSIC_0_Val          _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2442 #define   US_IMR_LIN_CTSIC_1_Val          _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2443 #define US_IMR_LIN_CTSIC_0          (US_IMR_LIN_CTSIC_0_Val        << US_IMR_LIN_CTSIC_Pos)
2444 #define US_IMR_LIN_CTSIC_1          (US_IMR_LIN_CTSIC_1_Val        << US_IMR_LIN_CTSIC_Pos)
2445 #define US_IMR_LIN_LINBE_Pos        25           /**< \brief (US_IMR_LIN) LIN Bus Error Interrupt Mask */
2446 #define US_IMR_LIN_LINBE            (_U_(0x1) << US_IMR_LIN_LINBE_Pos)
2447 #define US_IMR_LIN_LINISFE_Pos      26           /**< \brief (US_IMR_LIN) LIN Inconsistent Synch Field Error Interrupt Mask */
2448 #define US_IMR_LIN_LINISFE          (_U_(0x1) << US_IMR_LIN_LINISFE_Pos)
2449 #define US_IMR_LIN_LINIPE_Pos       27           /**< \brief (US_IMR_LIN) LIN Identifier Parity Interrupt Mask */
2450 #define US_IMR_LIN_LINIPE           (_U_(0x1) << US_IMR_LIN_LINIPE_Pos)
2451 #define US_IMR_LIN_LINCE_Pos        28           /**< \brief (US_IMR_LIN) LIN Checksum Error Interrupt Mask */
2452 #define US_IMR_LIN_LINCE            (_U_(0x1) << US_IMR_LIN_LINCE_Pos)
2453 #define US_IMR_LIN_LINSNRE_Pos      29           /**< \brief (US_IMR_LIN) LIN Slave Not Responding Error Interrupt Mask */
2454 #define US_IMR_LIN_LINSNRE          (_U_(0x1) << US_IMR_LIN_LINSNRE_Pos)
2455 #define US_IMR_LIN_LINSTE_Pos       30           /**< \brief (US_IMR_LIN) LIN Synch Tolerance Error Interrupt Mask */
2456 #define US_IMR_LIN_LINSTE           (_U_(0x1) << US_IMR_LIN_LINSTE_Pos)
2457 #define   US_IMR_LIN_LINSTE_0_Val         _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2458 #define   US_IMR_LIN_LINSTE_1_Val         _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2459 #define US_IMR_LIN_LINSTE_0         (US_IMR_LIN_LINSTE_0_Val       << US_IMR_LIN_LINSTE_Pos)
2460 #define US_IMR_LIN_LINSTE_1         (US_IMR_LIN_LINSTE_1_Val       << US_IMR_LIN_LINSTE_Pos)
2461 #define US_IMR_LIN_LINHTE_Pos       31           /**< \brief (US_IMR_LIN) LIN Header Timeout Error Interrupt Mask */
2462 #define US_IMR_LIN_LINHTE           (_U_(0x1) << US_IMR_LIN_LINHTE_Pos)
2463 #define   US_IMR_LIN_LINHTE_0_Val         _U_(0x0)   /**< \brief (US_IMR_LIN) The interrupt is disabled */
2464 #define   US_IMR_LIN_LINHTE_1_Val         _U_(0x1)   /**< \brief (US_IMR_LIN) The interrupt is enabled */
2465 #define US_IMR_LIN_LINHTE_0         (US_IMR_LIN_LINHTE_0_Val       << US_IMR_LIN_LINHTE_Pos)
2466 #define US_IMR_LIN_LINHTE_1         (US_IMR_LIN_LINHTE_1_Val       << US_IMR_LIN_LINHTE_Pos)
2467 #define US_IMR_LIN_MASK             _U_(0xFE0FFFE7) /**< \brief (US_IMR_LIN) MASK Register */
2468 
2469 // SPI_SLAVE mode
2470 #define US_IMR_SPI_SLAVE_RXRDY_Pos  0            /**< \brief (US_IMR_SPI_SLAVE) RXRDY Interrupt Mask */
2471 #define US_IMR_SPI_SLAVE_RXRDY      (_U_(0x1) << US_IMR_SPI_SLAVE_RXRDY_Pos)
2472 #define   US_IMR_SPI_SLAVE_RXRDY_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2473 #define   US_IMR_SPI_SLAVE_RXRDY_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2474 #define US_IMR_SPI_SLAVE_RXRDY_0    (US_IMR_SPI_SLAVE_RXRDY_0_Val  << US_IMR_SPI_SLAVE_RXRDY_Pos)
2475 #define US_IMR_SPI_SLAVE_RXRDY_1    (US_IMR_SPI_SLAVE_RXRDY_1_Val  << US_IMR_SPI_SLAVE_RXRDY_Pos)
2476 #define US_IMR_SPI_SLAVE_TXRDY_Pos  1            /**< \brief (US_IMR_SPI_SLAVE) TXRDY Interrupt Mask */
2477 #define US_IMR_SPI_SLAVE_TXRDY      (_U_(0x1) << US_IMR_SPI_SLAVE_TXRDY_Pos)
2478 #define   US_IMR_SPI_SLAVE_TXRDY_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2479 #define   US_IMR_SPI_SLAVE_TXRDY_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2480 #define US_IMR_SPI_SLAVE_TXRDY_0    (US_IMR_SPI_SLAVE_TXRDY_0_Val  << US_IMR_SPI_SLAVE_TXRDY_Pos)
2481 #define US_IMR_SPI_SLAVE_TXRDY_1    (US_IMR_SPI_SLAVE_TXRDY_1_Val  << US_IMR_SPI_SLAVE_TXRDY_Pos)
2482 #define US_IMR_SPI_SLAVE_RXBRK_Pos  2            /**< \brief (US_IMR_SPI_SLAVE) Receiver Break Interrupt Mask */
2483 #define US_IMR_SPI_SLAVE_RXBRK      (_U_(0x1) << US_IMR_SPI_SLAVE_RXBRK_Pos)
2484 #define   US_IMR_SPI_SLAVE_RXBRK_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2485 #define   US_IMR_SPI_SLAVE_RXBRK_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2486 #define US_IMR_SPI_SLAVE_RXBRK_0    (US_IMR_SPI_SLAVE_RXBRK_0_Val  << US_IMR_SPI_SLAVE_RXBRK_Pos)
2487 #define US_IMR_SPI_SLAVE_RXBRK_1    (US_IMR_SPI_SLAVE_RXBRK_1_Val  << US_IMR_SPI_SLAVE_RXBRK_Pos)
2488 #define US_IMR_SPI_SLAVE_OVRE_Pos   5            /**< \brief (US_IMR_SPI_SLAVE) Overrun Error Interrupt Mask */
2489 #define US_IMR_SPI_SLAVE_OVRE       (_U_(0x1) << US_IMR_SPI_SLAVE_OVRE_Pos)
2490 #define   US_IMR_SPI_SLAVE_OVRE_0_Val     _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2491 #define   US_IMR_SPI_SLAVE_OVRE_1_Val     _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2492 #define US_IMR_SPI_SLAVE_OVRE_0     (US_IMR_SPI_SLAVE_OVRE_0_Val   << US_IMR_SPI_SLAVE_OVRE_Pos)
2493 #define US_IMR_SPI_SLAVE_OVRE_1     (US_IMR_SPI_SLAVE_OVRE_1_Val   << US_IMR_SPI_SLAVE_OVRE_Pos)
2494 #define US_IMR_SPI_SLAVE_FRAME_Pos  6            /**< \brief (US_IMR_SPI_SLAVE) Framing Error Interrupt Mask */
2495 #define US_IMR_SPI_SLAVE_FRAME      (_U_(0x1) << US_IMR_SPI_SLAVE_FRAME_Pos)
2496 #define   US_IMR_SPI_SLAVE_FRAME_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2497 #define   US_IMR_SPI_SLAVE_FRAME_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2498 #define US_IMR_SPI_SLAVE_FRAME_0    (US_IMR_SPI_SLAVE_FRAME_0_Val  << US_IMR_SPI_SLAVE_FRAME_Pos)
2499 #define US_IMR_SPI_SLAVE_FRAME_1    (US_IMR_SPI_SLAVE_FRAME_1_Val  << US_IMR_SPI_SLAVE_FRAME_Pos)
2500 #define US_IMR_SPI_SLAVE_PARE_Pos   7            /**< \brief (US_IMR_SPI_SLAVE) Parity Error Interrupt Mask */
2501 #define US_IMR_SPI_SLAVE_PARE       (_U_(0x1) << US_IMR_SPI_SLAVE_PARE_Pos)
2502 #define   US_IMR_SPI_SLAVE_PARE_0_Val     _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2503 #define   US_IMR_SPI_SLAVE_PARE_1_Val     _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2504 #define US_IMR_SPI_SLAVE_PARE_0     (US_IMR_SPI_SLAVE_PARE_0_Val   << US_IMR_SPI_SLAVE_PARE_Pos)
2505 #define US_IMR_SPI_SLAVE_PARE_1     (US_IMR_SPI_SLAVE_PARE_1_Val   << US_IMR_SPI_SLAVE_PARE_Pos)
2506 #define US_IMR_SPI_SLAVE_TIMEOUT_Pos 8            /**< \brief (US_IMR_SPI_SLAVE) Time-out Interrupt Mask */
2507 #define US_IMR_SPI_SLAVE_TIMEOUT    (_U_(0x1) << US_IMR_SPI_SLAVE_TIMEOUT_Pos)
2508 #define   US_IMR_SPI_SLAVE_TIMEOUT_0_Val  _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2509 #define   US_IMR_SPI_SLAVE_TIMEOUT_1_Val  _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2510 #define US_IMR_SPI_SLAVE_TIMEOUT_0  (US_IMR_SPI_SLAVE_TIMEOUT_0_Val << US_IMR_SPI_SLAVE_TIMEOUT_Pos)
2511 #define US_IMR_SPI_SLAVE_TIMEOUT_1  (US_IMR_SPI_SLAVE_TIMEOUT_1_Val << US_IMR_SPI_SLAVE_TIMEOUT_Pos)
2512 #define US_IMR_SPI_SLAVE_TXEMPTY_Pos 9            /**< \brief (US_IMR_SPI_SLAVE) TXEMPTY Interrupt Mask */
2513 #define US_IMR_SPI_SLAVE_TXEMPTY    (_U_(0x1) << US_IMR_SPI_SLAVE_TXEMPTY_Pos)
2514 #define   US_IMR_SPI_SLAVE_TXEMPTY_0_Val  _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2515 #define   US_IMR_SPI_SLAVE_TXEMPTY_1_Val  _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2516 #define US_IMR_SPI_SLAVE_TXEMPTY_0  (US_IMR_SPI_SLAVE_TXEMPTY_0_Val << US_IMR_SPI_SLAVE_TXEMPTY_Pos)
2517 #define US_IMR_SPI_SLAVE_TXEMPTY_1  (US_IMR_SPI_SLAVE_TXEMPTY_1_Val << US_IMR_SPI_SLAVE_TXEMPTY_Pos)
2518 #define US_IMR_SPI_SLAVE_UNRE_Pos   10           /**< \brief (US_IMR_SPI_SLAVE) SPI Underrun Error Interrupt Mask */
2519 #define US_IMR_SPI_SLAVE_UNRE       (_U_(0x1) << US_IMR_SPI_SLAVE_UNRE_Pos)
2520 #define   US_IMR_SPI_SLAVE_UNRE_0_Val     _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2521 #define   US_IMR_SPI_SLAVE_UNRE_1_Val     _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2522 #define US_IMR_SPI_SLAVE_UNRE_0     (US_IMR_SPI_SLAVE_UNRE_0_Val   << US_IMR_SPI_SLAVE_UNRE_Pos)
2523 #define US_IMR_SPI_SLAVE_UNRE_1     (US_IMR_SPI_SLAVE_UNRE_1_Val   << US_IMR_SPI_SLAVE_UNRE_Pos)
2524 #define US_IMR_SPI_SLAVE_TXBUFE_Pos 11           /**< \brief (US_IMR_SPI_SLAVE) Buffer Empty Interrupt Mask */
2525 #define US_IMR_SPI_SLAVE_TXBUFE     (_U_(0x1) << US_IMR_SPI_SLAVE_TXBUFE_Pos)
2526 #define   US_IMR_SPI_SLAVE_TXBUFE_0_Val   _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2527 #define   US_IMR_SPI_SLAVE_TXBUFE_1_Val   _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2528 #define US_IMR_SPI_SLAVE_TXBUFE_0   (US_IMR_SPI_SLAVE_TXBUFE_0_Val << US_IMR_SPI_SLAVE_TXBUFE_Pos)
2529 #define US_IMR_SPI_SLAVE_TXBUFE_1   (US_IMR_SPI_SLAVE_TXBUFE_1_Val << US_IMR_SPI_SLAVE_TXBUFE_Pos)
2530 #define US_IMR_SPI_SLAVE_RXBUFF_Pos 12           /**< \brief (US_IMR_SPI_SLAVE) Buffer Full Interrupt Mask */
2531 #define US_IMR_SPI_SLAVE_RXBUFF     (_U_(0x1) << US_IMR_SPI_SLAVE_RXBUFF_Pos)
2532 #define   US_IMR_SPI_SLAVE_RXBUFF_0_Val   _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2533 #define   US_IMR_SPI_SLAVE_RXBUFF_1_Val   _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2534 #define US_IMR_SPI_SLAVE_RXBUFF_0   (US_IMR_SPI_SLAVE_RXBUFF_0_Val << US_IMR_SPI_SLAVE_RXBUFF_Pos)
2535 #define US_IMR_SPI_SLAVE_RXBUFF_1   (US_IMR_SPI_SLAVE_RXBUFF_1_Val << US_IMR_SPI_SLAVE_RXBUFF_Pos)
2536 #define US_IMR_SPI_SLAVE_NACK_Pos   13           /**< \brief (US_IMR_SPI_SLAVE) Non Acknowledge Interrupt Mask */
2537 #define US_IMR_SPI_SLAVE_NACK       (_U_(0x1) << US_IMR_SPI_SLAVE_NACK_Pos)
2538 #define   US_IMR_SPI_SLAVE_NACK_0_Val     _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2539 #define   US_IMR_SPI_SLAVE_NACK_1_Val     _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2540 #define US_IMR_SPI_SLAVE_NACK_0     (US_IMR_SPI_SLAVE_NACK_0_Val   << US_IMR_SPI_SLAVE_NACK_Pos)
2541 #define US_IMR_SPI_SLAVE_NACK_1     (US_IMR_SPI_SLAVE_NACK_1_Val   << US_IMR_SPI_SLAVE_NACK_Pos)
2542 #define US_IMR_SPI_SLAVE_RIIC_Pos   16           /**< \brief (US_IMR_SPI_SLAVE) Ring Indicator Input Change Mask */
2543 #define US_IMR_SPI_SLAVE_RIIC       (_U_(0x1) << US_IMR_SPI_SLAVE_RIIC_Pos)
2544 #define   US_IMR_SPI_SLAVE_RIIC_0_Val     _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2545 #define   US_IMR_SPI_SLAVE_RIIC_1_Val     _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2546 #define US_IMR_SPI_SLAVE_RIIC_0     (US_IMR_SPI_SLAVE_RIIC_0_Val   << US_IMR_SPI_SLAVE_RIIC_Pos)
2547 #define US_IMR_SPI_SLAVE_RIIC_1     (US_IMR_SPI_SLAVE_RIIC_1_Val   << US_IMR_SPI_SLAVE_RIIC_Pos)
2548 #define US_IMR_SPI_SLAVE_DSRIC_Pos  17           /**< \brief (US_IMR_SPI_SLAVE) Data Set Ready Input Change Mask */
2549 #define US_IMR_SPI_SLAVE_DSRIC      (_U_(0x1) << US_IMR_SPI_SLAVE_DSRIC_Pos)
2550 #define   US_IMR_SPI_SLAVE_DSRIC_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2551 #define   US_IMR_SPI_SLAVE_DSRIC_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2552 #define US_IMR_SPI_SLAVE_DSRIC_0    (US_IMR_SPI_SLAVE_DSRIC_0_Val  << US_IMR_SPI_SLAVE_DSRIC_Pos)
2553 #define US_IMR_SPI_SLAVE_DSRIC_1    (US_IMR_SPI_SLAVE_DSRIC_1_Val  << US_IMR_SPI_SLAVE_DSRIC_Pos)
2554 #define US_IMR_SPI_SLAVE_DCDIC_Pos  18           /**< \brief (US_IMR_SPI_SLAVE) Data Carrier Detect Input Change Interrupt Mask */
2555 #define US_IMR_SPI_SLAVE_DCDIC      (_U_(0x1) << US_IMR_SPI_SLAVE_DCDIC_Pos)
2556 #define   US_IMR_SPI_SLAVE_DCDIC_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2557 #define   US_IMR_SPI_SLAVE_DCDIC_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2558 #define US_IMR_SPI_SLAVE_DCDIC_0    (US_IMR_SPI_SLAVE_DCDIC_0_Val  << US_IMR_SPI_SLAVE_DCDIC_Pos)
2559 #define US_IMR_SPI_SLAVE_DCDIC_1    (US_IMR_SPI_SLAVE_DCDIC_1_Val  << US_IMR_SPI_SLAVE_DCDIC_Pos)
2560 #define US_IMR_SPI_SLAVE_CTSIC_Pos  19           /**< \brief (US_IMR_SPI_SLAVE) Clear to Send Input Change Interrupt Mask */
2561 #define US_IMR_SPI_SLAVE_CTSIC      (_U_(0x1) << US_IMR_SPI_SLAVE_CTSIC_Pos)
2562 #define   US_IMR_SPI_SLAVE_CTSIC_0_Val    _U_(0x0)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is disabled */
2563 #define   US_IMR_SPI_SLAVE_CTSIC_1_Val    _U_(0x1)   /**< \brief (US_IMR_SPI_SLAVE) The interrupt is enabled */
2564 #define US_IMR_SPI_SLAVE_CTSIC_0    (US_IMR_SPI_SLAVE_CTSIC_0_Val  << US_IMR_SPI_SLAVE_CTSIC_Pos)
2565 #define US_IMR_SPI_SLAVE_CTSIC_1    (US_IMR_SPI_SLAVE_CTSIC_1_Val  << US_IMR_SPI_SLAVE_CTSIC_Pos)
2566 #define US_IMR_SPI_SLAVE_MASK       _U_(0x000F3FE7) /**< \brief (US_IMR_SPI_SLAVE) MASK Register */
2567 
2568 // USART mode
2569 #define US_IMR_USART_RXRDY_Pos      0            /**< \brief (US_IMR_USART) RXRDY Interrupt Mask */
2570 #define US_IMR_USART_RXRDY          (_U_(0x1) << US_IMR_USART_RXRDY_Pos)
2571 #define   US_IMR_USART_RXRDY_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2572 #define   US_IMR_USART_RXRDY_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2573 #define US_IMR_USART_RXRDY_0        (US_IMR_USART_RXRDY_0_Val      << US_IMR_USART_RXRDY_Pos)
2574 #define US_IMR_USART_RXRDY_1        (US_IMR_USART_RXRDY_1_Val      << US_IMR_USART_RXRDY_Pos)
2575 #define US_IMR_USART_TXRDY_Pos      1            /**< \brief (US_IMR_USART) TXRDY Interrupt Mask */
2576 #define US_IMR_USART_TXRDY          (_U_(0x1) << US_IMR_USART_TXRDY_Pos)
2577 #define   US_IMR_USART_TXRDY_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2578 #define   US_IMR_USART_TXRDY_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2579 #define US_IMR_USART_TXRDY_0        (US_IMR_USART_TXRDY_0_Val      << US_IMR_USART_TXRDY_Pos)
2580 #define US_IMR_USART_TXRDY_1        (US_IMR_USART_TXRDY_1_Val      << US_IMR_USART_TXRDY_Pos)
2581 #define US_IMR_USART_RXBRK_Pos      2            /**< \brief (US_IMR_USART) Receiver Break Interrupt Mask */
2582 #define US_IMR_USART_RXBRK          (_U_(0x1) << US_IMR_USART_RXBRK_Pos)
2583 #define   US_IMR_USART_RXBRK_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2584 #define   US_IMR_USART_RXBRK_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2585 #define US_IMR_USART_RXBRK_0        (US_IMR_USART_RXBRK_0_Val      << US_IMR_USART_RXBRK_Pos)
2586 #define US_IMR_USART_RXBRK_1        (US_IMR_USART_RXBRK_1_Val      << US_IMR_USART_RXBRK_Pos)
2587 #define US_IMR_USART_OVRE_Pos       5            /**< \brief (US_IMR_USART) Overrun Error Interrupt Mask */
2588 #define US_IMR_USART_OVRE           (_U_(0x1) << US_IMR_USART_OVRE_Pos)
2589 #define   US_IMR_USART_OVRE_0_Val         _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2590 #define   US_IMR_USART_OVRE_1_Val         _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2591 #define US_IMR_USART_OVRE_0         (US_IMR_USART_OVRE_0_Val       << US_IMR_USART_OVRE_Pos)
2592 #define US_IMR_USART_OVRE_1         (US_IMR_USART_OVRE_1_Val       << US_IMR_USART_OVRE_Pos)
2593 #define US_IMR_USART_FRAME_Pos      6            /**< \brief (US_IMR_USART) Framing Error Interrupt Mask */
2594 #define US_IMR_USART_FRAME          (_U_(0x1) << US_IMR_USART_FRAME_Pos)
2595 #define   US_IMR_USART_FRAME_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2596 #define   US_IMR_USART_FRAME_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2597 #define US_IMR_USART_FRAME_0        (US_IMR_USART_FRAME_0_Val      << US_IMR_USART_FRAME_Pos)
2598 #define US_IMR_USART_FRAME_1        (US_IMR_USART_FRAME_1_Val      << US_IMR_USART_FRAME_Pos)
2599 #define US_IMR_USART_PARE_Pos       7            /**< \brief (US_IMR_USART) Parity Error Interrupt Mask */
2600 #define US_IMR_USART_PARE           (_U_(0x1) << US_IMR_USART_PARE_Pos)
2601 #define   US_IMR_USART_PARE_0_Val         _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2602 #define   US_IMR_USART_PARE_1_Val         _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2603 #define US_IMR_USART_PARE_0         (US_IMR_USART_PARE_0_Val       << US_IMR_USART_PARE_Pos)
2604 #define US_IMR_USART_PARE_1         (US_IMR_USART_PARE_1_Val       << US_IMR_USART_PARE_Pos)
2605 #define US_IMR_USART_TIMEOUT_Pos    8            /**< \brief (US_IMR_USART) Time-out Interrupt Mask */
2606 #define US_IMR_USART_TIMEOUT        (_U_(0x1) << US_IMR_USART_TIMEOUT_Pos)
2607 #define   US_IMR_USART_TIMEOUT_0_Val      _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2608 #define   US_IMR_USART_TIMEOUT_1_Val      _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2609 #define US_IMR_USART_TIMEOUT_0      (US_IMR_USART_TIMEOUT_0_Val    << US_IMR_USART_TIMEOUT_Pos)
2610 #define US_IMR_USART_TIMEOUT_1      (US_IMR_USART_TIMEOUT_1_Val    << US_IMR_USART_TIMEOUT_Pos)
2611 #define US_IMR_USART_TXEMPTY_Pos    9            /**< \brief (US_IMR_USART) TXEMPTY Interrupt Mask */
2612 #define US_IMR_USART_TXEMPTY        (_U_(0x1) << US_IMR_USART_TXEMPTY_Pos)
2613 #define   US_IMR_USART_TXEMPTY_0_Val      _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2614 #define   US_IMR_USART_TXEMPTY_1_Val      _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2615 #define US_IMR_USART_TXEMPTY_0      (US_IMR_USART_TXEMPTY_0_Val    << US_IMR_USART_TXEMPTY_Pos)
2616 #define US_IMR_USART_TXEMPTY_1      (US_IMR_USART_TXEMPTY_1_Val    << US_IMR_USART_TXEMPTY_Pos)
2617 #define US_IMR_USART_ITER_Pos       10           /**< \brief (US_IMR_USART) Iteration Interrupt Mask */
2618 #define US_IMR_USART_ITER           (_U_(0x1) << US_IMR_USART_ITER_Pos)
2619 #define   US_IMR_USART_ITER_0_Val         _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2620 #define   US_IMR_USART_ITER_1_Val         _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2621 #define US_IMR_USART_ITER_0         (US_IMR_USART_ITER_0_Val       << US_IMR_USART_ITER_Pos)
2622 #define US_IMR_USART_ITER_1         (US_IMR_USART_ITER_1_Val       << US_IMR_USART_ITER_Pos)
2623 #define US_IMR_USART_TXBUFE_Pos     11           /**< \brief (US_IMR_USART) Buffer Empty Interrupt Mask */
2624 #define US_IMR_USART_TXBUFE         (_U_(0x1) << US_IMR_USART_TXBUFE_Pos)
2625 #define   US_IMR_USART_TXBUFE_0_Val       _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2626 #define   US_IMR_USART_TXBUFE_1_Val       _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2627 #define US_IMR_USART_TXBUFE_0       (US_IMR_USART_TXBUFE_0_Val     << US_IMR_USART_TXBUFE_Pos)
2628 #define US_IMR_USART_TXBUFE_1       (US_IMR_USART_TXBUFE_1_Val     << US_IMR_USART_TXBUFE_Pos)
2629 #define US_IMR_USART_RXBUFF_Pos     12           /**< \brief (US_IMR_USART) Buffer Full Interrupt Mask */
2630 #define US_IMR_USART_RXBUFF         (_U_(0x1) << US_IMR_USART_RXBUFF_Pos)
2631 #define   US_IMR_USART_RXBUFF_0_Val       _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2632 #define   US_IMR_USART_RXBUFF_1_Val       _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2633 #define US_IMR_USART_RXBUFF_0       (US_IMR_USART_RXBUFF_0_Val     << US_IMR_USART_RXBUFF_Pos)
2634 #define US_IMR_USART_RXBUFF_1       (US_IMR_USART_RXBUFF_1_Val     << US_IMR_USART_RXBUFF_Pos)
2635 #define US_IMR_USART_NACK_Pos       13           /**< \brief (US_IMR_USART) Non Acknowledge Interrupt Mask */
2636 #define US_IMR_USART_NACK           (_U_(0x1) << US_IMR_USART_NACK_Pos)
2637 #define   US_IMR_USART_NACK_0_Val         _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2638 #define   US_IMR_USART_NACK_1_Val         _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2639 #define US_IMR_USART_NACK_0         (US_IMR_USART_NACK_0_Val       << US_IMR_USART_NACK_Pos)
2640 #define US_IMR_USART_NACK_1         (US_IMR_USART_NACK_1_Val       << US_IMR_USART_NACK_Pos)
2641 #define US_IMR_USART_RIIC_Pos       16           /**< \brief (US_IMR_USART) Ring Indicator Input Change Mask */
2642 #define US_IMR_USART_RIIC           (_U_(0x1) << US_IMR_USART_RIIC_Pos)
2643 #define   US_IMR_USART_RIIC_0_Val         _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2644 #define   US_IMR_USART_RIIC_1_Val         _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2645 #define US_IMR_USART_RIIC_0         (US_IMR_USART_RIIC_0_Val       << US_IMR_USART_RIIC_Pos)
2646 #define US_IMR_USART_RIIC_1         (US_IMR_USART_RIIC_1_Val       << US_IMR_USART_RIIC_Pos)
2647 #define US_IMR_USART_DSRIC_Pos      17           /**< \brief (US_IMR_USART) Data Set Ready Input Change Mask */
2648 #define US_IMR_USART_DSRIC          (_U_(0x1) << US_IMR_USART_DSRIC_Pos)
2649 #define   US_IMR_USART_DSRIC_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2650 #define   US_IMR_USART_DSRIC_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2651 #define US_IMR_USART_DSRIC_0        (US_IMR_USART_DSRIC_0_Val      << US_IMR_USART_DSRIC_Pos)
2652 #define US_IMR_USART_DSRIC_1        (US_IMR_USART_DSRIC_1_Val      << US_IMR_USART_DSRIC_Pos)
2653 #define US_IMR_USART_DCDIC_Pos      18           /**< \brief (US_IMR_USART) Data Carrier Detect Input Change Interrupt Mask */
2654 #define US_IMR_USART_DCDIC          (_U_(0x1) << US_IMR_USART_DCDIC_Pos)
2655 #define   US_IMR_USART_DCDIC_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2656 #define   US_IMR_USART_DCDIC_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2657 #define US_IMR_USART_DCDIC_0        (US_IMR_USART_DCDIC_0_Val      << US_IMR_USART_DCDIC_Pos)
2658 #define US_IMR_USART_DCDIC_1        (US_IMR_USART_DCDIC_1_Val      << US_IMR_USART_DCDIC_Pos)
2659 #define US_IMR_USART_CTSIC_Pos      19           /**< \brief (US_IMR_USART) Clear to Send Input Change Interrupt Mask */
2660 #define US_IMR_USART_CTSIC          (_U_(0x1) << US_IMR_USART_CTSIC_Pos)
2661 #define   US_IMR_USART_CTSIC_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2662 #define   US_IMR_USART_CTSIC_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2663 #define US_IMR_USART_CTSIC_0        (US_IMR_USART_CTSIC_0_Val      << US_IMR_USART_CTSIC_Pos)
2664 #define US_IMR_USART_CTSIC_1        (US_IMR_USART_CTSIC_1_Val      << US_IMR_USART_CTSIC_Pos)
2665 #define US_IMR_USART_MANE_Pos       20           /**< \brief (US_IMR_USART) Manchester Error Interrupt Mask */
2666 #define US_IMR_USART_MANE           (_U_(0x1) << US_IMR_USART_MANE_Pos)
2667 #define US_IMR_USART_MANEA_Pos      24           /**< \brief (US_IMR_USART) Manchester Error Interrupt Mask */
2668 #define US_IMR_USART_MANEA          (_U_(0x1) << US_IMR_USART_MANEA_Pos)
2669 #define   US_IMR_USART_MANEA_0_Val        _U_(0x0)   /**< \brief (US_IMR_USART) The interrupt is disabled */
2670 #define   US_IMR_USART_MANEA_1_Val        _U_(0x1)   /**< \brief (US_IMR_USART) The interrupt is enabled */
2671 #define US_IMR_USART_MANEA_0        (US_IMR_USART_MANEA_0_Val      << US_IMR_USART_MANEA_Pos)
2672 #define US_IMR_USART_MANEA_1        (US_IMR_USART_MANEA_1_Val      << US_IMR_USART_MANEA_Pos)
2673 #define US_IMR_USART_MASK           _U_(0x011F3FE7) /**< \brief (US_IMR_USART) MASK Register */
2674 
2675 // Any mode
2676 #define US_IMR_RXRDY_Pos            0            /**< \brief (US_IMR) RXRDY Interrupt Mask */
2677 #define US_IMR_RXRDY                (_U_(0x1) << US_IMR_RXRDY_Pos)
2678 #define   US_IMR_RXRDY_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2679 #define   US_IMR_RXRDY_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2680 #define US_IMR_RXRDY_0              (US_IMR_RXRDY_0_Val            << US_IMR_RXRDY_Pos)
2681 #define US_IMR_RXRDY_1              (US_IMR_RXRDY_1_Val            << US_IMR_RXRDY_Pos)
2682 #define US_IMR_TXRDY_Pos            1            /**< \brief (US_IMR) TXRDY Interrupt Mask */
2683 #define US_IMR_TXRDY                (_U_(0x1) << US_IMR_TXRDY_Pos)
2684 #define   US_IMR_TXRDY_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2685 #define   US_IMR_TXRDY_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2686 #define US_IMR_TXRDY_0              (US_IMR_TXRDY_0_Val            << US_IMR_TXRDY_Pos)
2687 #define US_IMR_TXRDY_1              (US_IMR_TXRDY_1_Val            << US_IMR_TXRDY_Pos)
2688 #define US_IMR_RXBRK_Pos            2            /**< \brief (US_IMR) Receiver Break Interrupt Mask */
2689 #define US_IMR_RXBRK                (_U_(0x1) << US_IMR_RXBRK_Pos)
2690 #define   US_IMR_RXBRK_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2691 #define   US_IMR_RXBRK_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2692 #define US_IMR_RXBRK_0              (US_IMR_RXBRK_0_Val            << US_IMR_RXBRK_Pos)
2693 #define US_IMR_RXBRK_1              (US_IMR_RXBRK_1_Val            << US_IMR_RXBRK_Pos)
2694 #define US_IMR_OVRE_Pos             5            /**< \brief (US_IMR) Overrun Error Interrupt Mask */
2695 #define US_IMR_OVRE                 (_U_(0x1) << US_IMR_OVRE_Pos)
2696 #define   US_IMR_OVRE_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2697 #define   US_IMR_OVRE_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2698 #define US_IMR_OVRE_0               (US_IMR_OVRE_0_Val             << US_IMR_OVRE_Pos)
2699 #define US_IMR_OVRE_1               (US_IMR_OVRE_1_Val             << US_IMR_OVRE_Pos)
2700 #define US_IMR_FRAME_Pos            6            /**< \brief (US_IMR) Framing Error Interrupt Mask */
2701 #define US_IMR_FRAME                (_U_(0x1) << US_IMR_FRAME_Pos)
2702 #define   US_IMR_FRAME_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2703 #define   US_IMR_FRAME_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2704 #define US_IMR_FRAME_0              (US_IMR_FRAME_0_Val            << US_IMR_FRAME_Pos)
2705 #define US_IMR_FRAME_1              (US_IMR_FRAME_1_Val            << US_IMR_FRAME_Pos)
2706 #define US_IMR_PARE_Pos             7            /**< \brief (US_IMR) Parity Error Interrupt Mask */
2707 #define US_IMR_PARE                 (_U_(0x1) << US_IMR_PARE_Pos)
2708 #define   US_IMR_PARE_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2709 #define   US_IMR_PARE_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2710 #define US_IMR_PARE_0               (US_IMR_PARE_0_Val             << US_IMR_PARE_Pos)
2711 #define US_IMR_PARE_1               (US_IMR_PARE_1_Val             << US_IMR_PARE_Pos)
2712 #define US_IMR_TIMEOUT_Pos          8            /**< \brief (US_IMR) Time-out Interrupt Mask */
2713 #define US_IMR_TIMEOUT              (_U_(0x1) << US_IMR_TIMEOUT_Pos)
2714 #define   US_IMR_TIMEOUT_0_Val            _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2715 #define   US_IMR_TIMEOUT_1_Val            _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2716 #define US_IMR_TIMEOUT_0            (US_IMR_TIMEOUT_0_Val          << US_IMR_TIMEOUT_Pos)
2717 #define US_IMR_TIMEOUT_1            (US_IMR_TIMEOUT_1_Val          << US_IMR_TIMEOUT_Pos)
2718 #define US_IMR_TXEMPTY_Pos          9            /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
2719 #define US_IMR_TXEMPTY              (_U_(0x1) << US_IMR_TXEMPTY_Pos)
2720 #define   US_IMR_TXEMPTY_0_Val            _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2721 #define   US_IMR_TXEMPTY_1_Val            _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2722 #define US_IMR_TXEMPTY_0            (US_IMR_TXEMPTY_0_Val          << US_IMR_TXEMPTY_Pos)
2723 #define US_IMR_TXEMPTY_1            (US_IMR_TXEMPTY_1_Val          << US_IMR_TXEMPTY_Pos)
2724 #define US_IMR_ITER_Pos             10           /**< \brief (US_IMR) Iteration Interrupt Mask */
2725 #define US_IMR_ITER                 (_U_(0x1) << US_IMR_ITER_Pos)
2726 #define   US_IMR_ITER_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2727 #define   US_IMR_ITER_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2728 #define US_IMR_ITER_0               (US_IMR_ITER_0_Val             << US_IMR_ITER_Pos)
2729 #define US_IMR_ITER_1               (US_IMR_ITER_1_Val             << US_IMR_ITER_Pos)
2730 #define US_IMR_UNRE_Pos             10           /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */
2731 #define US_IMR_UNRE                 (_U_(0x1) << US_IMR_UNRE_Pos)
2732 #define   US_IMR_UNRE_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2733 #define   US_IMR_UNRE_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2734 #define US_IMR_UNRE_0               (US_IMR_UNRE_0_Val             << US_IMR_UNRE_Pos)
2735 #define US_IMR_UNRE_1               (US_IMR_UNRE_1_Val             << US_IMR_UNRE_Pos)
2736 #define US_IMR_ITER_Pos             10           /**< \brief (US_IMR) Iteration Interrupt Mask */
2737 #define US_IMR_ITER                 (_U_(0x1) << US_IMR_ITER_Pos)
2738 #define   US_IMR_ITER_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2739 #define   US_IMR_ITER_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2740 #define US_IMR_ITER_0               (US_IMR_ITER_0_Val             << US_IMR_ITER_Pos)
2741 #define US_IMR_ITER_1               (US_IMR_ITER_1_Val             << US_IMR_ITER_Pos)
2742 #define US_IMR_TXBUFE_Pos           11           /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
2743 #define US_IMR_TXBUFE               (_U_(0x1) << US_IMR_TXBUFE_Pos)
2744 #define   US_IMR_TXBUFE_0_Val             _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2745 #define   US_IMR_TXBUFE_1_Val             _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2746 #define US_IMR_TXBUFE_0             (US_IMR_TXBUFE_0_Val           << US_IMR_TXBUFE_Pos)
2747 #define US_IMR_TXBUFE_1             (US_IMR_TXBUFE_1_Val           << US_IMR_TXBUFE_Pos)
2748 #define US_IMR_RXBUFF_Pos           12           /**< \brief (US_IMR) Buffer Full Interrupt Mask */
2749 #define US_IMR_RXBUFF               (_U_(0x1) << US_IMR_RXBUFF_Pos)
2750 #define   US_IMR_RXBUFF_0_Val             _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2751 #define   US_IMR_RXBUFF_1_Val             _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2752 #define US_IMR_RXBUFF_0             (US_IMR_RXBUFF_0_Val           << US_IMR_RXBUFF_Pos)
2753 #define US_IMR_RXBUFF_1             (US_IMR_RXBUFF_1_Val           << US_IMR_RXBUFF_Pos)
2754 #define US_IMR_NACK_Pos             13           /**< \brief (US_IMR) Non Acknowledge  or LIN Break Sent or LIN Break Received Interrupt Mask */
2755 #define US_IMR_NACK                 (_U_(0x1) << US_IMR_NACK_Pos)
2756 #define   US_IMR_NACK_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2757 #define   US_IMR_NACK_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2758 #define US_IMR_NACK_0               (US_IMR_NACK_0_Val             << US_IMR_NACK_Pos)
2759 #define US_IMR_NACK_1               (US_IMR_NACK_1_Val             << US_IMR_NACK_Pos)
2760 #define US_IMR_LINID_Pos            14           /**< \brief (US_IMR) LIN Identifier Sent or LIN Received Interrupt Mask */
2761 #define US_IMR_LINID                (_U_(0x1) << US_IMR_LINID_Pos)
2762 #define US_IMR_LINTC_Pos            15           /**< \brief (US_IMR) LIN Transfer Conpleted Interrupt Mask */
2763 #define US_IMR_LINTC                (_U_(0x1) << US_IMR_LINTC_Pos)
2764 #define US_IMR_RIIC_Pos             16           /**< \brief (US_IMR) Ring Indicator Input Change Mask */
2765 #define US_IMR_RIIC                 (_U_(0x1) << US_IMR_RIIC_Pos)
2766 #define   US_IMR_RIIC_0_Val               _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2767 #define   US_IMR_RIIC_1_Val               _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2768 #define US_IMR_RIIC_0               (US_IMR_RIIC_0_Val             << US_IMR_RIIC_Pos)
2769 #define US_IMR_RIIC_1               (US_IMR_RIIC_1_Val             << US_IMR_RIIC_Pos)
2770 #define US_IMR_DSRIC_Pos            17           /**< \brief (US_IMR) Data Set Ready Input Change Mask */
2771 #define US_IMR_DSRIC                (_U_(0x1) << US_IMR_DSRIC_Pos)
2772 #define   US_IMR_DSRIC_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2773 #define   US_IMR_DSRIC_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2774 #define US_IMR_DSRIC_0              (US_IMR_DSRIC_0_Val            << US_IMR_DSRIC_Pos)
2775 #define US_IMR_DSRIC_1              (US_IMR_DSRIC_1_Val            << US_IMR_DSRIC_Pos)
2776 #define US_IMR_DCDIC_Pos            18           /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
2777 #define US_IMR_DCDIC                (_U_(0x1) << US_IMR_DCDIC_Pos)
2778 #define   US_IMR_DCDIC_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2779 #define   US_IMR_DCDIC_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2780 #define US_IMR_DCDIC_0              (US_IMR_DCDIC_0_Val            << US_IMR_DCDIC_Pos)
2781 #define US_IMR_DCDIC_1              (US_IMR_DCDIC_1_Val            << US_IMR_DCDIC_Pos)
2782 #define US_IMR_CTSIC_Pos            19           /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
2783 #define US_IMR_CTSIC                (_U_(0x1) << US_IMR_CTSIC_Pos)
2784 #define   US_IMR_CTSIC_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2785 #define   US_IMR_CTSIC_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2786 #define US_IMR_CTSIC_0              (US_IMR_CTSIC_0_Val            << US_IMR_CTSIC_Pos)
2787 #define US_IMR_CTSIC_1              (US_IMR_CTSIC_1_Val            << US_IMR_CTSIC_Pos)
2788 #define US_IMR_MANE_Pos             20           /**< \brief (US_IMR) Manchester Error Interrupt Mask */
2789 #define US_IMR_MANE                 (_U_(0x1) << US_IMR_MANE_Pos)
2790 #define US_IMR_MANEA_Pos            24           /**< \brief (US_IMR) Manchester Error Interrupt Mask */
2791 #define US_IMR_MANEA                (_U_(0x1) << US_IMR_MANEA_Pos)
2792 #define   US_IMR_MANEA_0_Val              _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2793 #define   US_IMR_MANEA_1_Val              _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2794 #define US_IMR_MANEA_0              (US_IMR_MANEA_0_Val            << US_IMR_MANEA_Pos)
2795 #define US_IMR_MANEA_1              (US_IMR_MANEA_1_Val            << US_IMR_MANEA_Pos)
2796 #define US_IMR_LINBE_Pos            25           /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */
2797 #define US_IMR_LINBE                (_U_(0x1) << US_IMR_LINBE_Pos)
2798 #define US_IMR_LINISFE_Pos          26           /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */
2799 #define US_IMR_LINISFE              (_U_(0x1) << US_IMR_LINISFE_Pos)
2800 #define US_IMR_LINIPE_Pos           27           /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */
2801 #define US_IMR_LINIPE               (_U_(0x1) << US_IMR_LINIPE_Pos)
2802 #define US_IMR_LINCE_Pos            28           /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */
2803 #define US_IMR_LINCE                (_U_(0x1) << US_IMR_LINCE_Pos)
2804 #define US_IMR_LINSNRE_Pos          29           /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */
2805 #define US_IMR_LINSNRE              (_U_(0x1) << US_IMR_LINSNRE_Pos)
2806 #define US_IMR_LINSTE_Pos           30           /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */
2807 #define US_IMR_LINSTE               (_U_(0x1) << US_IMR_LINSTE_Pos)
2808 #define   US_IMR_LINSTE_0_Val             _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2809 #define   US_IMR_LINSTE_1_Val             _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2810 #define US_IMR_LINSTE_0             (US_IMR_LINSTE_0_Val           << US_IMR_LINSTE_Pos)
2811 #define US_IMR_LINSTE_1             (US_IMR_LINSTE_1_Val           << US_IMR_LINSTE_Pos)
2812 #define US_IMR_LINHTE_Pos           31           /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */
2813 #define US_IMR_LINHTE               (_U_(0x1) << US_IMR_LINHTE_Pos)
2814 #define   US_IMR_LINHTE_0_Val             _U_(0x0)   /**< \brief (US_IMR) The interrupt is disabled */
2815 #define   US_IMR_LINHTE_1_Val             _U_(0x1)   /**< \brief (US_IMR) The interrupt is enabled */
2816 #define US_IMR_LINHTE_0             (US_IMR_LINHTE_0_Val           << US_IMR_LINHTE_Pos)
2817 #define US_IMR_LINHTE_1             (US_IMR_LINHTE_1_Val           << US_IMR_LINHTE_Pos)
2818 #define US_IMR_MASK                 _U_(0xFF1FFFE7) /**< \brief (US_IMR) MASK Register */
2819 
2820 /* -------- US_CSR : (USART Offset: 0x14) (R/  32) Channel Status Register -------- */
2821 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
2822 typedef union {
2823   struct { // LIN mode
2824     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready                     */
2825     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready                  */
2826     uint32_t RXBRK:1;          /*!< bit:      2  Break Received/End of Break        */
2827     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
2828     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error                      */
2829     uint32_t FRAME:1;          /*!< bit:      6  Framing Error                      */
2830     uint32_t PARE:1;           /*!< bit:      7  Parity Error                       */
2831     uint32_t TIMEOUT:1;        /*!< bit:      8  Receiver Time-out                  */
2832     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty                  */
2833     uint32_t ITER:1;           /*!< bit:     10  Max number of Repetitions Reached  */
2834     uint32_t TXBUFE:1;         /*!< bit:     11  Transmission Buffer Empty          */
2835     uint32_t RXBUFF:1;         /*!< bit:     12  Reception Buffer Full              */
2836     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge or LIN Break Sent or LIN Break Received */
2837     uint32_t LINID:1;          /*!< bit:     14  LIN Identifier Sent or LIN Identifier Received */
2838     uint32_t LINTC:1;          /*!< bit:     15  LIN Transfer Conpleted             */
2839     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Flag   */
2840     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Flag   */
2841     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Flag */
2842     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Flag    */
2843     uint32_t RI:1;             /*!< bit:     20  Image of RI Input                  */
2844     uint32_t DSR:1;            /*!< bit:     21  Image of DSR Input                 */
2845     uint32_t DCD:1;            /*!< bit:     22  Image of DCD Input                 */
2846     uint32_t LINBLS:1;         /*!< bit:     23  LIN Bus Line Status                */
2847     uint32_t :1;               /*!< bit:     24  Reserved                           */
2848     uint32_t LINBE:1;          /*!< bit:     25  LIN Bit Error                      */
2849     uint32_t LINISFE:1;        /*!< bit:     26  LIN Inconsistent Synch Field Error */
2850     uint32_t LINIPE:1;         /*!< bit:     27  LIN Identifier Parity Error        */
2851     uint32_t LINCE:1;          /*!< bit:     28  LIN Checksum Error                 */
2852     uint32_t LINSNRE:1;        /*!< bit:     29  LIN Slave Not Responding Error     */
2853     uint32_t LINSTE:1;         /*!< bit:     30  LIN Synch Tolerance Error          */
2854     uint32_t LINHTE:1;         /*!< bit:     31  LIN Header Timeout Error           */
2855   } LIN;                       /*!< Structure used for LIN                          */
2856   struct { // SPI_SLAVE mode
2857     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready                     */
2858     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready                  */
2859     uint32_t RXBRK:1;          /*!< bit:      2  Break Received/End of Break        */
2860     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
2861     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error                      */
2862     uint32_t FRAME:1;          /*!< bit:      6  Framing Error                      */
2863     uint32_t PARE:1;           /*!< bit:      7  Parity Error                       */
2864     uint32_t TIMEOUT:1;        /*!< bit:      8  Receiver Time-out                  */
2865     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty                  */
2866     uint32_t UNRE:1;           /*!< bit:     10  SPI Underrun Error                 */
2867     uint32_t TXBUFE:1;         /*!< bit:     11  Transmission Buffer Empty          */
2868     uint32_t RXBUFF:1;         /*!< bit:     12  Reception Buffer Full              */
2869     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge                    */
2870     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
2871     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Flag   */
2872     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Flag   */
2873     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Flag */
2874     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Flag    */
2875     uint32_t RI:1;             /*!< bit:     20  Image of RI Input                  */
2876     uint32_t DSR:1;            /*!< bit:     21  Image of DSR Input                 */
2877     uint32_t DCD:1;            /*!< bit:     22  Image of DCD Input                 */
2878     uint32_t CTS:1;            /*!< bit:     23  Image of CTS Input                 */
2879     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
2880   } SPI_SLAVE;                 /*!< Structure used for SPI_SLAVE                    */
2881   struct { // USART mode
2882     uint32_t RXRDY:1;          /*!< bit:      0  Receiver Ready                     */
2883     uint32_t TXRDY:1;          /*!< bit:      1  Transmitter Ready                  */
2884     uint32_t RXBRK:1;          /*!< bit:      2  Break Received/End of Break        */
2885     uint32_t :2;               /*!< bit:  3.. 4  Reserved                           */
2886     uint32_t OVRE:1;           /*!< bit:      5  Overrun Error                      */
2887     uint32_t FRAME:1;          /*!< bit:      6  Framing Error                      */
2888     uint32_t PARE:1;           /*!< bit:      7  Parity Error                       */
2889     uint32_t TIMEOUT:1;        /*!< bit:      8  Receiver Time-out                  */
2890     uint32_t TXEMPTY:1;        /*!< bit:      9  Transmitter Empty                  */
2891     uint32_t ITER:1;           /*!< bit:     10  Max number of Repetitions Reached  */
2892     uint32_t TXBUFE:1;         /*!< bit:     11  Transmission Buffer Empty          */
2893     uint32_t RXBUFF:1;         /*!< bit:     12  Reception Buffer Full              */
2894     uint32_t NACK:1;           /*!< bit:     13  Non Acknowledge                    */
2895     uint32_t :2;               /*!< bit: 14..15  Reserved                           */
2896     uint32_t RIIC:1;           /*!< bit:     16  Ring Indicator Input Change Flag   */
2897     uint32_t DSRIC:1;          /*!< bit:     17  Data Set Ready Input Change Flag   */
2898     uint32_t DCDIC:1;          /*!< bit:     18  Data Carrier Detect Input Change Flag */
2899     uint32_t CTSIC:1;          /*!< bit:     19  Clear to Send Input Change Flag    */
2900     uint32_t RI:1;             /*!< bit:     20  Image of RI Input                  */
2901     uint32_t DSR:1;            /*!< bit:     21  Image of DSR Input                 */
2902     uint32_t DCD:1;            /*!< bit:     22  Image of DCD Input                 */
2903     uint32_t CTS:1;            /*!< bit:     23  Image of CTS Input                 */
2904     uint32_t MANERR:1;         /*!< bit:     24  Manchester Error                   */
2905     uint32_t :7;               /*!< bit: 25..31  Reserved                           */
2906   } USART;                     /*!< Structure used for USART                        */
2907   uint32_t reg;                /*!< Type      used for register access              */
2908 } US_CSR_Type;
2909 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
2910 
2911 #define US_CSR_OFFSET               0x14         /**< \brief (US_CSR offset) Channel Status Register */
2912 #define US_CSR_RESETVALUE           _U_(0x00000000); /**< \brief (US_CSR reset_value) Channel Status Register */
2913 
2914 // LIN mode
2915 #define US_CSR_LIN_RXRDY_Pos        0            /**< \brief (US_CSR_LIN) Receiver Ready */
2916 #define US_CSR_LIN_RXRDY            (_U_(0x1) << US_CSR_LIN_RXRDY_Pos)
2917 #define   US_CSR_LIN_RXRDY_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */
2918 #define   US_CSR_LIN_RXRDY_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) At least one complete character has been received and RHR has not yet been read */
2919 #define US_CSR_LIN_RXRDY_0          (US_CSR_LIN_RXRDY_0_Val        << US_CSR_LIN_RXRDY_Pos)
2920 #define US_CSR_LIN_RXRDY_1          (US_CSR_LIN_RXRDY_1_Val        << US_CSR_LIN_RXRDY_Pos)
2921 #define US_CSR_LIN_TXRDY_Pos        1            /**< \brief (US_CSR_LIN) Transmitter Ready */
2922 #define US_CSR_LIN_TXRDY            (_U_(0x1) << US_CSR_LIN_TXRDY_Pos)
2923 #define   US_CSR_LIN_TXRDY_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */
2924 #define   US_CSR_LIN_TXRDY_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) There is no character in the THR */
2925 #define US_CSR_LIN_TXRDY_0          (US_CSR_LIN_TXRDY_0_Val        << US_CSR_LIN_TXRDY_Pos)
2926 #define US_CSR_LIN_TXRDY_1          (US_CSR_LIN_TXRDY_1_Val        << US_CSR_LIN_TXRDY_Pos)
2927 #define US_CSR_LIN_RXBRK_Pos        2            /**< \brief (US_CSR_LIN) Break Received/End of Break */
2928 #define US_CSR_LIN_RXBRK            (_U_(0x1) << US_CSR_LIN_RXBRK_Pos)
2929 #define   US_CSR_LIN_RXBRK_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) No Break received or End of Break detected since the last RSTSTA */
2930 #define   US_CSR_LIN_RXBRK_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) Break Received or End of Break detected since the last RSTSTA */
2931 #define US_CSR_LIN_RXBRK_0          (US_CSR_LIN_RXBRK_0_Val        << US_CSR_LIN_RXBRK_Pos)
2932 #define US_CSR_LIN_RXBRK_1          (US_CSR_LIN_RXBRK_1_Val        << US_CSR_LIN_RXBRK_Pos)
2933 #define US_CSR_LIN_OVRE_Pos         5            /**< \brief (US_CSR_LIN) Overrun Error */
2934 #define US_CSR_LIN_OVRE             (_U_(0x1) << US_CSR_LIN_OVRE_Pos)
2935 #define   US_CSR_LIN_OVRE_0_Val           _U_(0x0)   /**< \brief (US_CSR_LIN) No overrun error has occurred since since the last RSTSTA */
2936 #define   US_CSR_LIN_OVRE_1_Val           _U_(0x1)   /**< \brief (US_CSR_LIN) At least one overrun error has occurred since the last RSTSTA */
2937 #define US_CSR_LIN_OVRE_0           (US_CSR_LIN_OVRE_0_Val         << US_CSR_LIN_OVRE_Pos)
2938 #define US_CSR_LIN_OVRE_1           (US_CSR_LIN_OVRE_1_Val         << US_CSR_LIN_OVRE_Pos)
2939 #define US_CSR_LIN_FRAME_Pos        6            /**< \brief (US_CSR_LIN) Framing Error */
2940 #define US_CSR_LIN_FRAME            (_U_(0x1) << US_CSR_LIN_FRAME_Pos)
2941 #define   US_CSR_LIN_FRAME_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) No stop bit has been detected low since the last RSTSTA */
2942 #define   US_CSR_LIN_FRAME_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) At least one stop bit has been detected low since the last RSTSTA */
2943 #define US_CSR_LIN_FRAME_0          (US_CSR_LIN_FRAME_0_Val        << US_CSR_LIN_FRAME_Pos)
2944 #define US_CSR_LIN_FRAME_1          (US_CSR_LIN_FRAME_1_Val        << US_CSR_LIN_FRAME_Pos)
2945 #define US_CSR_LIN_PARE_Pos         7            /**< \brief (US_CSR_LIN) Parity Error */
2946 #define US_CSR_LIN_PARE             (_U_(0x1) << US_CSR_LIN_PARE_Pos)
2947 #define   US_CSR_LIN_PARE_0_Val           _U_(0x0)   /**< \brief (US_CSR_LIN) No parity error has been detected since the last RSTSTA */
2948 #define   US_CSR_LIN_PARE_1_Val           _U_(0x1)   /**< \brief (US_CSR_LIN) At least one parity error has been detected since the last RSTSTA */
2949 #define US_CSR_LIN_PARE_0           (US_CSR_LIN_PARE_0_Val         << US_CSR_LIN_PARE_Pos)
2950 #define US_CSR_LIN_PARE_1           (US_CSR_LIN_PARE_1_Val         << US_CSR_LIN_PARE_Pos)
2951 #define US_CSR_LIN_TIMEOUT_Pos      8            /**< \brief (US_CSR_LIN) Receiver Time-out */
2952 #define US_CSR_LIN_TIMEOUT          (_U_(0x1) << US_CSR_LIN_TIMEOUT_Pos)
2953 #define   US_CSR_LIN_TIMEOUT_0_Val        _U_(0x0)   /**< \brief (US_CSR_LIN) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */
2954 #define   US_CSR_LIN_TIMEOUT_1_Val        _U_(0x1)   /**< \brief (US_CSR_LIN) There has been a time-out since the last Start Time-out command */
2955 #define US_CSR_LIN_TIMEOUT_0        (US_CSR_LIN_TIMEOUT_0_Val      << US_CSR_LIN_TIMEOUT_Pos)
2956 #define US_CSR_LIN_TIMEOUT_1        (US_CSR_LIN_TIMEOUT_1_Val      << US_CSR_LIN_TIMEOUT_Pos)
2957 #define US_CSR_LIN_TXEMPTY_Pos      9            /**< \brief (US_CSR_LIN) Transmitter Empty */
2958 #define US_CSR_LIN_TXEMPTY          (_U_(0x1) << US_CSR_LIN_TXEMPTY_Pos)
2959 #define   US_CSR_LIN_TXEMPTY_0_Val        _U_(0x0)   /**< \brief (US_CSR_LIN) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */
2960 #define   US_CSR_LIN_TXEMPTY_1_Val        _U_(0x1)   /**< \brief (US_CSR_LIN) There is at least one character in either THR or the Transmit Shift Register */
2961 #define US_CSR_LIN_TXEMPTY_0        (US_CSR_LIN_TXEMPTY_0_Val      << US_CSR_LIN_TXEMPTY_Pos)
2962 #define US_CSR_LIN_TXEMPTY_1        (US_CSR_LIN_TXEMPTY_1_Val      << US_CSR_LIN_TXEMPTY_Pos)
2963 #define US_CSR_LIN_ITER_Pos         10           /**< \brief (US_CSR_LIN) Max number of Repetitions Reached */
2964 #define US_CSR_LIN_ITER             (_U_(0x1) << US_CSR_LIN_ITER_Pos)
2965 #define   US_CSR_LIN_ITER_0_Val           _U_(0x0)   /**< \brief (US_CSR_LIN) Maximum number of repetitions has not been reached since the last RSIT */
2966 #define   US_CSR_LIN_ITER_1_Val           _U_(0x1)   /**< \brief (US_CSR_LIN) Maximum number of repetitions has been reached since the last RSIT */
2967 #define US_CSR_LIN_ITER_0           (US_CSR_LIN_ITER_0_Val         << US_CSR_LIN_ITER_Pos)
2968 #define US_CSR_LIN_ITER_1           (US_CSR_LIN_ITER_1_Val         << US_CSR_LIN_ITER_Pos)
2969 #define US_CSR_LIN_TXBUFE_Pos       11           /**< \brief (US_CSR_LIN) Transmission Buffer Empty */
2970 #define US_CSR_LIN_TXBUFE           (_U_(0x1) << US_CSR_LIN_TXBUFE_Pos)
2971 #define   US_CSR_LIN_TXBUFE_0_Val         _U_(0x0)   /**< \brief (US_CSR_LIN) The signal Buffer Empty from the Transmit PDC channel is inactive */
2972 #define   US_CSR_LIN_TXBUFE_1_Val         _U_(0x1)   /**< \brief (US_CSR_LIN) The signal Buffer Empty from the Transmit PDC channel is active */
2973 #define US_CSR_LIN_TXBUFE_0         (US_CSR_LIN_TXBUFE_0_Val       << US_CSR_LIN_TXBUFE_Pos)
2974 #define US_CSR_LIN_TXBUFE_1         (US_CSR_LIN_TXBUFE_1_Val       << US_CSR_LIN_TXBUFE_Pos)
2975 #define US_CSR_LIN_RXBUFF_Pos       12           /**< \brief (US_CSR_LIN) Reception Buffer Full */
2976 #define US_CSR_LIN_RXBUFF           (_U_(0x1) << US_CSR_LIN_RXBUFF_Pos)
2977 #define   US_CSR_LIN_RXBUFF_0_Val         _U_(0x0)   /**< \brief (US_CSR_LIN) The signal Buffer Full from the Receive PDC channel is inactive */
2978 #define   US_CSR_LIN_RXBUFF_1_Val         _U_(0x1)   /**< \brief (US_CSR_LIN) The signal Buffer Full from the Receive PDC channel is active */
2979 #define US_CSR_LIN_RXBUFF_0         (US_CSR_LIN_RXBUFF_0_Val       << US_CSR_LIN_RXBUFF_Pos)
2980 #define US_CSR_LIN_RXBUFF_1         (US_CSR_LIN_RXBUFF_1_Val       << US_CSR_LIN_RXBUFF_Pos)
2981 #define US_CSR_LIN_NACK_Pos         13           /**< \brief (US_CSR_LIN) Non Acknowledge or LIN Break Sent or LIN Break Received */
2982 #define US_CSR_LIN_NACK             (_U_(0x1) << US_CSR_LIN_NACK_Pos)
2983 #define   US_CSR_LIN_NACK_0_Val           _U_(0x0)   /**< \brief (US_CSR_LIN) No Non Acknowledge has not been detected since the last RSTNACK */
2984 #define   US_CSR_LIN_NACK_1_Val           _U_(0x1)   /**< \brief (US_CSR_LIN) At least one Non Acknowledge has been detected since the last RSTNACK */
2985 #define US_CSR_LIN_NACK_0           (US_CSR_LIN_NACK_0_Val         << US_CSR_LIN_NACK_Pos)
2986 #define US_CSR_LIN_NACK_1           (US_CSR_LIN_NACK_1_Val         << US_CSR_LIN_NACK_Pos)
2987 #define US_CSR_LIN_LINID_Pos        14           /**< \brief (US_CSR_LIN) LIN Identifier Sent or LIN Identifier Received */
2988 #define US_CSR_LIN_LINID            (_U_(0x1) << US_CSR_LIN_LINID_Pos)
2989 #define US_CSR_LIN_LINTC_Pos        15           /**< \brief (US_CSR_LIN) LIN Transfer Conpleted */
2990 #define US_CSR_LIN_LINTC            (_U_(0x1) << US_CSR_LIN_LINTC_Pos)
2991 #define US_CSR_LIN_RIIC_Pos         16           /**< \brief (US_CSR_LIN) Ring Indicator Input Change Flag */
2992 #define US_CSR_LIN_RIIC             (_U_(0x1) << US_CSR_LIN_RIIC_Pos)
2993 #define   US_CSR_LIN_RIIC_0_Val           _U_(0x0)   /**< \brief (US_CSR_LIN) No input change has been detected on the RI pin since the last read of CSR */
2994 #define   US_CSR_LIN_RIIC_1_Val           _U_(0x1)   /**< \brief (US_CSR_LIN) At least one input change has been detected on the RI pin since the last read of CSR */
2995 #define US_CSR_LIN_RIIC_0           (US_CSR_LIN_RIIC_0_Val         << US_CSR_LIN_RIIC_Pos)
2996 #define US_CSR_LIN_RIIC_1           (US_CSR_LIN_RIIC_1_Val         << US_CSR_LIN_RIIC_Pos)
2997 #define US_CSR_LIN_DSRIC_Pos        17           /**< \brief (US_CSR_LIN) Data Set Ready Input Change Flag */
2998 #define US_CSR_LIN_DSRIC            (_U_(0x1) << US_CSR_LIN_DSRIC_Pos)
2999 #define   US_CSR_LIN_DSRIC_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) No input change has been detected on the DSR pin since the last read of CSR */
3000 #define   US_CSR_LIN_DSRIC_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) At least one input change has been detected on the DSR pin since the last read of CSR */
3001 #define US_CSR_LIN_DSRIC_0          (US_CSR_LIN_DSRIC_0_Val        << US_CSR_LIN_DSRIC_Pos)
3002 #define US_CSR_LIN_DSRIC_1          (US_CSR_LIN_DSRIC_1_Val        << US_CSR_LIN_DSRIC_Pos)
3003 #define US_CSR_LIN_DCDIC_Pos        18           /**< \brief (US_CSR_LIN) Data Carrier Detect Input Change Flag */
3004 #define US_CSR_LIN_DCDIC            (_U_(0x1) << US_CSR_LIN_DCDIC_Pos)
3005 #define   US_CSR_LIN_DCDIC_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) No input change has been detected on the DCD pin since the last read of CSR */
3006 #define   US_CSR_LIN_DCDIC_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) At least one input change has been detected on the DCD pin since the last read of CSR */
3007 #define US_CSR_LIN_DCDIC_0          (US_CSR_LIN_DCDIC_0_Val        << US_CSR_LIN_DCDIC_Pos)
3008 #define US_CSR_LIN_DCDIC_1          (US_CSR_LIN_DCDIC_1_Val        << US_CSR_LIN_DCDIC_Pos)
3009 #define US_CSR_LIN_CTSIC_Pos        19           /**< \brief (US_CSR_LIN) Clear to Send Input Change Flag */
3010 #define US_CSR_LIN_CTSIC            (_U_(0x1) << US_CSR_LIN_CTSIC_Pos)
3011 #define   US_CSR_LIN_CTSIC_0_Val          _U_(0x0)   /**< \brief (US_CSR_LIN) No input change has been detected on the CTS pin since the last read of CSR */
3012 #define   US_CSR_LIN_CTSIC_1_Val          _U_(0x1)   /**< \brief (US_CSR_LIN) At least one input change has been detected on the CTS pin since the last read of CSR */
3013 #define US_CSR_LIN_CTSIC_0          (US_CSR_LIN_CTSIC_0_Val        << US_CSR_LIN_CTSIC_Pos)
3014 #define US_CSR_LIN_CTSIC_1          (US_CSR_LIN_CTSIC_1_Val        << US_CSR_LIN_CTSIC_Pos)
3015 #define US_CSR_LIN_RI_Pos           20           /**< \brief (US_CSR_LIN) Image of RI Input */
3016 #define US_CSR_LIN_RI               (_U_(0x1) << US_CSR_LIN_RI_Pos)
3017 #define   US_CSR_LIN_RI_0_Val             _U_(0x0)   /**< \brief (US_CSR_LIN) RI is at 0 */
3018 #define   US_CSR_LIN_RI_1_Val             _U_(0x1)   /**< \brief (US_CSR_LIN) RI is at 1 */
3019 #define US_CSR_LIN_RI_0             (US_CSR_LIN_RI_0_Val           << US_CSR_LIN_RI_Pos)
3020 #define US_CSR_LIN_RI_1             (US_CSR_LIN_RI_1_Val           << US_CSR_LIN_RI_Pos)
3021 #define US_CSR_LIN_DSR_Pos          21           /**< \brief (US_CSR_LIN) Image of DSR Input */
3022 #define US_CSR_LIN_DSR              (_U_(0x1) << US_CSR_LIN_DSR_Pos)
3023 #define   US_CSR_LIN_DSR_0_Val            _U_(0x0)   /**< \brief (US_CSR_LIN) DSR is at 0 */
3024 #define   US_CSR_LIN_DSR_1_Val            _U_(0x1)   /**< \brief (US_CSR_LIN) DSR is at 1 */
3025 #define US_CSR_LIN_DSR_0            (US_CSR_LIN_DSR_0_Val          << US_CSR_LIN_DSR_Pos)
3026 #define US_CSR_LIN_DSR_1            (US_CSR_LIN_DSR_1_Val          << US_CSR_LIN_DSR_Pos)
3027 #define US_CSR_LIN_DCD_Pos          22           /**< \brief (US_CSR_LIN) Image of DCD Input */
3028 #define US_CSR_LIN_DCD              (_U_(0x1) << US_CSR_LIN_DCD_Pos)
3029 #define   US_CSR_LIN_DCD_0_Val            _U_(0x0)   /**< \brief (US_CSR_LIN) DCD is at 0 */
3030 #define   US_CSR_LIN_DCD_1_Val            _U_(0x1)   /**< \brief (US_CSR_LIN) DCD is at 1 */
3031 #define US_CSR_LIN_DCD_0            (US_CSR_LIN_DCD_0_Val          << US_CSR_LIN_DCD_Pos)
3032 #define US_CSR_LIN_DCD_1            (US_CSR_LIN_DCD_1_Val          << US_CSR_LIN_DCD_Pos)
3033 #define US_CSR_LIN_LINBLS_Pos       23           /**< \brief (US_CSR_LIN) LIN Bus Line Status */
3034 #define US_CSR_LIN_LINBLS           (_U_(0x1) << US_CSR_LIN_LINBLS_Pos)
3035 #define   US_CSR_LIN_LINBLS_0_Val         _U_(0x0)   /**< \brief (US_CSR_LIN) CTS is at 0 */
3036 #define   US_CSR_LIN_LINBLS_1_Val         _U_(0x1)   /**< \brief (US_CSR_LIN) CTS is at 1 */
3037 #define US_CSR_LIN_LINBLS_0         (US_CSR_LIN_LINBLS_0_Val       << US_CSR_LIN_LINBLS_Pos)
3038 #define US_CSR_LIN_LINBLS_1         (US_CSR_LIN_LINBLS_1_Val       << US_CSR_LIN_LINBLS_Pos)
3039 #define US_CSR_LIN_LINBE_Pos        25           /**< \brief (US_CSR_LIN) LIN Bit Error */
3040 #define US_CSR_LIN_LINBE            (_U_(0x1) << US_CSR_LIN_LINBE_Pos)
3041 #define US_CSR_LIN_LINISFE_Pos      26           /**< \brief (US_CSR_LIN) LIN Inconsistent Synch Field Error */
3042 #define US_CSR_LIN_LINISFE          (_U_(0x1) << US_CSR_LIN_LINISFE_Pos)
3043 #define US_CSR_LIN_LINIPE_Pos       27           /**< \brief (US_CSR_LIN) LIN Identifier Parity Error */
3044 #define US_CSR_LIN_LINIPE           (_U_(0x1) << US_CSR_LIN_LINIPE_Pos)
3045 #define US_CSR_LIN_LINCE_Pos        28           /**< \brief (US_CSR_LIN) LIN Checksum Error */
3046 #define US_CSR_LIN_LINCE            (_U_(0x1) << US_CSR_LIN_LINCE_Pos)
3047 #define US_CSR_LIN_LINSNRE_Pos      29           /**< \brief (US_CSR_LIN) LIN Slave Not Responding Error */
3048 #define US_CSR_LIN_LINSNRE          (_U_(0x1) << US_CSR_LIN_LINSNRE_Pos)
3049 #define US_CSR_LIN_LINSTE_Pos       30           /**< \brief (US_CSR_LIN) LIN Synch Tolerance Error */
3050 #define US_CSR_LIN_LINSTE           (_U_(0x1) << US_CSR_LIN_LINSTE_Pos)
3051 #define   US_CSR_LIN_LINSTE_0_Val         _U_(0x0)   /**< \brief (US_CSR_LIN) COMM_TX is at 0 */
3052 #define   US_CSR_LIN_LINSTE_1_Val         _U_(0x1)   /**< \brief (US_CSR_LIN) COMM_TX is at 1 */
3053 #define US_CSR_LIN_LINSTE_0         (US_CSR_LIN_LINSTE_0_Val       << US_CSR_LIN_LINSTE_Pos)
3054 #define US_CSR_LIN_LINSTE_1         (US_CSR_LIN_LINSTE_1_Val       << US_CSR_LIN_LINSTE_Pos)
3055 #define US_CSR_LIN_LINHTE_Pos       31           /**< \brief (US_CSR_LIN) LIN Header Timeout Error */
3056 #define US_CSR_LIN_LINHTE           (_U_(0x1) << US_CSR_LIN_LINHTE_Pos)
3057 #define   US_CSR_LIN_LINHTE_0_Val         _U_(0x0)   /**< \brief (US_CSR_LIN) COMM_RX is at 0 */
3058 #define   US_CSR_LIN_LINHTE_1_Val         _U_(0x1)   /**< \brief (US_CSR_LIN) COMM_RX is at 1 */
3059 #define US_CSR_LIN_LINHTE_0         (US_CSR_LIN_LINHTE_0_Val       << US_CSR_LIN_LINHTE_Pos)
3060 #define US_CSR_LIN_LINHTE_1         (US_CSR_LIN_LINHTE_1_Val       << US_CSR_LIN_LINHTE_Pos)
3061 #define US_CSR_LIN_MASK             _U_(0xFEFFFFE7) /**< \brief (US_CSR_LIN) MASK Register */
3062 
3063 // SPI_SLAVE mode
3064 #define US_CSR_SPI_SLAVE_RXRDY_Pos  0            /**< \brief (US_CSR_SPI_SLAVE) Receiver Ready */
3065 #define US_CSR_SPI_SLAVE_RXRDY      (_U_(0x1) << US_CSR_SPI_SLAVE_RXRDY_Pos)
3066 #define   US_CSR_SPI_SLAVE_RXRDY_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */
3067 #define   US_CSR_SPI_SLAVE_RXRDY_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one complete character has been received and RHR has not yet been read */
3068 #define US_CSR_SPI_SLAVE_RXRDY_0    (US_CSR_SPI_SLAVE_RXRDY_0_Val  << US_CSR_SPI_SLAVE_RXRDY_Pos)
3069 #define US_CSR_SPI_SLAVE_RXRDY_1    (US_CSR_SPI_SLAVE_RXRDY_1_Val  << US_CSR_SPI_SLAVE_RXRDY_Pos)
3070 #define US_CSR_SPI_SLAVE_TXRDY_Pos  1            /**< \brief (US_CSR_SPI_SLAVE) Transmitter Ready */
3071 #define US_CSR_SPI_SLAVE_TXRDY      (_U_(0x1) << US_CSR_SPI_SLAVE_TXRDY_Pos)
3072 #define   US_CSR_SPI_SLAVE_TXRDY_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */
3073 #define   US_CSR_SPI_SLAVE_TXRDY_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) There is no character in the THR */
3074 #define US_CSR_SPI_SLAVE_TXRDY_0    (US_CSR_SPI_SLAVE_TXRDY_0_Val  << US_CSR_SPI_SLAVE_TXRDY_Pos)
3075 #define US_CSR_SPI_SLAVE_TXRDY_1    (US_CSR_SPI_SLAVE_TXRDY_1_Val  << US_CSR_SPI_SLAVE_TXRDY_Pos)
3076 #define US_CSR_SPI_SLAVE_RXBRK_Pos  2            /**< \brief (US_CSR_SPI_SLAVE) Break Received/End of Break */
3077 #define US_CSR_SPI_SLAVE_RXBRK      (_U_(0x1) << US_CSR_SPI_SLAVE_RXBRK_Pos)
3078 #define   US_CSR_SPI_SLAVE_RXBRK_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No Break received or End of Break detected since the last RSTSTA */
3079 #define   US_CSR_SPI_SLAVE_RXBRK_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) Break Received or End of Break detected since the last RSTSTA */
3080 #define US_CSR_SPI_SLAVE_RXBRK_0    (US_CSR_SPI_SLAVE_RXBRK_0_Val  << US_CSR_SPI_SLAVE_RXBRK_Pos)
3081 #define US_CSR_SPI_SLAVE_RXBRK_1    (US_CSR_SPI_SLAVE_RXBRK_1_Val  << US_CSR_SPI_SLAVE_RXBRK_Pos)
3082 #define US_CSR_SPI_SLAVE_OVRE_Pos   5            /**< \brief (US_CSR_SPI_SLAVE) Overrun Error */
3083 #define US_CSR_SPI_SLAVE_OVRE       (_U_(0x1) << US_CSR_SPI_SLAVE_OVRE_Pos)
3084 #define   US_CSR_SPI_SLAVE_OVRE_0_Val     _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No overrun error has occurred since since the last RSTSTA */
3085 #define   US_CSR_SPI_SLAVE_OVRE_1_Val     _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one overrun error has occurred since the last RSTSTA */
3086 #define US_CSR_SPI_SLAVE_OVRE_0     (US_CSR_SPI_SLAVE_OVRE_0_Val   << US_CSR_SPI_SLAVE_OVRE_Pos)
3087 #define US_CSR_SPI_SLAVE_OVRE_1     (US_CSR_SPI_SLAVE_OVRE_1_Val   << US_CSR_SPI_SLAVE_OVRE_Pos)
3088 #define US_CSR_SPI_SLAVE_FRAME_Pos  6            /**< \brief (US_CSR_SPI_SLAVE) Framing Error */
3089 #define US_CSR_SPI_SLAVE_FRAME      (_U_(0x1) << US_CSR_SPI_SLAVE_FRAME_Pos)
3090 #define   US_CSR_SPI_SLAVE_FRAME_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No stop bit has been detected low since the last RSTSTA */
3091 #define   US_CSR_SPI_SLAVE_FRAME_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one stop bit has been detected low since the last RSTSTA */
3092 #define US_CSR_SPI_SLAVE_FRAME_0    (US_CSR_SPI_SLAVE_FRAME_0_Val  << US_CSR_SPI_SLAVE_FRAME_Pos)
3093 #define US_CSR_SPI_SLAVE_FRAME_1    (US_CSR_SPI_SLAVE_FRAME_1_Val  << US_CSR_SPI_SLAVE_FRAME_Pos)
3094 #define US_CSR_SPI_SLAVE_PARE_Pos   7            /**< \brief (US_CSR_SPI_SLAVE) Parity Error */
3095 #define US_CSR_SPI_SLAVE_PARE       (_U_(0x1) << US_CSR_SPI_SLAVE_PARE_Pos)
3096 #define   US_CSR_SPI_SLAVE_PARE_0_Val     _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No parity error has been detected since the last RSTSTA */
3097 #define   US_CSR_SPI_SLAVE_PARE_1_Val     _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one parity error has been detected since the last RSTSTA */
3098 #define US_CSR_SPI_SLAVE_PARE_0     (US_CSR_SPI_SLAVE_PARE_0_Val   << US_CSR_SPI_SLAVE_PARE_Pos)
3099 #define US_CSR_SPI_SLAVE_PARE_1     (US_CSR_SPI_SLAVE_PARE_1_Val   << US_CSR_SPI_SLAVE_PARE_Pos)
3100 #define US_CSR_SPI_SLAVE_TIMEOUT_Pos 8            /**< \brief (US_CSR_SPI_SLAVE) Receiver Time-out */
3101 #define US_CSR_SPI_SLAVE_TIMEOUT    (_U_(0x1) << US_CSR_SPI_SLAVE_TIMEOUT_Pos)
3102 #define   US_CSR_SPI_SLAVE_TIMEOUT_0_Val  _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */
3103 #define   US_CSR_SPI_SLAVE_TIMEOUT_1_Val  _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) There has been a time-out since the last Start Time-out command */
3104 #define US_CSR_SPI_SLAVE_TIMEOUT_0  (US_CSR_SPI_SLAVE_TIMEOUT_0_Val << US_CSR_SPI_SLAVE_TIMEOUT_Pos)
3105 #define US_CSR_SPI_SLAVE_TIMEOUT_1  (US_CSR_SPI_SLAVE_TIMEOUT_1_Val << US_CSR_SPI_SLAVE_TIMEOUT_Pos)
3106 #define US_CSR_SPI_SLAVE_TXEMPTY_Pos 9            /**< \brief (US_CSR_SPI_SLAVE) Transmitter Empty */
3107 #define US_CSR_SPI_SLAVE_TXEMPTY    (_U_(0x1) << US_CSR_SPI_SLAVE_TXEMPTY_Pos)
3108 #define   US_CSR_SPI_SLAVE_TXEMPTY_0_Val  _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */
3109 #define   US_CSR_SPI_SLAVE_TXEMPTY_1_Val  _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) There is at least one character in either THR or the Transmit Shift Register */
3110 #define US_CSR_SPI_SLAVE_TXEMPTY_0  (US_CSR_SPI_SLAVE_TXEMPTY_0_Val << US_CSR_SPI_SLAVE_TXEMPTY_Pos)
3111 #define US_CSR_SPI_SLAVE_TXEMPTY_1  (US_CSR_SPI_SLAVE_TXEMPTY_1_Val << US_CSR_SPI_SLAVE_TXEMPTY_Pos)
3112 #define US_CSR_SPI_SLAVE_UNRE_Pos   10           /**< \brief (US_CSR_SPI_SLAVE) SPI Underrun Error */
3113 #define US_CSR_SPI_SLAVE_UNRE       (_U_(0x1) << US_CSR_SPI_SLAVE_UNRE_Pos)
3114 #define   US_CSR_SPI_SLAVE_UNRE_0_Val     _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No SPI underrun error has occurred since the last RSTSTA */
3115 #define   US_CSR_SPI_SLAVE_UNRE_1_Val     _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one SPI underrun error has occurred since the last RSTSTA */
3116 #define US_CSR_SPI_SLAVE_UNRE_0     (US_CSR_SPI_SLAVE_UNRE_0_Val   << US_CSR_SPI_SLAVE_UNRE_Pos)
3117 #define US_CSR_SPI_SLAVE_UNRE_1     (US_CSR_SPI_SLAVE_UNRE_1_Val   << US_CSR_SPI_SLAVE_UNRE_Pos)
3118 #define US_CSR_SPI_SLAVE_TXBUFE_Pos 11           /**< \brief (US_CSR_SPI_SLAVE) Transmission Buffer Empty */
3119 #define US_CSR_SPI_SLAVE_TXBUFE     (_U_(0x1) << US_CSR_SPI_SLAVE_TXBUFE_Pos)
3120 #define   US_CSR_SPI_SLAVE_TXBUFE_0_Val   _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) The signal Buffer Empty from the Transmit PDC channel is inactive */
3121 #define   US_CSR_SPI_SLAVE_TXBUFE_1_Val   _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) The signal Buffer Empty from the Transmit PDC channel is active */
3122 #define US_CSR_SPI_SLAVE_TXBUFE_0   (US_CSR_SPI_SLAVE_TXBUFE_0_Val << US_CSR_SPI_SLAVE_TXBUFE_Pos)
3123 #define US_CSR_SPI_SLAVE_TXBUFE_1   (US_CSR_SPI_SLAVE_TXBUFE_1_Val << US_CSR_SPI_SLAVE_TXBUFE_Pos)
3124 #define US_CSR_SPI_SLAVE_RXBUFF_Pos 12           /**< \brief (US_CSR_SPI_SLAVE) Reception Buffer Full */
3125 #define US_CSR_SPI_SLAVE_RXBUFF     (_U_(0x1) << US_CSR_SPI_SLAVE_RXBUFF_Pos)
3126 #define   US_CSR_SPI_SLAVE_RXBUFF_0_Val   _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) The signal Buffer Full from the Receive PDC channel is inactive */
3127 #define   US_CSR_SPI_SLAVE_RXBUFF_1_Val   _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) The signal Buffer Full from the Receive PDC channel is active */
3128 #define US_CSR_SPI_SLAVE_RXBUFF_0   (US_CSR_SPI_SLAVE_RXBUFF_0_Val << US_CSR_SPI_SLAVE_RXBUFF_Pos)
3129 #define US_CSR_SPI_SLAVE_RXBUFF_1   (US_CSR_SPI_SLAVE_RXBUFF_1_Val << US_CSR_SPI_SLAVE_RXBUFF_Pos)
3130 #define US_CSR_SPI_SLAVE_NACK_Pos   13           /**< \brief (US_CSR_SPI_SLAVE) Non Acknowledge */
3131 #define US_CSR_SPI_SLAVE_NACK       (_U_(0x1) << US_CSR_SPI_SLAVE_NACK_Pos)
3132 #define   US_CSR_SPI_SLAVE_NACK_0_Val     _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No Non Acknowledge has not been detected since the last RSTNACK */
3133 #define   US_CSR_SPI_SLAVE_NACK_1_Val     _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one Non Acknowledge has been detected since the last RSTNACK */
3134 #define US_CSR_SPI_SLAVE_NACK_0     (US_CSR_SPI_SLAVE_NACK_0_Val   << US_CSR_SPI_SLAVE_NACK_Pos)
3135 #define US_CSR_SPI_SLAVE_NACK_1     (US_CSR_SPI_SLAVE_NACK_1_Val   << US_CSR_SPI_SLAVE_NACK_Pos)
3136 #define US_CSR_SPI_SLAVE_RIIC_Pos   16           /**< \brief (US_CSR_SPI_SLAVE) Ring Indicator Input Change Flag */
3137 #define US_CSR_SPI_SLAVE_RIIC       (_U_(0x1) << US_CSR_SPI_SLAVE_RIIC_Pos)
3138 #define   US_CSR_SPI_SLAVE_RIIC_0_Val     _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No input change has been detected on the RI pin since the last read of CSR */
3139 #define   US_CSR_SPI_SLAVE_RIIC_1_Val     _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one input change has been detected on the RI pin since the last read of CSR */
3140 #define US_CSR_SPI_SLAVE_RIIC_0     (US_CSR_SPI_SLAVE_RIIC_0_Val   << US_CSR_SPI_SLAVE_RIIC_Pos)
3141 #define US_CSR_SPI_SLAVE_RIIC_1     (US_CSR_SPI_SLAVE_RIIC_1_Val   << US_CSR_SPI_SLAVE_RIIC_Pos)
3142 #define US_CSR_SPI_SLAVE_DSRIC_Pos  17           /**< \brief (US_CSR_SPI_SLAVE) Data Set Ready Input Change Flag */
3143 #define US_CSR_SPI_SLAVE_DSRIC      (_U_(0x1) << US_CSR_SPI_SLAVE_DSRIC_Pos)
3144 #define   US_CSR_SPI_SLAVE_DSRIC_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No input change has been detected on the DSR pin since the last read of CSR */
3145 #define   US_CSR_SPI_SLAVE_DSRIC_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one input change has been detected on the DSR pin since the last read of CSR */
3146 #define US_CSR_SPI_SLAVE_DSRIC_0    (US_CSR_SPI_SLAVE_DSRIC_0_Val  << US_CSR_SPI_SLAVE_DSRIC_Pos)
3147 #define US_CSR_SPI_SLAVE_DSRIC_1    (US_CSR_SPI_SLAVE_DSRIC_1_Val  << US_CSR_SPI_SLAVE_DSRIC_Pos)
3148 #define US_CSR_SPI_SLAVE_DCDIC_Pos  18           /**< \brief (US_CSR_SPI_SLAVE) Data Carrier Detect Input Change Flag */
3149 #define US_CSR_SPI_SLAVE_DCDIC      (_U_(0x1) << US_CSR_SPI_SLAVE_DCDIC_Pos)
3150 #define   US_CSR_SPI_SLAVE_DCDIC_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No input change has been detected on the DCD pin since the last read of CSR */
3151 #define   US_CSR_SPI_SLAVE_DCDIC_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one input change has been detected on the DCD pin since the last read of CSR */
3152 #define US_CSR_SPI_SLAVE_DCDIC_0    (US_CSR_SPI_SLAVE_DCDIC_0_Val  << US_CSR_SPI_SLAVE_DCDIC_Pos)
3153 #define US_CSR_SPI_SLAVE_DCDIC_1    (US_CSR_SPI_SLAVE_DCDIC_1_Val  << US_CSR_SPI_SLAVE_DCDIC_Pos)
3154 #define US_CSR_SPI_SLAVE_CTSIC_Pos  19           /**< \brief (US_CSR_SPI_SLAVE) Clear to Send Input Change Flag */
3155 #define US_CSR_SPI_SLAVE_CTSIC      (_U_(0x1) << US_CSR_SPI_SLAVE_CTSIC_Pos)
3156 #define   US_CSR_SPI_SLAVE_CTSIC_0_Val    _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) No input change has been detected on the CTS pin since the last read of CSR */
3157 #define   US_CSR_SPI_SLAVE_CTSIC_1_Val    _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) At least one input change has been detected on the CTS pin since the last read of CSR */
3158 #define US_CSR_SPI_SLAVE_CTSIC_0    (US_CSR_SPI_SLAVE_CTSIC_0_Val  << US_CSR_SPI_SLAVE_CTSIC_Pos)
3159 #define US_CSR_SPI_SLAVE_CTSIC_1    (US_CSR_SPI_SLAVE_CTSIC_1_Val  << US_CSR_SPI_SLAVE_CTSIC_Pos)
3160 #define US_CSR_SPI_SLAVE_RI_Pos     20           /**< \brief (US_CSR_SPI_SLAVE) Image of RI Input */
3161 #define US_CSR_SPI_SLAVE_RI         (_U_(0x1) << US_CSR_SPI_SLAVE_RI_Pos)
3162 #define   US_CSR_SPI_SLAVE_RI_0_Val       _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) RI is at 0 */
3163 #define   US_CSR_SPI_SLAVE_RI_1_Val       _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) RI is at 1 */
3164 #define US_CSR_SPI_SLAVE_RI_0       (US_CSR_SPI_SLAVE_RI_0_Val     << US_CSR_SPI_SLAVE_RI_Pos)
3165 #define US_CSR_SPI_SLAVE_RI_1       (US_CSR_SPI_SLAVE_RI_1_Val     << US_CSR_SPI_SLAVE_RI_Pos)
3166 #define US_CSR_SPI_SLAVE_DSR_Pos    21           /**< \brief (US_CSR_SPI_SLAVE) Image of DSR Input */
3167 #define US_CSR_SPI_SLAVE_DSR        (_U_(0x1) << US_CSR_SPI_SLAVE_DSR_Pos)
3168 #define   US_CSR_SPI_SLAVE_DSR_0_Val      _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) DSR is at 0 */
3169 #define   US_CSR_SPI_SLAVE_DSR_1_Val      _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) DSR is at 1 */
3170 #define US_CSR_SPI_SLAVE_DSR_0      (US_CSR_SPI_SLAVE_DSR_0_Val    << US_CSR_SPI_SLAVE_DSR_Pos)
3171 #define US_CSR_SPI_SLAVE_DSR_1      (US_CSR_SPI_SLAVE_DSR_1_Val    << US_CSR_SPI_SLAVE_DSR_Pos)
3172 #define US_CSR_SPI_SLAVE_DCD_Pos    22           /**< \brief (US_CSR_SPI_SLAVE) Image of DCD Input */
3173 #define US_CSR_SPI_SLAVE_DCD        (_U_(0x1) << US_CSR_SPI_SLAVE_DCD_Pos)
3174 #define   US_CSR_SPI_SLAVE_DCD_0_Val      _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) DCD is at 0 */
3175 #define   US_CSR_SPI_SLAVE_DCD_1_Val      _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) DCD is at 1 */
3176 #define US_CSR_SPI_SLAVE_DCD_0      (US_CSR_SPI_SLAVE_DCD_0_Val    << US_CSR_SPI_SLAVE_DCD_Pos)
3177 #define US_CSR_SPI_SLAVE_DCD_1      (US_CSR_SPI_SLAVE_DCD_1_Val    << US_CSR_SPI_SLAVE_DCD_Pos)
3178 #define US_CSR_SPI_SLAVE_CTS_Pos    23           /**< \brief (US_CSR_SPI_SLAVE) Image of CTS Input */
3179 #define US_CSR_SPI_SLAVE_CTS        (_U_(0x1) << US_CSR_SPI_SLAVE_CTS_Pos)
3180 #define   US_CSR_SPI_SLAVE_CTS_0_Val      _U_(0x0)   /**< \brief (US_CSR_SPI_SLAVE) CTS is at 0 */
3181 #define   US_CSR_SPI_SLAVE_CTS_1_Val      _U_(0x1)   /**< \brief (US_CSR_SPI_SLAVE) CTS is at 1 */
3182 #define US_CSR_SPI_SLAVE_CTS_0      (US_CSR_SPI_SLAVE_CTS_0_Val    << US_CSR_SPI_SLAVE_CTS_Pos)
3183 #define US_CSR_SPI_SLAVE_CTS_1      (US_CSR_SPI_SLAVE_CTS_1_Val    << US_CSR_SPI_SLAVE_CTS_Pos)
3184 #define US_CSR_SPI_SLAVE_MASK       _U_(0x00FF3FE7) /**< \brief (US_CSR_SPI_SLAVE) MASK Register */
3185 
3186 // USART mode
3187 #define US_CSR_USART_RXRDY_Pos      0            /**< \brief (US_CSR_USART) Receiver Ready */
3188 #define US_CSR_USART_RXRDY          (_U_(0x1) << US_CSR_USART_RXRDY_Pos)
3189 #define   US_CSR_USART_RXRDY_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */
3190 #define   US_CSR_USART_RXRDY_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) At least one complete character has been received and RHR has not yet been read */
3191 #define US_CSR_USART_RXRDY_0        (US_CSR_USART_RXRDY_0_Val      << US_CSR_USART_RXRDY_Pos)
3192 #define US_CSR_USART_RXRDY_1        (US_CSR_USART_RXRDY_1_Val      << US_CSR_USART_RXRDY_Pos)
3193 #define US_CSR_USART_TXRDY_Pos      1            /**< \brief (US_CSR_USART) Transmitter Ready */
3194 #define US_CSR_USART_TXRDY          (_U_(0x1) << US_CSR_USART_TXRDY_Pos)
3195 #define   US_CSR_USART_TXRDY_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */
3196 #define   US_CSR_USART_TXRDY_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) There is no character in the THR */
3197 #define US_CSR_USART_TXRDY_0        (US_CSR_USART_TXRDY_0_Val      << US_CSR_USART_TXRDY_Pos)
3198 #define US_CSR_USART_TXRDY_1        (US_CSR_USART_TXRDY_1_Val      << US_CSR_USART_TXRDY_Pos)
3199 #define US_CSR_USART_RXBRK_Pos      2            /**< \brief (US_CSR_USART) Break Received/End of Break */
3200 #define US_CSR_USART_RXBRK          (_U_(0x1) << US_CSR_USART_RXBRK_Pos)
3201 #define   US_CSR_USART_RXBRK_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) No Break received or End of Break detected since the last RSTSTA */
3202 #define   US_CSR_USART_RXBRK_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) Break Received or End of Break detected since the last RSTSTA */
3203 #define US_CSR_USART_RXBRK_0        (US_CSR_USART_RXBRK_0_Val      << US_CSR_USART_RXBRK_Pos)
3204 #define US_CSR_USART_RXBRK_1        (US_CSR_USART_RXBRK_1_Val      << US_CSR_USART_RXBRK_Pos)
3205 #define US_CSR_USART_OVRE_Pos       5            /**< \brief (US_CSR_USART) Overrun Error */
3206 #define US_CSR_USART_OVRE           (_U_(0x1) << US_CSR_USART_OVRE_Pos)
3207 #define   US_CSR_USART_OVRE_0_Val         _U_(0x0)   /**< \brief (US_CSR_USART) No overrun error has occurred since since the last RSTSTA */
3208 #define   US_CSR_USART_OVRE_1_Val         _U_(0x1)   /**< \brief (US_CSR_USART) At least one overrun error has occurred since the last RSTSTA */
3209 #define US_CSR_USART_OVRE_0         (US_CSR_USART_OVRE_0_Val       << US_CSR_USART_OVRE_Pos)
3210 #define US_CSR_USART_OVRE_1         (US_CSR_USART_OVRE_1_Val       << US_CSR_USART_OVRE_Pos)
3211 #define US_CSR_USART_FRAME_Pos      6            /**< \brief (US_CSR_USART) Framing Error */
3212 #define US_CSR_USART_FRAME          (_U_(0x1) << US_CSR_USART_FRAME_Pos)
3213 #define   US_CSR_USART_FRAME_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) No stop bit has been detected low since the last RSTSTA */
3214 #define   US_CSR_USART_FRAME_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) At least one stop bit has been detected low since the last RSTSTA */
3215 #define US_CSR_USART_FRAME_0        (US_CSR_USART_FRAME_0_Val      << US_CSR_USART_FRAME_Pos)
3216 #define US_CSR_USART_FRAME_1        (US_CSR_USART_FRAME_1_Val      << US_CSR_USART_FRAME_Pos)
3217 #define US_CSR_USART_PARE_Pos       7            /**< \brief (US_CSR_USART) Parity Error */
3218 #define US_CSR_USART_PARE           (_U_(0x1) << US_CSR_USART_PARE_Pos)
3219 #define   US_CSR_USART_PARE_0_Val         _U_(0x0)   /**< \brief (US_CSR_USART) No parity error has been detected since the last RSTSTA */
3220 #define   US_CSR_USART_PARE_1_Val         _U_(0x1)   /**< \brief (US_CSR_USART) At least one parity error has been detected since the last RSTSTA */
3221 #define US_CSR_USART_PARE_0         (US_CSR_USART_PARE_0_Val       << US_CSR_USART_PARE_Pos)
3222 #define US_CSR_USART_PARE_1         (US_CSR_USART_PARE_1_Val       << US_CSR_USART_PARE_Pos)
3223 #define US_CSR_USART_TIMEOUT_Pos    8            /**< \brief (US_CSR_USART) Receiver Time-out */
3224 #define US_CSR_USART_TIMEOUT        (_U_(0x1) << US_CSR_USART_TIMEOUT_Pos)
3225 #define   US_CSR_USART_TIMEOUT_0_Val      _U_(0x0)   /**< \brief (US_CSR_USART) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */
3226 #define   US_CSR_USART_TIMEOUT_1_Val      _U_(0x1)   /**< \brief (US_CSR_USART) There has been a time-out since the last Start Time-out command */
3227 #define US_CSR_USART_TIMEOUT_0      (US_CSR_USART_TIMEOUT_0_Val    << US_CSR_USART_TIMEOUT_Pos)
3228 #define US_CSR_USART_TIMEOUT_1      (US_CSR_USART_TIMEOUT_1_Val    << US_CSR_USART_TIMEOUT_Pos)
3229 #define US_CSR_USART_TXEMPTY_Pos    9            /**< \brief (US_CSR_USART) Transmitter Empty */
3230 #define US_CSR_USART_TXEMPTY        (_U_(0x1) << US_CSR_USART_TXEMPTY_Pos)
3231 #define   US_CSR_USART_TXEMPTY_0_Val      _U_(0x0)   /**< \brief (US_CSR_USART) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */
3232 #define   US_CSR_USART_TXEMPTY_1_Val      _U_(0x1)   /**< \brief (US_CSR_USART) There is at least one character in either THR or the Transmit Shift Register */
3233 #define US_CSR_USART_TXEMPTY_0      (US_CSR_USART_TXEMPTY_0_Val    << US_CSR_USART_TXEMPTY_Pos)
3234 #define US_CSR_USART_TXEMPTY_1      (US_CSR_USART_TXEMPTY_1_Val    << US_CSR_USART_TXEMPTY_Pos)
3235 #define US_CSR_USART_ITER_Pos       10           /**< \brief (US_CSR_USART) Max number of Repetitions Reached */
3236 #define US_CSR_USART_ITER           (_U_(0x1) << US_CSR_USART_ITER_Pos)
3237 #define   US_CSR_USART_ITER_0_Val         _U_(0x0)   /**< \brief (US_CSR_USART) Maximum number of repetitions has not been reached since the last RSIT */
3238 #define   US_CSR_USART_ITER_1_Val         _U_(0x1)   /**< \brief (US_CSR_USART) Maximum number of repetitions has been reached since the last RSIT */
3239 #define US_CSR_USART_ITER_0         (US_CSR_USART_ITER_0_Val       << US_CSR_USART_ITER_Pos)
3240 #define US_CSR_USART_ITER_1         (US_CSR_USART_ITER_1_Val       << US_CSR_USART_ITER_Pos)
3241 #define US_CSR_USART_TXBUFE_Pos     11           /**< \brief (US_CSR_USART) Transmission Buffer Empty */
3242 #define US_CSR_USART_TXBUFE         (_U_(0x1) << US_CSR_USART_TXBUFE_Pos)
3243 #define   US_CSR_USART_TXBUFE_0_Val       _U_(0x0)   /**< \brief (US_CSR_USART) The signal Buffer Empty from the Transmit PDC channel is inactive */
3244 #define   US_CSR_USART_TXBUFE_1_Val       _U_(0x1)   /**< \brief (US_CSR_USART) The signal Buffer Empty from the Transmit PDC channel is active */
3245 #define US_CSR_USART_TXBUFE_0       (US_CSR_USART_TXBUFE_0_Val     << US_CSR_USART_TXBUFE_Pos)
3246 #define US_CSR_USART_TXBUFE_1       (US_CSR_USART_TXBUFE_1_Val     << US_CSR_USART_TXBUFE_Pos)
3247 #define US_CSR_USART_RXBUFF_Pos     12           /**< \brief (US_CSR_USART) Reception Buffer Full */
3248 #define US_CSR_USART_RXBUFF         (_U_(0x1) << US_CSR_USART_RXBUFF_Pos)
3249 #define   US_CSR_USART_RXBUFF_0_Val       _U_(0x0)   /**< \brief (US_CSR_USART) The signal Buffer Full from the Receive PDC channel is inactive */
3250 #define   US_CSR_USART_RXBUFF_1_Val       _U_(0x1)   /**< \brief (US_CSR_USART) The signal Buffer Full from the Receive PDC channel is active */
3251 #define US_CSR_USART_RXBUFF_0       (US_CSR_USART_RXBUFF_0_Val     << US_CSR_USART_RXBUFF_Pos)
3252 #define US_CSR_USART_RXBUFF_1       (US_CSR_USART_RXBUFF_1_Val     << US_CSR_USART_RXBUFF_Pos)
3253 #define US_CSR_USART_NACK_Pos       13           /**< \brief (US_CSR_USART) Non Acknowledge */
3254 #define US_CSR_USART_NACK           (_U_(0x1) << US_CSR_USART_NACK_Pos)
3255 #define   US_CSR_USART_NACK_0_Val         _U_(0x0)   /**< \brief (US_CSR_USART) No Non Acknowledge has not been detected since the last RSTNACK */
3256 #define   US_CSR_USART_NACK_1_Val         _U_(0x1)   /**< \brief (US_CSR_USART) At least one Non Acknowledge has been detected since the last RSTNACK */
3257 #define US_CSR_USART_NACK_0         (US_CSR_USART_NACK_0_Val       << US_CSR_USART_NACK_Pos)
3258 #define US_CSR_USART_NACK_1         (US_CSR_USART_NACK_1_Val       << US_CSR_USART_NACK_Pos)
3259 #define US_CSR_USART_RIIC_Pos       16           /**< \brief (US_CSR_USART) Ring Indicator Input Change Flag */
3260 #define US_CSR_USART_RIIC           (_U_(0x1) << US_CSR_USART_RIIC_Pos)
3261 #define   US_CSR_USART_RIIC_0_Val         _U_(0x0)   /**< \brief (US_CSR_USART) No input change has been detected on the RI pin since the last read of CSR */
3262 #define   US_CSR_USART_RIIC_1_Val         _U_(0x1)   /**< \brief (US_CSR_USART) At least one input change has been detected on the RI pin since the last read of CSR */
3263 #define US_CSR_USART_RIIC_0         (US_CSR_USART_RIIC_0_Val       << US_CSR_USART_RIIC_Pos)
3264 #define US_CSR_USART_RIIC_1         (US_CSR_USART_RIIC_1_Val       << US_CSR_USART_RIIC_Pos)
3265 #define US_CSR_USART_DSRIC_Pos      17           /**< \brief (US_CSR_USART) Data Set Ready Input Change Flag */
3266 #define US_CSR_USART_DSRIC          (_U_(0x1) << US_CSR_USART_DSRIC_Pos)
3267 #define   US_CSR_USART_DSRIC_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) No input change has been detected on the DSR pin since the last read of CSR */
3268 #define   US_CSR_USART_DSRIC_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) At least one input change has been detected on the DSR pin since the last read of CSR */
3269 #define US_CSR_USART_DSRIC_0        (US_CSR_USART_DSRIC_0_Val      << US_CSR_USART_DSRIC_Pos)
3270 #define US_CSR_USART_DSRIC_1        (US_CSR_USART_DSRIC_1_Val      << US_CSR_USART_DSRIC_Pos)
3271 #define US_CSR_USART_DCDIC_Pos      18           /**< \brief (US_CSR_USART) Data Carrier Detect Input Change Flag */
3272 #define US_CSR_USART_DCDIC          (_U_(0x1) << US_CSR_USART_DCDIC_Pos)
3273 #define   US_CSR_USART_DCDIC_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) No input change has been detected on the DCD pin since the last read of CSR */
3274 #define   US_CSR_USART_DCDIC_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) At least one input change has been detected on the DCD pin since the last read of CSR */
3275 #define US_CSR_USART_DCDIC_0        (US_CSR_USART_DCDIC_0_Val      << US_CSR_USART_DCDIC_Pos)
3276 #define US_CSR_USART_DCDIC_1        (US_CSR_USART_DCDIC_1_Val      << US_CSR_USART_DCDIC_Pos)
3277 #define US_CSR_USART_CTSIC_Pos      19           /**< \brief (US_CSR_USART) Clear to Send Input Change Flag */
3278 #define US_CSR_USART_CTSIC          (_U_(0x1) << US_CSR_USART_CTSIC_Pos)
3279 #define   US_CSR_USART_CTSIC_0_Val        _U_(0x0)   /**< \brief (US_CSR_USART) No input change has been detected on the CTS pin since the last read of CSR */
3280 #define   US_CSR_USART_CTSIC_1_Val        _U_(0x1)   /**< \brief (US_CSR_USART) At least one input change has been detected on the CTS pin since the last read of CSR */
3281 #define US_CSR_USART_CTSIC_0        (US_CSR_USART_CTSIC_0_Val      << US_CSR_USART_CTSIC_Pos)
3282 #define US_CSR_USART_CTSIC_1        (US_CSR_USART_CTSIC_1_Val      << US_CSR_USART_CTSIC_Pos)
3283 #define US_CSR_USART_RI_Pos         20           /**< \brief (US_CSR_USART) Image of RI Input */
3284 #define US_CSR_USART_RI             (_U_(0x1) << US_CSR_USART_RI_Pos)
3285 #define   US_CSR_USART_RI_0_Val           _U_(0x0)   /**< \brief (US_CSR_USART) RI is at 0 */
3286 #define   US_CSR_USART_RI_1_Val           _U_(0x1)   /**< \brief (US_CSR_USART) RI is at 1 */
3287 #define US_CSR_USART_RI_0           (US_CSR_USART_RI_0_Val         << US_CSR_USART_RI_Pos)
3288 #define US_CSR_USART_RI_1           (US_CSR_USART_RI_1_Val         << US_CSR_USART_RI_Pos)
3289 #define US_CSR_USART_DSR_Pos        21           /**< \brief (US_CSR_USART) Image of DSR Input */
3290 #define US_CSR_USART_DSR            (_U_(0x1) << US_CSR_USART_DSR_Pos)
3291 #define   US_CSR_USART_DSR_0_Val          _U_(0x0)   /**< \brief (US_CSR_USART) DSR is at 0 */
3292 #define   US_CSR_USART_DSR_1_Val          _U_(0x1)   /**< \brief (US_CSR_USART) DSR is at 1 */
3293 #define US_CSR_USART_DSR_0          (US_CSR_USART_DSR_0_Val        << US_CSR_USART_DSR_Pos)
3294 #define US_CSR_USART_DSR_1          (US_CSR_USART_DSR_1_Val        << US_CSR_USART_DSR_Pos)
3295 #define US_CSR_USART_DCD_Pos        22           /**< \brief (US_CSR_USART) Image of DCD Input */
3296 #define US_CSR_USART_DCD            (_U_(0x1) << US_CSR_USART_DCD_Pos)
3297 #define   US_CSR_USART_DCD_0_Val          _U_(0x0)   /**< \brief (US_CSR_USART) DCD is at 0 */
3298 #define   US_CSR_USART_DCD_1_Val          _U_(0x1)   /**< \brief (US_CSR_USART) DCD is at 1 */
3299 #define US_CSR_USART_DCD_0          (US_CSR_USART_DCD_0_Val        << US_CSR_USART_DCD_Pos)
3300 #define US_CSR_USART_DCD_1          (US_CSR_USART_DCD_1_Val        << US_CSR_USART_DCD_Pos)
3301 #define US_CSR_USART_CTS_Pos        23           /**< \brief (US_CSR_USART) Image of CTS Input */
3302 #define US_CSR_USART_CTS            (_U_(0x1) << US_CSR_USART_CTS_Pos)
3303 #define   US_CSR_USART_CTS_0_Val          _U_(0x0)   /**< \brief (US_CSR_USART) CTS is at 0 */
3304 #define   US_CSR_USART_CTS_1_Val          _U_(0x1)   /**< \brief (US_CSR_USART) CTS is at 1 */
3305 #define US_CSR_USART_CTS_0          (US_CSR_USART_CTS_0_Val        << US_CSR_USART_CTS_Pos)
3306 #define US_CSR_USART_CTS_1          (US_CSR_USART_CTS_1_Val        << US_CSR_USART_CTS_Pos)
3307 #define US_CSR_USART_MANERR_Pos     24           /**< \brief (US_CSR_USART) Manchester Error */
3308 #define US_CSR_USART_MANERR         (_U_(0x1) << US_CSR_USART_MANERR_Pos)
3309 #define   US_CSR_USART_MANERR_0_Val       _U_(0x0)   /**< \brief (US_CSR_USART) No Manchester error has been detected since the last RSTSTA */
3310 #define   US_CSR_USART_MANERR_1_Val       _U_(0x1)   /**< \brief (US_CSR_USART) At least one Manchester error has been detected since the last RSTSTA */
3311 #define US_CSR_USART_MANERR_0       (US_CSR_USART_MANERR_0_Val     << US_CSR_USART_MANERR_Pos)
3312 #define US_CSR_USART_MANERR_1       (US_CSR_USART_MANERR_1_Val     << US_CSR_USART_MANERR_Pos)
3313 #define US_CSR_USART_MASK           _U_(0x01FF3FE7) /**< \brief (US_CSR_USART) MASK Register */
3314 
3315 // Any mode
3316 #define US_CSR_RXRDY_Pos            0            /**< \brief (US_CSR) Receiver Ready */
3317 #define US_CSR_RXRDY                (_U_(0x1) << US_CSR_RXRDY_Pos)
3318 #define   US_CSR_RXRDY_0_Val              _U_(0x0)   /**< \brief (US_CSR) No complete character has been received since the last read of RHR or the receiver is disabled. If characters werebeing received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled */
3319 #define   US_CSR_RXRDY_1_Val              _U_(0x1)   /**< \brief (US_CSR) At least one complete character has been received and RHR has not yet been read */
3320 #define US_CSR_RXRDY_0              (US_CSR_RXRDY_0_Val            << US_CSR_RXRDY_Pos)
3321 #define US_CSR_RXRDY_1              (US_CSR_RXRDY_1_Val            << US_CSR_RXRDY_Pos)
3322 #define US_CSR_TXRDY_Pos            1            /**< \brief (US_CSR) Transmitter Ready */
3323 #define US_CSR_TXRDY                (_U_(0x1) << US_CSR_TXRDY_Pos)
3324 #define   US_CSR_TXRDY_0_Val              _U_(0x0)   /**< \brief (US_CSR) A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1 */
3325 #define   US_CSR_TXRDY_1_Val              _U_(0x1)   /**< \brief (US_CSR) There is no character in the THR */
3326 #define US_CSR_TXRDY_0              (US_CSR_TXRDY_0_Val            << US_CSR_TXRDY_Pos)
3327 #define US_CSR_TXRDY_1              (US_CSR_TXRDY_1_Val            << US_CSR_TXRDY_Pos)
3328 #define US_CSR_RXBRK_Pos            2            /**< \brief (US_CSR) Break Received/End of Break */
3329 #define US_CSR_RXBRK                (_U_(0x1) << US_CSR_RXBRK_Pos)
3330 #define   US_CSR_RXBRK_0_Val              _U_(0x0)   /**< \brief (US_CSR) No Break received or End of Break detected since the last RSTSTA */
3331 #define   US_CSR_RXBRK_1_Val              _U_(0x1)   /**< \brief (US_CSR) Break Received or End of Break detected since the last RSTSTA */
3332 #define US_CSR_RXBRK_0              (US_CSR_RXBRK_0_Val            << US_CSR_RXBRK_Pos)
3333 #define US_CSR_RXBRK_1              (US_CSR_RXBRK_1_Val            << US_CSR_RXBRK_Pos)
3334 #define US_CSR_OVRE_Pos             5            /**< \brief (US_CSR) Overrun Error */
3335 #define US_CSR_OVRE                 (_U_(0x1) << US_CSR_OVRE_Pos)
3336 #define   US_CSR_OVRE_0_Val               _U_(0x0)   /**< \brief (US_CSR) No overrun error has occurred since since the last RSTSTA */
3337 #define   US_CSR_OVRE_1_Val               _U_(0x1)   /**< \brief (US_CSR) At least one overrun error has occurred since the last RSTSTA */
3338 #define US_CSR_OVRE_0               (US_CSR_OVRE_0_Val             << US_CSR_OVRE_Pos)
3339 #define US_CSR_OVRE_1               (US_CSR_OVRE_1_Val             << US_CSR_OVRE_Pos)
3340 #define US_CSR_FRAME_Pos            6            /**< \brief (US_CSR) Framing Error */
3341 #define US_CSR_FRAME                (_U_(0x1) << US_CSR_FRAME_Pos)
3342 #define   US_CSR_FRAME_0_Val              _U_(0x0)   /**< \brief (US_CSR) No stop bit has been detected low since the last RSTSTA */
3343 #define   US_CSR_FRAME_1_Val              _U_(0x1)   /**< \brief (US_CSR) At least one stop bit has been detected low since the last RSTSTA */
3344 #define US_CSR_FRAME_0              (US_CSR_FRAME_0_Val            << US_CSR_FRAME_Pos)
3345 #define US_CSR_FRAME_1              (US_CSR_FRAME_1_Val            << US_CSR_FRAME_Pos)
3346 #define US_CSR_PARE_Pos             7            /**< \brief (US_CSR) Parity Error */
3347 #define US_CSR_PARE                 (_U_(0x1) << US_CSR_PARE_Pos)
3348 #define   US_CSR_PARE_0_Val               _U_(0x0)   /**< \brief (US_CSR) No parity error has been detected since the last RSTSTA */
3349 #define   US_CSR_PARE_1_Val               _U_(0x1)   /**< \brief (US_CSR) At least one parity error has been detected since the last RSTSTA */
3350 #define US_CSR_PARE_0               (US_CSR_PARE_0_Val             << US_CSR_PARE_Pos)
3351 #define US_CSR_PARE_1               (US_CSR_PARE_1_Val             << US_CSR_PARE_Pos)
3352 #define US_CSR_TIMEOUT_Pos          8            /**< \brief (US_CSR) Receiver Time-out */
3353 #define US_CSR_TIMEOUT              (_U_(0x1) << US_CSR_TIMEOUT_Pos)
3354 #define   US_CSR_TIMEOUT_0_Val            _U_(0x0)   /**< \brief (US_CSR) There has not been a time-out since the last Start Time-out command or the Time-out Register is 0 */
3355 #define   US_CSR_TIMEOUT_1_Val            _U_(0x1)   /**< \brief (US_CSR) There has been a time-out since the last Start Time-out command */
3356 #define US_CSR_TIMEOUT_0            (US_CSR_TIMEOUT_0_Val          << US_CSR_TIMEOUT_Pos)
3357 #define US_CSR_TIMEOUT_1            (US_CSR_TIMEOUT_1_Val          << US_CSR_TIMEOUT_Pos)
3358 #define US_CSR_TXEMPTY_Pos          9            /**< \brief (US_CSR) Transmitter Empty */
3359 #define US_CSR_TXEMPTY              (_U_(0x1) << US_CSR_TXEMPTY_Pos)
3360 #define   US_CSR_TXEMPTY_0_Val            _U_(0x0)   /**< \brief (US_CSR) There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled */
3361 #define   US_CSR_TXEMPTY_1_Val            _U_(0x1)   /**< \brief (US_CSR) There is at least one character in either THR or the Transmit Shift Register */
3362 #define US_CSR_TXEMPTY_0            (US_CSR_TXEMPTY_0_Val          << US_CSR_TXEMPTY_Pos)
3363 #define US_CSR_TXEMPTY_1            (US_CSR_TXEMPTY_1_Val          << US_CSR_TXEMPTY_Pos)
3364 #define US_CSR_ITER_Pos             10           /**< \brief (US_CSR) Max number of Repetitions Reached */
3365 #define US_CSR_ITER                 (_U_(0x1) << US_CSR_ITER_Pos)
3366 #define   US_CSR_ITER_0_Val               _U_(0x0)   /**< \brief (US_CSR) Maximum number of repetitions has not been reached since the last RSIT */
3367 #define   US_CSR_ITER_1_Val               _U_(0x1)   /**< \brief (US_CSR) Maximum number of repetitions has been reached since the last RSIT */
3368 #define US_CSR_ITER_0               (US_CSR_ITER_0_Val             << US_CSR_ITER_Pos)
3369 #define US_CSR_ITER_1               (US_CSR_ITER_1_Val             << US_CSR_ITER_Pos)
3370 #define US_CSR_UNRE_Pos             10           /**< \brief (US_CSR) SPI Underrun Error */
3371 #define US_CSR_UNRE                 (_U_(0x1) << US_CSR_UNRE_Pos)
3372 #define   US_CSR_UNRE_0_Val               _U_(0x0)   /**< \brief (US_CSR) No SPI underrun error has occurred since the last RSTSTA */
3373 #define   US_CSR_UNRE_1_Val               _U_(0x1)   /**< \brief (US_CSR) At least one SPI underrun error has occurred since the last RSTSTA */
3374 #define US_CSR_UNRE_0               (US_CSR_UNRE_0_Val             << US_CSR_UNRE_Pos)
3375 #define US_CSR_UNRE_1               (US_CSR_UNRE_1_Val             << US_CSR_UNRE_Pos)
3376 #define US_CSR_ITER_Pos             10           /**< \brief (US_CSR) Max number of Repetitions Reached */
3377 #define US_CSR_ITER                 (_U_(0x1) << US_CSR_ITER_Pos)
3378 #define   US_CSR_ITER_0_Val               _U_(0x0)   /**< \brief (US_CSR) Maximum number of repetitions has not been reached since the last RSIT */
3379 #define   US_CSR_ITER_1_Val               _U_(0x1)   /**< \brief (US_CSR) Maximum number of repetitions has been reached since the last RSIT */
3380 #define US_CSR_ITER_0               (US_CSR_ITER_0_Val             << US_CSR_ITER_Pos)
3381 #define US_CSR_ITER_1               (US_CSR_ITER_1_Val             << US_CSR_ITER_Pos)
3382 #define US_CSR_TXBUFE_Pos           11           /**< \brief (US_CSR) Transmission Buffer Empty */
3383 #define US_CSR_TXBUFE               (_U_(0x1) << US_CSR_TXBUFE_Pos)
3384 #define   US_CSR_TXBUFE_0_Val             _U_(0x0)   /**< \brief (US_CSR) The signal Buffer Empty from the Transmit PDC channel is inactive */
3385 #define   US_CSR_TXBUFE_1_Val             _U_(0x1)   /**< \brief (US_CSR) The signal Buffer Empty from the Transmit PDC channel is active */
3386 #define US_CSR_TXBUFE_0             (US_CSR_TXBUFE_0_Val           << US_CSR_TXBUFE_Pos)
3387 #define US_CSR_TXBUFE_1             (US_CSR_TXBUFE_1_Val           << US_CSR_TXBUFE_Pos)
3388 #define US_CSR_RXBUFF_Pos           12           /**< \brief (US_CSR) Reception Buffer Full */
3389 #define US_CSR_RXBUFF               (_U_(0x1) << US_CSR_RXBUFF_Pos)
3390 #define   US_CSR_RXBUFF_0_Val             _U_(0x0)   /**< \brief (US_CSR) The signal Buffer Full from the Receive PDC channel is inactive */
3391 #define   US_CSR_RXBUFF_1_Val             _U_(0x1)   /**< \brief (US_CSR) The signal Buffer Full from the Receive PDC channel is active */
3392 #define US_CSR_RXBUFF_0             (US_CSR_RXBUFF_0_Val           << US_CSR_RXBUFF_Pos)
3393 #define US_CSR_RXBUFF_1             (US_CSR_RXBUFF_1_Val           << US_CSR_RXBUFF_Pos)
3394 #define US_CSR_NACK_Pos             13           /**< \brief (US_CSR) Non Acknowledge or LIN Break Sent or LIN Break Received */
3395 #define US_CSR_NACK                 (_U_(0x1) << US_CSR_NACK_Pos)
3396 #define   US_CSR_NACK_0_Val               _U_(0x0)   /**< \brief (US_CSR) No Non Acknowledge has not been detected since the last RSTNACK */
3397 #define   US_CSR_NACK_1_Val               _U_(0x1)   /**< \brief (US_CSR) At least one Non Acknowledge has been detected since the last RSTNACK */
3398 #define US_CSR_NACK_0               (US_CSR_NACK_0_Val             << US_CSR_NACK_Pos)
3399 #define US_CSR_NACK_1               (US_CSR_NACK_1_Val             << US_CSR_NACK_Pos)
3400 #define US_CSR_LINID_Pos            14           /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received */
3401 #define US_CSR_LINID                (_U_(0x1) << US_CSR_LINID_Pos)
3402 #define US_CSR_LINTC_Pos            15           /**< \brief (US_CSR) LIN Transfer Conpleted */
3403 #define US_CSR_LINTC                (_U_(0x1) << US_CSR_LINTC_Pos)
3404 #define US_CSR_RIIC_Pos             16           /**< \brief (US_CSR) Ring Indicator Input Change Flag */
3405 #define US_CSR_RIIC                 (_U_(0x1) << US_CSR_RIIC_Pos)
3406 #define   US_CSR_RIIC_0_Val               _U_(0x0)   /**< \brief (US_CSR) No input change has been detected on the RI pin since the last read of CSR */
3407 #define   US_CSR_RIIC_1_Val               _U_(0x1)   /**< \brief (US_CSR) At least one input change has been detected on the RI pin since the last read of CSR */
3408 #define US_CSR_RIIC_0               (US_CSR_RIIC_0_Val             << US_CSR_RIIC_Pos)
3409 #define US_CSR_RIIC_1               (US_CSR_RIIC_1_Val             << US_CSR_RIIC_Pos)
3410 #define US_CSR_DSRIC_Pos            17           /**< \brief (US_CSR) Data Set Ready Input Change Flag */
3411 #define US_CSR_DSRIC                (_U_(0x1) << US_CSR_DSRIC_Pos)
3412 #define   US_CSR_DSRIC_0_Val              _U_(0x0)   /**< \brief (US_CSR) No input change has been detected on the DSR pin since the last read of CSR */
3413 #define   US_CSR_DSRIC_1_Val              _U_(0x1)   /**< \brief (US_CSR) At least one input change has been detected on the DSR pin since the last read of CSR */
3414 #define US_CSR_DSRIC_0              (US_CSR_DSRIC_0_Val            << US_CSR_DSRIC_Pos)
3415 #define US_CSR_DSRIC_1              (US_CSR_DSRIC_1_Val            << US_CSR_DSRIC_Pos)
3416 #define US_CSR_DCDIC_Pos            18           /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
3417 #define US_CSR_DCDIC                (_U_(0x1) << US_CSR_DCDIC_Pos)
3418 #define   US_CSR_DCDIC_0_Val              _U_(0x0)   /**< \brief (US_CSR) No input change has been detected on the DCD pin since the last read of CSR */
3419 #define   US_CSR_DCDIC_1_Val              _U_(0x1)   /**< \brief (US_CSR) At least one input change has been detected on the DCD pin since the last read of CSR */
3420 #define US_CSR_DCDIC_0              (US_CSR_DCDIC_0_Val            << US_CSR_DCDIC_Pos)
3421 #define US_CSR_DCDIC_1              (US_CSR_DCDIC_1_Val            << US_CSR_DCDIC_Pos)
3422 #define US_CSR_CTSIC_Pos            19           /**< \brief (US_CSR) Clear to Send Input Change Flag */
3423 #define US_CSR_CTSIC                (_U_(0x1) << US_CSR_CTSIC_Pos)
3424 #define   US_CSR_CTSIC_0_Val              _U_(0x0)   /**< \brief (US_CSR) No input change has been detected on the CTS pin since the last read of CSR */
3425 #define   US_CSR_CTSIC_1_Val              _U_(0x1)   /**< \brief (US_CSR) At least one input change has been detected on the CTS pin since the last read of CSR */
3426 #define US_CSR_CTSIC_0              (US_CSR_CTSIC_0_Val            << US_CSR_CTSIC_Pos)
3427 #define US_CSR_CTSIC_1              (US_CSR_CTSIC_1_Val            << US_CSR_CTSIC_Pos)
3428 #define US_CSR_RI_Pos               20           /**< \brief (US_CSR) Image of RI Input */
3429 #define US_CSR_RI                   (_U_(0x1) << US_CSR_RI_Pos)
3430 #define   US_CSR_RI_0_Val                 _U_(0x0)   /**< \brief (US_CSR) RI is at 0 */
3431 #define   US_CSR_RI_1_Val                 _U_(0x1)   /**< \brief (US_CSR) RI is at 1 */
3432 #define US_CSR_RI_0                 (US_CSR_RI_0_Val               << US_CSR_RI_Pos)
3433 #define US_CSR_RI_1                 (US_CSR_RI_1_Val               << US_CSR_RI_Pos)
3434 #define US_CSR_DSR_Pos              21           /**< \brief (US_CSR) Image of DSR Input */
3435 #define US_CSR_DSR                  (_U_(0x1) << US_CSR_DSR_Pos)
3436 #define   US_CSR_DSR_0_Val                _U_(0x0)   /**< \brief (US_CSR) DSR is at 0 */
3437 #define   US_CSR_DSR_1_Val                _U_(0x1)   /**< \brief (US_CSR) DSR is at 1 */
3438 #define US_CSR_DSR_0                (US_CSR_DSR_0_Val              << US_CSR_DSR_Pos)
3439 #define US_CSR_DSR_1                (US_CSR_DSR_1_Val              << US_CSR_DSR_Pos)
3440 #define US_CSR_DCD_Pos              22           /**< \brief (US_CSR) Image of DCD Input */
3441 #define US_CSR_DCD                  (_U_(0x1) << US_CSR_DCD_Pos)
3442 #define   US_CSR_DCD_0_Val                _U_(0x0)   /**< \brief (US_CSR) DCD is at 0 */
3443 #define   US_CSR_DCD_1_Val                _U_(0x1)   /**< \brief (US_CSR) DCD is at 1 */
3444 #define US_CSR_DCD_0                (US_CSR_DCD_0_Val              << US_CSR_DCD_Pos)
3445 #define US_CSR_DCD_1                (US_CSR_DCD_1_Val              << US_CSR_DCD_Pos)
3446 #define US_CSR_LINBLS_Pos           23           /**< \brief (US_CSR) LIN Bus Line Status */
3447 #define US_CSR_LINBLS               (_U_(0x1) << US_CSR_LINBLS_Pos)
3448 #define   US_CSR_LINBLS_0_Val             _U_(0x0)   /**< \brief (US_CSR) CTS is at 0 */
3449 #define   US_CSR_LINBLS_1_Val             _U_(0x1)   /**< \brief (US_CSR) CTS is at 1 */
3450 #define US_CSR_LINBLS_0             (US_CSR_LINBLS_0_Val           << US_CSR_LINBLS_Pos)
3451 #define US_CSR_LINBLS_1             (US_CSR_LINBLS_1_Val           << US_CSR_LINBLS_Pos)
3452 #define US_CSR_CTS_Pos              23           /**< \brief (US_CSR) Image of CTS Input */
3453 #define US_CSR_CTS                  (_U_(0x1) << US_CSR_CTS_Pos)
3454 #define   US_CSR_CTS_0_Val                _U_(0x0)   /**< \brief (US_CSR) CTS is at 0 */
3455 #define   US_CSR_CTS_1_Val                _U_(0x1)   /**< \brief (US_CSR) CTS is at 1 */
3456 #define US_CSR_CTS_0                (US_CSR_CTS_0_Val              << US_CSR_CTS_Pos)
3457 #define US_CSR_CTS_1                (US_CSR_CTS_1_Val              << US_CSR_CTS_Pos)
3458 #define US_CSR_MANERR_Pos           24           /**< \brief (US_CSR) Manchester Error */
3459 #define US_CSR_MANERR               (_U_(0x1) << US_CSR_MANERR_Pos)
3460 #define   US_CSR_MANERR_0_Val             _U_(0x0)   /**< \brief (US_CSR) No Manchester error has been detected since the last RSTSTA */
3461 #define   US_CSR_MANERR_1_Val             _U_(0x1)   /**< \brief (US_CSR) At least one Manchester error has been detected since the last RSTSTA */
3462 #define US_CSR_MANERR_0             (US_CSR_MANERR_0_Val           << US_CSR_MANERR_Pos)
3463 #define US_CSR_MANERR_1             (US_CSR_MANERR_1_Val           << US_CSR_MANERR_Pos)
3464 #define US_CSR_LINBE_Pos            25           /**< \brief (US_CSR) LIN Bit Error */
3465 #define US_CSR_LINBE                (_U_(0x1) << US_CSR_LINBE_Pos)
3466 #define US_CSR_LINISFE_Pos          26           /**< \brief (US_CSR) LIN Inconsistent Synch Field Error */
3467 #define US_CSR_LINISFE              (_U_(0x1) << US_CSR_LINISFE_Pos)
3468 #define US_CSR_LINIPE_Pos           27           /**< \brief (US_CSR) LIN Identifier Parity Error */
3469 #define US_CSR_LINIPE               (_U_(0x1) << US_CSR_LINIPE_Pos)
3470 #define US_CSR_LINCE_Pos            28           /**< \brief (US_CSR) LIN Checksum Error */
3471 #define US_CSR_LINCE                (_U_(0x1) << US_CSR_LINCE_Pos)
3472 #define US_CSR_LINSNRE_Pos          29           /**< \brief (US_CSR) LIN Slave Not Responding Error */
3473 #define US_CSR_LINSNRE              (_U_(0x1) << US_CSR_LINSNRE_Pos)
3474 #define US_CSR_LINSTE_Pos           30           /**< \brief (US_CSR) LIN Synch Tolerance Error */
3475 #define US_CSR_LINSTE               (_U_(0x1) << US_CSR_LINSTE_Pos)
3476 #define   US_CSR_LINSTE_0_Val             _U_(0x0)   /**< \brief (US_CSR) COMM_TX is at 0 */
3477 #define   US_CSR_LINSTE_1_Val             _U_(0x1)   /**< \brief (US_CSR) COMM_TX is at 1 */
3478 #define US_CSR_LINSTE_0             (US_CSR_LINSTE_0_Val           << US_CSR_LINSTE_Pos)
3479 #define US_CSR_LINSTE_1             (US_CSR_LINSTE_1_Val           << US_CSR_LINSTE_Pos)
3480 #define US_CSR_LINHTE_Pos           31           /**< \brief (US_CSR) LIN Header Timeout Error */
3481 #define US_CSR_LINHTE               (_U_(0x1) << US_CSR_LINHTE_Pos)
3482 #define   US_CSR_LINHTE_0_Val             _U_(0x0)   /**< \brief (US_CSR) COMM_RX is at 0 */
3483 #define   US_CSR_LINHTE_1_Val             _U_(0x1)   /**< \brief (US_CSR) COMM_RX is at 1 */
3484 #define US_CSR_LINHTE_0             (US_CSR_LINHTE_0_Val           << US_CSR_LINHTE_Pos)
3485 #define US_CSR_LINHTE_1             (US_CSR_LINHTE_1_Val           << US_CSR_LINHTE_Pos)
3486 #define US_CSR_MASK                 _U_(0xFFFFFFE7) /**< \brief (US_CSR) MASK Register */
3487 
3488 /* -------- US_RHR : (USART Offset: 0x18) (R/  32) Receiver Holding Register -------- */
3489 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3490 typedef union {
3491   struct {
3492     uint32_t RXCHR:9;          /*!< bit:  0.. 8  Received Character                 */
3493     uint32_t :6;               /*!< bit:  9..14  Reserved                           */
3494     uint32_t RXSYNH:1;         /*!< bit:     15  Received Sync                      */
3495     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
3496   } bit;                       /*!< Structure used for bit  access                  */
3497   uint32_t reg;                /*!< Type      used for register access              */
3498 } US_RHR_Type;
3499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3500 
3501 #define US_RHR_OFFSET               0x18         /**< \brief (US_RHR offset) Receiver Holding Register */
3502 #define US_RHR_RESETVALUE           _U_(0x00000000); /**< \brief (US_RHR reset_value) Receiver Holding Register */
3503 
3504 #define US_RHR_RXCHR_Pos            0            /**< \brief (US_RHR) Received Character */
3505 #define US_RHR_RXCHR_Msk            (_U_(0x1FF) << US_RHR_RXCHR_Pos)
3506 #define US_RHR_RXCHR(value)         (US_RHR_RXCHR_Msk & ((value) << US_RHR_RXCHR_Pos))
3507 #define US_RHR_RXSYNH_Pos           15           /**< \brief (US_RHR) Received Sync */
3508 #define US_RHR_RXSYNH               (_U_(0x1) << US_RHR_RXSYNH_Pos)
3509 #define   US_RHR_RXSYNH_0_Val             _U_(0x0)   /**< \brief (US_RHR) Last character received is a Data */
3510 #define   US_RHR_RXSYNH_1_Val             _U_(0x1)   /**< \brief (US_RHR) Last character received is a Command */
3511 #define US_RHR_RXSYNH_0             (US_RHR_RXSYNH_0_Val           << US_RHR_RXSYNH_Pos)
3512 #define US_RHR_RXSYNH_1             (US_RHR_RXSYNH_1_Val           << US_RHR_RXSYNH_Pos)
3513 #define US_RHR_MASK                 _U_(0x000081FF) /**< \brief (US_RHR) MASK Register */
3514 
3515 /* -------- US_THR : (USART Offset: 0x1C) ( /W 32) Transmitter Holding Register -------- */
3516 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3517 typedef union {
3518   struct {
3519     uint32_t TXCHR:9;          /*!< bit:  0.. 8  Character to be Transmitted        */
3520     uint32_t :6;               /*!< bit:  9..14  Reserved                           */
3521     uint32_t TXSYNH:1;         /*!< bit:     15  Sync Field to be transmitted       */
3522     uint32_t :16;              /*!< bit: 16..31  Reserved                           */
3523   } bit;                       /*!< Structure used for bit  access                  */
3524   uint32_t reg;                /*!< Type      used for register access              */
3525 } US_THR_Type;
3526 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3527 
3528 #define US_THR_OFFSET               0x1C         /**< \brief (US_THR offset) Transmitter Holding Register */
3529 #define US_THR_RESETVALUE           _U_(0x00000000); /**< \brief (US_THR reset_value) Transmitter Holding Register */
3530 
3531 #define US_THR_TXCHR_Pos            0            /**< \brief (US_THR) Character to be Transmitted */
3532 #define US_THR_TXCHR_Msk            (_U_(0x1FF) << US_THR_TXCHR_Pos)
3533 #define US_THR_TXCHR(value)         (US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))
3534 #define US_THR_TXSYNH_Pos           15           /**< \brief (US_THR) Sync Field to be transmitted */
3535 #define US_THR_TXSYNH               (_U_(0x1) << US_THR_TXSYNH_Pos)
3536 #define   US_THR_TXSYNH_0_Val             _U_(0x0)   /**< \brief (US_THR) The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC */
3537 #define   US_THR_TXSYNH_1_Val             _U_(0x1)   /**< \brief (US_THR) The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC */
3538 #define US_THR_TXSYNH_0             (US_THR_TXSYNH_0_Val           << US_THR_TXSYNH_Pos)
3539 #define US_THR_TXSYNH_1             (US_THR_TXSYNH_1_Val           << US_THR_TXSYNH_Pos)
3540 #define US_THR_MASK                 _U_(0x000081FF) /**< \brief (US_THR) MASK Register */
3541 
3542 /* -------- US_BRGR : (USART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */
3543 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3544 typedef union {
3545   struct {
3546     uint32_t CD:16;            /*!< bit:  0..15  Clock Divisor                      */
3547     uint32_t FP:3;             /*!< bit: 16..18  Fractional Part                    */
3548     uint32_t :13;              /*!< bit: 19..31  Reserved                           */
3549   } bit;                       /*!< Structure used for bit  access                  */
3550   uint32_t reg;                /*!< Type      used for register access              */
3551 } US_BRGR_Type;
3552 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3553 
3554 #define US_BRGR_OFFSET              0x20         /**< \brief (US_BRGR offset) Baud Rate Generator Register */
3555 #define US_BRGR_RESETVALUE          _U_(0x00000000); /**< \brief (US_BRGR reset_value) Baud Rate Generator Register */
3556 
3557 #define US_BRGR_CD_Pos              0            /**< \brief (US_BRGR) Clock Divisor */
3558 #define US_BRGR_CD_Msk              (_U_(0xFFFF) << US_BRGR_CD_Pos)
3559 #define US_BRGR_CD(value)           (US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))
3560 #define   US_BRGR_CD_DISABLE_Val          _U_(0x0)   /**< \brief (US_BRGR) Disables the clock */
3561 #define   US_BRGR_CD_BYPASS_Val           _U_(0x1)   /**< \brief (US_BRGR) Clock Divisor Bypass */
3562 #define   US_BRGR_CD_2_Val                _U_(0x2)   /**< \brief (US_BRGR) Baud Rate (Asynchronous Mode) = Selected Clock/(16 x CD) or (8 x CD); Baud Rate (Synchronous Mode) = Selected Clock/CD; */
3563 #define US_BRGR_CD_DISABLE          (US_BRGR_CD_DISABLE_Val        << US_BRGR_CD_Pos)
3564 #define US_BRGR_CD_BYPASS           (US_BRGR_CD_BYPASS_Val         << US_BRGR_CD_Pos)
3565 #define US_BRGR_CD_2                (US_BRGR_CD_2_Val              << US_BRGR_CD_Pos)
3566 #define US_BRGR_FP_Pos              16           /**< \brief (US_BRGR) Fractional Part */
3567 #define US_BRGR_FP_Msk              (_U_(0x7) << US_BRGR_FP_Pos)
3568 #define US_BRGR_FP(value)           (US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))
3569 #define   US_BRGR_FP_0_Val                _U_(0x0)   /**< \brief (US_BRGR) Fractional divider is disabled */
3570 #define US_BRGR_FP_0                (US_BRGR_FP_0_Val              << US_BRGR_FP_Pos)
3571 #define US_BRGR_MASK                _U_(0x0007FFFF) /**< \brief (US_BRGR) MASK Register */
3572 
3573 /* -------- US_RTOR : (USART Offset: 0x24) (R/W 32) Receiver Time-out Register -------- */
3574 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3575 typedef union {
3576   struct {
3577     uint32_t TO:17;            /*!< bit:  0..16  Time-out Value                     */
3578     uint32_t :15;              /*!< bit: 17..31  Reserved                           */
3579   } bit;                       /*!< Structure used for bit  access                  */
3580   uint32_t reg;                /*!< Type      used for register access              */
3581 } US_RTOR_Type;
3582 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3583 
3584 #define US_RTOR_OFFSET              0x24         /**< \brief (US_RTOR offset) Receiver Time-out Register */
3585 #define US_RTOR_RESETVALUE          _U_(0x00000000); /**< \brief (US_RTOR reset_value) Receiver Time-out Register */
3586 
3587 #define US_RTOR_TO_Pos              0            /**< \brief (US_RTOR) Time-out Value */
3588 #define US_RTOR_TO_Msk              (_U_(0x1FFFF) << US_RTOR_TO_Pos)
3589 #define US_RTOR_TO(value)           (US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))
3590 #define   US_RTOR_TO_DISABLE_Val          _U_(0x0)   /**< \brief (US_RTOR) Disables the RX Time-out function */
3591 #define US_RTOR_TO_DISABLE          (US_RTOR_TO_DISABLE_Val        << US_RTOR_TO_Pos)
3592 #define US_RTOR_MASK                _U_(0x0001FFFF) /**< \brief (US_RTOR) MASK Register */
3593 
3594 /* -------- US_TTGR : (USART Offset: 0x28) (R/W 32) Transmitter Timeguard Register -------- */
3595 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3596 typedef union {
3597   struct {
3598     uint32_t TG:8;             /*!< bit:  0.. 7  Timeguard Value                    */
3599     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
3600   } bit;                       /*!< Structure used for bit  access                  */
3601   uint32_t reg;                /*!< Type      used for register access              */
3602 } US_TTGR_Type;
3603 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3604 
3605 #define US_TTGR_OFFSET              0x28         /**< \brief (US_TTGR offset) Transmitter Timeguard Register */
3606 #define US_TTGR_RESETVALUE          _U_(0x00000000); /**< \brief (US_TTGR reset_value) Transmitter Timeguard Register */
3607 
3608 #define US_TTGR_TG_Pos              0            /**< \brief (US_TTGR) Timeguard Value */
3609 #define US_TTGR_TG_Msk              (_U_(0xFF) << US_TTGR_TG_Pos)
3610 #define US_TTGR_TG(value)           (US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))
3611 #define   US_TTGR_TG_DISABLE_Val          _U_(0x0)   /**< \brief (US_TTGR) Disables the TX Timeguard function. */
3612 #define US_TTGR_TG_DISABLE          (US_TTGR_TG_DISABLE_Val        << US_TTGR_TG_Pos)
3613 #define US_TTGR_MASK                _U_(0x000000FF) /**< \brief (US_TTGR) MASK Register */
3614 
3615 /* -------- US_FIDI : (USART Offset: 0x40) (R/W 32) FI DI Ratio Register -------- */
3616 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3617 typedef union {
3618   struct {
3619     uint32_t FI_DI_RATIO:11;   /*!< bit:  0..10  FI Over DI Ratio Value             */
3620     uint32_t :21;              /*!< bit: 11..31  Reserved                           */
3621   } bit;                       /*!< Structure used for bit  access                  */
3622   uint32_t reg;                /*!< Type      used for register access              */
3623 } US_FIDI_Type;
3624 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3625 
3626 #define US_FIDI_OFFSET              0x40         /**< \brief (US_FIDI offset) FI DI Ratio Register */
3627 #define US_FIDI_RESETVALUE          _U_(0x00000174); /**< \brief (US_FIDI reset_value) FI DI Ratio Register */
3628 
3629 #define US_FIDI_FI_DI_RATIO_Pos     0            /**< \brief (US_FIDI) FI Over DI Ratio Value */
3630 #define US_FIDI_FI_DI_RATIO_Msk     (_U_(0x7FF) << US_FIDI_FI_DI_RATIO_Pos)
3631 #define US_FIDI_FI_DI_RATIO(value)  (US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))
3632 #define   US_FIDI_FI_DI_RATIO_DISABLE_Val _U_(0x0)   /**< \brief (US_FIDI) Baud Rate = 0 */
3633 #define US_FIDI_FI_DI_RATIO_DISABLE (US_FIDI_FI_DI_RATIO_DISABLE_Val << US_FIDI_FI_DI_RATIO_Pos)
3634 #define US_FIDI_MASK                _U_(0x000007FF) /**< \brief (US_FIDI) MASK Register */
3635 
3636 /* -------- US_NER : (USART Offset: 0x44) (R/  32) Number of Errors Register -------- */
3637 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3638 typedef union {
3639   struct {
3640     uint32_t NB_ERRORS:8;      /*!< bit:  0.. 7  Error number during ISO7816 transfers */
3641     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
3642   } bit;                       /*!< Structure used for bit  access                  */
3643   uint32_t reg;                /*!< Type      used for register access              */
3644 } US_NER_Type;
3645 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3646 
3647 #define US_NER_OFFSET               0x44         /**< \brief (US_NER offset) Number of Errors Register */
3648 #define US_NER_RESETVALUE           _U_(0x00000000); /**< \brief (US_NER reset_value) Number of Errors Register */
3649 
3650 #define US_NER_NB_ERRORS_Pos        0            /**< \brief (US_NER) Error number during ISO7816 transfers */
3651 #define US_NER_NB_ERRORS_Msk        (_U_(0xFF) << US_NER_NB_ERRORS_Pos)
3652 #define US_NER_NB_ERRORS(value)     (US_NER_NB_ERRORS_Msk & ((value) << US_NER_NB_ERRORS_Pos))
3653 #define US_NER_MASK                 _U_(0x000000FF) /**< \brief (US_NER) MASK Register */
3654 
3655 /* -------- US_IFR : (USART Offset: 0x4C) (R/W 32) IrDA Filter Register -------- */
3656 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3657 typedef union {
3658   struct {
3659     uint32_t IRDA_FILTER:8;    /*!< bit:  0.. 7  Irda filter                        */
3660     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
3661   } bit;                       /*!< Structure used for bit  access                  */
3662   uint32_t reg;                /*!< Type      used for register access              */
3663 } US_IFR_Type;
3664 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3665 
3666 #define US_IFR_OFFSET               0x4C         /**< \brief (US_IFR offset) IrDA Filter Register */
3667 #define US_IFR_RESETVALUE           _U_(0x00000000); /**< \brief (US_IFR reset_value) IrDA Filter Register */
3668 
3669 #define US_IFR_IRDA_FILTER_Pos      0            /**< \brief (US_IFR) Irda filter */
3670 #define US_IFR_IRDA_FILTER_Msk      (_U_(0xFF) << US_IFR_IRDA_FILTER_Pos)
3671 #define US_IFR_IRDA_FILTER(value)   (US_IFR_IRDA_FILTER_Msk & ((value) << US_IFR_IRDA_FILTER_Pos))
3672 #define US_IFR_MASK                 _U_(0x000000FF) /**< \brief (US_IFR) MASK Register */
3673 
3674 /* -------- US_MAN : (USART Offset: 0x50) (R/W 32) Manchester Configuration Register -------- */
3675 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3676 typedef union {
3677   struct {
3678     uint32_t TX_PL:4;          /*!< bit:  0.. 3  Transmitter Preamble Length        */
3679     uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
3680     uint32_t TX_PP:2;          /*!< bit:  8.. 9  Transmitter Preamble Pattern       */
3681     uint32_t :2;               /*!< bit: 10..11  Reserved                           */
3682     uint32_t TX_MPOL:1;        /*!< bit:     12  Transmitter Manchester Polarity    */
3683     uint32_t :3;               /*!< bit: 13..15  Reserved                           */
3684     uint32_t RX_PL:4;          /*!< bit: 16..19  Receiver Preamble Length           */
3685     uint32_t :4;               /*!< bit: 20..23  Reserved                           */
3686     uint32_t RX_PP:2;          /*!< bit: 24..25  Receiver Preamble Pattern detected */
3687     uint32_t :2;               /*!< bit: 26..27  Reserved                           */
3688     uint32_t RX_MPOL:1;        /*!< bit:     28  Receiver Manchester Polarity       */
3689     uint32_t :1;               /*!< bit:     29  Reserved                           */
3690     uint32_t DRIFT:1;          /*!< bit:     30  Drift compensation                 */
3691     uint32_t :1;               /*!< bit:     31  Reserved                           */
3692   } bit;                       /*!< Structure used for bit  access                  */
3693   uint32_t reg;                /*!< Type      used for register access              */
3694 } US_MAN_Type;
3695 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3696 
3697 #define US_MAN_OFFSET               0x50         /**< \brief (US_MAN offset) Manchester Configuration Register */
3698 #define US_MAN_RESETVALUE           _U_(0x30011004); /**< \brief (US_MAN reset_value) Manchester Configuration Register */
3699 
3700 #define US_MAN_TX_PL_Pos            0            /**< \brief (US_MAN) Transmitter Preamble Length */
3701 #define US_MAN_TX_PL_Msk            (_U_(0xF) << US_MAN_TX_PL_Pos)
3702 #define US_MAN_TX_PL(value)         (US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))
3703 #define   US_MAN_TX_PL_0_Val              _U_(0x0)   /**< \brief (US_MAN) The Transmitter Preamble pattern generation is disabled */
3704 #define US_MAN_TX_PL_0              (US_MAN_TX_PL_0_Val            << US_MAN_TX_PL_Pos)
3705 #define US_MAN_TX_PP_Pos            8            /**< \brief (US_MAN) Transmitter Preamble Pattern */
3706 #define US_MAN_TX_PP_Msk            (_U_(0x3) << US_MAN_TX_PP_Pos)
3707 #define US_MAN_TX_PP(value)         (US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))
3708 #define   US_MAN_TX_PP_0_Val              _U_(0x0)   /**< \brief (US_MAN) ALL_ONE */
3709 #define   US_MAN_TX_PP_1_Val              _U_(0x1)   /**< \brief (US_MAN) ALL_ZERO */
3710 #define   US_MAN_TX_PP_2_Val              _U_(0x2)   /**< \brief (US_MAN) ZERO_ONE */
3711 #define   US_MAN_TX_PP_3_Val              _U_(0x3)   /**< \brief (US_MAN) ONE_ZERO */
3712 #define US_MAN_TX_PP_0              (US_MAN_TX_PP_0_Val            << US_MAN_TX_PP_Pos)
3713 #define US_MAN_TX_PP_1              (US_MAN_TX_PP_1_Val            << US_MAN_TX_PP_Pos)
3714 #define US_MAN_TX_PP_2              (US_MAN_TX_PP_2_Val            << US_MAN_TX_PP_Pos)
3715 #define US_MAN_TX_PP_3              (US_MAN_TX_PP_3_Val            << US_MAN_TX_PP_Pos)
3716 #define US_MAN_TX_MPOL_Pos          12           /**< \brief (US_MAN) Transmitter Manchester Polarity */
3717 #define US_MAN_TX_MPOL              (_U_(0x1) << US_MAN_TX_MPOL_Pos)
3718 #define   US_MAN_TX_MPOL_0_Val            _U_(0x0)   /**< \brief (US_MAN) Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition */
3719 #define   US_MAN_TX_MPOL_1_Val            _U_(0x1)   /**< \brief (US_MAN) Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition */
3720 #define US_MAN_TX_MPOL_0            (US_MAN_TX_MPOL_0_Val          << US_MAN_TX_MPOL_Pos)
3721 #define US_MAN_TX_MPOL_1            (US_MAN_TX_MPOL_1_Val          << US_MAN_TX_MPOL_Pos)
3722 #define US_MAN_RX_PL_Pos            16           /**< \brief (US_MAN) Receiver Preamble Length */
3723 #define US_MAN_RX_PL_Msk            (_U_(0xF) << US_MAN_RX_PL_Pos)
3724 #define US_MAN_RX_PL(value)         (US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))
3725 #define   US_MAN_RX_PL_0_Val              _U_(0x0)   /**< \brief (US_MAN) The receiver preamble pattern detection is disabled */
3726 #define US_MAN_RX_PL_0              (US_MAN_RX_PL_0_Val            << US_MAN_RX_PL_Pos)
3727 #define US_MAN_RX_PP_Pos            24           /**< \brief (US_MAN) Receiver Preamble Pattern detected */
3728 #define US_MAN_RX_PP_Msk            (_U_(0x3) << US_MAN_RX_PP_Pos)
3729 #define US_MAN_RX_PP(value)         (US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))
3730 #define   US_MAN_RX_PP_0_Val              _U_(0x0)   /**< \brief (US_MAN) ALL_ONE */
3731 #define   US_MAN_RX_PP_1_Val              _U_(0x1)   /**< \brief (US_MAN) ALL_ZERO */
3732 #define   US_MAN_RX_PP_2_Val              _U_(0x2)   /**< \brief (US_MAN) ZERO_ONE */
3733 #define   US_MAN_RX_PP_3_Val              _U_(0x3)   /**< \brief (US_MAN) ONE_ZERO */
3734 #define US_MAN_RX_PP_0              (US_MAN_RX_PP_0_Val            << US_MAN_RX_PP_Pos)
3735 #define US_MAN_RX_PP_1              (US_MAN_RX_PP_1_Val            << US_MAN_RX_PP_Pos)
3736 #define US_MAN_RX_PP_2              (US_MAN_RX_PP_2_Val            << US_MAN_RX_PP_Pos)
3737 #define US_MAN_RX_PP_3              (US_MAN_RX_PP_3_Val            << US_MAN_RX_PP_Pos)
3738 #define US_MAN_RX_MPOL_Pos          28           /**< \brief (US_MAN) Receiver Manchester Polarity */
3739 #define US_MAN_RX_MPOL              (_U_(0x1) << US_MAN_RX_MPOL_Pos)
3740 #define   US_MAN_RX_MPOL_0_Val            _U_(0x0)   /**< \brief (US_MAN) Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition */
3741 #define   US_MAN_RX_MPOL_1_Val            _U_(0x1)   /**< \brief (US_MAN) Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition */
3742 #define US_MAN_RX_MPOL_0            (US_MAN_RX_MPOL_0_Val          << US_MAN_RX_MPOL_Pos)
3743 #define US_MAN_RX_MPOL_1            (US_MAN_RX_MPOL_1_Val          << US_MAN_RX_MPOL_Pos)
3744 #define US_MAN_DRIFT_Pos            30           /**< \brief (US_MAN) Drift compensation */
3745 #define US_MAN_DRIFT                (_U_(0x1) << US_MAN_DRIFT_Pos)
3746 #define   US_MAN_DRIFT_0_Val              _U_(0x0)   /**< \brief (US_MAN) The USART can not recover from an important clock drift */
3747 #define   US_MAN_DRIFT_1_Val              _U_(0x1)   /**< \brief (US_MAN) The USART can recover from clock drift. The 16X clock mode must be enabled */
3748 #define US_MAN_DRIFT_0              (US_MAN_DRIFT_0_Val            << US_MAN_DRIFT_Pos)
3749 #define US_MAN_DRIFT_1              (US_MAN_DRIFT_1_Val            << US_MAN_DRIFT_Pos)
3750 #define US_MAN_MASK                 _U_(0x530F130F) /**< \brief (US_MAN) MASK Register */
3751 
3752 /* -------- US_LINMR : (USART Offset: 0x54) (R/W 32) LIN Mode Register -------- */
3753 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3754 typedef union {
3755   struct {
3756     uint32_t NACT:2;           /*!< bit:  0.. 1  LIN Node Action                    */
3757     uint32_t PARDIS:1;         /*!< bit:      2  Parity Disable                     */
3758     uint32_t CHKDIS:1;         /*!< bit:      3  Checksum Disable                   */
3759     uint32_t CHKTYP:1;         /*!< bit:      4  Checksum Type                      */
3760     uint32_t DLM:1;            /*!< bit:      5  Data Length Mode                   */
3761     uint32_t FSDIS:1;          /*!< bit:      6  Frame Slot Mode Disable            */
3762     uint32_t WKUPTYP:1;        /*!< bit:      7  Wakeup Signal Type                 */
3763     uint32_t DLC:8;            /*!< bit:  8..15  Data Length Control                */
3764     uint32_t PDCM:1;           /*!< bit:     16  PDC Mode                           */
3765     uint32_t SYNCDIS:1;        /*!< bit:     17  Synchronization Disable            */
3766     uint32_t :14;              /*!< bit: 18..31  Reserved                           */
3767   } bit;                       /*!< Structure used for bit  access                  */
3768   uint32_t reg;                /*!< Type      used for register access              */
3769 } US_LINMR_Type;
3770 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3771 
3772 #define US_LINMR_OFFSET             0x54         /**< \brief (US_LINMR offset) LIN Mode Register */
3773 #define US_LINMR_RESETVALUE         _U_(0x00000000); /**< \brief (US_LINMR reset_value) LIN Mode Register */
3774 
3775 #define US_LINMR_NACT_Pos           0            /**< \brief (US_LINMR) LIN Node Action */
3776 #define US_LINMR_NACT_Msk           (_U_(0x3) << US_LINMR_NACT_Pos)
3777 #define US_LINMR_NACT(value)        (US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))
3778 #define   US_LINMR_NACT_PUBLISH_Val       _U_(0x0)   /**< \brief (US_LINMR) The LIN Controller transmits the response */
3779 #define   US_LINMR_NACT_SUBSCRIBE_Val     _U_(0x1)   /**< \brief (US_LINMR) The LIN Controller receives the response */
3780 #define   US_LINMR_NACT_IGNORE_Val        _U_(0x2)   /**< \brief (US_LINMR) The LIN Controller doesn't transmit and doesn't receive the response */
3781 #define US_LINMR_NACT_PUBLISH       (US_LINMR_NACT_PUBLISH_Val     << US_LINMR_NACT_Pos)
3782 #define US_LINMR_NACT_SUBSCRIBE     (US_LINMR_NACT_SUBSCRIBE_Val   << US_LINMR_NACT_Pos)
3783 #define US_LINMR_NACT_IGNORE        (US_LINMR_NACT_IGNORE_Val      << US_LINMR_NACT_Pos)
3784 #define US_LINMR_PARDIS_Pos         2            /**< \brief (US_LINMR) Parity Disable */
3785 #define US_LINMR_PARDIS             (_U_(0x1) << US_LINMR_PARDIS_Pos)
3786 #define US_LINMR_CHKDIS_Pos         3            /**< \brief (US_LINMR) Checksum Disable */
3787 #define US_LINMR_CHKDIS             (_U_(0x1) << US_LINMR_CHKDIS_Pos)
3788 #define US_LINMR_CHKTYP_Pos         4            /**< \brief (US_LINMR) Checksum Type */
3789 #define US_LINMR_CHKTYP             (_U_(0x1) << US_LINMR_CHKTYP_Pos)
3790 #define US_LINMR_DLM_Pos            5            /**< \brief (US_LINMR) Data Length Mode */
3791 #define US_LINMR_DLM                (_U_(0x1) << US_LINMR_DLM_Pos)
3792 #define US_LINMR_FSDIS_Pos          6            /**< \brief (US_LINMR) Frame Slot Mode Disable */
3793 #define US_LINMR_FSDIS              (_U_(0x1) << US_LINMR_FSDIS_Pos)
3794 #define US_LINMR_WKUPTYP_Pos        7            /**< \brief (US_LINMR) Wakeup Signal Type */
3795 #define US_LINMR_WKUPTYP            (_U_(0x1) << US_LINMR_WKUPTYP_Pos)
3796 #define US_LINMR_DLC_Pos            8            /**< \brief (US_LINMR) Data Length Control */
3797 #define US_LINMR_DLC_Msk            (_U_(0xFF) << US_LINMR_DLC_Pos)
3798 #define US_LINMR_DLC(value)         (US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))
3799 #define US_LINMR_PDCM_Pos           16           /**< \brief (US_LINMR) PDC Mode */
3800 #define US_LINMR_PDCM               (_U_(0x1) << US_LINMR_PDCM_Pos)
3801 #define US_LINMR_SYNCDIS_Pos        17           /**< \brief (US_LINMR) Synchronization Disable */
3802 #define US_LINMR_SYNCDIS            (_U_(0x1) << US_LINMR_SYNCDIS_Pos)
3803 #define US_LINMR_MASK               _U_(0x0003FFFF) /**< \brief (US_LINMR) MASK Register */
3804 
3805 /* -------- US_LINIR : (USART Offset: 0x58) (R/W 32) LIN Identifier Register -------- */
3806 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3807 typedef union {
3808   struct {
3809     uint32_t IDCHR:8;          /*!< bit:  0.. 7  Identifier Character               */
3810     uint32_t :24;              /*!< bit:  8..31  Reserved                           */
3811   } bit;                       /*!< Structure used for bit  access                  */
3812   uint32_t reg;                /*!< Type      used for register access              */
3813 } US_LINIR_Type;
3814 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3815 
3816 #define US_LINIR_OFFSET             0x58         /**< \brief (US_LINIR offset) LIN Identifier Register */
3817 #define US_LINIR_RESETVALUE         _U_(0x00000000); /**< \brief (US_LINIR reset_value) LIN Identifier Register */
3818 
3819 #define US_LINIR_IDCHR_Pos          0            /**< \brief (US_LINIR) Identifier Character */
3820 #define US_LINIR_IDCHR_Msk          (_U_(0xFF) << US_LINIR_IDCHR_Pos)
3821 #define US_LINIR_IDCHR(value)       (US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))
3822 #define US_LINIR_MASK               _U_(0x000000FF) /**< \brief (US_LINIR) MASK Register */
3823 
3824 /* -------- US_LINBRR : (USART Offset: 0x5C) (R/  32) LIN Baud Rate Register -------- */
3825 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3826 typedef union {
3827   struct {
3828     uint32_t LINCD:16;         /*!< bit:  0..15  Clock Divider after Synchronization */
3829     uint32_t LINFP:3;          /*!< bit: 16..18  Fractional Part after Synchronization */
3830     uint32_t :13;              /*!< bit: 19..31  Reserved                           */
3831   } bit;                       /*!< Structure used for bit  access                  */
3832   uint32_t reg;                /*!< Type      used for register access              */
3833 } US_LINBRR_Type;
3834 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3835 
3836 #define US_LINBRR_OFFSET            0x5C         /**< \brief (US_LINBRR offset) LIN Baud Rate Register */
3837 #define US_LINBRR_RESETVALUE        _U_(0x00000000); /**< \brief (US_LINBRR reset_value) LIN Baud Rate Register */
3838 
3839 #define US_LINBRR_LINCD_Pos         0            /**< \brief (US_LINBRR) Clock Divider after Synchronization */
3840 #define US_LINBRR_LINCD_Msk         (_U_(0xFFFF) << US_LINBRR_LINCD_Pos)
3841 #define US_LINBRR_LINCD(value)      (US_LINBRR_LINCD_Msk & ((value) << US_LINBRR_LINCD_Pos))
3842 #define US_LINBRR_LINFP_Pos         16           /**< \brief (US_LINBRR) Fractional Part after Synchronization */
3843 #define US_LINBRR_LINFP_Msk         (_U_(0x7) << US_LINBRR_LINFP_Pos)
3844 #define US_LINBRR_LINFP(value)      (US_LINBRR_LINFP_Msk & ((value) << US_LINBRR_LINFP_Pos))
3845 #define US_LINBRR_MASK              _U_(0x0007FFFF) /**< \brief (US_LINBRR) MASK Register */
3846 
3847 /* -------- US_WPMR : (USART Offset: 0xE4) (R/W 32) Write Protect Mode Register -------- */
3848 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3849 typedef union {
3850   struct {
3851     uint32_t WPEN:1;           /*!< bit:      0  Write Protect Enable               */
3852     uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
3853     uint32_t WPKEY:24;         /*!< bit:  8..31  Write Protect Key                  */
3854   } bit;                       /*!< Structure used for bit  access                  */
3855   uint32_t reg;                /*!< Type      used for register access              */
3856 } US_WPMR_Type;
3857 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3858 
3859 #define US_WPMR_OFFSET              0xE4         /**< \brief (US_WPMR offset) Write Protect Mode Register */
3860 #define US_WPMR_RESETVALUE          _U_(0x00000000); /**< \brief (US_WPMR reset_value) Write Protect Mode Register */
3861 
3862 #define US_WPMR_WPEN_Pos            0            /**< \brief (US_WPMR) Write Protect Enable */
3863 #define US_WPMR_WPEN                (_U_(0x1) << US_WPMR_WPEN_Pos)
3864 #define   US_WPMR_WPEN_0_Val              _U_(0x0)   /**< \brief (US_WPMR) Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) */
3865 #define   US_WPMR_WPEN_1_Val              _U_(0x1)   /**< \brief (US_WPMR) Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ACII) */
3866 #define US_WPMR_WPEN_0              (US_WPMR_WPEN_0_Val            << US_WPMR_WPEN_Pos)
3867 #define US_WPMR_WPEN_1              (US_WPMR_WPEN_1_Val            << US_WPMR_WPEN_Pos)
3868 #define US_WPMR_WPKEY_Pos           8            /**< \brief (US_WPMR) Write Protect Key */
3869 #define US_WPMR_WPKEY_Msk           (_U_(0xFFFFFF) << US_WPMR_WPKEY_Pos)
3870 #define US_WPMR_WPKEY(value)        (US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))
3871 #define US_WPMR_MASK                _U_(0xFFFFFF01) /**< \brief (US_WPMR) MASK Register */
3872 
3873 /* -------- US_WPSR : (USART Offset: 0xE8) (R/  32) Write Protect Status Register -------- */
3874 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3875 typedef union {
3876   struct {
3877     uint32_t WPV:1;            /*!< bit:      0  Write Protect Violation Status     */
3878     uint32_t :7;               /*!< bit:  1.. 7  Reserved                           */
3879     uint32_t WPVSRC:16;        /*!< bit:  8..23  Write Protect Violation Source     */
3880     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
3881   } bit;                       /*!< Structure used for bit  access                  */
3882   uint32_t reg;                /*!< Type      used for register access              */
3883 } US_WPSR_Type;
3884 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3885 
3886 #define US_WPSR_OFFSET              0xE8         /**< \brief (US_WPSR offset) Write Protect Status Register */
3887 #define US_WPSR_RESETVALUE          _U_(0x00000000); /**< \brief (US_WPSR reset_value) Write Protect Status Register */
3888 
3889 #define US_WPSR_WPV_Pos             0            /**< \brief (US_WPSR) Write Protect Violation Status */
3890 #define US_WPSR_WPV                 (_U_(0x1) << US_WPSR_WPV_Pos)
3891 #define   US_WPSR_WPV_0_Val               _U_(0x0)   /**< \brief (US_WPSR) No Write Protect Violation has occurred since the last read of the WPSR register */
3892 #define   US_WPSR_WPV_1_Val               _U_(0x1)   /**< \brief (US_WPSR) A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC */
3893 #define US_WPSR_WPV_0               (US_WPSR_WPV_0_Val             << US_WPSR_WPV_Pos)
3894 #define US_WPSR_WPV_1               (US_WPSR_WPV_1_Val             << US_WPSR_WPV_Pos)
3895 #define US_WPSR_WPVSRC_Pos          8            /**< \brief (US_WPSR) Write Protect Violation Source */
3896 #define US_WPSR_WPVSRC_Msk          (_U_(0xFFFF) << US_WPSR_WPVSRC_Pos)
3897 #define US_WPSR_WPVSRC(value)       (US_WPSR_WPVSRC_Msk & ((value) << US_WPSR_WPVSRC_Pos))
3898 #define US_WPSR_MASK                _U_(0x00FFFF01) /**< \brief (US_WPSR) MASK Register */
3899 
3900 /* -------- US_VERSION : (USART Offset: 0xFC) (R/  32) Version Register -------- */
3901 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3902 typedef union {
3903   struct {
3904     uint32_t VERSION:12;       /*!< bit:  0..11  Version                            */
3905     uint32_t :4;               /*!< bit: 12..15  Reserved                           */
3906     uint32_t MFN:4;            /*!< bit: 16..19  MFN                                */
3907     uint32_t :12;              /*!< bit: 20..31  Reserved                           */
3908   } bit;                       /*!< Structure used for bit  access                  */
3909   uint32_t reg;                /*!< Type      used for register access              */
3910 } US_VERSION_Type;
3911 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3912 
3913 #define US_VERSION_OFFSET           0xFC         /**< \brief (US_VERSION offset) Version Register */
3914 #define US_VERSION_RESETVALUE       _U_(0x00000602); /**< \brief (US_VERSION reset_value) Version Register */
3915 
3916 #define US_VERSION_VERSION_Pos      0            /**< \brief (US_VERSION) Version */
3917 #define US_VERSION_VERSION_Msk      (_U_(0xFFF) << US_VERSION_VERSION_Pos)
3918 #define US_VERSION_VERSION(value)   (US_VERSION_VERSION_Msk & ((value) << US_VERSION_VERSION_Pos))
3919 #define US_VERSION_MFN_Pos          16           /**< \brief (US_VERSION) MFN */
3920 #define US_VERSION_MFN_Msk          (_U_(0xF) << US_VERSION_MFN_Pos)
3921 #define US_VERSION_MFN(value)       (US_VERSION_MFN_Msk & ((value) << US_VERSION_MFN_Pos))
3922 #define US_VERSION_MASK             _U_(0x000F0FFF) /**< \brief (US_VERSION) MASK Register */
3923 
3924 /** \brief USART hardware registers */
3925 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
3926 typedef struct {
3927   __O  uint32_t US_CR;          /**< (USART Offset: 0x00) Control Register */
3928   __IO uint32_t US_MR;          /**< (USART Offset: 0x04) Mode Register */
3929   __O  uint32_t US_IER;         /**< (USART Offset: 0x08) Interrupt Enable Register */
3930   __O  uint32_t US_IDR;         /**< (USART Offset: 0x0C) Interrupt Disable Register */
3931   __I  uint32_t US_IMR;         /**< (USART Offset: 0x10) Interrupt Mask Register */
3932   __I  uint32_t US_CSR;         /**< (USART Offset: 0x14) Channel Status Register */
3933   __I  uint32_t US_RHR;         /**< (USART Offset: 0x18) Receive Holding Register */
3934   __O  uint32_t US_THR;         /**< (USART Offset: 0x1C) Transmit Holding Register */
3935   __IO uint32_t US_BRGR;        /**< (USART Offset: 0x20) Baud Rate Generator Register */
3936   __IO uint32_t US_RTOR;        /**< (USART Offset: 0x24) Receiver Timeout Register */
3937   __IO uint32_t US_TTGR;        /**< (USART Offset: 0x28) Transmitter Timeguard Register */
3938   __I  uint8_t  Reserved1[20];
3939   __IO uint32_t US_FIDI;        /**< (USART Offset: 0x40) FI DI Ratio Register */
3940   __I  uint32_t US_NER;         /**< (USART Offset: 0x44) Number of Errors Register */
3941   __I  uint8_t  Reserved2[4];
3942   __IO uint32_t US_IF;          /**< (USART Offset: 0x4C) IrDA Filter Register */
3943   __IO uint32_t US_MAN;         /**< (USART Offset: 0x50) Manchester Configuration Register */
3944   __IO uint32_t US_LINMR;       /**< (USART Offset: 0x54) LIN Mode Register */
3945   __IO uint32_t US_LINIR;       /**< (USART Offset: 0x58) LIN Identifier Register */
3946   __I  uint32_t US_LINBRR;      /**< (USART Offset: 0x5C) LIN Baud Rate Register */
3947   __I  uint8_t  Reserved3[132];
3948   __IO uint32_t US_WPMR;        /**< (USART Offset: 0xE4) Write Protection Mode Register */
3949   __I  uint32_t US_WPSR;        /**< (USART Offset: 0xE8) Write Protection Status Register */
3950   __I  uint8_t  Reserved4[16];
3951   __I  uint32_t US_VERSION;     /**< (USART Offset: 0xFC) Version Register */
3952 } Usart;
3953 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
3954 
3955 /*@}*/
3956 
3957 #endif /* _SAM4L_USART_COMPONENT_ */
3958