1 /** 2 * \file 3 * 4 * \brief Component description for TWIM 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TWIM_COMPONENT_ 30 #define _SAM4L_TWIM_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TWIM */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_TWIM Two-wire Master Interface */ 36 /*@{*/ 37 38 #define TWIM_I7535 39 #define REV_TWIM 0x120 40 41 /* -------- TWIM_CR : (TWIM Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t MEN:1; /*!< bit: 0 Master Enable */ 46 uint32_t MDIS:1; /*!< bit: 1 Master Disable */ 47 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 48 uint32_t SMEN:1; /*!< bit: 4 SMBus Enable */ 49 uint32_t SMDIS:1; /*!< bit: 5 SMBus Disable */ 50 uint32_t :1; /*!< bit: 6 Reserved */ 51 uint32_t SWRST:1; /*!< bit: 7 Software Reset */ 52 uint32_t STOP:1; /*!< bit: 8 Stop the current transfer */ 53 uint32_t :23; /*!< bit: 9..31 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 uint32_t reg; /*!< Type used for register access */ 56 } TWIM_CR_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define TWIM_CR_OFFSET 0x00 /**< \brief (TWIM_CR offset) Control Register */ 60 #define TWIM_CR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_CR reset_value) Control Register */ 61 62 #define TWIM_CR_MEN_Pos 0 /**< \brief (TWIM_CR) Master Enable */ 63 #define TWIM_CR_MEN (_U_(0x1) << TWIM_CR_MEN_Pos) 64 #define TWIM_CR_MDIS_Pos 1 /**< \brief (TWIM_CR) Master Disable */ 65 #define TWIM_CR_MDIS (_U_(0x1) << TWIM_CR_MDIS_Pos) 66 #define TWIM_CR_SMEN_Pos 4 /**< \brief (TWIM_CR) SMBus Enable */ 67 #define TWIM_CR_SMEN (_U_(0x1) << TWIM_CR_SMEN_Pos) 68 #define TWIM_CR_SMDIS_Pos 5 /**< \brief (TWIM_CR) SMBus Disable */ 69 #define TWIM_CR_SMDIS (_U_(0x1) << TWIM_CR_SMDIS_Pos) 70 #define TWIM_CR_SWRST_Pos 7 /**< \brief (TWIM_CR) Software Reset */ 71 #define TWIM_CR_SWRST (_U_(0x1) << TWIM_CR_SWRST_Pos) 72 #define TWIM_CR_STOP_Pos 8 /**< \brief (TWIM_CR) Stop the current transfer */ 73 #define TWIM_CR_STOP (_U_(0x1) << TWIM_CR_STOP_Pos) 74 #define TWIM_CR_MASK _U_(0x000001B3) /**< \brief (TWIM_CR) MASK Register */ 75 76 /* -------- TWIM_CWGR : (TWIM Offset: 0x04) (R/W 32) Clock Waveform Generator Register -------- */ 77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 78 typedef union { 79 struct { 80 uint32_t LOW:8; /*!< bit: 0.. 7 Clock Low Cycles */ 81 uint32_t HIGH:8; /*!< bit: 8..15 Clock High Cycles */ 82 uint32_t STASTO:8; /*!< bit: 16..23 START and STOP Cycles */ 83 uint32_t DATA:4; /*!< bit: 24..27 Data Setup and Hold Cycles */ 84 uint32_t EXP:3; /*!< bit: 28..30 Clock Prescaler */ 85 uint32_t :1; /*!< bit: 31 Reserved */ 86 } bit; /*!< Structure used for bit access */ 87 uint32_t reg; /*!< Type used for register access */ 88 } TWIM_CWGR_Type; 89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 91 #define TWIM_CWGR_OFFSET 0x04 /**< \brief (TWIM_CWGR offset) Clock Waveform Generator Register */ 92 #define TWIM_CWGR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_CWGR reset_value) Clock Waveform Generator Register */ 93 94 #define TWIM_CWGR_LOW_Pos 0 /**< \brief (TWIM_CWGR) Clock Low Cycles */ 95 #define TWIM_CWGR_LOW_Msk (_U_(0xFF) << TWIM_CWGR_LOW_Pos) 96 #define TWIM_CWGR_LOW(value) (TWIM_CWGR_LOW_Msk & ((value) << TWIM_CWGR_LOW_Pos)) 97 #define TWIM_CWGR_HIGH_Pos 8 /**< \brief (TWIM_CWGR) Clock High Cycles */ 98 #define TWIM_CWGR_HIGH_Msk (_U_(0xFF) << TWIM_CWGR_HIGH_Pos) 99 #define TWIM_CWGR_HIGH(value) (TWIM_CWGR_HIGH_Msk & ((value) << TWIM_CWGR_HIGH_Pos)) 100 #define TWIM_CWGR_STASTO_Pos 16 /**< \brief (TWIM_CWGR) START and STOP Cycles */ 101 #define TWIM_CWGR_STASTO_Msk (_U_(0xFF) << TWIM_CWGR_STASTO_Pos) 102 #define TWIM_CWGR_STASTO(value) (TWIM_CWGR_STASTO_Msk & ((value) << TWIM_CWGR_STASTO_Pos)) 103 #define TWIM_CWGR_DATA_Pos 24 /**< \brief (TWIM_CWGR) Data Setup and Hold Cycles */ 104 #define TWIM_CWGR_DATA_Msk (_U_(0xF) << TWIM_CWGR_DATA_Pos) 105 #define TWIM_CWGR_DATA(value) (TWIM_CWGR_DATA_Msk & ((value) << TWIM_CWGR_DATA_Pos)) 106 #define TWIM_CWGR_EXP_Pos 28 /**< \brief (TWIM_CWGR) Clock Prescaler */ 107 #define TWIM_CWGR_EXP_Msk (_U_(0x7) << TWIM_CWGR_EXP_Pos) 108 #define TWIM_CWGR_EXP(value) (TWIM_CWGR_EXP_Msk & ((value) << TWIM_CWGR_EXP_Pos)) 109 #define TWIM_CWGR_MASK _U_(0x7FFFFFFF) /**< \brief (TWIM_CWGR) MASK Register */ 110 111 /* -------- TWIM_SMBTR : (TWIM Offset: 0x08) (R/W 32) SMBus Timing Register -------- */ 112 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 113 typedef union { 114 struct { 115 uint32_t TLOWS:8; /*!< bit: 0.. 7 Slave Clock stretch maximum cycles */ 116 uint32_t TLOWM:8; /*!< bit: 8..15 Master Clock stretch maximum cycles */ 117 uint32_t THMAX:8; /*!< bit: 16..23 Clock High maximum cycles */ 118 uint32_t :4; /*!< bit: 24..27 Reserved */ 119 uint32_t EXP:4; /*!< bit: 28..31 SMBus Timeout Clock prescaler */ 120 } bit; /*!< Structure used for bit access */ 121 uint32_t reg; /*!< Type used for register access */ 122 } TWIM_SMBTR_Type; 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 124 125 #define TWIM_SMBTR_OFFSET 0x08 /**< \brief (TWIM_SMBTR offset) SMBus Timing Register */ 126 #define TWIM_SMBTR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_SMBTR reset_value) SMBus Timing Register */ 127 128 #define TWIM_SMBTR_TLOWS_Pos 0 /**< \brief (TWIM_SMBTR) Slave Clock stretch maximum cycles */ 129 #define TWIM_SMBTR_TLOWS_Msk (_U_(0xFF) << TWIM_SMBTR_TLOWS_Pos) 130 #define TWIM_SMBTR_TLOWS(value) (TWIM_SMBTR_TLOWS_Msk & ((value) << TWIM_SMBTR_TLOWS_Pos)) 131 #define TWIM_SMBTR_TLOWM_Pos 8 /**< \brief (TWIM_SMBTR) Master Clock stretch maximum cycles */ 132 #define TWIM_SMBTR_TLOWM_Msk (_U_(0xFF) << TWIM_SMBTR_TLOWM_Pos) 133 #define TWIM_SMBTR_TLOWM(value) (TWIM_SMBTR_TLOWM_Msk & ((value) << TWIM_SMBTR_TLOWM_Pos)) 134 #define TWIM_SMBTR_THMAX_Pos 16 /**< \brief (TWIM_SMBTR) Clock High maximum cycles */ 135 #define TWIM_SMBTR_THMAX_Msk (_U_(0xFF) << TWIM_SMBTR_THMAX_Pos) 136 #define TWIM_SMBTR_THMAX(value) (TWIM_SMBTR_THMAX_Msk & ((value) << TWIM_SMBTR_THMAX_Pos)) 137 #define TWIM_SMBTR_EXP_Pos 28 /**< \brief (TWIM_SMBTR) SMBus Timeout Clock prescaler */ 138 #define TWIM_SMBTR_EXP_Msk (_U_(0xF) << TWIM_SMBTR_EXP_Pos) 139 #define TWIM_SMBTR_EXP(value) (TWIM_SMBTR_EXP_Msk & ((value) << TWIM_SMBTR_EXP_Pos)) 140 #define TWIM_SMBTR_MASK _U_(0xF0FFFFFF) /**< \brief (TWIM_SMBTR) MASK Register */ 141 142 /* -------- TWIM_CMDR : (TWIM Offset: 0x0C) (R/W 32) Command Register -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint32_t READ:1; /*!< bit: 0 Transfer Direction */ 147 uint32_t SADR:10; /*!< bit: 1..10 Slave Address */ 148 uint32_t TENBIT:1; /*!< bit: 11 Ten Bit Addressing Mode */ 149 uint32_t REPSAME:1; /*!< bit: 12 Transfer is to same address as previous address */ 150 uint32_t START:1; /*!< bit: 13 Send START condition */ 151 uint32_t STOP:1; /*!< bit: 14 Send STOP condition */ 152 uint32_t VALID:1; /*!< bit: 15 CMDR Valid */ 153 uint32_t NBYTES:8; /*!< bit: 16..23 Number of data bytes in transfer */ 154 uint32_t PECEN:1; /*!< bit: 24 Packet Error Checking Enable */ 155 uint32_t ACKLAST:1; /*!< bit: 25 ACK Last Master RX Byte */ 156 uint32_t HS:1; /*!< bit: 26 HS-mode */ 157 uint32_t :1; /*!< bit: 27 Reserved */ 158 uint32_t HSMCODE:3; /*!< bit: 28..30 HS-mode Master Code */ 159 uint32_t :1; /*!< bit: 31 Reserved */ 160 } bit; /*!< Structure used for bit access */ 161 uint32_t reg; /*!< Type used for register access */ 162 } TWIM_CMDR_Type; 163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 164 165 #define TWIM_CMDR_OFFSET 0x0C /**< \brief (TWIM_CMDR offset) Command Register */ 166 #define TWIM_CMDR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_CMDR reset_value) Command Register */ 167 168 #define TWIM_CMDR_READ_Pos 0 /**< \brief (TWIM_CMDR) Transfer Direction */ 169 #define TWIM_CMDR_READ (_U_(0x1) << TWIM_CMDR_READ_Pos) 170 #define TWIM_CMDR_SADR_Pos 1 /**< \brief (TWIM_CMDR) Slave Address */ 171 #define TWIM_CMDR_SADR_Msk (_U_(0x3FF) << TWIM_CMDR_SADR_Pos) 172 #define TWIM_CMDR_SADR(value) (TWIM_CMDR_SADR_Msk & ((value) << TWIM_CMDR_SADR_Pos)) 173 #define TWIM_CMDR_TENBIT_Pos 11 /**< \brief (TWIM_CMDR) Ten Bit Addressing Mode */ 174 #define TWIM_CMDR_TENBIT (_U_(0x1) << TWIM_CMDR_TENBIT_Pos) 175 #define TWIM_CMDR_REPSAME_Pos 12 /**< \brief (TWIM_CMDR) Transfer is to same address as previous address */ 176 #define TWIM_CMDR_REPSAME (_U_(0x1) << TWIM_CMDR_REPSAME_Pos) 177 #define TWIM_CMDR_START_Pos 13 /**< \brief (TWIM_CMDR) Send START condition */ 178 #define TWIM_CMDR_START (_U_(0x1) << TWIM_CMDR_START_Pos) 179 #define TWIM_CMDR_STOP_Pos 14 /**< \brief (TWIM_CMDR) Send STOP condition */ 180 #define TWIM_CMDR_STOP (_U_(0x1) << TWIM_CMDR_STOP_Pos) 181 #define TWIM_CMDR_VALID_Pos 15 /**< \brief (TWIM_CMDR) CMDR Valid */ 182 #define TWIM_CMDR_VALID (_U_(0x1) << TWIM_CMDR_VALID_Pos) 183 #define TWIM_CMDR_NBYTES_Pos 16 /**< \brief (TWIM_CMDR) Number of data bytes in transfer */ 184 #define TWIM_CMDR_NBYTES_Msk (_U_(0xFF) << TWIM_CMDR_NBYTES_Pos) 185 #define TWIM_CMDR_NBYTES(value) (TWIM_CMDR_NBYTES_Msk & ((value) << TWIM_CMDR_NBYTES_Pos)) 186 #define TWIM_CMDR_PECEN_Pos 24 /**< \brief (TWIM_CMDR) Packet Error Checking Enable */ 187 #define TWIM_CMDR_PECEN (_U_(0x1) << TWIM_CMDR_PECEN_Pos) 188 #define TWIM_CMDR_ACKLAST_Pos 25 /**< \brief (TWIM_CMDR) ACK Last Master RX Byte */ 189 #define TWIM_CMDR_ACKLAST (_U_(0x1) << TWIM_CMDR_ACKLAST_Pos) 190 #define TWIM_CMDR_HS_Pos 26 /**< \brief (TWIM_CMDR) HS-mode */ 191 #define TWIM_CMDR_HS (_U_(0x1) << TWIM_CMDR_HS_Pos) 192 #define TWIM_CMDR_HSMCODE_Pos 28 /**< \brief (TWIM_CMDR) HS-mode Master Code */ 193 #define TWIM_CMDR_HSMCODE_Msk (_U_(0x7) << TWIM_CMDR_HSMCODE_Pos) 194 #define TWIM_CMDR_HSMCODE(value) (TWIM_CMDR_HSMCODE_Msk & ((value) << TWIM_CMDR_HSMCODE_Pos)) 195 #define TWIM_CMDR_MASK _U_(0x77FFFFFF) /**< \brief (TWIM_CMDR) MASK Register */ 196 197 /* -------- TWIM_NCMDR : (TWIM Offset: 0x10) (R/W 32) Next Command Register -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint32_t READ:1; /*!< bit: 0 Transfer Direction */ 202 uint32_t SADR:10; /*!< bit: 1..10 Slave Address */ 203 uint32_t TENBIT:1; /*!< bit: 11 Ten Bit Addressing Mode */ 204 uint32_t REPSAME:1; /*!< bit: 12 Transfer is to same address as previous address */ 205 uint32_t START:1; /*!< bit: 13 Send START condition */ 206 uint32_t STOP:1; /*!< bit: 14 Send STOP condition */ 207 uint32_t VALID:1; /*!< bit: 15 CMDR Valid */ 208 uint32_t NBYTES:8; /*!< bit: 16..23 Number of data bytes in transfer */ 209 uint32_t PECEN:1; /*!< bit: 24 Packet Error Checking Enable */ 210 uint32_t ACKLAST:1; /*!< bit: 25 ACK Last Master RX Byte */ 211 uint32_t HS:1; /*!< bit: 26 HS-mode */ 212 uint32_t :1; /*!< bit: 27 Reserved */ 213 uint32_t HSMCODE:3; /*!< bit: 28..30 HS-mode Master Code */ 214 uint32_t :1; /*!< bit: 31 Reserved */ 215 } bit; /*!< Structure used for bit access */ 216 uint32_t reg; /*!< Type used for register access */ 217 } TWIM_NCMDR_Type; 218 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 219 220 #define TWIM_NCMDR_OFFSET 0x10 /**< \brief (TWIM_NCMDR offset) Next Command Register */ 221 #define TWIM_NCMDR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_NCMDR reset_value) Next Command Register */ 222 223 #define TWIM_NCMDR_READ_Pos 0 /**< \brief (TWIM_NCMDR) Transfer Direction */ 224 #define TWIM_NCMDR_READ (_U_(0x1) << TWIM_NCMDR_READ_Pos) 225 #define TWIM_NCMDR_SADR_Pos 1 /**< \brief (TWIM_NCMDR) Slave Address */ 226 #define TWIM_NCMDR_SADR_Msk (_U_(0x3FF) << TWIM_NCMDR_SADR_Pos) 227 #define TWIM_NCMDR_SADR(value) (TWIM_NCMDR_SADR_Msk & ((value) << TWIM_NCMDR_SADR_Pos)) 228 #define TWIM_NCMDR_TENBIT_Pos 11 /**< \brief (TWIM_NCMDR) Ten Bit Addressing Mode */ 229 #define TWIM_NCMDR_TENBIT (_U_(0x1) << TWIM_NCMDR_TENBIT_Pos) 230 #define TWIM_NCMDR_REPSAME_Pos 12 /**< \brief (TWIM_NCMDR) Transfer is to same address as previous address */ 231 #define TWIM_NCMDR_REPSAME (_U_(0x1) << TWIM_NCMDR_REPSAME_Pos) 232 #define TWIM_NCMDR_START_Pos 13 /**< \brief (TWIM_NCMDR) Send START condition */ 233 #define TWIM_NCMDR_START (_U_(0x1) << TWIM_NCMDR_START_Pos) 234 #define TWIM_NCMDR_STOP_Pos 14 /**< \brief (TWIM_NCMDR) Send STOP condition */ 235 #define TWIM_NCMDR_STOP (_U_(0x1) << TWIM_NCMDR_STOP_Pos) 236 #define TWIM_NCMDR_VALID_Pos 15 /**< \brief (TWIM_NCMDR) CMDR Valid */ 237 #define TWIM_NCMDR_VALID (_U_(0x1) << TWIM_NCMDR_VALID_Pos) 238 #define TWIM_NCMDR_NBYTES_Pos 16 /**< \brief (TWIM_NCMDR) Number of data bytes in transfer */ 239 #define TWIM_NCMDR_NBYTES_Msk (_U_(0xFF) << TWIM_NCMDR_NBYTES_Pos) 240 #define TWIM_NCMDR_NBYTES(value) (TWIM_NCMDR_NBYTES_Msk & ((value) << TWIM_NCMDR_NBYTES_Pos)) 241 #define TWIM_NCMDR_PECEN_Pos 24 /**< \brief (TWIM_NCMDR) Packet Error Checking Enable */ 242 #define TWIM_NCMDR_PECEN (_U_(0x1) << TWIM_NCMDR_PECEN_Pos) 243 #define TWIM_NCMDR_ACKLAST_Pos 25 /**< \brief (TWIM_NCMDR) ACK Last Master RX Byte */ 244 #define TWIM_NCMDR_ACKLAST (_U_(0x1) << TWIM_NCMDR_ACKLAST_Pos) 245 #define TWIM_NCMDR_HS_Pos 26 /**< \brief (TWIM_NCMDR) HS-mode */ 246 #define TWIM_NCMDR_HS (_U_(0x1) << TWIM_NCMDR_HS_Pos) 247 #define TWIM_NCMDR_HSMCODE_Pos 28 /**< \brief (TWIM_NCMDR) HS-mode Master Code */ 248 #define TWIM_NCMDR_HSMCODE_Msk (_U_(0x7) << TWIM_NCMDR_HSMCODE_Pos) 249 #define TWIM_NCMDR_HSMCODE(value) (TWIM_NCMDR_HSMCODE_Msk & ((value) << TWIM_NCMDR_HSMCODE_Pos)) 250 #define TWIM_NCMDR_MASK _U_(0x77FFFFFF) /**< \brief (TWIM_NCMDR) MASK Register */ 251 252 /* -------- TWIM_RHR : (TWIM Offset: 0x14) (R/ 32) Receive Holding Register -------- */ 253 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 254 typedef union { 255 struct { 256 uint32_t RXDATA:8; /*!< bit: 0.. 7 Received Data */ 257 uint32_t :24; /*!< bit: 8..31 Reserved */ 258 } bit; /*!< Structure used for bit access */ 259 uint32_t reg; /*!< Type used for register access */ 260 } TWIM_RHR_Type; 261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 262 263 #define TWIM_RHR_OFFSET 0x14 /**< \brief (TWIM_RHR offset) Receive Holding Register */ 264 #define TWIM_RHR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_RHR reset_value) Receive Holding Register */ 265 266 #define TWIM_RHR_RXDATA_Pos 0 /**< \brief (TWIM_RHR) Received Data */ 267 #define TWIM_RHR_RXDATA_Msk (_U_(0xFF) << TWIM_RHR_RXDATA_Pos) 268 #define TWIM_RHR_RXDATA(value) (TWIM_RHR_RXDATA_Msk & ((value) << TWIM_RHR_RXDATA_Pos)) 269 #define TWIM_RHR_MASK _U_(0x000000FF) /**< \brief (TWIM_RHR) MASK Register */ 270 271 /* -------- TWIM_THR : (TWIM Offset: 0x18) ( /W 32) Transmit Holding Register -------- */ 272 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 273 typedef union { 274 struct { 275 uint32_t TXDATA:8; /*!< bit: 0.. 7 Data to Transmit */ 276 uint32_t :24; /*!< bit: 8..31 Reserved */ 277 } bit; /*!< Structure used for bit access */ 278 uint32_t reg; /*!< Type used for register access */ 279 } TWIM_THR_Type; 280 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 #define TWIM_THR_OFFSET 0x18 /**< \brief (TWIM_THR offset) Transmit Holding Register */ 283 #define TWIM_THR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_THR reset_value) Transmit Holding Register */ 284 285 #define TWIM_THR_TXDATA_Pos 0 /**< \brief (TWIM_THR) Data to Transmit */ 286 #define TWIM_THR_TXDATA_Msk (_U_(0xFF) << TWIM_THR_TXDATA_Pos) 287 #define TWIM_THR_TXDATA(value) (TWIM_THR_TXDATA_Msk & ((value) << TWIM_THR_TXDATA_Pos)) 288 #define TWIM_THR_MASK _U_(0x000000FF) /**< \brief (TWIM_THR) MASK Register */ 289 290 /* -------- TWIM_SR : (TWIM Offset: 0x1C) (R/ 32) Status Register -------- */ 291 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 292 typedef union { 293 struct { 294 uint32_t RXRDY:1; /*!< bit: 0 RHR Data Ready */ 295 uint32_t TXRDY:1; /*!< bit: 1 THR Data Ready */ 296 uint32_t CRDY:1; /*!< bit: 2 Ready for More Commands */ 297 uint32_t CCOMP:1; /*!< bit: 3 Command Complete */ 298 uint32_t IDLE:1; /*!< bit: 4 Master Interface is Idle */ 299 uint32_t BUSFREE:1; /*!< bit: 5 Two-wire Bus is Free */ 300 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 301 uint32_t ANAK:1; /*!< bit: 8 NAK in Address Phase Received */ 302 uint32_t DNAK:1; /*!< bit: 9 NAK in Data Phase Received */ 303 uint32_t ARBLST:1; /*!< bit: 10 Arbitration Lost */ 304 uint32_t SMBALERT:1; /*!< bit: 11 SMBus Alert */ 305 uint32_t TOUT:1; /*!< bit: 12 Timeout */ 306 uint32_t PECERR:1; /*!< bit: 13 PEC Error */ 307 uint32_t STOP:1; /*!< bit: 14 Stop Request Accepted */ 308 uint32_t :1; /*!< bit: 15 Reserved */ 309 uint32_t MENB:1; /*!< bit: 16 Master Interface Enable */ 310 uint32_t HSMCACK:1; /*!< bit: 17 ACK in HS-mode Master Code Phase Received */ 311 uint32_t :14; /*!< bit: 18..31 Reserved */ 312 } bit; /*!< Structure used for bit access */ 313 uint32_t reg; /*!< Type used for register access */ 314 } TWIM_SR_Type; 315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 316 317 #define TWIM_SR_OFFSET 0x1C /**< \brief (TWIM_SR offset) Status Register */ 318 #define TWIM_SR_RESETVALUE _U_(0x00000002); /**< \brief (TWIM_SR reset_value) Status Register */ 319 320 #define TWIM_SR_RXRDY_Pos 0 /**< \brief (TWIM_SR) RHR Data Ready */ 321 #define TWIM_SR_RXRDY (_U_(0x1) << TWIM_SR_RXRDY_Pos) 322 #define TWIM_SR_TXRDY_Pos 1 /**< \brief (TWIM_SR) THR Data Ready */ 323 #define TWIM_SR_TXRDY (_U_(0x1) << TWIM_SR_TXRDY_Pos) 324 #define TWIM_SR_CRDY_Pos 2 /**< \brief (TWIM_SR) Ready for More Commands */ 325 #define TWIM_SR_CRDY (_U_(0x1) << TWIM_SR_CRDY_Pos) 326 #define TWIM_SR_CCOMP_Pos 3 /**< \brief (TWIM_SR) Command Complete */ 327 #define TWIM_SR_CCOMP (_U_(0x1) << TWIM_SR_CCOMP_Pos) 328 #define TWIM_SR_IDLE_Pos 4 /**< \brief (TWIM_SR) Master Interface is Idle */ 329 #define TWIM_SR_IDLE (_U_(0x1) << TWIM_SR_IDLE_Pos) 330 #define TWIM_SR_BUSFREE_Pos 5 /**< \brief (TWIM_SR) Two-wire Bus is Free */ 331 #define TWIM_SR_BUSFREE (_U_(0x1) << TWIM_SR_BUSFREE_Pos) 332 #define TWIM_SR_ANAK_Pos 8 /**< \brief (TWIM_SR) NAK in Address Phase Received */ 333 #define TWIM_SR_ANAK (_U_(0x1) << TWIM_SR_ANAK_Pos) 334 #define TWIM_SR_DNAK_Pos 9 /**< \brief (TWIM_SR) NAK in Data Phase Received */ 335 #define TWIM_SR_DNAK (_U_(0x1) << TWIM_SR_DNAK_Pos) 336 #define TWIM_SR_ARBLST_Pos 10 /**< \brief (TWIM_SR) Arbitration Lost */ 337 #define TWIM_SR_ARBLST (_U_(0x1) << TWIM_SR_ARBLST_Pos) 338 #define TWIM_SR_SMBALERT_Pos 11 /**< \brief (TWIM_SR) SMBus Alert */ 339 #define TWIM_SR_SMBALERT (_U_(0x1) << TWIM_SR_SMBALERT_Pos) 340 #define TWIM_SR_TOUT_Pos 12 /**< \brief (TWIM_SR) Timeout */ 341 #define TWIM_SR_TOUT (_U_(0x1) << TWIM_SR_TOUT_Pos) 342 #define TWIM_SR_PECERR_Pos 13 /**< \brief (TWIM_SR) PEC Error */ 343 #define TWIM_SR_PECERR (_U_(0x1) << TWIM_SR_PECERR_Pos) 344 #define TWIM_SR_STOP_Pos 14 /**< \brief (TWIM_SR) Stop Request Accepted */ 345 #define TWIM_SR_STOP (_U_(0x1) << TWIM_SR_STOP_Pos) 346 #define TWIM_SR_MENB_Pos 16 /**< \brief (TWIM_SR) Master Interface Enable */ 347 #define TWIM_SR_MENB (_U_(0x1) << TWIM_SR_MENB_Pos) 348 #define TWIM_SR_HSMCACK_Pos 17 /**< \brief (TWIM_SR) ACK in HS-mode Master Code Phase Received */ 349 #define TWIM_SR_HSMCACK (_U_(0x1) << TWIM_SR_HSMCACK_Pos) 350 #define TWIM_SR_MASK _U_(0x00037F3F) /**< \brief (TWIM_SR) MASK Register */ 351 352 /* -------- TWIM_IER : (TWIM Offset: 0x20) ( /W 32) Interrupt Enable Register -------- */ 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 typedef union { 355 struct { 356 uint32_t RXRDY:1; /*!< bit: 0 RHR Data Ready */ 357 uint32_t TXRDY:1; /*!< bit: 1 THR Data Ready */ 358 uint32_t CRDY:1; /*!< bit: 2 Ready for More Commands */ 359 uint32_t CCOMP:1; /*!< bit: 3 Command Complete */ 360 uint32_t IDLE:1; /*!< bit: 4 Master Interface is Idle */ 361 uint32_t BUSFREE:1; /*!< bit: 5 Two-wire Bus is Free */ 362 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 363 uint32_t ANAK:1; /*!< bit: 8 NAK in Address Phase Received */ 364 uint32_t DNAK:1; /*!< bit: 9 NAK in Data Phase Received */ 365 uint32_t ARBLST:1; /*!< bit: 10 Arbitration Lost */ 366 uint32_t SMBALERT:1; /*!< bit: 11 SMBus Alert */ 367 uint32_t TOUT:1; /*!< bit: 12 Timeout */ 368 uint32_t PECERR:1; /*!< bit: 13 PEC Error */ 369 uint32_t STOP:1; /*!< bit: 14 Stop Request Accepted */ 370 uint32_t :2; /*!< bit: 15..16 Reserved */ 371 uint32_t HSMCACK:1; /*!< bit: 17 ACK in HS-mode Master Code Phase Received */ 372 uint32_t :14; /*!< bit: 18..31 Reserved */ 373 } bit; /*!< Structure used for bit access */ 374 uint32_t reg; /*!< Type used for register access */ 375 } TWIM_IER_Type; 376 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 377 378 #define TWIM_IER_OFFSET 0x20 /**< \brief (TWIM_IER offset) Interrupt Enable Register */ 379 #define TWIM_IER_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_IER reset_value) Interrupt Enable Register */ 380 381 #define TWIM_IER_RXRDY_Pos 0 /**< \brief (TWIM_IER) RHR Data Ready */ 382 #define TWIM_IER_RXRDY (_U_(0x1) << TWIM_IER_RXRDY_Pos) 383 #define TWIM_IER_TXRDY_Pos 1 /**< \brief (TWIM_IER) THR Data Ready */ 384 #define TWIM_IER_TXRDY (_U_(0x1) << TWIM_IER_TXRDY_Pos) 385 #define TWIM_IER_CRDY_Pos 2 /**< \brief (TWIM_IER) Ready for More Commands */ 386 #define TWIM_IER_CRDY (_U_(0x1) << TWIM_IER_CRDY_Pos) 387 #define TWIM_IER_CCOMP_Pos 3 /**< \brief (TWIM_IER) Command Complete */ 388 #define TWIM_IER_CCOMP (_U_(0x1) << TWIM_IER_CCOMP_Pos) 389 #define TWIM_IER_IDLE_Pos 4 /**< \brief (TWIM_IER) Master Interface is Idle */ 390 #define TWIM_IER_IDLE (_U_(0x1) << TWIM_IER_IDLE_Pos) 391 #define TWIM_IER_BUSFREE_Pos 5 /**< \brief (TWIM_IER) Two-wire Bus is Free */ 392 #define TWIM_IER_BUSFREE (_U_(0x1) << TWIM_IER_BUSFREE_Pos) 393 #define TWIM_IER_ANAK_Pos 8 /**< \brief (TWIM_IER) NAK in Address Phase Received */ 394 #define TWIM_IER_ANAK (_U_(0x1) << TWIM_IER_ANAK_Pos) 395 #define TWIM_IER_DNAK_Pos 9 /**< \brief (TWIM_IER) NAK in Data Phase Received */ 396 #define TWIM_IER_DNAK (_U_(0x1) << TWIM_IER_DNAK_Pos) 397 #define TWIM_IER_ARBLST_Pos 10 /**< \brief (TWIM_IER) Arbitration Lost */ 398 #define TWIM_IER_ARBLST (_U_(0x1) << TWIM_IER_ARBLST_Pos) 399 #define TWIM_IER_SMBALERT_Pos 11 /**< \brief (TWIM_IER) SMBus Alert */ 400 #define TWIM_IER_SMBALERT (_U_(0x1) << TWIM_IER_SMBALERT_Pos) 401 #define TWIM_IER_TOUT_Pos 12 /**< \brief (TWIM_IER) Timeout */ 402 #define TWIM_IER_TOUT (_U_(0x1) << TWIM_IER_TOUT_Pos) 403 #define TWIM_IER_PECERR_Pos 13 /**< \brief (TWIM_IER) PEC Error */ 404 #define TWIM_IER_PECERR (_U_(0x1) << TWIM_IER_PECERR_Pos) 405 #define TWIM_IER_STOP_Pos 14 /**< \brief (TWIM_IER) Stop Request Accepted */ 406 #define TWIM_IER_STOP (_U_(0x1) << TWIM_IER_STOP_Pos) 407 #define TWIM_IER_HSMCACK_Pos 17 /**< \brief (TWIM_IER) ACK in HS-mode Master Code Phase Received */ 408 #define TWIM_IER_HSMCACK (_U_(0x1) << TWIM_IER_HSMCACK_Pos) 409 #define TWIM_IER_MASK _U_(0x00027F3F) /**< \brief (TWIM_IER) MASK Register */ 410 411 /* -------- TWIM_IDR : (TWIM Offset: 0x24) ( /W 32) Interrupt Disable Register -------- */ 412 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 413 typedef union { 414 struct { 415 uint32_t RXRDY:1; /*!< bit: 0 RHR Data Ready */ 416 uint32_t TXRDY:1; /*!< bit: 1 THR Data Ready */ 417 uint32_t CRDY:1; /*!< bit: 2 Ready for More Commands */ 418 uint32_t CCOMP:1; /*!< bit: 3 Command Complete */ 419 uint32_t IDLE:1; /*!< bit: 4 Master Interface is Idle */ 420 uint32_t BUSFREE:1; /*!< bit: 5 Two-wire Bus is Free */ 421 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 422 uint32_t ANAK:1; /*!< bit: 8 NAK in Address Phase Received */ 423 uint32_t DNAK:1; /*!< bit: 9 NAK in Data Phase Received */ 424 uint32_t ARBLST:1; /*!< bit: 10 Arbitration Lost */ 425 uint32_t SMBALERT:1; /*!< bit: 11 SMBus Alert */ 426 uint32_t TOUT:1; /*!< bit: 12 Timeout */ 427 uint32_t PECERR:1; /*!< bit: 13 PEC Error */ 428 uint32_t STOP:1; /*!< bit: 14 Stop Request Accepted */ 429 uint32_t :2; /*!< bit: 15..16 Reserved */ 430 uint32_t HSMCACK:1; /*!< bit: 17 ACK in HS-mode Master Code Phase Received */ 431 uint32_t :14; /*!< bit: 18..31 Reserved */ 432 } bit; /*!< Structure used for bit access */ 433 uint32_t reg; /*!< Type used for register access */ 434 } TWIM_IDR_Type; 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define TWIM_IDR_OFFSET 0x24 /**< \brief (TWIM_IDR offset) Interrupt Disable Register */ 438 #define TWIM_IDR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_IDR reset_value) Interrupt Disable Register */ 439 440 #define TWIM_IDR_RXRDY_Pos 0 /**< \brief (TWIM_IDR) RHR Data Ready */ 441 #define TWIM_IDR_RXRDY (_U_(0x1) << TWIM_IDR_RXRDY_Pos) 442 #define TWIM_IDR_TXRDY_Pos 1 /**< \brief (TWIM_IDR) THR Data Ready */ 443 #define TWIM_IDR_TXRDY (_U_(0x1) << TWIM_IDR_TXRDY_Pos) 444 #define TWIM_IDR_CRDY_Pos 2 /**< \brief (TWIM_IDR) Ready for More Commands */ 445 #define TWIM_IDR_CRDY (_U_(0x1) << TWIM_IDR_CRDY_Pos) 446 #define TWIM_IDR_CCOMP_Pos 3 /**< \brief (TWIM_IDR) Command Complete */ 447 #define TWIM_IDR_CCOMP (_U_(0x1) << TWIM_IDR_CCOMP_Pos) 448 #define TWIM_IDR_IDLE_Pos 4 /**< \brief (TWIM_IDR) Master Interface is Idle */ 449 #define TWIM_IDR_IDLE (_U_(0x1) << TWIM_IDR_IDLE_Pos) 450 #define TWIM_IDR_BUSFREE_Pos 5 /**< \brief (TWIM_IDR) Two-wire Bus is Free */ 451 #define TWIM_IDR_BUSFREE (_U_(0x1) << TWIM_IDR_BUSFREE_Pos) 452 #define TWIM_IDR_ANAK_Pos 8 /**< \brief (TWIM_IDR) NAK in Address Phase Received */ 453 #define TWIM_IDR_ANAK (_U_(0x1) << TWIM_IDR_ANAK_Pos) 454 #define TWIM_IDR_DNAK_Pos 9 /**< \brief (TWIM_IDR) NAK in Data Phase Received */ 455 #define TWIM_IDR_DNAK (_U_(0x1) << TWIM_IDR_DNAK_Pos) 456 #define TWIM_IDR_ARBLST_Pos 10 /**< \brief (TWIM_IDR) Arbitration Lost */ 457 #define TWIM_IDR_ARBLST (_U_(0x1) << TWIM_IDR_ARBLST_Pos) 458 #define TWIM_IDR_SMBALERT_Pos 11 /**< \brief (TWIM_IDR) SMBus Alert */ 459 #define TWIM_IDR_SMBALERT (_U_(0x1) << TWIM_IDR_SMBALERT_Pos) 460 #define TWIM_IDR_TOUT_Pos 12 /**< \brief (TWIM_IDR) Timeout */ 461 #define TWIM_IDR_TOUT (_U_(0x1) << TWIM_IDR_TOUT_Pos) 462 #define TWIM_IDR_PECERR_Pos 13 /**< \brief (TWIM_IDR) PEC Error */ 463 #define TWIM_IDR_PECERR (_U_(0x1) << TWIM_IDR_PECERR_Pos) 464 #define TWIM_IDR_STOP_Pos 14 /**< \brief (TWIM_IDR) Stop Request Accepted */ 465 #define TWIM_IDR_STOP (_U_(0x1) << TWIM_IDR_STOP_Pos) 466 #define TWIM_IDR_HSMCACK_Pos 17 /**< \brief (TWIM_IDR) ACK in HS-mode Master Code Phase Received */ 467 #define TWIM_IDR_HSMCACK (_U_(0x1) << TWIM_IDR_HSMCACK_Pos) 468 #define TWIM_IDR_MASK _U_(0x00027F3F) /**< \brief (TWIM_IDR) MASK Register */ 469 470 /* -------- TWIM_IMR : (TWIM Offset: 0x28) (R/ 32) Interrupt Mask Register -------- */ 471 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 472 typedef union { 473 struct { 474 uint32_t RXRDY:1; /*!< bit: 0 RHR Data Ready */ 475 uint32_t TXRDY:1; /*!< bit: 1 THR Data Ready */ 476 uint32_t CRDY:1; /*!< bit: 2 Ready for More Commands */ 477 uint32_t CCOMP:1; /*!< bit: 3 Command Complete */ 478 uint32_t IDLE:1; /*!< bit: 4 Master Interface is Idle */ 479 uint32_t BUSFREE:1; /*!< bit: 5 Two-wire Bus is Free */ 480 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 481 uint32_t ANAK:1; /*!< bit: 8 NAK in Address Phase Received */ 482 uint32_t DNAK:1; /*!< bit: 9 NAK in Data Phase Received */ 483 uint32_t ARBLST:1; /*!< bit: 10 Arbitration Lost */ 484 uint32_t SMBALERT:1; /*!< bit: 11 SMBus Alert */ 485 uint32_t TOUT:1; /*!< bit: 12 Timeout */ 486 uint32_t PECERR:1; /*!< bit: 13 PEC Error */ 487 uint32_t STOP:1; /*!< bit: 14 Stop Request Accepted */ 488 uint32_t :2; /*!< bit: 15..16 Reserved */ 489 uint32_t HSMCACK:1; /*!< bit: 17 ACK in HS-mode Master Code Phase Received */ 490 uint32_t :14; /*!< bit: 18..31 Reserved */ 491 } bit; /*!< Structure used for bit access */ 492 uint32_t reg; /*!< Type used for register access */ 493 } TWIM_IMR_Type; 494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 495 496 #define TWIM_IMR_OFFSET 0x28 /**< \brief (TWIM_IMR offset) Interrupt Mask Register */ 497 #define TWIM_IMR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_IMR reset_value) Interrupt Mask Register */ 498 499 #define TWIM_IMR_RXRDY_Pos 0 /**< \brief (TWIM_IMR) RHR Data Ready */ 500 #define TWIM_IMR_RXRDY (_U_(0x1) << TWIM_IMR_RXRDY_Pos) 501 #define TWIM_IMR_TXRDY_Pos 1 /**< \brief (TWIM_IMR) THR Data Ready */ 502 #define TWIM_IMR_TXRDY (_U_(0x1) << TWIM_IMR_TXRDY_Pos) 503 #define TWIM_IMR_CRDY_Pos 2 /**< \brief (TWIM_IMR) Ready for More Commands */ 504 #define TWIM_IMR_CRDY (_U_(0x1) << TWIM_IMR_CRDY_Pos) 505 #define TWIM_IMR_CCOMP_Pos 3 /**< \brief (TWIM_IMR) Command Complete */ 506 #define TWIM_IMR_CCOMP (_U_(0x1) << TWIM_IMR_CCOMP_Pos) 507 #define TWIM_IMR_IDLE_Pos 4 /**< \brief (TWIM_IMR) Master Interface is Idle */ 508 #define TWIM_IMR_IDLE (_U_(0x1) << TWIM_IMR_IDLE_Pos) 509 #define TWIM_IMR_BUSFREE_Pos 5 /**< \brief (TWIM_IMR) Two-wire Bus is Free */ 510 #define TWIM_IMR_BUSFREE (_U_(0x1) << TWIM_IMR_BUSFREE_Pos) 511 #define TWIM_IMR_ANAK_Pos 8 /**< \brief (TWIM_IMR) NAK in Address Phase Received */ 512 #define TWIM_IMR_ANAK (_U_(0x1) << TWIM_IMR_ANAK_Pos) 513 #define TWIM_IMR_DNAK_Pos 9 /**< \brief (TWIM_IMR) NAK in Data Phase Received */ 514 #define TWIM_IMR_DNAK (_U_(0x1) << TWIM_IMR_DNAK_Pos) 515 #define TWIM_IMR_ARBLST_Pos 10 /**< \brief (TWIM_IMR) Arbitration Lost */ 516 #define TWIM_IMR_ARBLST (_U_(0x1) << TWIM_IMR_ARBLST_Pos) 517 #define TWIM_IMR_SMBALERT_Pos 11 /**< \brief (TWIM_IMR) SMBus Alert */ 518 #define TWIM_IMR_SMBALERT (_U_(0x1) << TWIM_IMR_SMBALERT_Pos) 519 #define TWIM_IMR_TOUT_Pos 12 /**< \brief (TWIM_IMR) Timeout */ 520 #define TWIM_IMR_TOUT (_U_(0x1) << TWIM_IMR_TOUT_Pos) 521 #define TWIM_IMR_PECERR_Pos 13 /**< \brief (TWIM_IMR) PEC Error */ 522 #define TWIM_IMR_PECERR (_U_(0x1) << TWIM_IMR_PECERR_Pos) 523 #define TWIM_IMR_STOP_Pos 14 /**< \brief (TWIM_IMR) Stop Request Accepted */ 524 #define TWIM_IMR_STOP (_U_(0x1) << TWIM_IMR_STOP_Pos) 525 #define TWIM_IMR_HSMCACK_Pos 17 /**< \brief (TWIM_IMR) ACK in HS-mode Master Code Phase Received */ 526 #define TWIM_IMR_HSMCACK (_U_(0x1) << TWIM_IMR_HSMCACK_Pos) 527 #define TWIM_IMR_MASK _U_(0x00027F3F) /**< \brief (TWIM_IMR) MASK Register */ 528 529 /* -------- TWIM_SCR : (TWIM Offset: 0x2C) ( /W 32) Status Clear Register -------- */ 530 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 531 typedef union { 532 struct { 533 uint32_t :3; /*!< bit: 0.. 2 Reserved */ 534 uint32_t CCOMP:1; /*!< bit: 3 Command Complete */ 535 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 536 uint32_t ANAK:1; /*!< bit: 8 NAK in Address Phase Received */ 537 uint32_t DNAK:1; /*!< bit: 9 NAK in Data Phase Received */ 538 uint32_t ARBLST:1; /*!< bit: 10 Arbitration Lost */ 539 uint32_t SMBALERT:1; /*!< bit: 11 SMBus Alert */ 540 uint32_t TOUT:1; /*!< bit: 12 Timeout */ 541 uint32_t PECERR:1; /*!< bit: 13 PEC Error */ 542 uint32_t STOP:1; /*!< bit: 14 Stop Request Accepted */ 543 uint32_t :2; /*!< bit: 15..16 Reserved */ 544 uint32_t HSMCACK:1; /*!< bit: 17 ACK in HS-mode Master Code Phase Received */ 545 uint32_t :14; /*!< bit: 18..31 Reserved */ 546 } bit; /*!< Structure used for bit access */ 547 uint32_t reg; /*!< Type used for register access */ 548 } TWIM_SCR_Type; 549 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 550 551 #define TWIM_SCR_OFFSET 0x2C /**< \brief (TWIM_SCR offset) Status Clear Register */ 552 #define TWIM_SCR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_SCR reset_value) Status Clear Register */ 553 554 #define TWIM_SCR_CCOMP_Pos 3 /**< \brief (TWIM_SCR) Command Complete */ 555 #define TWIM_SCR_CCOMP (_U_(0x1) << TWIM_SCR_CCOMP_Pos) 556 #define TWIM_SCR_ANAK_Pos 8 /**< \brief (TWIM_SCR) NAK in Address Phase Received */ 557 #define TWIM_SCR_ANAK (_U_(0x1) << TWIM_SCR_ANAK_Pos) 558 #define TWIM_SCR_DNAK_Pos 9 /**< \brief (TWIM_SCR) NAK in Data Phase Received */ 559 #define TWIM_SCR_DNAK (_U_(0x1) << TWIM_SCR_DNAK_Pos) 560 #define TWIM_SCR_ARBLST_Pos 10 /**< \brief (TWIM_SCR) Arbitration Lost */ 561 #define TWIM_SCR_ARBLST (_U_(0x1) << TWIM_SCR_ARBLST_Pos) 562 #define TWIM_SCR_SMBALERT_Pos 11 /**< \brief (TWIM_SCR) SMBus Alert */ 563 #define TWIM_SCR_SMBALERT (_U_(0x1) << TWIM_SCR_SMBALERT_Pos) 564 #define TWIM_SCR_TOUT_Pos 12 /**< \brief (TWIM_SCR) Timeout */ 565 #define TWIM_SCR_TOUT (_U_(0x1) << TWIM_SCR_TOUT_Pos) 566 #define TWIM_SCR_PECERR_Pos 13 /**< \brief (TWIM_SCR) PEC Error */ 567 #define TWIM_SCR_PECERR (_U_(0x1) << TWIM_SCR_PECERR_Pos) 568 #define TWIM_SCR_STOP_Pos 14 /**< \brief (TWIM_SCR) Stop Request Accepted */ 569 #define TWIM_SCR_STOP (_U_(0x1) << TWIM_SCR_STOP_Pos) 570 #define TWIM_SCR_HSMCACK_Pos 17 /**< \brief (TWIM_SCR) ACK in HS-mode Master Code Phase Received */ 571 #define TWIM_SCR_HSMCACK (_U_(0x1) << TWIM_SCR_HSMCACK_Pos) 572 #define TWIM_SCR_MASK _U_(0x00027F08) /**< \brief (TWIM_SCR) MASK Register */ 573 574 /* -------- TWIM_PR : (TWIM Offset: 0x30) (R/ 32) Parameter Register -------- */ 575 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 576 typedef union { 577 struct { 578 uint32_t HS:1; /*!< bit: 0 HS-mode */ 579 uint32_t :31; /*!< bit: 1..31 Reserved */ 580 } bit; /*!< Structure used for bit access */ 581 uint32_t reg; /*!< Type used for register access */ 582 } TWIM_PR_Type; 583 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 584 585 #define TWIM_PR_OFFSET 0x30 /**< \brief (TWIM_PR offset) Parameter Register */ 586 #define TWIM_PR_RESETVALUE _U_(0x00000001); /**< \brief (TWIM_PR reset_value) Parameter Register */ 587 588 #define TWIM_PR_HS_Pos 0 /**< \brief (TWIM_PR) HS-mode */ 589 #define TWIM_PR_HS (_U_(0x1) << TWIM_PR_HS_Pos) 590 #define TWIM_PR_MASK _U_(0x00000001) /**< \brief (TWIM_PR) MASK Register */ 591 592 /* -------- TWIM_VR : (TWIM Offset: 0x34) (R/ 32) Version Register -------- */ 593 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 594 typedef union { 595 struct { 596 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 597 uint32_t :4; /*!< bit: 12..15 Reserved */ 598 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 599 uint32_t :12; /*!< bit: 20..31 Reserved */ 600 } bit; /*!< Structure used for bit access */ 601 uint32_t reg; /*!< Type used for register access */ 602 } TWIM_VR_Type; 603 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 604 605 #define TWIM_VR_OFFSET 0x34 /**< \brief (TWIM_VR offset) Version Register */ 606 #define TWIM_VR_RESETVALUE _U_(0x00000120); /**< \brief (TWIM_VR reset_value) Version Register */ 607 608 #define TWIM_VR_VERSION_Pos 0 /**< \brief (TWIM_VR) Version number */ 609 #define TWIM_VR_VERSION_Msk (_U_(0xFFF) << TWIM_VR_VERSION_Pos) 610 #define TWIM_VR_VERSION(value) (TWIM_VR_VERSION_Msk & ((value) << TWIM_VR_VERSION_Pos)) 611 #define TWIM_VR_VARIANT_Pos 16 /**< \brief (TWIM_VR) Variant number */ 612 #define TWIM_VR_VARIANT_Msk (_U_(0xF) << TWIM_VR_VARIANT_Pos) 613 #define TWIM_VR_VARIANT(value) (TWIM_VR_VARIANT_Msk & ((value) << TWIM_VR_VARIANT_Pos)) 614 #define TWIM_VR_MASK _U_(0x000F0FFF) /**< \brief (TWIM_VR) MASK Register */ 615 616 /* -------- TWIM_HSCWGR : (TWIM Offset: 0x38) (R/W 32) HS-mode Clock Waveform Generator -------- */ 617 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 618 typedef union { 619 struct { 620 uint32_t LOW:8; /*!< bit: 0.. 7 Clock Low Cycles */ 621 uint32_t HIGH:8; /*!< bit: 8..15 Clock High Cycles */ 622 uint32_t STASTO:8; /*!< bit: 16..23 START and STOP Cycles */ 623 uint32_t DATA:4; /*!< bit: 24..27 Data Setup and Hold Cycles */ 624 uint32_t EXP:3; /*!< bit: 28..30 Clock Prescaler */ 625 uint32_t :1; /*!< bit: 31 Reserved */ 626 } bit; /*!< Structure used for bit access */ 627 uint32_t reg; /*!< Type used for register access */ 628 } TWIM_HSCWGR_Type; 629 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 630 631 #define TWIM_HSCWGR_OFFSET 0x38 /**< \brief (TWIM_HSCWGR offset) HS-mode Clock Waveform Generator */ 632 #define TWIM_HSCWGR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_HSCWGR reset_value) HS-mode Clock Waveform Generator */ 633 634 #define TWIM_HSCWGR_LOW_Pos 0 /**< \brief (TWIM_HSCWGR) Clock Low Cycles */ 635 #define TWIM_HSCWGR_LOW_Msk (_U_(0xFF) << TWIM_HSCWGR_LOW_Pos) 636 #define TWIM_HSCWGR_LOW(value) (TWIM_HSCWGR_LOW_Msk & ((value) << TWIM_HSCWGR_LOW_Pos)) 637 #define TWIM_HSCWGR_HIGH_Pos 8 /**< \brief (TWIM_HSCWGR) Clock High Cycles */ 638 #define TWIM_HSCWGR_HIGH_Msk (_U_(0xFF) << TWIM_HSCWGR_HIGH_Pos) 639 #define TWIM_HSCWGR_HIGH(value) (TWIM_HSCWGR_HIGH_Msk & ((value) << TWIM_HSCWGR_HIGH_Pos)) 640 #define TWIM_HSCWGR_STASTO_Pos 16 /**< \brief (TWIM_HSCWGR) START and STOP Cycles */ 641 #define TWIM_HSCWGR_STASTO_Msk (_U_(0xFF) << TWIM_HSCWGR_STASTO_Pos) 642 #define TWIM_HSCWGR_STASTO(value) (TWIM_HSCWGR_STASTO_Msk & ((value) << TWIM_HSCWGR_STASTO_Pos)) 643 #define TWIM_HSCWGR_DATA_Pos 24 /**< \brief (TWIM_HSCWGR) Data Setup and Hold Cycles */ 644 #define TWIM_HSCWGR_DATA_Msk (_U_(0xF) << TWIM_HSCWGR_DATA_Pos) 645 #define TWIM_HSCWGR_DATA(value) (TWIM_HSCWGR_DATA_Msk & ((value) << TWIM_HSCWGR_DATA_Pos)) 646 #define TWIM_HSCWGR_EXP_Pos 28 /**< \brief (TWIM_HSCWGR) Clock Prescaler */ 647 #define TWIM_HSCWGR_EXP_Msk (_U_(0x7) << TWIM_HSCWGR_EXP_Pos) 648 #define TWIM_HSCWGR_EXP(value) (TWIM_HSCWGR_EXP_Msk & ((value) << TWIM_HSCWGR_EXP_Pos)) 649 #define TWIM_HSCWGR_MASK _U_(0x7FFFFFFF) /**< \brief (TWIM_HSCWGR) MASK Register */ 650 651 /* -------- TWIM_SRR : (TWIM Offset: 0x3C) (R/W 32) Slew Rate Register -------- */ 652 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 653 typedef union { 654 struct { 655 uint32_t DADRIVEL:3; /*!< bit: 0.. 2 Data Drive Strength LOW */ 656 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 657 uint32_t DASLEW:2; /*!< bit: 8.. 9 Data Slew Limit */ 658 uint32_t :6; /*!< bit: 10..15 Reserved */ 659 uint32_t CLDRIVEL:3; /*!< bit: 16..18 Clock Drive Strength LOW */ 660 uint32_t :5; /*!< bit: 19..23 Reserved */ 661 uint32_t CLSLEW:2; /*!< bit: 24..25 Clock Slew Limit */ 662 uint32_t :2; /*!< bit: 26..27 Reserved */ 663 uint32_t FILTER:2; /*!< bit: 28..29 Input Spike Filter Control */ 664 uint32_t :2; /*!< bit: 30..31 Reserved */ 665 } bit; /*!< Structure used for bit access */ 666 uint32_t reg; /*!< Type used for register access */ 667 } TWIM_SRR_Type; 668 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 669 670 #define TWIM_SRR_OFFSET 0x3C /**< \brief (TWIM_SRR offset) Slew Rate Register */ 671 #define TWIM_SRR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_SRR reset_value) Slew Rate Register */ 672 673 #define TWIM_SRR_DADRIVEL_Pos 0 /**< \brief (TWIM_SRR) Data Drive Strength LOW */ 674 #define TWIM_SRR_DADRIVEL_Msk (_U_(0x7) << TWIM_SRR_DADRIVEL_Pos) 675 #define TWIM_SRR_DADRIVEL(value) (TWIM_SRR_DADRIVEL_Msk & ((value) << TWIM_SRR_DADRIVEL_Pos)) 676 #define TWIM_SRR_DASLEW_Pos 8 /**< \brief (TWIM_SRR) Data Slew Limit */ 677 #define TWIM_SRR_DASLEW_Msk (_U_(0x3) << TWIM_SRR_DASLEW_Pos) 678 #define TWIM_SRR_DASLEW(value) (TWIM_SRR_DASLEW_Msk & ((value) << TWIM_SRR_DASLEW_Pos)) 679 #define TWIM_SRR_CLDRIVEL_Pos 16 /**< \brief (TWIM_SRR) Clock Drive Strength LOW */ 680 #define TWIM_SRR_CLDRIVEL_Msk (_U_(0x7) << TWIM_SRR_CLDRIVEL_Pos) 681 #define TWIM_SRR_CLDRIVEL(value) (TWIM_SRR_CLDRIVEL_Msk & ((value) << TWIM_SRR_CLDRIVEL_Pos)) 682 #define TWIM_SRR_CLSLEW_Pos 24 /**< \brief (TWIM_SRR) Clock Slew Limit */ 683 #define TWIM_SRR_CLSLEW_Msk (_U_(0x3) << TWIM_SRR_CLSLEW_Pos) 684 #define TWIM_SRR_CLSLEW(value) (TWIM_SRR_CLSLEW_Msk & ((value) << TWIM_SRR_CLSLEW_Pos)) 685 #define TWIM_SRR_FILTER_Pos 28 /**< \brief (TWIM_SRR) Input Spike Filter Control */ 686 #define TWIM_SRR_FILTER_Msk (_U_(0x3) << TWIM_SRR_FILTER_Pos) 687 #define TWIM_SRR_FILTER(value) (TWIM_SRR_FILTER_Msk & ((value) << TWIM_SRR_FILTER_Pos)) 688 #define TWIM_SRR_MASK _U_(0x33070307) /**< \brief (TWIM_SRR) MASK Register */ 689 690 /* -------- TWIM_HSSRR : (TWIM Offset: 0x40) (R/W 32) HS-mode Slew Rate Register -------- */ 691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 692 typedef union { 693 struct { 694 uint32_t DADRIVEL:3; /*!< bit: 0.. 2 Data Drive Strength LOW */ 695 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 696 uint32_t DASLEW:2; /*!< bit: 8.. 9 Data Slew Limit */ 697 uint32_t :6; /*!< bit: 10..15 Reserved */ 698 uint32_t CLDRIVEL:3; /*!< bit: 16..18 Clock Drive Strength LOW */ 699 uint32_t :1; /*!< bit: 19 Reserved */ 700 uint32_t CLDRIVEH:2; /*!< bit: 20..21 Clock Drive Strength HIGH */ 701 uint32_t :2; /*!< bit: 22..23 Reserved */ 702 uint32_t CLSLEW:2; /*!< bit: 24..25 Clock Slew Limit */ 703 uint32_t :2; /*!< bit: 26..27 Reserved */ 704 uint32_t FILTER:2; /*!< bit: 28..29 Input Spike Filter Control */ 705 uint32_t :2; /*!< bit: 30..31 Reserved */ 706 } bit; /*!< Structure used for bit access */ 707 uint32_t reg; /*!< Type used for register access */ 708 } TWIM_HSSRR_Type; 709 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 710 711 #define TWIM_HSSRR_OFFSET 0x40 /**< \brief (TWIM_HSSRR offset) HS-mode Slew Rate Register */ 712 #define TWIM_HSSRR_RESETVALUE _U_(0x00000000); /**< \brief (TWIM_HSSRR reset_value) HS-mode Slew Rate Register */ 713 714 #define TWIM_HSSRR_DADRIVEL_Pos 0 /**< \brief (TWIM_HSSRR) Data Drive Strength LOW */ 715 #define TWIM_HSSRR_DADRIVEL_Msk (_U_(0x7) << TWIM_HSSRR_DADRIVEL_Pos) 716 #define TWIM_HSSRR_DADRIVEL(value) (TWIM_HSSRR_DADRIVEL_Msk & ((value) << TWIM_HSSRR_DADRIVEL_Pos)) 717 #define TWIM_HSSRR_DASLEW_Pos 8 /**< \brief (TWIM_HSSRR) Data Slew Limit */ 718 #define TWIM_HSSRR_DASLEW_Msk (_U_(0x3) << TWIM_HSSRR_DASLEW_Pos) 719 #define TWIM_HSSRR_DASLEW(value) (TWIM_HSSRR_DASLEW_Msk & ((value) << TWIM_HSSRR_DASLEW_Pos)) 720 #define TWIM_HSSRR_CLDRIVEL_Pos 16 /**< \brief (TWIM_HSSRR) Clock Drive Strength LOW */ 721 #define TWIM_HSSRR_CLDRIVEL_Msk (_U_(0x7) << TWIM_HSSRR_CLDRIVEL_Pos) 722 #define TWIM_HSSRR_CLDRIVEL(value) (TWIM_HSSRR_CLDRIVEL_Msk & ((value) << TWIM_HSSRR_CLDRIVEL_Pos)) 723 #define TWIM_HSSRR_CLDRIVEH_Pos 20 /**< \brief (TWIM_HSSRR) Clock Drive Strength HIGH */ 724 #define TWIM_HSSRR_CLDRIVEH_Msk (_U_(0x3) << TWIM_HSSRR_CLDRIVEH_Pos) 725 #define TWIM_HSSRR_CLDRIVEH(value) (TWIM_HSSRR_CLDRIVEH_Msk & ((value) << TWIM_HSSRR_CLDRIVEH_Pos)) 726 #define TWIM_HSSRR_CLSLEW_Pos 24 /**< \brief (TWIM_HSSRR) Clock Slew Limit */ 727 #define TWIM_HSSRR_CLSLEW_Msk (_U_(0x3) << TWIM_HSSRR_CLSLEW_Pos) 728 #define TWIM_HSSRR_CLSLEW(value) (TWIM_HSSRR_CLSLEW_Msk & ((value) << TWIM_HSSRR_CLSLEW_Pos)) 729 #define TWIM_HSSRR_FILTER_Pos 28 /**< \brief (TWIM_HSSRR) Input Spike Filter Control */ 730 #define TWIM_HSSRR_FILTER_Msk (_U_(0x3) << TWIM_HSSRR_FILTER_Pos) 731 #define TWIM_HSSRR_FILTER(value) (TWIM_HSSRR_FILTER_Msk & ((value) << TWIM_HSSRR_FILTER_Pos)) 732 #define TWIM_HSSRR_MASK _U_(0x33370307) /**< \brief (TWIM_HSSRR) MASK Register */ 733 734 /** \brief TWIM hardware registers */ 735 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 736 typedef struct { 737 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 738 __IO uint32_t CWGR; /**< \brief Offset: 0x04 (R/W 32) Clock Waveform Generator Register */ 739 __IO uint32_t SMBTR; /**< \brief Offset: 0x08 (R/W 32) SMBus Timing Register */ 740 __IO uint32_t CMDR; /**< \brief Offset: 0x0C (R/W 32) Command Register */ 741 __IO uint32_t NCMDR; /**< \brief Offset: 0x10 (R/W 32) Next Command Register */ 742 __I uint32_t RHR; /**< \brief Offset: 0x14 (R/ 32) Receive Holding Register */ 743 __O uint32_t THR; /**< \brief Offset: 0x18 ( /W 32) Transmit Holding Register */ 744 __I uint32_t SR; /**< \brief Offset: 0x1C (R/ 32) Status Register */ 745 __O uint32_t IER; /**< \brief Offset: 0x20 ( /W 32) Interrupt Enable Register */ 746 __O uint32_t IDR; /**< \brief Offset: 0x24 ( /W 32) Interrupt Disable Register */ 747 __I uint32_t IMR; /**< \brief Offset: 0x28 (R/ 32) Interrupt Mask Register */ 748 __O uint32_t SCR; /**< \brief Offset: 0x2C ( /W 32) Status Clear Register */ 749 __I uint32_t PR; /**< \brief Offset: 0x30 (R/ 32) Parameter Register */ 750 __I uint32_t VR; /**< \brief Offset: 0x34 (R/ 32) Version Register */ 751 __IO uint32_t HSCWGR; /**< \brief Offset: 0x38 (R/W 32) HS-mode Clock Waveform Generator */ 752 __IO uint32_t SRR; /**< \brief Offset: 0x3C (R/W 32) Slew Rate Register */ 753 __IO uint32_t HSSRR; /**< \brief Offset: 0x40 (R/W 32) HS-mode Slew Rate Register */ 754 } Twim; 755 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 756 757 /*@}*/ 758 759 #endif /* _SAM4L_TWIM_COMPONENT_ */ 760
