1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TC_COMPONENT_ 30 #define _SAM4L_TC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_TC Timer/Counter */ 36 /*@{*/ 37 38 #define TC_I7604 39 #define REV_TC 0x402 40 41 /* -------- TC_CCR : (TC Offset: 0x00) ( /W 32) channel Channel Control Register Channel -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t CLKEN:1; /*!< bit: 0 Counter Clock Enable Command */ 46 uint32_t CLKDIS:1; /*!< bit: 1 Counter Clock Disable Command */ 47 uint32_t SWTRG:1; /*!< bit: 2 Software Trigger Command */ 48 uint32_t :29; /*!< bit: 3..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } TC_CCR_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define TC_CCR_OFFSET 0x00 /**< \brief (TC_CCR offset) Channel Control Register Channel */ 55 #define TC_CCR_RESETVALUE _U_(0x00000000); /**< \brief (TC_CCR reset_value) Channel Control Register Channel */ 56 57 #define TC_CCR_CLKEN_Pos 0 /**< \brief (TC_CCR) Counter Clock Enable Command */ 58 #define TC_CCR_CLKEN (_U_(0x1) << TC_CCR_CLKEN_Pos) 59 #define TC_CCR_CLKEN_0_Val _U_(0x0) /**< \brief (TC_CCR) No effect. */ 60 #define TC_CCR_CLKEN_1_Val _U_(0x1) /**< \brief (TC_CCR) Enables the clock if CLKDIS is not 1. */ 61 #define TC_CCR_CLKEN_0 (TC_CCR_CLKEN_0_Val << TC_CCR_CLKEN_Pos) 62 #define TC_CCR_CLKEN_1 (TC_CCR_CLKEN_1_Val << TC_CCR_CLKEN_Pos) 63 #define TC_CCR_CLKDIS_Pos 1 /**< \brief (TC_CCR) Counter Clock Disable Command */ 64 #define TC_CCR_CLKDIS (_U_(0x1) << TC_CCR_CLKDIS_Pos) 65 #define TC_CCR_CLKDIS_0_Val _U_(0x0) /**< \brief (TC_CCR) No effect. */ 66 #define TC_CCR_CLKDIS_1_Val _U_(0x1) /**< \brief (TC_CCR) Disables the clock. */ 67 #define TC_CCR_CLKDIS_0 (TC_CCR_CLKDIS_0_Val << TC_CCR_CLKDIS_Pos) 68 #define TC_CCR_CLKDIS_1 (TC_CCR_CLKDIS_1_Val << TC_CCR_CLKDIS_Pos) 69 #define TC_CCR_SWTRG_Pos 2 /**< \brief (TC_CCR) Software Trigger Command */ 70 #define TC_CCR_SWTRG (_U_(0x1) << TC_CCR_SWTRG_Pos) 71 #define TC_CCR_SWTRG_0_Val _U_(0x0) /**< \brief (TC_CCR) No effect. */ 72 #define TC_CCR_SWTRG_1_Val _U_(0x1) /**< \brief (TC_CCR) A software trigger is performed:the counter is reset and clock is started. */ 73 #define TC_CCR_SWTRG_0 (TC_CCR_SWTRG_0_Val << TC_CCR_SWTRG_Pos) 74 #define TC_CCR_SWTRG_1 (TC_CCR_SWTRG_1_Val << TC_CCR_SWTRG_Pos) 75 #define TC_CCR_MASK _U_(0x00000007) /**< \brief (TC_CCR) MASK Register */ 76 77 /* -------- TC_CMR : (TC Offset: 0x04) (R/W 32) channel Channel Mode Register Channel -------- */ 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 79 typedef union { 80 struct { // CAPTURE mode 81 uint32_t TCCLKS:3; /*!< bit: 0.. 2 Clock Selection */ 82 uint32_t CLKI:1; /*!< bit: 3 Clock Invert */ 83 uint32_t BURST:2; /*!< bit: 4.. 5 Burst Signal Selection */ 84 uint32_t LDBSTOP:1; /*!< bit: 6 Counter Clock Stopped with RB Loading */ 85 uint32_t LDBDIS:1; /*!< bit: 7 Counter Clock Disable with RB Loading */ 86 uint32_t ETRGEDG:2; /*!< bit: 8.. 9 External Trigger Edge Selection */ 87 uint32_t ABETRG:1; /*!< bit: 10 TIOA or TIOB External Trigger Selection */ 88 uint32_t :3; /*!< bit: 11..13 Reserved */ 89 uint32_t CPCTRG:1; /*!< bit: 14 RC Compare Trigger Enable */ 90 uint32_t WAVE:1; /*!< bit: 15 Wave */ 91 uint32_t LDRA:2; /*!< bit: 16..17 RA Loading Selection */ 92 uint32_t LDRB:2; /*!< bit: 18..19 RB Loading Selection */ 93 uint32_t :12; /*!< bit: 20..31 Reserved */ 94 } CAPTURE; /*!< Structure used for CAPTURE */ 95 struct { // WAVEFORM mode 96 uint32_t TCCLKS:3; /*!< bit: 0.. 2 Clock Selection */ 97 uint32_t CLKI:1; /*!< bit: 3 Clock Invert */ 98 uint32_t BURST:2; /*!< bit: 4.. 5 Burst Signal Selection */ 99 uint32_t CPCSTOP:1; /*!< bit: 6 Counter Clock Stopped with RC Compare */ 100 uint32_t CPCDIS:1; /*!< bit: 7 Counter Clock Disable with RC Compare */ 101 uint32_t EEVTEDG:2; /*!< bit: 8.. 9 External Event Edge Selection */ 102 uint32_t EEVT:2; /*!< bit: 10..11 External Event Selection */ 103 uint32_t ENETRG:1; /*!< bit: 12 External Event Trigger Enable */ 104 uint32_t WAVSEL:2; /*!< bit: 13..14 Waveform Selection */ 105 uint32_t WAVE:1; /*!< bit: 15 WAVE */ 106 uint32_t ACPA:2; /*!< bit: 16..17 RA Compare Effect on TIOA */ 107 uint32_t ACPC:2; /*!< bit: 18..19 RC Compare Effect on TIOA */ 108 uint32_t AEEVT:2; /*!< bit: 20..21 External Event Effect on TIOA */ 109 uint32_t ASWTRG:2; /*!< bit: 22..23 Software Trigger Effect on TIOA */ 110 uint32_t BCPB:2; /*!< bit: 24..25 RB Compare Effect on TIOB */ 111 uint32_t BCPC:2; /*!< bit: 26..27 RC Compare Effect on TIOB */ 112 uint32_t BEEVT:2; /*!< bit: 28..29 External Event Effect on TIOB */ 113 uint32_t BSWTRG:2; /*!< bit: 30..31 Software Trigger Effect on TIOB */ 114 } WAVEFORM; /*!< Structure used for WAVEFORM */ 115 uint32_t reg; /*!< Type used for register access */ 116 } TC_CMR_Type; 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 118 119 #define TC_CMR_OFFSET 0x04 /**< \brief (TC_CMR offset) Channel Mode Register Channel */ 120 #define TC_CMR_RESETVALUE _U_(0x00000000); /**< \brief (TC_CMR reset_value) Channel Mode Register Channel */ 121 122 // CAPTURE mode 123 #define TC_CMR_CAPTURE_TCCLKS_Pos 0 /**< \brief (TC_CMR_CAPTURE) Clock Selection */ 124 #define TC_CMR_CAPTURE_TCCLKS_Msk (_U_(0x7) << TC_CMR_CAPTURE_TCCLKS_Pos) 125 #define TC_CMR_CAPTURE_TCCLKS(value) (TC_CMR_CAPTURE_TCCLKS_Msk & ((value) << TC_CMR_CAPTURE_TCCLKS_Pos)) 126 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) TIMER_CLOCK1 */ 127 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) TIMER_CLOCK2 */ 128 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< \brief (TC_CMR_CAPTURE) TIMER_CLOCK3 */ 129 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< \brief (TC_CMR_CAPTURE) TIMER_CLOCK4 */ 130 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< \brief (TC_CMR_CAPTURE) TIMER_CLOCK5 */ 131 #define TC_CMR_CAPTURE_TCCLKS_XC0_Val _U_(0x5) /**< \brief (TC_CMR_CAPTURE) XC0 */ 132 #define TC_CMR_CAPTURE_TCCLKS_XC1_Val _U_(0x6) /**< \brief (TC_CMR_CAPTURE) XC1 */ 133 #define TC_CMR_CAPTURE_TCCLKS_XC2_Val _U_(0x7) /**< \brief (TC_CMR_CAPTURE) XC2 */ 134 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK1 (TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 135 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK2 (TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 136 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK3 (TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 137 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK4 (TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 138 #define TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK5 (TC_CMR_CAPTURE_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 139 #define TC_CMR_CAPTURE_TCCLKS_XC0 (TC_CMR_CAPTURE_TCCLKS_XC0_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 140 #define TC_CMR_CAPTURE_TCCLKS_XC1 (TC_CMR_CAPTURE_TCCLKS_XC1_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 141 #define TC_CMR_CAPTURE_TCCLKS_XC2 (TC_CMR_CAPTURE_TCCLKS_XC2_Val << TC_CMR_CAPTURE_TCCLKS_Pos) 142 #define TC_CMR_CAPTURE_CLKI_Pos 3 /**< \brief (TC_CMR_CAPTURE) Clock Invert */ 143 #define TC_CMR_CAPTURE_CLKI (_U_(0x1) << TC_CMR_CAPTURE_CLKI_Pos) 144 #define TC_CMR_CAPTURE_CLKI_0_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) Counter is incremented on rising edge of the clock. */ 145 #define TC_CMR_CAPTURE_CLKI_1_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) Counter is incremented on falling edge of the clock. */ 146 #define TC_CMR_CAPTURE_CLKI_0 (TC_CMR_CAPTURE_CLKI_0_Val << TC_CMR_CAPTURE_CLKI_Pos) 147 #define TC_CMR_CAPTURE_CLKI_1 (TC_CMR_CAPTURE_CLKI_1_Val << TC_CMR_CAPTURE_CLKI_Pos) 148 #define TC_CMR_CAPTURE_BURST_Pos 4 /**< \brief (TC_CMR_CAPTURE) Burst Signal Selection */ 149 #define TC_CMR_CAPTURE_BURST_Msk (_U_(0x3) << TC_CMR_CAPTURE_BURST_Pos) 150 #define TC_CMR_CAPTURE_BURST(value) (TC_CMR_CAPTURE_BURST_Msk & ((value) << TC_CMR_CAPTURE_BURST_Pos)) 151 #define TC_CMR_CAPTURE_BURST_NOT_GATED_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) The clock is not gated by an external signal. */ 152 #define TC_CMR_CAPTURE_BURST_CLK_AND_XC0_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) XC0 is ANDed with the selected clock. */ 153 #define TC_CMR_CAPTURE_BURST_CLK_AND_XC1_Val _U_(0x2) /**< \brief (TC_CMR_CAPTURE) XC1 is ANDed with the selected clock. */ 154 #define TC_CMR_CAPTURE_BURST_CLK_AND_XC2_Val _U_(0x3) /**< \brief (TC_CMR_CAPTURE) XC2 is ANDed with the selected clock. */ 155 #define TC_CMR_CAPTURE_BURST_NOT_GATED (TC_CMR_CAPTURE_BURST_NOT_GATED_Val << TC_CMR_CAPTURE_BURST_Pos) 156 #define TC_CMR_CAPTURE_BURST_CLK_AND_XC0 (TC_CMR_CAPTURE_BURST_CLK_AND_XC0_Val << TC_CMR_CAPTURE_BURST_Pos) 157 #define TC_CMR_CAPTURE_BURST_CLK_AND_XC1 (TC_CMR_CAPTURE_BURST_CLK_AND_XC1_Val << TC_CMR_CAPTURE_BURST_Pos) 158 #define TC_CMR_CAPTURE_BURST_CLK_AND_XC2 (TC_CMR_CAPTURE_BURST_CLK_AND_XC2_Val << TC_CMR_CAPTURE_BURST_Pos) 159 #define TC_CMR_CAPTURE_LDBSTOP_Pos 6 /**< \brief (TC_CMR_CAPTURE) Counter Clock Stopped with RB Loading */ 160 #define TC_CMR_CAPTURE_LDBSTOP (_U_(0x1) << TC_CMR_CAPTURE_LDBSTOP_Pos) 161 #define TC_CMR_CAPTURE_LDBSTOP_0_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) Counter clock is not stopped when RB loading occurs. */ 162 #define TC_CMR_CAPTURE_LDBSTOP_1_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) Counter clock is stopped when RB loading occurs. */ 163 #define TC_CMR_CAPTURE_LDBSTOP_0 (TC_CMR_CAPTURE_LDBSTOP_0_Val << TC_CMR_CAPTURE_LDBSTOP_Pos) 164 #define TC_CMR_CAPTURE_LDBSTOP_1 (TC_CMR_CAPTURE_LDBSTOP_1_Val << TC_CMR_CAPTURE_LDBSTOP_Pos) 165 #define TC_CMR_CAPTURE_LDBDIS_Pos 7 /**< \brief (TC_CMR_CAPTURE) Counter Clock Disable with RB Loading */ 166 #define TC_CMR_CAPTURE_LDBDIS (_U_(0x1) << TC_CMR_CAPTURE_LDBDIS_Pos) 167 #define TC_CMR_CAPTURE_LDBDIS_0_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) Counter clock is not disabled when RB loading occurs. */ 168 #define TC_CMR_CAPTURE_LDBDIS_1_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) Counter clock is disabled when RB loading occurs. */ 169 #define TC_CMR_CAPTURE_LDBDIS_0 (TC_CMR_CAPTURE_LDBDIS_0_Val << TC_CMR_CAPTURE_LDBDIS_Pos) 170 #define TC_CMR_CAPTURE_LDBDIS_1 (TC_CMR_CAPTURE_LDBDIS_1_Val << TC_CMR_CAPTURE_LDBDIS_Pos) 171 #define TC_CMR_CAPTURE_ETRGEDG_Pos 8 /**< \brief (TC_CMR_CAPTURE) External Trigger Edge Selection */ 172 #define TC_CMR_CAPTURE_ETRGEDG_Msk (_U_(0x3) << TC_CMR_CAPTURE_ETRGEDG_Pos) 173 #define TC_CMR_CAPTURE_ETRGEDG(value) (TC_CMR_CAPTURE_ETRGEDG_Msk & ((value) << TC_CMR_CAPTURE_ETRGEDG_Pos)) 174 #define TC_CMR_CAPTURE_ETRGEDG_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) none */ 175 #define TC_CMR_CAPTURE_ETRGEDG_POS_EDGE_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) rising edge */ 176 #define TC_CMR_CAPTURE_ETRGEDG_NEG_EDGE_Val _U_(0x2) /**< \brief (TC_CMR_CAPTURE) falling edge */ 177 #define TC_CMR_CAPTURE_ETRGEDG_BOTH_EDGES_Val _U_(0x3) /**< \brief (TC_CMR_CAPTURE) each edge */ 178 #define TC_CMR_CAPTURE_ETRGEDG_NO_EDGE (TC_CMR_CAPTURE_ETRGEDG_NO_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) 179 #define TC_CMR_CAPTURE_ETRGEDG_POS_EDGE (TC_CMR_CAPTURE_ETRGEDG_POS_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) 180 #define TC_CMR_CAPTURE_ETRGEDG_NEG_EDGE (TC_CMR_CAPTURE_ETRGEDG_NEG_EDGE_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) 181 #define TC_CMR_CAPTURE_ETRGEDG_BOTH_EDGES (TC_CMR_CAPTURE_ETRGEDG_BOTH_EDGES_Val << TC_CMR_CAPTURE_ETRGEDG_Pos) 182 #define TC_CMR_CAPTURE_ABETRG_Pos 10 /**< \brief (TC_CMR_CAPTURE) TIOA or TIOB External Trigger Selection */ 183 #define TC_CMR_CAPTURE_ABETRG (_U_(0x1) << TC_CMR_CAPTURE_ABETRG_Pos) 184 #define TC_CMR_CAPTURE_ABETRG_0_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) TIOB is used as an external trigger. */ 185 #define TC_CMR_CAPTURE_ABETRG_1_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) TIOA is used as an external trigger. */ 186 #define TC_CMR_CAPTURE_ABETRG_0 (TC_CMR_CAPTURE_ABETRG_0_Val << TC_CMR_CAPTURE_ABETRG_Pos) 187 #define TC_CMR_CAPTURE_ABETRG_1 (TC_CMR_CAPTURE_ABETRG_1_Val << TC_CMR_CAPTURE_ABETRG_Pos) 188 #define TC_CMR_CAPTURE_CPCTRG_Pos 14 /**< \brief (TC_CMR_CAPTURE) RC Compare Trigger Enable */ 189 #define TC_CMR_CAPTURE_CPCTRG (_U_(0x1) << TC_CMR_CAPTURE_CPCTRG_Pos) 190 #define TC_CMR_CAPTURE_CPCTRG_0_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) RC Compare has no effect on the counter and its clock. */ 191 #define TC_CMR_CAPTURE_CPCTRG_1_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) RC Compare resets the counter and starts the counter clock. */ 192 #define TC_CMR_CAPTURE_CPCTRG_0 (TC_CMR_CAPTURE_CPCTRG_0_Val << TC_CMR_CAPTURE_CPCTRG_Pos) 193 #define TC_CMR_CAPTURE_CPCTRG_1 (TC_CMR_CAPTURE_CPCTRG_1_Val << TC_CMR_CAPTURE_CPCTRG_Pos) 194 #define TC_CMR_CAPTURE_WAVE_Pos 15 /**< \brief (TC_CMR_CAPTURE) Wave */ 195 #define TC_CMR_CAPTURE_WAVE (_U_(0x1) << TC_CMR_CAPTURE_WAVE_Pos) 196 #define TC_CMR_CAPTURE_WAVE_0_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) Capture Mode is enabled. */ 197 #define TC_CMR_CAPTURE_WAVE_1_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) Capture Mode is disabled (Waveform Mode is enabled). */ 198 #define TC_CMR_CAPTURE_WAVE_0 (TC_CMR_CAPTURE_WAVE_0_Val << TC_CMR_CAPTURE_WAVE_Pos) 199 #define TC_CMR_CAPTURE_WAVE_1 (TC_CMR_CAPTURE_WAVE_1_Val << TC_CMR_CAPTURE_WAVE_Pos) 200 #define TC_CMR_CAPTURE_LDRA_Pos 16 /**< \brief (TC_CMR_CAPTURE) RA Loading Selection */ 201 #define TC_CMR_CAPTURE_LDRA_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRA_Pos) 202 #define TC_CMR_CAPTURE_LDRA(value) (TC_CMR_CAPTURE_LDRA_Msk & ((value) << TC_CMR_CAPTURE_LDRA_Pos)) 203 #define TC_CMR_CAPTURE_LDRA_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) none */ 204 #define TC_CMR_CAPTURE_LDRA_POS_EDGE_TIOA_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) rising edge of TIOA */ 205 #define TC_CMR_CAPTURE_LDRA_NEG_EDGE_TIOA_Val _U_(0x2) /**< \brief (TC_CMR_CAPTURE) falling edge of TIOA */ 206 #define TC_CMR_CAPTURE_LDRA_BOTH_EDGES_TIOA_Val _U_(0x3) /**< \brief (TC_CMR_CAPTURE) each edge of TIOA */ 207 #define TC_CMR_CAPTURE_LDRA_NO_EDGE (TC_CMR_CAPTURE_LDRA_NO_EDGE_Val << TC_CMR_CAPTURE_LDRA_Pos) 208 #define TC_CMR_CAPTURE_LDRA_POS_EDGE_TIOA (TC_CMR_CAPTURE_LDRA_POS_EDGE_TIOA_Val << TC_CMR_CAPTURE_LDRA_Pos) 209 #define TC_CMR_CAPTURE_LDRA_NEG_EDGE_TIOA (TC_CMR_CAPTURE_LDRA_NEG_EDGE_TIOA_Val << TC_CMR_CAPTURE_LDRA_Pos) 210 #define TC_CMR_CAPTURE_LDRA_BOTH_EDGES_TIOA (TC_CMR_CAPTURE_LDRA_BOTH_EDGES_TIOA_Val << TC_CMR_CAPTURE_LDRA_Pos) 211 #define TC_CMR_CAPTURE_LDRB_Pos 18 /**< \brief (TC_CMR_CAPTURE) RB Loading Selection */ 212 #define TC_CMR_CAPTURE_LDRB_Msk (_U_(0x3) << TC_CMR_CAPTURE_LDRB_Pos) 213 #define TC_CMR_CAPTURE_LDRB(value) (TC_CMR_CAPTURE_LDRB_Msk & ((value) << TC_CMR_CAPTURE_LDRB_Pos)) 214 #define TC_CMR_CAPTURE_LDRB_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR_CAPTURE) none */ 215 #define TC_CMR_CAPTURE_LDRB_POS_EDGE_TIOA_Val _U_(0x1) /**< \brief (TC_CMR_CAPTURE) rising edge of TIOA */ 216 #define TC_CMR_CAPTURE_LDRB_NEG_EDGE_TIOA_Val _U_(0x2) /**< \brief (TC_CMR_CAPTURE) falling edge of TIOA */ 217 #define TC_CMR_CAPTURE_LDRB_BOTH_EDGES_TIOA_Val _U_(0x3) /**< \brief (TC_CMR_CAPTURE) each edge of TIOA */ 218 #define TC_CMR_CAPTURE_LDRB_NO_EDGE (TC_CMR_CAPTURE_LDRB_NO_EDGE_Val << TC_CMR_CAPTURE_LDRB_Pos) 219 #define TC_CMR_CAPTURE_LDRB_POS_EDGE_TIOA (TC_CMR_CAPTURE_LDRB_POS_EDGE_TIOA_Val << TC_CMR_CAPTURE_LDRB_Pos) 220 #define TC_CMR_CAPTURE_LDRB_NEG_EDGE_TIOA (TC_CMR_CAPTURE_LDRB_NEG_EDGE_TIOA_Val << TC_CMR_CAPTURE_LDRB_Pos) 221 #define TC_CMR_CAPTURE_LDRB_BOTH_EDGES_TIOA (TC_CMR_CAPTURE_LDRB_BOTH_EDGES_TIOA_Val << TC_CMR_CAPTURE_LDRB_Pos) 222 #define TC_CMR_CAPTURE_MASK _U_(0x000FC7FF) /**< \brief (TC_CMR_CAPTURE) MASK Register */ 223 224 // WAVEFORM mode 225 #define TC_CMR_WAVEFORM_TCCLKS_Pos 0 /**< \brief (TC_CMR_WAVEFORM) Clock Selection */ 226 #define TC_CMR_WAVEFORM_TCCLKS_Msk (_U_(0x7) << TC_CMR_WAVEFORM_TCCLKS_Pos) 227 #define TC_CMR_WAVEFORM_TCCLKS(value) (TC_CMR_WAVEFORM_TCCLKS_Msk & ((value) << TC_CMR_WAVEFORM_TCCLKS_Pos)) 228 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV1_CLOCK_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) TIMER_DIV1_CLOCK */ 229 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV2_CLOCK_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) TIMER_DIV2_CLOCK */ 230 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV3_CLOCK_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) TIMER_DIV3_CLOCK */ 231 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV4_CLOCK_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) TIMER_DIV4_CLOCK */ 232 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV5_CLOCK_Val _U_(0x4) /**< \brief (TC_CMR_WAVEFORM) TIMER_DIV5_CLOCK */ 233 #define TC_CMR_WAVEFORM_TCCLKS_XC0_Val _U_(0x5) /**< \brief (TC_CMR_WAVEFORM) XC0 */ 234 #define TC_CMR_WAVEFORM_TCCLKS_XC1_Val _U_(0x6) /**< \brief (TC_CMR_WAVEFORM) XC1 */ 235 #define TC_CMR_WAVEFORM_TCCLKS_XC2_Val _U_(0x7) /**< \brief (TC_CMR_WAVEFORM) XC2 */ 236 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV1_CLOCK (TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV1_CLOCK_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 237 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV2_CLOCK (TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV2_CLOCK_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 238 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV3_CLOCK (TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV3_CLOCK_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 239 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV4_CLOCK (TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV4_CLOCK_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 240 #define TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV5_CLOCK (TC_CMR_WAVEFORM_TCCLKS_TIMER_DIV5_CLOCK_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 241 #define TC_CMR_WAVEFORM_TCCLKS_XC0 (TC_CMR_WAVEFORM_TCCLKS_XC0_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 242 #define TC_CMR_WAVEFORM_TCCLKS_XC1 (TC_CMR_WAVEFORM_TCCLKS_XC1_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 243 #define TC_CMR_WAVEFORM_TCCLKS_XC2 (TC_CMR_WAVEFORM_TCCLKS_XC2_Val << TC_CMR_WAVEFORM_TCCLKS_Pos) 244 #define TC_CMR_WAVEFORM_CLKI_Pos 3 /**< \brief (TC_CMR_WAVEFORM) Clock Invert */ 245 #define TC_CMR_WAVEFORM_CLKI (_U_(0x1) << TC_CMR_WAVEFORM_CLKI_Pos) 246 #define TC_CMR_WAVEFORM_CLKI_0_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) Counter is incremented on rising edge of the clock. */ 247 #define TC_CMR_WAVEFORM_CLKI_1_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) Counter is incremented on falling edge of the clock. */ 248 #define TC_CMR_WAVEFORM_CLKI_0 (TC_CMR_WAVEFORM_CLKI_0_Val << TC_CMR_WAVEFORM_CLKI_Pos) 249 #define TC_CMR_WAVEFORM_CLKI_1 (TC_CMR_WAVEFORM_CLKI_1_Val << TC_CMR_WAVEFORM_CLKI_Pos) 250 #define TC_CMR_WAVEFORM_BURST_Pos 4 /**< \brief (TC_CMR_WAVEFORM) Burst Signal Selection */ 251 #define TC_CMR_WAVEFORM_BURST_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BURST_Pos) 252 #define TC_CMR_WAVEFORM_BURST(value) (TC_CMR_WAVEFORM_BURST_Msk & ((value) << TC_CMR_WAVEFORM_BURST_Pos)) 253 #define TC_CMR_WAVEFORM_BURST_NOT_GATED_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) The clock is not gated by an external signal. */ 254 #define TC_CMR_WAVEFORM_BURST_CLK_AND_XC0_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) XC0 is ANDed with the selected clock. */ 255 #define TC_CMR_WAVEFORM_BURST_CLK_AND_XC1_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) XC1 is ANDed with the selected clock. */ 256 #define TC_CMR_WAVEFORM_BURST_CLK_AND_XC2_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) XC2 is ANDed with the selected clock. */ 257 #define TC_CMR_WAVEFORM_BURST_NOT_GATED (TC_CMR_WAVEFORM_BURST_NOT_GATED_Val << TC_CMR_WAVEFORM_BURST_Pos) 258 #define TC_CMR_WAVEFORM_BURST_CLK_AND_XC0 (TC_CMR_WAVEFORM_BURST_CLK_AND_XC0_Val << TC_CMR_WAVEFORM_BURST_Pos) 259 #define TC_CMR_WAVEFORM_BURST_CLK_AND_XC1 (TC_CMR_WAVEFORM_BURST_CLK_AND_XC1_Val << TC_CMR_WAVEFORM_BURST_Pos) 260 #define TC_CMR_WAVEFORM_BURST_CLK_AND_XC2 (TC_CMR_WAVEFORM_BURST_CLK_AND_XC2_Val << TC_CMR_WAVEFORM_BURST_Pos) 261 #define TC_CMR_WAVEFORM_CPCSTOP_Pos 6 /**< \brief (TC_CMR_WAVEFORM) Counter Clock Stopped with RC Compare */ 262 #define TC_CMR_WAVEFORM_CPCSTOP (_U_(0x1) << TC_CMR_WAVEFORM_CPCSTOP_Pos) 263 #define TC_CMR_WAVEFORM_CPCSTOP_0_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) Counter clock is not stopped when counter reaches RC. */ 264 #define TC_CMR_WAVEFORM_CPCSTOP_1_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) Counter clock is stopped when counter reaches RC. */ 265 #define TC_CMR_WAVEFORM_CPCSTOP_0 (TC_CMR_WAVEFORM_CPCSTOP_0_Val << TC_CMR_WAVEFORM_CPCSTOP_Pos) 266 #define TC_CMR_WAVEFORM_CPCSTOP_1 (TC_CMR_WAVEFORM_CPCSTOP_1_Val << TC_CMR_WAVEFORM_CPCSTOP_Pos) 267 #define TC_CMR_WAVEFORM_CPCDIS_Pos 7 /**< \brief (TC_CMR_WAVEFORM) Counter Clock Disable with RC Compare */ 268 #define TC_CMR_WAVEFORM_CPCDIS (_U_(0x1) << TC_CMR_WAVEFORM_CPCDIS_Pos) 269 #define TC_CMR_WAVEFORM_CPCDIS_0_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) Counter clock is not disabled when counter reaches RC. */ 270 #define TC_CMR_WAVEFORM_CPCDIS_1_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) Counter clock is disabled when counter reaches RC. */ 271 #define TC_CMR_WAVEFORM_CPCDIS_0 (TC_CMR_WAVEFORM_CPCDIS_0_Val << TC_CMR_WAVEFORM_CPCDIS_Pos) 272 #define TC_CMR_WAVEFORM_CPCDIS_1 (TC_CMR_WAVEFORM_CPCDIS_1_Val << TC_CMR_WAVEFORM_CPCDIS_Pos) 273 #define TC_CMR_WAVEFORM_EEVTEDG_Pos 8 /**< \brief (TC_CMR_WAVEFORM) External Event Edge Selection */ 274 #define TC_CMR_WAVEFORM_EEVTEDG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVTEDG_Pos) 275 #define TC_CMR_WAVEFORM_EEVTEDG(value) (TC_CMR_WAVEFORM_EEVTEDG_Msk & ((value) << TC_CMR_WAVEFORM_EEVTEDG_Pos)) 276 #define TC_CMR_WAVEFORM_EEVTEDG_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 277 #define TC_CMR_WAVEFORM_EEVTEDG_POS_EDGE_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) rising edge */ 278 #define TC_CMR_WAVEFORM_EEVTEDG_NEG_EDGE_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) falling edge */ 279 #define TC_CMR_WAVEFORM_EEVTEDG_BOTH_EDGES_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) each edge */ 280 #define TC_CMR_WAVEFORM_EEVTEDG_NO_EDGE (TC_CMR_WAVEFORM_EEVTEDG_NO_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) 281 #define TC_CMR_WAVEFORM_EEVTEDG_POS_EDGE (TC_CMR_WAVEFORM_EEVTEDG_POS_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) 282 #define TC_CMR_WAVEFORM_EEVTEDG_NEG_EDGE (TC_CMR_WAVEFORM_EEVTEDG_NEG_EDGE_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) 283 #define TC_CMR_WAVEFORM_EEVTEDG_BOTH_EDGES (TC_CMR_WAVEFORM_EEVTEDG_BOTH_EDGES_Val << TC_CMR_WAVEFORM_EEVTEDG_Pos) 284 #define TC_CMR_WAVEFORM_EEVT_Pos 10 /**< \brief (TC_CMR_WAVEFORM) External Event Selection */ 285 #define TC_CMR_WAVEFORM_EEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_EEVT_Pos) 286 #define TC_CMR_WAVEFORM_EEVT(value) (TC_CMR_WAVEFORM_EEVT_Msk & ((value) << TC_CMR_WAVEFORM_EEVT_Pos)) 287 #define TC_CMR_WAVEFORM_EEVT_TIOB_INPUT_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. */ 288 #define TC_CMR_WAVEFORM_EEVT_XC0_OUTPUT_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) XC0 output */ 289 #define TC_CMR_WAVEFORM_EEVT_XC1_OUTPUT_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) XC1 output */ 290 #define TC_CMR_WAVEFORM_EEVT_XC2_OUTPUT_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) XC2 output */ 291 #define TC_CMR_WAVEFORM_EEVT_TIOB_INPUT (TC_CMR_WAVEFORM_EEVT_TIOB_INPUT_Val << TC_CMR_WAVEFORM_EEVT_Pos) 292 #define TC_CMR_WAVEFORM_EEVT_XC0_OUTPUT (TC_CMR_WAVEFORM_EEVT_XC0_OUTPUT_Val << TC_CMR_WAVEFORM_EEVT_Pos) 293 #define TC_CMR_WAVEFORM_EEVT_XC1_OUTPUT (TC_CMR_WAVEFORM_EEVT_XC1_OUTPUT_Val << TC_CMR_WAVEFORM_EEVT_Pos) 294 #define TC_CMR_WAVEFORM_EEVT_XC2_OUTPUT (TC_CMR_WAVEFORM_EEVT_XC2_OUTPUT_Val << TC_CMR_WAVEFORM_EEVT_Pos) 295 #define TC_CMR_WAVEFORM_ENETRG_Pos 12 /**< \brief (TC_CMR_WAVEFORM) External Event Trigger Enable */ 296 #define TC_CMR_WAVEFORM_ENETRG (_U_(0x1) << TC_CMR_WAVEFORM_ENETRG_Pos) 297 #define TC_CMR_WAVEFORM_ENETRG_0_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. */ 298 #define TC_CMR_WAVEFORM_ENETRG_1_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) The external event resets the counter and starts the counter clock. */ 299 #define TC_CMR_WAVEFORM_ENETRG_0 (TC_CMR_WAVEFORM_ENETRG_0_Val << TC_CMR_WAVEFORM_ENETRG_Pos) 300 #define TC_CMR_WAVEFORM_ENETRG_1 (TC_CMR_WAVEFORM_ENETRG_1_Val << TC_CMR_WAVEFORM_ENETRG_Pos) 301 #define TC_CMR_WAVEFORM_WAVSEL_Pos 13 /**< \brief (TC_CMR_WAVEFORM) Waveform Selection */ 302 #define TC_CMR_WAVEFORM_WAVSEL_Msk (_U_(0x3) << TC_CMR_WAVEFORM_WAVSEL_Pos) 303 #define TC_CMR_WAVEFORM_WAVSEL(value) (TC_CMR_WAVEFORM_WAVSEL_Msk & ((value) << TC_CMR_WAVEFORM_WAVSEL_Pos)) 304 #define TC_CMR_WAVEFORM_WAVSEL_UP_NO_AUTO_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) UP mode without automatic trigger on RC Compare */ 305 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_NO_AUTO_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) UPDOWN mode without automatic trigger on RC Compare */ 306 #define TC_CMR_WAVEFORM_WAVSEL_UP_AUTO_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) UP mode with automatic trigger on RC Compare */ 307 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_AUTO_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) UPDOWN mode with automatic trigger on RC Compare */ 308 #define TC_CMR_WAVEFORM_WAVSEL_UP_NO_AUTO (TC_CMR_WAVEFORM_WAVSEL_UP_NO_AUTO_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) 309 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_NO_AUTO (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_NO_AUTO_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) 310 #define TC_CMR_WAVEFORM_WAVSEL_UP_AUTO (TC_CMR_WAVEFORM_WAVSEL_UP_AUTO_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) 311 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_AUTO (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_AUTO_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) 312 #define TC_CMR_WAVEFORM_WAVSEL_UP_Val _U_(0x0) /**< (TC_CMR) WAVEFORM UP mode without automatic trigger on RC Compare */ 313 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val _U_(0x1) /**< (TC_CMR) WAVEFORM UPDOWN mode without automatic trigger on RC Compare */ 314 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val _U_(0x2) /**< (TC_CMR) WAVEFORM UP mode with automatic trigger on RC Compare */ 315 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val _U_(0x3) /**< (TC_CMR) WAVEFORM UPDOWN mode with automatic trigger on RC Compare */ 316 #define TC_CMR_WAVEFORM_WAVSEL_UP (TC_CMR_WAVEFORM_WAVSEL_UP_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode without automatic trigger on RC Compare Position */ 317 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode without automatic trigger on RC Compare Position */ 318 #define TC_CMR_WAVEFORM_WAVSEL_UP_RC (TC_CMR_WAVEFORM_WAVSEL_UP_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UP mode with automatic trigger on RC Compare Position */ 319 #define TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC (TC_CMR_WAVEFORM_WAVSEL_UPDOWN_RC_Val << TC_CMR_WAVEFORM_WAVSEL_Pos) /**< (TC_CMR) UPDOWN mode with automatic trigger on RC Compare Position */ 320 #define TC_CMR_WAVEFORM_WAVE_Pos 15 /**< \brief (TC_CMR_WAVEFORM) WAVE */ 321 #define TC_CMR_WAVEFORM_WAVE (_U_(0x1) << TC_CMR_WAVEFORM_WAVE_Pos) 322 #define TC_CMR_WAVEFORM_WAVE_0_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) Waveform Mode is disabled (Capture Mode is enabled). */ 323 #define TC_CMR_WAVEFORM_WAVE_1_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) Waveform Mode is enabled. */ 324 #define TC_CMR_WAVEFORM_WAVE_0 (TC_CMR_WAVEFORM_WAVE_0_Val << TC_CMR_WAVEFORM_WAVE_Pos) 325 #define TC_CMR_WAVEFORM_WAVE_1 (TC_CMR_WAVEFORM_WAVE_1_Val << TC_CMR_WAVEFORM_WAVE_Pos) 326 #define TC_CMR_WAVEFORM_ACPA_Pos 16 /**< \brief (TC_CMR_WAVEFORM) RA Compare Effect on TIOA */ 327 #define TC_CMR_WAVEFORM_ACPA_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPA_Pos) 328 #define TC_CMR_WAVEFORM_ACPA(value) (TC_CMR_WAVEFORM_ACPA_Msk & ((value) << TC_CMR_WAVEFORM_ACPA_Pos)) 329 #define TC_CMR_WAVEFORM_ACPA_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 330 #define TC_CMR_WAVEFORM_ACPA_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 331 #define TC_CMR_WAVEFORM_ACPA_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 332 #define TC_CMR_WAVEFORM_ACPA_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 333 #define TC_CMR_WAVEFORM_ACPA_NONE (TC_CMR_WAVEFORM_ACPA_NONE_Val << TC_CMR_WAVEFORM_ACPA_Pos) 334 #define TC_CMR_WAVEFORM_ACPA_SET (TC_CMR_WAVEFORM_ACPA_SET_Val << TC_CMR_WAVEFORM_ACPA_Pos) 335 #define TC_CMR_WAVEFORM_ACPA_CLEAR (TC_CMR_WAVEFORM_ACPA_CLEAR_Val << TC_CMR_WAVEFORM_ACPA_Pos) 336 #define TC_CMR_WAVEFORM_ACPA_TOGGLE (TC_CMR_WAVEFORM_ACPA_TOGGLE_Val << TC_CMR_WAVEFORM_ACPA_Pos) 337 #define TC_CMR_WAVEFORM_ACPC_Pos 18 /**< \brief (TC_CMR_WAVEFORM) RC Compare Effect on TIOA */ 338 #define TC_CMR_WAVEFORM_ACPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ACPC_Pos) 339 #define TC_CMR_WAVEFORM_ACPC(value) (TC_CMR_WAVEFORM_ACPC_Msk & ((value) << TC_CMR_WAVEFORM_ACPC_Pos)) 340 #define TC_CMR_WAVEFORM_ACPC_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 341 #define TC_CMR_WAVEFORM_ACPC_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 342 #define TC_CMR_WAVEFORM_ACPC_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 343 #define TC_CMR_WAVEFORM_ACPC_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 344 #define TC_CMR_WAVEFORM_ACPC_NONE (TC_CMR_WAVEFORM_ACPC_NONE_Val << TC_CMR_WAVEFORM_ACPC_Pos) 345 #define TC_CMR_WAVEFORM_ACPC_SET (TC_CMR_WAVEFORM_ACPC_SET_Val << TC_CMR_WAVEFORM_ACPC_Pos) 346 #define TC_CMR_WAVEFORM_ACPC_CLEAR (TC_CMR_WAVEFORM_ACPC_CLEAR_Val << TC_CMR_WAVEFORM_ACPC_Pos) 347 #define TC_CMR_WAVEFORM_ACPC_TOGGLE (TC_CMR_WAVEFORM_ACPC_TOGGLE_Val << TC_CMR_WAVEFORM_ACPC_Pos) 348 #define TC_CMR_WAVEFORM_AEEVT_Pos 20 /**< \brief (TC_CMR_WAVEFORM) External Event Effect on TIOA */ 349 #define TC_CMR_WAVEFORM_AEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_AEEVT_Pos) 350 #define TC_CMR_WAVEFORM_AEEVT(value) (TC_CMR_WAVEFORM_AEEVT_Msk & ((value) << TC_CMR_WAVEFORM_AEEVT_Pos)) 351 #define TC_CMR_WAVEFORM_AEEVT_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 352 #define TC_CMR_WAVEFORM_AEEVT_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 353 #define TC_CMR_WAVEFORM_AEEVT_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 354 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 355 #define TC_CMR_WAVEFORM_AEEVT_NONE (TC_CMR_WAVEFORM_AEEVT_NONE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) 356 #define TC_CMR_WAVEFORM_AEEVT_SET (TC_CMR_WAVEFORM_AEEVT_SET_Val << TC_CMR_WAVEFORM_AEEVT_Pos) 357 #define TC_CMR_WAVEFORM_AEEVT_CLEAR (TC_CMR_WAVEFORM_AEEVT_CLEAR_Val << TC_CMR_WAVEFORM_AEEVT_Pos) 358 #define TC_CMR_WAVEFORM_AEEVT_TOGGLE (TC_CMR_WAVEFORM_AEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_AEEVT_Pos) 359 #define TC_CMR_WAVEFORM_ASWTRG_Pos 22 /**< \brief (TC_CMR_WAVEFORM) Software Trigger Effect on TIOA */ 360 #define TC_CMR_WAVEFORM_ASWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_ASWTRG_Pos) 361 #define TC_CMR_WAVEFORM_ASWTRG(value) (TC_CMR_WAVEFORM_ASWTRG_Msk & ((value) << TC_CMR_WAVEFORM_ASWTRG_Pos)) 362 #define TC_CMR_WAVEFORM_ASWTRG_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 363 #define TC_CMR_WAVEFORM_ASWTRG_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 364 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 365 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 366 #define TC_CMR_WAVEFORM_ASWTRG_NONE (TC_CMR_WAVEFORM_ASWTRG_NONE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) 367 #define TC_CMR_WAVEFORM_ASWTRG_SET (TC_CMR_WAVEFORM_ASWTRG_SET_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) 368 #define TC_CMR_WAVEFORM_ASWTRG_CLEAR (TC_CMR_WAVEFORM_ASWTRG_CLEAR_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) 369 #define TC_CMR_WAVEFORM_ASWTRG_TOGGLE (TC_CMR_WAVEFORM_ASWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_ASWTRG_Pos) 370 #define TC_CMR_WAVEFORM_BCPB_Pos 24 /**< \brief (TC_CMR_WAVEFORM) RB Compare Effect on TIOB */ 371 #define TC_CMR_WAVEFORM_BCPB_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPB_Pos) 372 #define TC_CMR_WAVEFORM_BCPB(value) (TC_CMR_WAVEFORM_BCPB_Msk & ((value) << TC_CMR_WAVEFORM_BCPB_Pos)) 373 #define TC_CMR_WAVEFORM_BCPB_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 374 #define TC_CMR_WAVEFORM_BCPB_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 375 #define TC_CMR_WAVEFORM_BCPB_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 376 #define TC_CMR_WAVEFORM_BCPB_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 377 #define TC_CMR_WAVEFORM_BCPB_NONE (TC_CMR_WAVEFORM_BCPB_NONE_Val << TC_CMR_WAVEFORM_BCPB_Pos) 378 #define TC_CMR_WAVEFORM_BCPB_SET (TC_CMR_WAVEFORM_BCPB_SET_Val << TC_CMR_WAVEFORM_BCPB_Pos) 379 #define TC_CMR_WAVEFORM_BCPB_CLEAR (TC_CMR_WAVEFORM_BCPB_CLEAR_Val << TC_CMR_WAVEFORM_BCPB_Pos) 380 #define TC_CMR_WAVEFORM_BCPB_TOGGLE (TC_CMR_WAVEFORM_BCPB_TOGGLE_Val << TC_CMR_WAVEFORM_BCPB_Pos) 381 #define TC_CMR_WAVEFORM_BCPC_Pos 26 /**< \brief (TC_CMR_WAVEFORM) RC Compare Effect on TIOB */ 382 #define TC_CMR_WAVEFORM_BCPC_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BCPC_Pos) 383 #define TC_CMR_WAVEFORM_BCPC(value) (TC_CMR_WAVEFORM_BCPC_Msk & ((value) << TC_CMR_WAVEFORM_BCPC_Pos)) 384 #define TC_CMR_WAVEFORM_BCPC_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 385 #define TC_CMR_WAVEFORM_BCPC_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 386 #define TC_CMR_WAVEFORM_BCPC_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 387 #define TC_CMR_WAVEFORM_BCPC_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 388 #define TC_CMR_WAVEFORM_BCPC_NONE (TC_CMR_WAVEFORM_BCPC_NONE_Val << TC_CMR_WAVEFORM_BCPC_Pos) 389 #define TC_CMR_WAVEFORM_BCPC_SET (TC_CMR_WAVEFORM_BCPC_SET_Val << TC_CMR_WAVEFORM_BCPC_Pos) 390 #define TC_CMR_WAVEFORM_BCPC_CLEAR (TC_CMR_WAVEFORM_BCPC_CLEAR_Val << TC_CMR_WAVEFORM_BCPC_Pos) 391 #define TC_CMR_WAVEFORM_BCPC_TOGGLE (TC_CMR_WAVEFORM_BCPC_TOGGLE_Val << TC_CMR_WAVEFORM_BCPC_Pos) 392 #define TC_CMR_WAVEFORM_BEEVT_Pos 28 /**< \brief (TC_CMR_WAVEFORM) External Event Effect on TIOB */ 393 #define TC_CMR_WAVEFORM_BEEVT_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BEEVT_Pos) 394 #define TC_CMR_WAVEFORM_BEEVT(value) (TC_CMR_WAVEFORM_BEEVT_Msk & ((value) << TC_CMR_WAVEFORM_BEEVT_Pos)) 395 #define TC_CMR_WAVEFORM_BEEVT_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 396 #define TC_CMR_WAVEFORM_BEEVT_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 397 #define TC_CMR_WAVEFORM_BEEVT_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 398 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 399 #define TC_CMR_WAVEFORM_BEEVT_NONE (TC_CMR_WAVEFORM_BEEVT_NONE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) 400 #define TC_CMR_WAVEFORM_BEEVT_SET (TC_CMR_WAVEFORM_BEEVT_SET_Val << TC_CMR_WAVEFORM_BEEVT_Pos) 401 #define TC_CMR_WAVEFORM_BEEVT_CLEAR (TC_CMR_WAVEFORM_BEEVT_CLEAR_Val << TC_CMR_WAVEFORM_BEEVT_Pos) 402 #define TC_CMR_WAVEFORM_BEEVT_TOGGLE (TC_CMR_WAVEFORM_BEEVT_TOGGLE_Val << TC_CMR_WAVEFORM_BEEVT_Pos) 403 #define TC_CMR_WAVEFORM_BSWTRG_Pos 30 /**< \brief (TC_CMR_WAVEFORM) Software Trigger Effect on TIOB */ 404 #define TC_CMR_WAVEFORM_BSWTRG_Msk (_U_(0x3) << TC_CMR_WAVEFORM_BSWTRG_Pos) 405 #define TC_CMR_WAVEFORM_BSWTRG(value) (TC_CMR_WAVEFORM_BSWTRG_Msk & ((value) << TC_CMR_WAVEFORM_BSWTRG_Pos)) 406 #define TC_CMR_WAVEFORM_BSWTRG_NONE_Val _U_(0x0) /**< \brief (TC_CMR_WAVEFORM) none */ 407 #define TC_CMR_WAVEFORM_BSWTRG_SET_Val _U_(0x1) /**< \brief (TC_CMR_WAVEFORM) set */ 408 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR_WAVEFORM) clear */ 409 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR_WAVEFORM) toggle */ 410 #define TC_CMR_WAVEFORM_BSWTRG_NONE (TC_CMR_WAVEFORM_BSWTRG_NONE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) 411 #define TC_CMR_WAVEFORM_BSWTRG_SET (TC_CMR_WAVEFORM_BSWTRG_SET_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) 412 #define TC_CMR_WAVEFORM_BSWTRG_CLEAR (TC_CMR_WAVEFORM_BSWTRG_CLEAR_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) 413 #define TC_CMR_WAVEFORM_BSWTRG_TOGGLE (TC_CMR_WAVEFORM_BSWTRG_TOGGLE_Val << TC_CMR_WAVEFORM_BSWTRG_Pos) 414 #define TC_CMR_WAVEFORM_MASK _U_(0xFFFFFFFF) /**< \brief (TC_CMR_WAVEFORM) MASK Register */ 415 416 // Any mode 417 #define TC_CMR_TCCLKS_Pos 0 /**< \brief (TC_CMR) Clock Selection */ 418 #define TC_CMR_TCCLKS_Msk (_U_(0x7) << TC_CMR_TCCLKS_Pos) 419 #define TC_CMR_TCCLKS(value) (TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos)) 420 #define TC_CMR_TCCLKS_TIMER_CLOCK1_Val _U_(0x0) /**< \brief (TC_CMR) TIMER_CLOCK1 */ 421 #define TC_CMR_TCCLKS_TIMER_CLOCK2_Val _U_(0x1) /**< \brief (TC_CMR) TIMER_CLOCK2 */ 422 #define TC_CMR_TCCLKS_TIMER_CLOCK3_Val _U_(0x2) /**< \brief (TC_CMR) TIMER_CLOCK3 */ 423 #define TC_CMR_TCCLKS_TIMER_CLOCK4_Val _U_(0x3) /**< \brief (TC_CMR) TIMER_CLOCK4 */ 424 #define TC_CMR_TCCLKS_TIMER_CLOCK5_Val _U_(0x4) /**< \brief (TC_CMR) TIMER_CLOCK5 */ 425 #define TC_CMR_TCCLKS_XC0_Val _U_(0x5) /**< \brief (TC_CMR) XC0 */ 426 #define TC_CMR_TCCLKS_XC1_Val _U_(0x6) /**< \brief (TC_CMR) XC1 */ 427 #define TC_CMR_TCCLKS_XC2_Val _U_(0x7) /**< \brief (TC_CMR) XC2 */ 428 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (TC_CMR_TCCLKS_TIMER_CLOCK1_Val << TC_CMR_TCCLKS_Pos) 429 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (TC_CMR_TCCLKS_TIMER_CLOCK2_Val << TC_CMR_TCCLKS_Pos) 430 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (TC_CMR_TCCLKS_TIMER_CLOCK3_Val << TC_CMR_TCCLKS_Pos) 431 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (TC_CMR_TCCLKS_TIMER_CLOCK4_Val << TC_CMR_TCCLKS_Pos) 432 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (TC_CMR_TCCLKS_TIMER_CLOCK5_Val << TC_CMR_TCCLKS_Pos) 433 #define TC_CMR_TCCLKS_XC0 (TC_CMR_TCCLKS_XC0_Val << TC_CMR_TCCLKS_Pos) 434 #define TC_CMR_TCCLKS_XC1 (TC_CMR_TCCLKS_XC1_Val << TC_CMR_TCCLKS_Pos) 435 #define TC_CMR_TCCLKS_XC2 (TC_CMR_TCCLKS_XC2_Val << TC_CMR_TCCLKS_Pos) 436 #define TC_CMR_CLKI_Pos 3 /**< \brief (TC_CMR) Clock Invert */ 437 #define TC_CMR_CLKI (_U_(0x1) << TC_CMR_CLKI_Pos) 438 #define TC_CMR_CLKI_0_Val _U_(0x0) /**< \brief (TC_CMR) Counter is incremented on rising edge of the clock. */ 439 #define TC_CMR_CLKI_1_Val _U_(0x1) /**< \brief (TC_CMR) Counter is incremented on falling edge of the clock. */ 440 #define TC_CMR_CLKI_0 (TC_CMR_CLKI_0_Val << TC_CMR_CLKI_Pos) 441 #define TC_CMR_CLKI_1 (TC_CMR_CLKI_1_Val << TC_CMR_CLKI_Pos) 442 #define TC_CMR_BURST_Pos 4 /**< \brief (TC_CMR) Burst Signal Selection */ 443 #define TC_CMR_BURST_Msk (_U_(0x3) << TC_CMR_BURST_Pos) 444 #define TC_CMR_BURST(value) (TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos)) 445 #define TC_CMR_BURST_NOT_GATED_Val _U_(0x0) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ 446 #define TC_CMR_BURST_CLK_AND_XC0_Val _U_(0x1) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ 447 #define TC_CMR_BURST_CLK_AND_XC1_Val _U_(0x2) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ 448 #define TC_CMR_BURST_CLK_AND_XC2_Val _U_(0x3) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ 449 #define TC_CMR_BURST_NOT_GATED (TC_CMR_BURST_NOT_GATED_Val << TC_CMR_BURST_Pos) 450 #define TC_CMR_BURST_CLK_AND_XC0 (TC_CMR_BURST_CLK_AND_XC0_Val << TC_CMR_BURST_Pos) 451 #define TC_CMR_BURST_CLK_AND_XC1 (TC_CMR_BURST_CLK_AND_XC1_Val << TC_CMR_BURST_Pos) 452 #define TC_CMR_BURST_CLK_AND_XC2 (TC_CMR_BURST_CLK_AND_XC2_Val << TC_CMR_BURST_Pos) 453 #define TC_CMR_LDBSTOP_Pos 6 /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ 454 #define TC_CMR_LDBSTOP (_U_(0x1) << TC_CMR_LDBSTOP_Pos) 455 #define TC_CMR_LDBSTOP_0_Val _U_(0x0) /**< \brief (TC_CMR) Counter clock is not stopped when RB loading occurs. */ 456 #define TC_CMR_LDBSTOP_1_Val _U_(0x1) /**< \brief (TC_CMR) Counter clock is stopped when RB loading occurs. */ 457 #define TC_CMR_LDBSTOP_0 (TC_CMR_LDBSTOP_0_Val << TC_CMR_LDBSTOP_Pos) 458 #define TC_CMR_LDBSTOP_1 (TC_CMR_LDBSTOP_1_Val << TC_CMR_LDBSTOP_Pos) 459 #define TC_CMR_CPCSTOP_Pos 6 /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ 460 #define TC_CMR_CPCSTOP (_U_(0x1) << TC_CMR_CPCSTOP_Pos) 461 #define TC_CMR_CPCSTOP_0_Val _U_(0x0) /**< \brief (TC_CMR) Counter clock is not stopped when counter reaches RC. */ 462 #define TC_CMR_CPCSTOP_1_Val _U_(0x1) /**< \brief (TC_CMR) Counter clock is stopped when counter reaches RC. */ 463 #define TC_CMR_CPCSTOP_0 (TC_CMR_CPCSTOP_0_Val << TC_CMR_CPCSTOP_Pos) 464 #define TC_CMR_CPCSTOP_1 (TC_CMR_CPCSTOP_1_Val << TC_CMR_CPCSTOP_Pos) 465 #define TC_CMR_LDBDIS_Pos 7 /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ 466 #define TC_CMR_LDBDIS (_U_(0x1) << TC_CMR_LDBDIS_Pos) 467 #define TC_CMR_LDBDIS_0_Val _U_(0x0) /**< \brief (TC_CMR) Counter clock is not disabled when RB loading occurs. */ 468 #define TC_CMR_LDBDIS_1_Val _U_(0x1) /**< \brief (TC_CMR) Counter clock is disabled when RB loading occurs. */ 469 #define TC_CMR_LDBDIS_0 (TC_CMR_LDBDIS_0_Val << TC_CMR_LDBDIS_Pos) 470 #define TC_CMR_LDBDIS_1 (TC_CMR_LDBDIS_1_Val << TC_CMR_LDBDIS_Pos) 471 #define TC_CMR_CPCDIS_Pos 7 /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ 472 #define TC_CMR_CPCDIS (_U_(0x1) << TC_CMR_CPCDIS_Pos) 473 #define TC_CMR_CPCDIS_0_Val _U_(0x0) /**< \brief (TC_CMR) Counter clock is not disabled when counter reaches RC. */ 474 #define TC_CMR_CPCDIS_1_Val _U_(0x1) /**< \brief (TC_CMR) Counter clock is disabled when counter reaches RC. */ 475 #define TC_CMR_CPCDIS_0 (TC_CMR_CPCDIS_0_Val << TC_CMR_CPCDIS_Pos) 476 #define TC_CMR_CPCDIS_1 (TC_CMR_CPCDIS_1_Val << TC_CMR_CPCDIS_Pos) 477 #define TC_CMR_ETRGEDG_Pos 8 /**< \brief (TC_CMR) External Trigger Edge Selection */ 478 #define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) 479 #define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)) 480 #define TC_CMR_ETRGEDG_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 481 #define TC_CMR_ETRGEDG_POS_EDGE_Val _U_(0x1) /**< \brief (TC_CMR) rising edge */ 482 #define TC_CMR_ETRGEDG_NEG_EDGE_Val _U_(0x2) /**< \brief (TC_CMR) falling edge */ 483 #define TC_CMR_ETRGEDG_BOTH_EDGES_Val _U_(0x3) /**< \brief (TC_CMR) each edge */ 484 #define TC_CMR_ETRGEDG_NO_EDGE (TC_CMR_ETRGEDG_NO_EDGE_Val << TC_CMR_ETRGEDG_Pos) 485 #define TC_CMR_ETRGEDG_POS_EDGE (TC_CMR_ETRGEDG_POS_EDGE_Val << TC_CMR_ETRGEDG_Pos) 486 #define TC_CMR_ETRGEDG_NEG_EDGE (TC_CMR_ETRGEDG_NEG_EDGE_Val << TC_CMR_ETRGEDG_Pos) 487 #define TC_CMR_ETRGEDG_BOTH_EDGES (TC_CMR_ETRGEDG_BOTH_EDGES_Val << TC_CMR_ETRGEDG_Pos) 488 #define TC_CMR_EEVTEDG_Pos 8 /**< \brief (TC_CMR) External Event Edge Selection */ 489 #define TC_CMR_EEVTEDG_Msk (_U_(0x3) << TC_CMR_EEVTEDG_Pos) 490 #define TC_CMR_EEVTEDG(value) (TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos)) 491 #define TC_CMR_EEVTEDG_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 492 #define TC_CMR_EEVTEDG_POS_EDGE_Val _U_(0x1) /**< \brief (TC_CMR) rising edge */ 493 #define TC_CMR_EEVTEDG_NEG_EDGE_Val _U_(0x2) /**< \brief (TC_CMR) falling edge */ 494 #define TC_CMR_EEVTEDG_BOTH_EDGES_Val _U_(0x3) /**< \brief (TC_CMR) each edge */ 495 #define TC_CMR_EEVTEDG_NO_EDGE (TC_CMR_EEVTEDG_NO_EDGE_Val << TC_CMR_EEVTEDG_Pos) 496 #define TC_CMR_EEVTEDG_POS_EDGE (TC_CMR_EEVTEDG_POS_EDGE_Val << TC_CMR_EEVTEDG_Pos) 497 #define TC_CMR_EEVTEDG_NEG_EDGE (TC_CMR_EEVTEDG_NEG_EDGE_Val << TC_CMR_EEVTEDG_Pos) 498 #define TC_CMR_EEVTEDG_BOTH_EDGES (TC_CMR_EEVTEDG_BOTH_EDGES_Val << TC_CMR_EEVTEDG_Pos) 499 #define TC_CMR_ABETRG_Pos 10 /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ 500 #define TC_CMR_ABETRG (_U_(0x1) << TC_CMR_ABETRG_Pos) 501 #define TC_CMR_ABETRG_0_Val _U_(0x0) /**< \brief (TC_CMR) TIOB is used as an external trigger. */ 502 #define TC_CMR_ABETRG_1_Val _U_(0x1) /**< \brief (TC_CMR) TIOA is used as an external trigger. */ 503 #define TC_CMR_ABETRG_0 (TC_CMR_ABETRG_0_Val << TC_CMR_ABETRG_Pos) 504 #define TC_CMR_ABETRG_1 (TC_CMR_ABETRG_1_Val << TC_CMR_ABETRG_Pos) 505 #define TC_CMR_EEVT_Pos 10 /**< \brief (TC_CMR) External Event Selection */ 506 #define TC_CMR_EEVT_Msk (_U_(0x3) << TC_CMR_EEVT_Pos) 507 #define TC_CMR_EEVT(value) (TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos)) 508 #define TC_CMR_EEVT_TIOB_INPUT_Val _U_(0x0) /**< \brief (TC_CMR) TIOB input. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. */ 509 #define TC_CMR_EEVT_XC0_OUTPUT_Val _U_(0x1) /**< \brief (TC_CMR) XC0 output */ 510 #define TC_CMR_EEVT_XC1_OUTPUT_Val _U_(0x2) /**< \brief (TC_CMR) XC1 output */ 511 #define TC_CMR_EEVT_XC2_OUTPUT_Val _U_(0x3) /**< \brief (TC_CMR) XC2 output */ 512 #define TC_CMR_EEVT_TIOB_INPUT (TC_CMR_EEVT_TIOB_INPUT_Val << TC_CMR_EEVT_Pos) 513 #define TC_CMR_EEVT_XC0_OUTPUT (TC_CMR_EEVT_XC0_OUTPUT_Val << TC_CMR_EEVT_Pos) 514 #define TC_CMR_EEVT_XC1_OUTPUT (TC_CMR_EEVT_XC1_OUTPUT_Val << TC_CMR_EEVT_Pos) 515 #define TC_CMR_EEVT_XC2_OUTPUT (TC_CMR_EEVT_XC2_OUTPUT_Val << TC_CMR_EEVT_Pos) 516 #define TC_CMR_ENETRG_Pos 12 /**< \brief (TC_CMR) External Event Trigger Enable */ 517 #define TC_CMR_ENETRG (_U_(0x1) << TC_CMR_ENETRG_Pos) 518 #define TC_CMR_ENETRG_0_Val _U_(0x0) /**< \brief (TC_CMR) The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. */ 519 #define TC_CMR_ENETRG_1_Val _U_(0x1) /**< \brief (TC_CMR) The external event resets the counter and starts the counter clock. */ 520 #define TC_CMR_ENETRG_0 (TC_CMR_ENETRG_0_Val << TC_CMR_ENETRG_Pos) 521 #define TC_CMR_ENETRG_1 (TC_CMR_ENETRG_1_Val << TC_CMR_ENETRG_Pos) 522 #define TC_CMR_WAVSEL_Pos 13 /**< \brief (TC_CMR) Waveform Selection */ 523 #define TC_CMR_WAVSEL_Msk (_U_(0x3) << TC_CMR_WAVSEL_Pos) 524 #define TC_CMR_WAVSEL(value) (TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos)) 525 #define TC_CMR_WAVSEL_UP_NO_AUTO_Val _U_(0x0) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ 526 #define TC_CMR_WAVSEL_UPDOWN_NO_AUTO_Val _U_(0x1) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ 527 #define TC_CMR_WAVSEL_UP_AUTO_Val _U_(0x2) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ 528 #define TC_CMR_WAVSEL_UPDOWN_AUTO_Val _U_(0x3) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ 529 #define TC_CMR_WAVSEL_UP_NO_AUTO (TC_CMR_WAVSEL_UP_NO_AUTO_Val << TC_CMR_WAVSEL_Pos) 530 #define TC_CMR_WAVSEL_UPDOWN_NO_AUTO (TC_CMR_WAVSEL_UPDOWN_NO_AUTO_Val << TC_CMR_WAVSEL_Pos) 531 #define TC_CMR_WAVSEL_UP_AUTO (TC_CMR_WAVSEL_UP_AUTO_Val << TC_CMR_WAVSEL_Pos) 532 #define TC_CMR_WAVSEL_UPDOWN_AUTO (TC_CMR_WAVSEL_UPDOWN_AUTO_Val << TC_CMR_WAVSEL_Pos) 533 #define TC_CMR_CPCTRG_Pos 14 /**< \brief (TC_CMR) RC Compare Trigger Enable */ 534 #define TC_CMR_CPCTRG (_U_(0x1) << TC_CMR_CPCTRG_Pos) 535 #define TC_CMR_CPCTRG_0_Val _U_(0x0) /**< \brief (TC_CMR) RC Compare has no effect on the counter and its clock. */ 536 #define TC_CMR_CPCTRG_1_Val _U_(0x1) /**< \brief (TC_CMR) RC Compare resets the counter and starts the counter clock. */ 537 #define TC_CMR_CPCTRG_0 (TC_CMR_CPCTRG_0_Val << TC_CMR_CPCTRG_Pos) 538 #define TC_CMR_CPCTRG_1 (TC_CMR_CPCTRG_1_Val << TC_CMR_CPCTRG_Pos) 539 #define TC_CMR_WAVE_Pos 15 /**< \brief (TC_CMR) Wave */ 540 #define TC_CMR_WAVE (_U_(0x1) << TC_CMR_WAVE_Pos) 541 #define TC_CMR_WAVE_0_Val _U_(0x0) /**< \brief (TC_CMR) Capture Mode is enabled. */ 542 #define TC_CMR_WAVE_1_Val _U_(0x1) /**< \brief (TC_CMR) Capture Mode is disabled (Waveform Mode is enabled). */ 543 #define TC_CMR_WAVE_0 (TC_CMR_WAVE_0_Val << TC_CMR_WAVE_Pos) 544 #define TC_CMR_WAVE_1 (TC_CMR_WAVE_1_Val << TC_CMR_WAVE_Pos) 545 #define TC_CMR_LDRA_Pos 16 /**< \brief (TC_CMR) RA Loading Selection */ 546 #define TC_CMR_LDRA_Msk (_U_(0x3) << TC_CMR_LDRA_Pos) 547 #define TC_CMR_LDRA(value) (TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos)) 548 #define TC_CMR_LDRA_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 549 #define TC_CMR_LDRA_POS_EDGE_TIOA_Val _U_(0x1) /**< \brief (TC_CMR) rising edge of TIOA */ 550 #define TC_CMR_LDRA_NEG_EDGE_TIOA_Val _U_(0x2) /**< \brief (TC_CMR) falling edge of TIOA */ 551 #define TC_CMR_LDRA_BOTH_EDGES_TIOA_Val _U_(0x3) /**< \brief (TC_CMR) each edge of TIOA */ 552 #define TC_CMR_LDRA_NO_EDGE (TC_CMR_LDRA_NO_EDGE_Val << TC_CMR_LDRA_Pos) 553 #define TC_CMR_LDRA_POS_EDGE_TIOA (TC_CMR_LDRA_POS_EDGE_TIOA_Val << TC_CMR_LDRA_Pos) 554 #define TC_CMR_LDRA_NEG_EDGE_TIOA (TC_CMR_LDRA_NEG_EDGE_TIOA_Val << TC_CMR_LDRA_Pos) 555 #define TC_CMR_LDRA_BOTH_EDGES_TIOA (TC_CMR_LDRA_BOTH_EDGES_TIOA_Val << TC_CMR_LDRA_Pos) 556 #define TC_CMR_ACPA_Pos 16 /**< \brief (TC_CMR) RA Compare Effect on TIOA */ 557 #define TC_CMR_ACPA_Msk (_U_(0x3) << TC_CMR_ACPA_Pos) 558 #define TC_CMR_ACPA(value) (TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos)) 559 #define TC_CMR_ACPA_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 560 #define TC_CMR_ACPA_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 561 #define TC_CMR_ACPA_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 562 #define TC_CMR_ACPA_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 563 #define TC_CMR_ACPA_NONE (TC_CMR_ACPA_NONE_Val << TC_CMR_ACPA_Pos) 564 #define TC_CMR_ACPA_SET (TC_CMR_ACPA_SET_Val << TC_CMR_ACPA_Pos) 565 #define TC_CMR_ACPA_CLEAR (TC_CMR_ACPA_CLEAR_Val << TC_CMR_ACPA_Pos) 566 #define TC_CMR_ACPA_TOGGLE (TC_CMR_ACPA_TOGGLE_Val << TC_CMR_ACPA_Pos) 567 #define TC_CMR_LDRB_Pos 18 /**< \brief (TC_CMR) RB Loading Selection */ 568 #define TC_CMR_LDRB_Msk (_U_(0x3) << TC_CMR_LDRB_Pos) 569 #define TC_CMR_LDRB(value) (TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos)) 570 #define TC_CMR_LDRB_NO_EDGE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 571 #define TC_CMR_LDRB_POS_EDGE_TIOA_Val _U_(0x1) /**< \brief (TC_CMR) rising edge of TIOA */ 572 #define TC_CMR_LDRB_NEG_EDGE_TIOA_Val _U_(0x2) /**< \brief (TC_CMR) falling edge of TIOA */ 573 #define TC_CMR_LDRB_BOTH_EDGES_TIOA_Val _U_(0x3) /**< \brief (TC_CMR) each edge of TIOA */ 574 #define TC_CMR_LDRB_NO_EDGE (TC_CMR_LDRB_NO_EDGE_Val << TC_CMR_LDRB_Pos) 575 #define TC_CMR_LDRB_POS_EDGE_TIOA (TC_CMR_LDRB_POS_EDGE_TIOA_Val << TC_CMR_LDRB_Pos) 576 #define TC_CMR_LDRB_NEG_EDGE_TIOA (TC_CMR_LDRB_NEG_EDGE_TIOA_Val << TC_CMR_LDRB_Pos) 577 #define TC_CMR_LDRB_BOTH_EDGES_TIOA (TC_CMR_LDRB_BOTH_EDGES_TIOA_Val << TC_CMR_LDRB_Pos) 578 #define TC_CMR_ACPC_Pos 18 /**< \brief (TC_CMR) RC Compare Effect on TIOA */ 579 #define TC_CMR_ACPC_Msk (_U_(0x3) << TC_CMR_ACPC_Pos) 580 #define TC_CMR_ACPC(value) (TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos)) 581 #define TC_CMR_ACPC_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 582 #define TC_CMR_ACPC_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 583 #define TC_CMR_ACPC_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 584 #define TC_CMR_ACPC_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 585 #define TC_CMR_ACPC_NONE (TC_CMR_ACPC_NONE_Val << TC_CMR_ACPC_Pos) 586 #define TC_CMR_ACPC_SET (TC_CMR_ACPC_SET_Val << TC_CMR_ACPC_Pos) 587 #define TC_CMR_ACPC_CLEAR (TC_CMR_ACPC_CLEAR_Val << TC_CMR_ACPC_Pos) 588 #define TC_CMR_ACPC_TOGGLE (TC_CMR_ACPC_TOGGLE_Val << TC_CMR_ACPC_Pos) 589 #define TC_CMR_AEEVT_Pos 20 /**< \brief (TC_CMR) External Event Effect on TIOA */ 590 #define TC_CMR_AEEVT_Msk (_U_(0x3) << TC_CMR_AEEVT_Pos) 591 #define TC_CMR_AEEVT(value) (TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos)) 592 #define TC_CMR_AEEVT_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 593 #define TC_CMR_AEEVT_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 594 #define TC_CMR_AEEVT_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 595 #define TC_CMR_AEEVT_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 596 #define TC_CMR_AEEVT_NONE (TC_CMR_AEEVT_NONE_Val << TC_CMR_AEEVT_Pos) 597 #define TC_CMR_AEEVT_SET (TC_CMR_AEEVT_SET_Val << TC_CMR_AEEVT_Pos) 598 #define TC_CMR_AEEVT_CLEAR (TC_CMR_AEEVT_CLEAR_Val << TC_CMR_AEEVT_Pos) 599 #define TC_CMR_AEEVT_TOGGLE (TC_CMR_AEEVT_TOGGLE_Val << TC_CMR_AEEVT_Pos) 600 #define TC_CMR_ASWTRG_Pos 22 /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ 601 #define TC_CMR_ASWTRG_Msk (_U_(0x3) << TC_CMR_ASWTRG_Pos) 602 #define TC_CMR_ASWTRG(value) (TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos)) 603 #define TC_CMR_ASWTRG_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 604 #define TC_CMR_ASWTRG_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 605 #define TC_CMR_ASWTRG_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 606 #define TC_CMR_ASWTRG_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 607 #define TC_CMR_ASWTRG_NONE (TC_CMR_ASWTRG_NONE_Val << TC_CMR_ASWTRG_Pos) 608 #define TC_CMR_ASWTRG_SET (TC_CMR_ASWTRG_SET_Val << TC_CMR_ASWTRG_Pos) 609 #define TC_CMR_ASWTRG_CLEAR (TC_CMR_ASWTRG_CLEAR_Val << TC_CMR_ASWTRG_Pos) 610 #define TC_CMR_ASWTRG_TOGGLE (TC_CMR_ASWTRG_TOGGLE_Val << TC_CMR_ASWTRG_Pos) 611 #define TC_CMR_BCPB_Pos 24 /**< \brief (TC_CMR) RB Compare Effect on TIOB */ 612 #define TC_CMR_BCPB_Msk (_U_(0x3) << TC_CMR_BCPB_Pos) 613 #define TC_CMR_BCPB(value) (TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos)) 614 #define TC_CMR_BCPB_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 615 #define TC_CMR_BCPB_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 616 #define TC_CMR_BCPB_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 617 #define TC_CMR_BCPB_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 618 #define TC_CMR_BCPB_NONE (TC_CMR_BCPB_NONE_Val << TC_CMR_BCPB_Pos) 619 #define TC_CMR_BCPB_SET (TC_CMR_BCPB_SET_Val << TC_CMR_BCPB_Pos) 620 #define TC_CMR_BCPB_CLEAR (TC_CMR_BCPB_CLEAR_Val << TC_CMR_BCPB_Pos) 621 #define TC_CMR_BCPB_TOGGLE (TC_CMR_BCPB_TOGGLE_Val << TC_CMR_BCPB_Pos) 622 #define TC_CMR_BCPC_Pos 26 /**< \brief (TC_CMR) RC Compare Effect on TIOB */ 623 #define TC_CMR_BCPC_Msk (_U_(0x3) << TC_CMR_BCPC_Pos) 624 #define TC_CMR_BCPC(value) (TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos)) 625 #define TC_CMR_BCPC_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 626 #define TC_CMR_BCPC_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 627 #define TC_CMR_BCPC_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 628 #define TC_CMR_BCPC_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 629 #define TC_CMR_BCPC_NONE (TC_CMR_BCPC_NONE_Val << TC_CMR_BCPC_Pos) 630 #define TC_CMR_BCPC_SET (TC_CMR_BCPC_SET_Val << TC_CMR_BCPC_Pos) 631 #define TC_CMR_BCPC_CLEAR (TC_CMR_BCPC_CLEAR_Val << TC_CMR_BCPC_Pos) 632 #define TC_CMR_BCPC_TOGGLE (TC_CMR_BCPC_TOGGLE_Val << TC_CMR_BCPC_Pos) 633 #define TC_CMR_BEEVT_Pos 28 /**< \brief (TC_CMR) External Event Effect on TIOB */ 634 #define TC_CMR_BEEVT_Msk (_U_(0x3) << TC_CMR_BEEVT_Pos) 635 #define TC_CMR_BEEVT(value) (TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos)) 636 #define TC_CMR_BEEVT_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 637 #define TC_CMR_BEEVT_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 638 #define TC_CMR_BEEVT_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 639 #define TC_CMR_BEEVT_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 640 #define TC_CMR_BEEVT_NONE (TC_CMR_BEEVT_NONE_Val << TC_CMR_BEEVT_Pos) 641 #define TC_CMR_BEEVT_SET (TC_CMR_BEEVT_SET_Val << TC_CMR_BEEVT_Pos) 642 #define TC_CMR_BEEVT_CLEAR (TC_CMR_BEEVT_CLEAR_Val << TC_CMR_BEEVT_Pos) 643 #define TC_CMR_BEEVT_TOGGLE (TC_CMR_BEEVT_TOGGLE_Val << TC_CMR_BEEVT_Pos) 644 #define TC_CMR_BSWTRG_Pos 30 /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ 645 #define TC_CMR_BSWTRG_Msk (_U_(0x3) << TC_CMR_BSWTRG_Pos) 646 #define TC_CMR_BSWTRG(value) (TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos)) 647 #define TC_CMR_BSWTRG_NONE_Val _U_(0x0) /**< \brief (TC_CMR) none */ 648 #define TC_CMR_BSWTRG_SET_Val _U_(0x1) /**< \brief (TC_CMR) set */ 649 #define TC_CMR_BSWTRG_CLEAR_Val _U_(0x2) /**< \brief (TC_CMR) clear */ 650 #define TC_CMR_BSWTRG_TOGGLE_Val _U_(0x3) /**< \brief (TC_CMR) toggle */ 651 #define TC_CMR_BSWTRG_NONE (TC_CMR_BSWTRG_NONE_Val << TC_CMR_BSWTRG_Pos) 652 #define TC_CMR_BSWTRG_SET (TC_CMR_BSWTRG_SET_Val << TC_CMR_BSWTRG_Pos) 653 #define TC_CMR_BSWTRG_CLEAR (TC_CMR_BSWTRG_CLEAR_Val << TC_CMR_BSWTRG_Pos) 654 #define TC_CMR_BSWTRG_TOGGLE (TC_CMR_BSWTRG_TOGGLE_Val << TC_CMR_BSWTRG_Pos) 655 #define TC_CMR_MASK _U_(0xFFFFFFFF) /**< \brief (TC_CMR) MASK Register */ 656 657 /* -------- TC_SMMR : (TC Offset: 0x08) (R/W 32) channel Stepper Motor Mode Register -------- */ 658 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 659 typedef union { 660 struct { 661 uint32_t GCEN:1; /*!< bit: 0 Gray Count Enable */ 662 uint32_t DOWN:1; /*!< bit: 1 Down Count */ 663 uint32_t :30; /*!< bit: 2..31 Reserved */ 664 } bit; /*!< Structure used for bit access */ 665 uint32_t reg; /*!< Type used for register access */ 666 } TC_SMMR_Type; 667 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 668 669 #define TC_SMMR_OFFSET 0x08 /**< \brief (TC_SMMR offset) Stepper Motor Mode Register */ 670 #define TC_SMMR_RESETVALUE _U_(0x00000000); /**< \brief (TC_SMMR reset_value) Stepper Motor Mode Register */ 671 672 #define TC_SMMR_GCEN_Pos 0 /**< \brief (TC_SMMR) Gray Count Enable */ 673 #define TC_SMMR_GCEN (_U_(0x1) << TC_SMMR_GCEN_Pos) 674 #define TC_SMMR_DOWN_Pos 1 /**< \brief (TC_SMMR) Down Count */ 675 #define TC_SMMR_DOWN (_U_(0x1) << TC_SMMR_DOWN_Pos) 676 #define TC_SMMR_MASK _U_(0x00000003) /**< \brief (TC_SMMR) MASK Register */ 677 678 /* -------- TC_CV : (TC Offset: 0x10) (R/ 32) channel Counter Value Channel -------- */ 679 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 680 typedef union { 681 struct { 682 uint32_t CV:16; /*!< bit: 0..15 Counter Value */ 683 uint32_t :16; /*!< bit: 16..31 Reserved */ 684 } bit; /*!< Structure used for bit access */ 685 uint32_t reg; /*!< Type used for register access */ 686 } TC_CV_Type; 687 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 688 689 #define TC_CV_OFFSET 0x10 /**< \brief (TC_CV offset) Counter Value Channel */ 690 #define TC_CV_RESETVALUE _U_(0x00000000); /**< \brief (TC_CV reset_value) Counter Value Channel */ 691 692 #define TC_CV_CV_Pos 0 /**< \brief (TC_CV) Counter Value */ 693 #define TC_CV_CV_Msk (_U_(0xFFFF) << TC_CV_CV_Pos) 694 #define TC_CV_CV(value) (TC_CV_CV_Msk & ((value) << TC_CV_CV_Pos)) 695 #define TC_CV_MASK _U_(0x0000FFFF) /**< \brief (TC_CV) MASK Register */ 696 697 /* -------- TC_RA : (TC Offset: 0x14) (R/W 32) channel Register A Channel -------- */ 698 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 699 typedef union { 700 struct { 701 uint32_t RA:16; /*!< bit: 0..15 Register A */ 702 uint32_t :16; /*!< bit: 16..31 Reserved */ 703 } bit; /*!< Structure used for bit access */ 704 uint32_t reg; /*!< Type used for register access */ 705 } TC_RA_Type; 706 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 707 708 #define TC_RA_OFFSET 0x14 /**< \brief (TC_RA offset) Register A Channel */ 709 #define TC_RA_RESETVALUE _U_(0x00000000); /**< \brief (TC_RA reset_value) Register A Channel */ 710 711 #define TC_RA_RA_Pos 0 /**< \brief (TC_RA) Register A */ 712 #define TC_RA_RA_Msk (_U_(0xFFFF) << TC_RA_RA_Pos) 713 #define TC_RA_RA(value) (TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)) 714 #define TC_RA_MASK _U_(0x0000FFFF) /**< \brief (TC_RA) MASK Register */ 715 716 /* -------- TC_RB : (TC Offset: 0x18) (R/W 32) channel Register B Channel -------- */ 717 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 718 typedef union { 719 struct { 720 uint32_t RB:16; /*!< bit: 0..15 Register B */ 721 uint32_t :16; /*!< bit: 16..31 Reserved */ 722 } bit; /*!< Structure used for bit access */ 723 uint32_t reg; /*!< Type used for register access */ 724 } TC_RB_Type; 725 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 726 727 #define TC_RB_OFFSET 0x18 /**< \brief (TC_RB offset) Register B Channel */ 728 #define TC_RB_RESETVALUE _U_(0x00000000); /**< \brief (TC_RB reset_value) Register B Channel */ 729 730 #define TC_RB_RB_Pos 0 /**< \brief (TC_RB) Register B */ 731 #define TC_RB_RB_Msk (_U_(0xFFFF) << TC_RB_RB_Pos) 732 #define TC_RB_RB(value) (TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)) 733 #define TC_RB_MASK _U_(0x0000FFFF) /**< \brief (TC_RB) MASK Register */ 734 735 /* -------- TC_RC : (TC Offset: 0x1C) (R/W 32) channel Register C Channel -------- */ 736 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 737 typedef union { 738 struct { 739 uint32_t RC:16; /*!< bit: 0..15 Register C */ 740 uint32_t :16; /*!< bit: 16..31 Reserved */ 741 } bit; /*!< Structure used for bit access */ 742 uint32_t reg; /*!< Type used for register access */ 743 } TC_RC_Type; 744 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 745 746 #define TC_RC_OFFSET 0x1C /**< \brief (TC_RC offset) Register C Channel */ 747 #define TC_RC_RESETVALUE _U_(0x00000000); /**< \brief (TC_RC reset_value) Register C Channel */ 748 749 #define TC_RC_RC_Pos 0 /**< \brief (TC_RC) Register C */ 750 #define TC_RC_RC_Msk (_U_(0xFFFF) << TC_RC_RC_Pos) 751 #define TC_RC_RC(value) (TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)) 752 #define TC_RC_MASK _U_(0x0000FFFF) /**< \brief (TC_RC) MASK Register */ 753 754 /* -------- TC_SR : (TC Offset: 0x20) (R/ 32) channel Status Register Channel -------- */ 755 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 756 typedef union { 757 struct { 758 uint32_t COVFS:1; /*!< bit: 0 Counter Overflow Status */ 759 uint32_t LOVRS:1; /*!< bit: 1 Load Overrun Status */ 760 uint32_t CPAS:1; /*!< bit: 2 RA Compare Status */ 761 uint32_t CPBS:1; /*!< bit: 3 RB Compare Status */ 762 uint32_t CPCS:1; /*!< bit: 4 RC Compare Status */ 763 uint32_t LDRAS:1; /*!< bit: 5 RA Loading Status */ 764 uint32_t LDRBS:1; /*!< bit: 6 RB Loading Status */ 765 uint32_t ETRGS:1; /*!< bit: 7 External Trigger Status */ 766 uint32_t :8; /*!< bit: 8..15 Reserved */ 767 uint32_t CLKSTA:1; /*!< bit: 16 Clock Enabling Status */ 768 uint32_t MTIOA:1; /*!< bit: 17 TIOA Mirror */ 769 uint32_t MTIOB:1; /*!< bit: 18 TIOB Mirror */ 770 uint32_t :13; /*!< bit: 19..31 Reserved */ 771 } bit; /*!< Structure used for bit access */ 772 uint32_t reg; /*!< Type used for register access */ 773 } TC_SR_Type; 774 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 775 776 #define TC_SR_OFFSET 0x20 /**< \brief (TC_SR offset) Status Register Channel */ 777 #define TC_SR_RESETVALUE _U_(0x00000000); /**< \brief (TC_SR reset_value) Status Register Channel */ 778 779 #define TC_SR_COVFS_Pos 0 /**< \brief (TC_SR) Counter Overflow Status */ 780 #define TC_SR_COVFS (_U_(0x1) << TC_SR_COVFS_Pos) 781 #define TC_SR_COVFS_0_Val _U_(0x0) /**< \brief (TC_SR) No counter overflow has occurred since the last read of the Status Register. */ 782 #define TC_SR_COVFS_1_Val _U_(0x1) /**< \brief (TC_SR) A counter overflow has occurred since the last read of the Status Register. */ 783 #define TC_SR_COVFS_0 (TC_SR_COVFS_0_Val << TC_SR_COVFS_Pos) 784 #define TC_SR_COVFS_1 (TC_SR_COVFS_1_Val << TC_SR_COVFS_Pos) 785 #define TC_SR_LOVRS_Pos 1 /**< \brief (TC_SR) Load Overrun Status */ 786 #define TC_SR_LOVRS (_U_(0x1) << TC_SR_LOVRS_Pos) 787 #define TC_SR_LOVRS_0_Val _U_(0x0) /**< \brief (TC_SR) Load overrun has not occurred since the last read of the Status Register or WAVE:1. */ 788 #define TC_SR_LOVRS_1_Val _U_(0x1) /**< \brief (TC_SR) RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the StatusRegister, if WAVE:0. */ 789 #define TC_SR_LOVRS_0 (TC_SR_LOVRS_0_Val << TC_SR_LOVRS_Pos) 790 #define TC_SR_LOVRS_1 (TC_SR_LOVRS_1_Val << TC_SR_LOVRS_Pos) 791 #define TC_SR_CPAS_Pos 2 /**< \brief (TC_SR) RA Compare Status */ 792 #define TC_SR_CPAS (_U_(0x1) << TC_SR_CPAS_Pos) 793 #define TC_SR_CPAS_0_Val _U_(0x0) /**< \brief (TC_SR) RA Compare has not occurred since the last read of the Status Register or WAVE:0. */ 794 #define TC_SR_CPAS_1_Val _U_(0x1) /**< \brief (TC_SR) RA Compare has occurred since the last read of the Status Register, if WAVE:1. */ 795 #define TC_SR_CPAS_0 (TC_SR_CPAS_0_Val << TC_SR_CPAS_Pos) 796 #define TC_SR_CPAS_1 (TC_SR_CPAS_1_Val << TC_SR_CPAS_Pos) 797 #define TC_SR_CPBS_Pos 3 /**< \brief (TC_SR) RB Compare Status */ 798 #define TC_SR_CPBS (_U_(0x1) << TC_SR_CPBS_Pos) 799 #define TC_SR_CPBS_0_Val _U_(0x0) /**< \brief (TC_SR) RB Compare has not occurred since the last read of the Status Register or WAVE:0. */ 800 #define TC_SR_CPBS_1_Val _U_(0x1) /**< \brief (TC_SR) RB Compare has occurred since the last read of the Status Register, if WAVE:1. */ 801 #define TC_SR_CPBS_0 (TC_SR_CPBS_0_Val << TC_SR_CPBS_Pos) 802 #define TC_SR_CPBS_1 (TC_SR_CPBS_1_Val << TC_SR_CPBS_Pos) 803 #define TC_SR_CPCS_Pos 4 /**< \brief (TC_SR) RC Compare Status */ 804 #define TC_SR_CPCS (_U_(0x1) << TC_SR_CPCS_Pos) 805 #define TC_SR_CPCS_0_Val _U_(0x0) /**< \brief (TC_SR) RC Compare has not occurred since the last read of the Status Register. */ 806 #define TC_SR_CPCS_1_Val _U_(0x1) /**< \brief (TC_SR) RC Compare has occurred since the last read of the Status Register. */ 807 #define TC_SR_CPCS_0 (TC_SR_CPCS_0_Val << TC_SR_CPCS_Pos) 808 #define TC_SR_CPCS_1 (TC_SR_CPCS_1_Val << TC_SR_CPCS_Pos) 809 #define TC_SR_LDRAS_Pos 5 /**< \brief (TC_SR) RA Loading Status */ 810 #define TC_SR_LDRAS (_U_(0x1) << TC_SR_LDRAS_Pos) 811 #define TC_SR_LDRAS_0_Val _U_(0x0) /**< \brief (TC_SR) RA Load has not occurred since the last read of the Status Register or WAVE:1. */ 812 #define TC_SR_LDRAS_1_Val _U_(0x1) /**< \brief (TC_SR) RA Load has occurred since the last read of the Status Register, if WAVE:0. */ 813 #define TC_SR_LDRAS_0 (TC_SR_LDRAS_0_Val << TC_SR_LDRAS_Pos) 814 #define TC_SR_LDRAS_1 (TC_SR_LDRAS_1_Val << TC_SR_LDRAS_Pos) 815 #define TC_SR_LDRBS_Pos 6 /**< \brief (TC_SR) RB Loading Status */ 816 #define TC_SR_LDRBS (_U_(0x1) << TC_SR_LDRBS_Pos) 817 #define TC_SR_LDRBS_0_Val _U_(0x0) /**< \brief (TC_SR) RB Load has not occurred since the last read of the Status Register or WAVE:1. */ 818 #define TC_SR_LDRBS_1_Val _U_(0x1) /**< \brief (TC_SR) RB Load has occurred since the last read of the Status Register, if WAVE:0. */ 819 #define TC_SR_LDRBS_0 (TC_SR_LDRBS_0_Val << TC_SR_LDRBS_Pos) 820 #define TC_SR_LDRBS_1 (TC_SR_LDRBS_1_Val << TC_SR_LDRBS_Pos) 821 #define TC_SR_ETRGS_Pos 7 /**< \brief (TC_SR) External Trigger Status */ 822 #define TC_SR_ETRGS (_U_(0x1) << TC_SR_ETRGS_Pos) 823 #define TC_SR_ETRGS_0_Val _U_(0x0) /**< \brief (TC_SR) External trigger has not occurred since the last read of the Status Register. */ 824 #define TC_SR_ETRGS_1_Val _U_(0x1) /**< \brief (TC_SR) External trigger has occurred since the last read of the Status Register. */ 825 #define TC_SR_ETRGS_0 (TC_SR_ETRGS_0_Val << TC_SR_ETRGS_Pos) 826 #define TC_SR_ETRGS_1 (TC_SR_ETRGS_1_Val << TC_SR_ETRGS_Pos) 827 #define TC_SR_CLKSTA_Pos 16 /**< \brief (TC_SR) Clock Enabling Status */ 828 #define TC_SR_CLKSTA (_U_(0x1) << TC_SR_CLKSTA_Pos) 829 #define TC_SR_CLKSTA_0_Val _U_(0x0) /**< \brief (TC_SR) Clock is disabled. */ 830 #define TC_SR_CLKSTA_1_Val _U_(0x1) /**< \brief (TC_SR) Clock is enabled. */ 831 #define TC_SR_CLKSTA_0 (TC_SR_CLKSTA_0_Val << TC_SR_CLKSTA_Pos) 832 #define TC_SR_CLKSTA_1 (TC_SR_CLKSTA_1_Val << TC_SR_CLKSTA_Pos) 833 #define TC_SR_MTIOA_Pos 17 /**< \brief (TC_SR) TIOA Mirror */ 834 #define TC_SR_MTIOA (_U_(0x1) << TC_SR_MTIOA_Pos) 835 #define TC_SR_MTIOA_0_Val _U_(0x0) /**< \brief (TC_SR) TIOA is low. If WAVE:0, this means that TIOA pin is low. If WAVE:1, this means that TIOA is driven low. */ 836 #define TC_SR_MTIOA_1_Val _U_(0x1) /**< \brief (TC_SR) TIOA is high. If WAVE:0, this means that TIOA pin is high. If WAVE:1, this means that TIOA is driven high. */ 837 #define TC_SR_MTIOA_0 (TC_SR_MTIOA_0_Val << TC_SR_MTIOA_Pos) 838 #define TC_SR_MTIOA_1 (TC_SR_MTIOA_1_Val << TC_SR_MTIOA_Pos) 839 #define TC_SR_MTIOB_Pos 18 /**< \brief (TC_SR) TIOB Mirror */ 840 #define TC_SR_MTIOB (_U_(0x1) << TC_SR_MTIOB_Pos) 841 #define TC_SR_MTIOB_0_Val _U_(0x0) /**< \brief (TC_SR) TIOB is low. If WAVE:0, this means that TIOB pin is low. If WAVE:1, this means that TIOB is driven low. */ 842 #define TC_SR_MTIOB_1_Val _U_(0x1) /**< \brief (TC_SR) TIOB is high. If WAVE:0, this means that TIOB pin is high. If WAVE:1, this means that TIOB is driven high. */ 843 #define TC_SR_MTIOB_0 (TC_SR_MTIOB_0_Val << TC_SR_MTIOB_Pos) 844 #define TC_SR_MTIOB_1 (TC_SR_MTIOB_1_Val << TC_SR_MTIOB_Pos) 845 #define TC_SR_MASK _U_(0x000700FF) /**< \brief (TC_SR) MASK Register */ 846 847 /* -------- TC_IER : (TC Offset: 0x24) ( /W 32) channel Interrupt Enable Register Channel -------- */ 848 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 849 typedef union { 850 struct { 851 uint32_t COVFS:1; /*!< bit: 0 Counter Overflow */ 852 uint32_t LOVRS:1; /*!< bit: 1 Load Overrun */ 853 uint32_t CPAS:1; /*!< bit: 2 RA Compare */ 854 uint32_t CPBS:1; /*!< bit: 3 RB Compare */ 855 uint32_t CPCS:1; /*!< bit: 4 RC Compare */ 856 uint32_t LDRAS:1; /*!< bit: 5 RA Loading */ 857 uint32_t LDRBS:1; /*!< bit: 6 RB Loading */ 858 uint32_t ETRGS:1; /*!< bit: 7 External Trigger */ 859 uint32_t :24; /*!< bit: 8..31 Reserved */ 860 } bit; /*!< Structure used for bit access */ 861 uint32_t reg; /*!< Type used for register access */ 862 } TC_IER_Type; 863 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 864 865 #define TC_IER_OFFSET 0x24 /**< \brief (TC_IER offset) Interrupt Enable Register Channel */ 866 #define TC_IER_RESETVALUE _U_(0x00000000); /**< \brief (TC_IER reset_value) Interrupt Enable Register Channel */ 867 868 #define TC_IER_COVFS_Pos 0 /**< \brief (TC_IER) Counter Overflow */ 869 #define TC_IER_COVFS (_U_(0x1) << TC_IER_COVFS_Pos) 870 #define TC_IER_COVFS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 871 #define TC_IER_COVFS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the Counter Overflow Interrupt. */ 872 #define TC_IER_COVFS_0 (TC_IER_COVFS_0_Val << TC_IER_COVFS_Pos) 873 #define TC_IER_COVFS_1 (TC_IER_COVFS_1_Val << TC_IER_COVFS_Pos) 874 #define TC_IER_LOVRS_Pos 1 /**< \brief (TC_IER) Load Overrun */ 875 #define TC_IER_LOVRS (_U_(0x1) << TC_IER_LOVRS_Pos) 876 #define TC_IER_LOVRS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 877 #define TC_IER_LOVRS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the Load Overrun Interrupt. */ 878 #define TC_IER_LOVRS_0 (TC_IER_LOVRS_0_Val << TC_IER_LOVRS_Pos) 879 #define TC_IER_LOVRS_1 (TC_IER_LOVRS_1_Val << TC_IER_LOVRS_Pos) 880 #define TC_IER_CPAS_Pos 2 /**< \brief (TC_IER) RA Compare */ 881 #define TC_IER_CPAS (_U_(0x1) << TC_IER_CPAS_Pos) 882 #define TC_IER_CPAS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 883 #define TC_IER_CPAS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the RA Compare Interrupt. */ 884 #define TC_IER_CPAS_0 (TC_IER_CPAS_0_Val << TC_IER_CPAS_Pos) 885 #define TC_IER_CPAS_1 (TC_IER_CPAS_1_Val << TC_IER_CPAS_Pos) 886 #define TC_IER_CPBS_Pos 3 /**< \brief (TC_IER) RB Compare */ 887 #define TC_IER_CPBS (_U_(0x1) << TC_IER_CPBS_Pos) 888 #define TC_IER_CPBS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 889 #define TC_IER_CPBS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the RB Compare Interrupt. */ 890 #define TC_IER_CPBS_0 (TC_IER_CPBS_0_Val << TC_IER_CPBS_Pos) 891 #define TC_IER_CPBS_1 (TC_IER_CPBS_1_Val << TC_IER_CPBS_Pos) 892 #define TC_IER_CPCS_Pos 4 /**< \brief (TC_IER) RC Compare */ 893 #define TC_IER_CPCS (_U_(0x1) << TC_IER_CPCS_Pos) 894 #define TC_IER_CPCS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 895 #define TC_IER_CPCS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the RC Compare Interrupt. */ 896 #define TC_IER_CPCS_0 (TC_IER_CPCS_0_Val << TC_IER_CPCS_Pos) 897 #define TC_IER_CPCS_1 (TC_IER_CPCS_1_Val << TC_IER_CPCS_Pos) 898 #define TC_IER_LDRAS_Pos 5 /**< \brief (TC_IER) RA Loading */ 899 #define TC_IER_LDRAS (_U_(0x1) << TC_IER_LDRAS_Pos) 900 #define TC_IER_LDRAS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 901 #define TC_IER_LDRAS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the RA Load Interrupt. */ 902 #define TC_IER_LDRAS_0 (TC_IER_LDRAS_0_Val << TC_IER_LDRAS_Pos) 903 #define TC_IER_LDRAS_1 (TC_IER_LDRAS_1_Val << TC_IER_LDRAS_Pos) 904 #define TC_IER_LDRBS_Pos 6 /**< \brief (TC_IER) RB Loading */ 905 #define TC_IER_LDRBS (_U_(0x1) << TC_IER_LDRBS_Pos) 906 #define TC_IER_LDRBS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 907 #define TC_IER_LDRBS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the RB Load Interrupt. */ 908 #define TC_IER_LDRBS_0 (TC_IER_LDRBS_0_Val << TC_IER_LDRBS_Pos) 909 #define TC_IER_LDRBS_1 (TC_IER_LDRBS_1_Val << TC_IER_LDRBS_Pos) 910 #define TC_IER_ETRGS_Pos 7 /**< \brief (TC_IER) External Trigger */ 911 #define TC_IER_ETRGS (_U_(0x1) << TC_IER_ETRGS_Pos) 912 #define TC_IER_ETRGS_0_Val _U_(0x0) /**< \brief (TC_IER) No effect. */ 913 #define TC_IER_ETRGS_1_Val _U_(0x1) /**< \brief (TC_IER) Enables the External Trigger Interrupt. */ 914 #define TC_IER_ETRGS_0 (TC_IER_ETRGS_0_Val << TC_IER_ETRGS_Pos) 915 #define TC_IER_ETRGS_1 (TC_IER_ETRGS_1_Val << TC_IER_ETRGS_Pos) 916 #define TC_IER_MASK _U_(0x000000FF) /**< \brief (TC_IER) MASK Register */ 917 918 /* -------- TC_IDR : (TC Offset: 0x28) ( /W 32) channel Interrupt Disable Register Channel -------- */ 919 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 920 typedef union { 921 struct { 922 uint32_t COVFS:1; /*!< bit: 0 Counter Overflow */ 923 uint32_t LOVRS:1; /*!< bit: 1 Load Overrun */ 924 uint32_t CPAS:1; /*!< bit: 2 RA Compare */ 925 uint32_t CPBS:1; /*!< bit: 3 RB Compare */ 926 uint32_t CPCS:1; /*!< bit: 4 RC Compare */ 927 uint32_t LDRAS:1; /*!< bit: 5 RA Loading */ 928 uint32_t LDRBS:1; /*!< bit: 6 RB Loading */ 929 uint32_t ETRGS:1; /*!< bit: 7 External Trigger */ 930 uint32_t :24; /*!< bit: 8..31 Reserved */ 931 } bit; /*!< Structure used for bit access */ 932 uint32_t reg; /*!< Type used for register access */ 933 } TC_IDR_Type; 934 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 935 936 #define TC_IDR_OFFSET 0x28 /**< \brief (TC_IDR offset) Interrupt Disable Register Channel */ 937 #define TC_IDR_RESETVALUE _U_(0x00000000); /**< \brief (TC_IDR reset_value) Interrupt Disable Register Channel */ 938 939 #define TC_IDR_COVFS_Pos 0 /**< \brief (TC_IDR) Counter Overflow */ 940 #define TC_IDR_COVFS (_U_(0x1) << TC_IDR_COVFS_Pos) 941 #define TC_IDR_COVFS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 942 #define TC_IDR_COVFS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the Counter Overflow Interrupt. */ 943 #define TC_IDR_COVFS_0 (TC_IDR_COVFS_0_Val << TC_IDR_COVFS_Pos) 944 #define TC_IDR_COVFS_1 (TC_IDR_COVFS_1_Val << TC_IDR_COVFS_Pos) 945 #define TC_IDR_LOVRS_Pos 1 /**< \brief (TC_IDR) Load Overrun */ 946 #define TC_IDR_LOVRS (_U_(0x1) << TC_IDR_LOVRS_Pos) 947 #define TC_IDR_LOVRS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 948 #define TC_IDR_LOVRS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the Load Overrun Interrupt (if WAVE:0). */ 949 #define TC_IDR_LOVRS_0 (TC_IDR_LOVRS_0_Val << TC_IDR_LOVRS_Pos) 950 #define TC_IDR_LOVRS_1 (TC_IDR_LOVRS_1_Val << TC_IDR_LOVRS_Pos) 951 #define TC_IDR_CPAS_Pos 2 /**< \brief (TC_IDR) RA Compare */ 952 #define TC_IDR_CPAS (_U_(0x1) << TC_IDR_CPAS_Pos) 953 #define TC_IDR_CPAS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 954 #define TC_IDR_CPAS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the RA Compare Interrupt (if WAVE:1). */ 955 #define TC_IDR_CPAS_0 (TC_IDR_CPAS_0_Val << TC_IDR_CPAS_Pos) 956 #define TC_IDR_CPAS_1 (TC_IDR_CPAS_1_Val << TC_IDR_CPAS_Pos) 957 #define TC_IDR_CPBS_Pos 3 /**< \brief (TC_IDR) RB Compare */ 958 #define TC_IDR_CPBS (_U_(0x1) << TC_IDR_CPBS_Pos) 959 #define TC_IDR_CPBS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 960 #define TC_IDR_CPBS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the RB Compare Interrupt (if WAVE:1). */ 961 #define TC_IDR_CPBS_0 (TC_IDR_CPBS_0_Val << TC_IDR_CPBS_Pos) 962 #define TC_IDR_CPBS_1 (TC_IDR_CPBS_1_Val << TC_IDR_CPBS_Pos) 963 #define TC_IDR_CPCS_Pos 4 /**< \brief (TC_IDR) RC Compare */ 964 #define TC_IDR_CPCS (_U_(0x1) << TC_IDR_CPCS_Pos) 965 #define TC_IDR_CPCS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 966 #define TC_IDR_CPCS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the RC Compare Interrupt. */ 967 #define TC_IDR_CPCS_0 (TC_IDR_CPCS_0_Val << TC_IDR_CPCS_Pos) 968 #define TC_IDR_CPCS_1 (TC_IDR_CPCS_1_Val << TC_IDR_CPCS_Pos) 969 #define TC_IDR_LDRAS_Pos 5 /**< \brief (TC_IDR) RA Loading */ 970 #define TC_IDR_LDRAS (_U_(0x1) << TC_IDR_LDRAS_Pos) 971 #define TC_IDR_LDRAS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 972 #define TC_IDR_LDRAS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the RA Load Interrupt (if WAVE:0). */ 973 #define TC_IDR_LDRAS_0 (TC_IDR_LDRAS_0_Val << TC_IDR_LDRAS_Pos) 974 #define TC_IDR_LDRAS_1 (TC_IDR_LDRAS_1_Val << TC_IDR_LDRAS_Pos) 975 #define TC_IDR_LDRBS_Pos 6 /**< \brief (TC_IDR) RB Loading */ 976 #define TC_IDR_LDRBS (_U_(0x1) << TC_IDR_LDRBS_Pos) 977 #define TC_IDR_LDRBS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 978 #define TC_IDR_LDRBS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the RB Load Interrupt (if WAVE:0). */ 979 #define TC_IDR_LDRBS_0 (TC_IDR_LDRBS_0_Val << TC_IDR_LDRBS_Pos) 980 #define TC_IDR_LDRBS_1 (TC_IDR_LDRBS_1_Val << TC_IDR_LDRBS_Pos) 981 #define TC_IDR_ETRGS_Pos 7 /**< \brief (TC_IDR) External Trigger */ 982 #define TC_IDR_ETRGS (_U_(0x1) << TC_IDR_ETRGS_Pos) 983 #define TC_IDR_ETRGS_0_Val _U_(0x0) /**< \brief (TC_IDR) No effect. */ 984 #define TC_IDR_ETRGS_1_Val _U_(0x1) /**< \brief (TC_IDR) Disables the External Trigger Interrupt. */ 985 #define TC_IDR_ETRGS_0 (TC_IDR_ETRGS_0_Val << TC_IDR_ETRGS_Pos) 986 #define TC_IDR_ETRGS_1 (TC_IDR_ETRGS_1_Val << TC_IDR_ETRGS_Pos) 987 #define TC_IDR_MASK _U_(0x000000FF) /**< \brief (TC_IDR) MASK Register */ 988 989 /* -------- TC_IMR : (TC Offset: 0x2C) (R/ 32) channel Interrupt Mask Register Channel -------- */ 990 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 991 typedef union { 992 struct { 993 uint32_t COVFS:1; /*!< bit: 0 Counter Overflow */ 994 uint32_t LOVRS:1; /*!< bit: 1 Load Overrun */ 995 uint32_t CPAS:1; /*!< bit: 2 RA Compare */ 996 uint32_t CPBS:1; /*!< bit: 3 RB Compare */ 997 uint32_t CPCS:1; /*!< bit: 4 RC Compare */ 998 uint32_t LDRAS:1; /*!< bit: 5 RA Loading */ 999 uint32_t LDRBS:1; /*!< bit: 6 RB Loading */ 1000 uint32_t ETRGS:1; /*!< bit: 7 External Trigger */ 1001 uint32_t :24; /*!< bit: 8..31 Reserved */ 1002 } bit; /*!< Structure used for bit access */ 1003 uint32_t reg; /*!< Type used for register access */ 1004 } TC_IMR_Type; 1005 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1006 1007 #define TC_IMR_OFFSET 0x2C /**< \brief (TC_IMR offset) Interrupt Mask Register Channel */ 1008 #define TC_IMR_RESETVALUE _U_(0x00000000); /**< \brief (TC_IMR reset_value) Interrupt Mask Register Channel */ 1009 1010 #define TC_IMR_COVFS_Pos 0 /**< \brief (TC_IMR) Counter Overflow */ 1011 #define TC_IMR_COVFS (_U_(0x1) << TC_IMR_COVFS_Pos) 1012 #define TC_IMR_COVFS_0_Val _U_(0x0) /**< \brief (TC_IMR) The Counter Overflow Interrupt is disabled. */ 1013 #define TC_IMR_COVFS_1_Val _U_(0x1) /**< \brief (TC_IMR) The Counter Overflow Interrupt is enabled. */ 1014 #define TC_IMR_COVFS_0 (TC_IMR_COVFS_0_Val << TC_IMR_COVFS_Pos) 1015 #define TC_IMR_COVFS_1 (TC_IMR_COVFS_1_Val << TC_IMR_COVFS_Pos) 1016 #define TC_IMR_LOVRS_Pos 1 /**< \brief (TC_IMR) Load Overrun */ 1017 #define TC_IMR_LOVRS (_U_(0x1) << TC_IMR_LOVRS_Pos) 1018 #define TC_IMR_LOVRS_0_Val _U_(0x0) /**< \brief (TC_IMR) The Load Overrun Interrupt is disabled. */ 1019 #define TC_IMR_LOVRS_1_Val _U_(0x1) /**< \brief (TC_IMR) The Load Overrun Interrupt is enabled. */ 1020 #define TC_IMR_LOVRS_0 (TC_IMR_LOVRS_0_Val << TC_IMR_LOVRS_Pos) 1021 #define TC_IMR_LOVRS_1 (TC_IMR_LOVRS_1_Val << TC_IMR_LOVRS_Pos) 1022 #define TC_IMR_CPAS_Pos 2 /**< \brief (TC_IMR) RA Compare */ 1023 #define TC_IMR_CPAS (_U_(0x1) << TC_IMR_CPAS_Pos) 1024 #define TC_IMR_CPAS_0_Val _U_(0x0) /**< \brief (TC_IMR) The RA Compare Interrupt is disabled. */ 1025 #define TC_IMR_CPAS_1_Val _U_(0x1) /**< \brief (TC_IMR) The RA Compare Interrupt is enabled. */ 1026 #define TC_IMR_CPAS_0 (TC_IMR_CPAS_0_Val << TC_IMR_CPAS_Pos) 1027 #define TC_IMR_CPAS_1 (TC_IMR_CPAS_1_Val << TC_IMR_CPAS_Pos) 1028 #define TC_IMR_CPBS_Pos 3 /**< \brief (TC_IMR) RB Compare */ 1029 #define TC_IMR_CPBS (_U_(0x1) << TC_IMR_CPBS_Pos) 1030 #define TC_IMR_CPBS_0_Val _U_(0x0) /**< \brief (TC_IMR) The RB Compare Interrupt is disabled. */ 1031 #define TC_IMR_CPBS_1_Val _U_(0x1) /**< \brief (TC_IMR) The RB Compare Interrupt is enabled. */ 1032 #define TC_IMR_CPBS_0 (TC_IMR_CPBS_0_Val << TC_IMR_CPBS_Pos) 1033 #define TC_IMR_CPBS_1 (TC_IMR_CPBS_1_Val << TC_IMR_CPBS_Pos) 1034 #define TC_IMR_CPCS_Pos 4 /**< \brief (TC_IMR) RC Compare */ 1035 #define TC_IMR_CPCS (_U_(0x1) << TC_IMR_CPCS_Pos) 1036 #define TC_IMR_CPCS_0_Val _U_(0x0) /**< \brief (TC_IMR) The RC Compare Interrupt is disabled. */ 1037 #define TC_IMR_CPCS_1_Val _U_(0x1) /**< \brief (TC_IMR) The RC Compare Interrupt is enabled. */ 1038 #define TC_IMR_CPCS_0 (TC_IMR_CPCS_0_Val << TC_IMR_CPCS_Pos) 1039 #define TC_IMR_CPCS_1 (TC_IMR_CPCS_1_Val << TC_IMR_CPCS_Pos) 1040 #define TC_IMR_LDRAS_Pos 5 /**< \brief (TC_IMR) RA Loading */ 1041 #define TC_IMR_LDRAS (_U_(0x1) << TC_IMR_LDRAS_Pos) 1042 #define TC_IMR_LDRAS_0_Val _U_(0x0) /**< \brief (TC_IMR) The Load RA Interrupt is disabled. */ 1043 #define TC_IMR_LDRAS_1_Val _U_(0x1) /**< \brief (TC_IMR) The Load RA Interrupt is enabled. */ 1044 #define TC_IMR_LDRAS_0 (TC_IMR_LDRAS_0_Val << TC_IMR_LDRAS_Pos) 1045 #define TC_IMR_LDRAS_1 (TC_IMR_LDRAS_1_Val << TC_IMR_LDRAS_Pos) 1046 #define TC_IMR_LDRBS_Pos 6 /**< \brief (TC_IMR) RB Loading */ 1047 #define TC_IMR_LDRBS (_U_(0x1) << TC_IMR_LDRBS_Pos) 1048 #define TC_IMR_LDRBS_0_Val _U_(0x0) /**< \brief (TC_IMR) The Load RB Interrupt is disabled. */ 1049 #define TC_IMR_LDRBS_1_Val _U_(0x1) /**< \brief (TC_IMR) The Load RB Interrupt is enabled. */ 1050 #define TC_IMR_LDRBS_0 (TC_IMR_LDRBS_0_Val << TC_IMR_LDRBS_Pos) 1051 #define TC_IMR_LDRBS_1 (TC_IMR_LDRBS_1_Val << TC_IMR_LDRBS_Pos) 1052 #define TC_IMR_ETRGS_Pos 7 /**< \brief (TC_IMR) External Trigger */ 1053 #define TC_IMR_ETRGS (_U_(0x1) << TC_IMR_ETRGS_Pos) 1054 #define TC_IMR_ETRGS_0_Val _U_(0x0) /**< \brief (TC_IMR) The External Trigger Interrupt is disabled. */ 1055 #define TC_IMR_ETRGS_1_Val _U_(0x1) /**< \brief (TC_IMR) The External Trigger Interrupt is enabled. */ 1056 #define TC_IMR_ETRGS_0 (TC_IMR_ETRGS_0_Val << TC_IMR_ETRGS_Pos) 1057 #define TC_IMR_ETRGS_1 (TC_IMR_ETRGS_1_Val << TC_IMR_ETRGS_Pos) 1058 #define TC_IMR_MASK _U_(0x000000FF) /**< \brief (TC_IMR) MASK Register */ 1059 1060 /* -------- TC_BCR : (TC Offset: 0xC0) ( /W 32) TC Block Control Register -------- */ 1061 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1062 typedef union { 1063 struct { 1064 uint32_t SYNC:1; /*!< bit: 0 Synchro Command */ 1065 uint32_t :31; /*!< bit: 1..31 Reserved */ 1066 } bit; /*!< Structure used for bit access */ 1067 uint32_t reg; /*!< Type used for register access */ 1068 } TC_BCR_Type; 1069 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1070 1071 #define TC_BCR_OFFSET 0xC0 /**< \brief (TC_BCR offset) TC Block Control Register */ 1072 #define TC_BCR_RESETVALUE _U_(0x00000000); /**< \brief (TC_BCR reset_value) TC Block Control Register */ 1073 1074 #define TC_BCR_SYNC_Pos 0 /**< \brief (TC_BCR) Synchro Command */ 1075 #define TC_BCR_SYNC (_U_(0x1) << TC_BCR_SYNC_Pos) 1076 #define TC_BCR_SYNC_0_Val _U_(0x0) /**< \brief (TC_BCR) No effect. */ 1077 #define TC_BCR_SYNC_1_Val _U_(0x1) /**< \brief (TC_BCR) Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. */ 1078 #define TC_BCR_SYNC_0 (TC_BCR_SYNC_0_Val << TC_BCR_SYNC_Pos) 1079 #define TC_BCR_SYNC_1 (TC_BCR_SYNC_1_Val << TC_BCR_SYNC_Pos) 1080 #define TC_BCR_MASK _U_(0x00000001) /**< \brief (TC_BCR) MASK Register */ 1081 1082 /* -------- TC_BMR : (TC Offset: 0xC4) (R/W 32) TC Block Mode Register -------- */ 1083 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1084 typedef union { 1085 struct { 1086 uint32_t TC0XC0S:2; /*!< bit: 0.. 1 External Clock Signal 0 Selection */ 1087 uint32_t TC1XC1S:2; /*!< bit: 2.. 3 External Clock Signal 1 Selection */ 1088 uint32_t TC2XC2S:2; /*!< bit: 4.. 5 External Clock Signal 2 Selection */ 1089 uint32_t :26; /*!< bit: 6..31 Reserved */ 1090 } bit; /*!< Structure used for bit access */ 1091 uint32_t reg; /*!< Type used for register access */ 1092 } TC_BMR_Type; 1093 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1094 1095 #define TC_BMR_OFFSET 0xC4 /**< \brief (TC_BMR offset) TC Block Mode Register */ 1096 #define TC_BMR_RESETVALUE _U_(0x00000000); /**< \brief (TC_BMR reset_value) TC Block Mode Register */ 1097 1098 #define TC_BMR_TC0XC0S_Pos 0 /**< \brief (TC_BMR) External Clock Signal 0 Selection */ 1099 #define TC_BMR_TC0XC0S_Msk (_U_(0x3) << TC_BMR_TC0XC0S_Pos) 1100 #define TC_BMR_TC0XC0S(value) (TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos)) 1101 #define TC_BMR_TC0XC0S_TCLK0_Val _U_(0x0) /**< \brief (TC_BMR) Select TCLK0 as clock signal 0. */ 1102 #define TC_BMR_TC0XC0S_NO_CLK_Val _U_(0x1) /**< \brief (TC_BMR) Select no clock as clock signal 0. */ 1103 #define TC_BMR_TC0XC0S_TIOA1_Val _U_(0x2) /**< \brief (TC_BMR) Select TIOA1 as clock signal 0. */ 1104 #define TC_BMR_TC0XC0S_TIOA2_Val _U_(0x3) /**< \brief (TC_BMR) Select TIOA2 as clock signal 0. */ 1105 #define TC_BMR_TC0XC0S_TCLK0 (TC_BMR_TC0XC0S_TCLK0_Val << TC_BMR_TC0XC0S_Pos) 1106 #define TC_BMR_TC0XC0S_NO_CLK (TC_BMR_TC0XC0S_NO_CLK_Val << TC_BMR_TC0XC0S_Pos) 1107 #define TC_BMR_TC0XC0S_TIOA1 (TC_BMR_TC0XC0S_TIOA1_Val << TC_BMR_TC0XC0S_Pos) 1108 #define TC_BMR_TC0XC0S_TIOA2 (TC_BMR_TC0XC0S_TIOA2_Val << TC_BMR_TC0XC0S_Pos) 1109 #define TC_BMR_TC1XC1S_Pos 2 /**< \brief (TC_BMR) External Clock Signal 1 Selection */ 1110 #define TC_BMR_TC1XC1S_Msk (_U_(0x3) << TC_BMR_TC1XC1S_Pos) 1111 #define TC_BMR_TC1XC1S(value) (TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos)) 1112 #define TC_BMR_TC1XC1S_TCLK1_Val _U_(0x0) /**< \brief (TC_BMR) Select TCLK1 as clock signal 1. */ 1113 #define TC_BMR_TC1XC1S_NO_CLK_Val _U_(0x1) /**< \brief (TC_BMR) Select no clock as clock signal 1. */ 1114 #define TC_BMR_TC1XC1S_TIOA0_Val _U_(0x2) /**< \brief (TC_BMR) Select TIOA0 as clock signal 1. */ 1115 #define TC_BMR_TC1XC1S_TIOA2_Val _U_(0x3) /**< \brief (TC_BMR) Select TIOA2 as clock signal 1. */ 1116 #define TC_BMR_TC1XC1S_TCLK1 (TC_BMR_TC1XC1S_TCLK1_Val << TC_BMR_TC1XC1S_Pos) 1117 #define TC_BMR_TC1XC1S_NO_CLK (TC_BMR_TC1XC1S_NO_CLK_Val << TC_BMR_TC1XC1S_Pos) 1118 #define TC_BMR_TC1XC1S_TIOA0 (TC_BMR_TC1XC1S_TIOA0_Val << TC_BMR_TC1XC1S_Pos) 1119 #define TC_BMR_TC1XC1S_TIOA2 (TC_BMR_TC1XC1S_TIOA2_Val << TC_BMR_TC1XC1S_Pos) 1120 #define TC_BMR_TC2XC2S_Pos 4 /**< \brief (TC_BMR) External Clock Signal 2 Selection */ 1121 #define TC_BMR_TC2XC2S_Msk (_U_(0x3) << TC_BMR_TC2XC2S_Pos) 1122 #define TC_BMR_TC2XC2S(value) (TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos)) 1123 #define TC_BMR_TC2XC2S_TCLK2_Val _U_(0x0) /**< \brief (TC_BMR) Select TCLK2 as clock signal 2. */ 1124 #define TC_BMR_TC2XC2S_NO_CLK_Val _U_(0x1) /**< \brief (TC_BMR) Select no clock as clock signal 2. */ 1125 #define TC_BMR_TC2XC2S_TIOA0_Val _U_(0x2) /**< \brief (TC_BMR) Select TIOA0 as clock signal 2. */ 1126 #define TC_BMR_TC2XC2S_TIOA1_Val _U_(0x3) /**< \brief (TC_BMR) Select TIOA1 as clock signal 2. */ 1127 #define TC_BMR_TC2XC2S_TCLK2 (TC_BMR_TC2XC2S_TCLK2_Val << TC_BMR_TC2XC2S_Pos) 1128 #define TC_BMR_TC2XC2S_NO_CLK (TC_BMR_TC2XC2S_NO_CLK_Val << TC_BMR_TC2XC2S_Pos) 1129 #define TC_BMR_TC2XC2S_TIOA0 (TC_BMR_TC2XC2S_TIOA0_Val << TC_BMR_TC2XC2S_Pos) 1130 #define TC_BMR_TC2XC2S_TIOA1 (TC_BMR_TC2XC2S_TIOA1_Val << TC_BMR_TC2XC2S_Pos) 1131 #define TC_BMR_MASK _U_(0x0000003F) /**< \brief (TC_BMR) MASK Register */ 1132 1133 /* -------- TC_WPMR : (TC Offset: 0xE4) (R/W 32) Write Protect Mode Register -------- */ 1134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1135 typedef union { 1136 struct { 1137 uint32_t WPEN:1; /*!< bit: 0 Write Protect Enable */ 1138 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 1139 uint32_t WPKEY:24; /*!< bit: 8..31 Write Protect Key */ 1140 } bit; /*!< Structure used for bit access */ 1141 uint32_t reg; /*!< Type used for register access */ 1142 } TC_WPMR_Type; 1143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1144 1145 #define TC_WPMR_OFFSET 0xE4 /**< \brief (TC_WPMR offset) Write Protect Mode Register */ 1146 #define TC_WPMR_RESETVALUE _U_(0x00000000); /**< \brief (TC_WPMR reset_value) Write Protect Mode Register */ 1147 1148 #define TC_WPMR_WPEN_Pos 0 /**< \brief (TC_WPMR) Write Protect Enable */ 1149 #define TC_WPMR_WPEN (_U_(0x1) << TC_WPMR_WPEN_Pos) 1150 #define TC_WPMR_WPKEY_Pos 8 /**< \brief (TC_WPMR) Write Protect Key */ 1151 #define TC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << TC_WPMR_WPKEY_Pos) 1152 #define TC_WPMR_WPKEY(value) (TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)) 1153 #define TC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (TC_WPMR) MASK Register */ 1154 1155 /* -------- TC_FEATURES : (TC Offset: 0xF8) (R/ 32) Features Register -------- */ 1156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1157 typedef union { 1158 struct { 1159 uint32_t CTRSIZE:8; /*!< bit: 0.. 7 Counter Size */ 1160 uint32_t UPDNIMPL:1; /*!< bit: 8 Up Down is Implemented */ 1161 uint32_t BRPBHSB:1; /*!< bit: 9 Bridge Type is PB to HSB */ 1162 uint32_t :22; /*!< bit: 10..31 Reserved */ 1163 } bit; /*!< Structure used for bit access */ 1164 uint32_t reg; /*!< Type used for register access */ 1165 } TC_FEATURES_Type; 1166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1167 1168 #define TC_FEATURES_OFFSET 0xF8 /**< \brief (TC_FEATURES offset) Features Register */ 1169 1170 #define TC_FEATURES_CTRSIZE_Pos 0 /**< \brief (TC_FEATURES) Counter Size */ 1171 #define TC_FEATURES_CTRSIZE_Msk (_U_(0xFF) << TC_FEATURES_CTRSIZE_Pos) 1172 #define TC_FEATURES_CTRSIZE(value) (TC_FEATURES_CTRSIZE_Msk & ((value) << TC_FEATURES_CTRSIZE_Pos)) 1173 #define TC_FEATURES_UPDNIMPL_Pos 8 /**< \brief (TC_FEATURES) Up Down is Implemented */ 1174 #define TC_FEATURES_UPDNIMPL (_U_(0x1) << TC_FEATURES_UPDNIMPL_Pos) 1175 #define TC_FEATURES_BRPBHSB_Pos 9 /**< \brief (TC_FEATURES) Bridge Type is PB to HSB */ 1176 #define TC_FEATURES_BRPBHSB (_U_(0x1) << TC_FEATURES_BRPBHSB_Pos) 1177 #define TC_FEATURES_MASK _U_(0x000003FF) /**< \brief (TC_FEATURES) MASK Register */ 1178 1179 /* -------- TC_VERSION : (TC Offset: 0xFC) (R/ 32) Version Register -------- */ 1180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1181 typedef union { 1182 struct { 1183 uint32_t VERSION:12; /*!< bit: 0..11 Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. */ 1184 uint32_t :4; /*!< bit: 12..15 Reserved */ 1185 uint32_t VARIANT:4; /*!< bit: 16..19 Reserved. Value subject to change. No functionality associated. */ 1186 uint32_t :12; /*!< bit: 20..31 Reserved */ 1187 } bit; /*!< Structure used for bit access */ 1188 uint32_t reg; /*!< Type used for register access */ 1189 } TC_VERSION_Type; 1190 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1191 1192 #define TC_VERSION_OFFSET 0xFC /**< \brief (TC_VERSION offset) Version Register */ 1193 #define TC_VERSION_RESETVALUE _U_(0x00000402); /**< \brief (TC_VERSION reset_value) Version Register */ 1194 1195 #define TC_VERSION_VERSION_Pos 0 /**< \brief (TC_VERSION) Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. */ 1196 #define TC_VERSION_VERSION_Msk (_U_(0xFFF) << TC_VERSION_VERSION_Pos) 1197 #define TC_VERSION_VERSION(value) (TC_VERSION_VERSION_Msk & ((value) << TC_VERSION_VERSION_Pos)) 1198 #define TC_VERSION_VARIANT_Pos 16 /**< \brief (TC_VERSION) Reserved. Value subject to change. No functionality associated. */ 1199 #define TC_VERSION_VARIANT_Msk (_U_(0xF) << TC_VERSION_VARIANT_Pos) 1200 #define TC_VERSION_VARIANT(value) (TC_VERSION_VARIANT_Msk & ((value) << TC_VERSION_VARIANT_Pos)) 1201 #define TC_VERSION_MASK _U_(0x000F0FFF) /**< \brief (TC_VERSION) MASK Register */ 1202 1203 /** \brief TcChannel hardware registers */ 1204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1205 typedef struct { 1206 WoReg TC_CCR; /**< \brief (TC Offset: 0x00) Channel Control Register Channel */ 1207 RwReg TC_CMR; /**< \brief (TC Offset: 0x04) Channel Mode Register Channel */ 1208 RwReg TC_SMMR; /**< \brief (TC Offset: 0x08) Stepper Motor Mode Register */ 1209 RoReg8 Reserved3[0x4]; 1210 RoReg TC_CV; /**< \brief (TC Offset: 0x10) Counter Value Channel */ 1211 RwReg TC_RA; /**< \brief (TC Offset: 0x14) Register A Channel */ 1212 RwReg TC_RB; /**< \brief (TC Offset: 0x18) Register B Channel */ 1213 RwReg TC_RC; /**< \brief (TC Offset: 0x1C) Register C Channel */ 1214 RoReg TC_SR; /**< \brief (TC Offset: 0x20) Status Register Channel */ 1215 WoReg TC_IER; /**< \brief (TC Offset: 0x24) Interrupt Enable Register Channel */ 1216 WoReg TC_IDR; /**< \brief (TC Offset: 0x28) Interrupt Disable Register Channel */ 1217 RoReg TC_IMR; /**< \brief (TC Offset: 0x2C) Interrupt Mask Register Channel */ 1218 RoReg8 Reserved4[0x10]; 1219 } TcChannel; 1220 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1221 1222 #define TCCHANNEL_NUMBER 3 1223 1224 /** \brief TC hardware registers */ 1225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1226 typedef struct { 1227 TcChannel TcChannel[3];/**< \brief Offset: 0x00 TcChannel groups */ 1228 __O uint32_t BCR; /**< \brief Offset: 0xC0 ( /W 32) TC Block Control Register */ 1229 __IO uint32_t BMR; /**< \brief Offset: 0xC4 (R/W 32) TC Block Mode Register */ 1230 RoReg8 Reserved1[0x1C]; 1231 __IO uint32_t WPMR; /**< \brief Offset: 0xE4 (R/W 32) Write Protect Mode Register */ 1232 RoReg8 Reserved2[0x10]; 1233 __I uint32_t FEATURES; /**< \brief Offset: 0xF8 (R/ 32) Features Register */ 1234 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 1235 } Tc; 1236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1237 1238 /*@}*/ 1239 1240 #endif /* _SAM4L_TC_COMPONENT_ */ 1241
