1 /** 2 * \file 3 * 4 * \brief Component description for SMAP 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_SMAP_COMPONENT_ 30 #define _SAM4L_SMAP_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR SMAP */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_SMAP System Manager Access Port */ 36 /*@{*/ 37 38 #define SMAP_I8321 39 #define REV_SMAP 0x100 40 41 /* -------- SMAP_CR : (SMAP Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 Enable */ 46 uint32_t DIS:1; /*!< bit: 1 Disable */ 47 uint32_t CRC:1; /*!< bit: 2 User Page Read */ 48 uint32_t FSPR:1; /*!< bit: 3 Flash Supplementary Page Read */ 49 uint32_t CE:1; /*!< bit: 4 Chip Erase */ 50 uint32_t :27; /*!< bit: 5..31 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint32_t reg; /*!< Type used for register access */ 53 } SMAP_CR_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define SMAP_CR_OFFSET 0x00 /**< \brief (SMAP_CR offset) Control Register */ 57 #define SMAP_CR_RESETVALUE _U_(0x00000000); /**< \brief (SMAP_CR reset_value) Control Register */ 58 59 #define SMAP_CR_EN_Pos 0 /**< \brief (SMAP_CR) Enable */ 60 #define SMAP_CR_EN (_U_(0x1) << SMAP_CR_EN_Pos) 61 #define SMAP_CR_DIS_Pos 1 /**< \brief (SMAP_CR) Disable */ 62 #define SMAP_CR_DIS (_U_(0x1) << SMAP_CR_DIS_Pos) 63 #define SMAP_CR_CRC_Pos 2 /**< \brief (SMAP_CR) User Page Read */ 64 #define SMAP_CR_CRC (_U_(0x1) << SMAP_CR_CRC_Pos) 65 #define SMAP_CR_FSPR_Pos 3 /**< \brief (SMAP_CR) Flash Supplementary Page Read */ 66 #define SMAP_CR_FSPR (_U_(0x1) << SMAP_CR_FSPR_Pos) 67 #define SMAP_CR_CE_Pos 4 /**< \brief (SMAP_CR) Chip Erase */ 68 #define SMAP_CR_CE (_U_(0x1) << SMAP_CR_CE_Pos) 69 #define SMAP_CR_MASK _U_(0x0000001F) /**< \brief (SMAP_CR) MASK Register */ 70 71 /* -------- SMAP_SR : (SMAP Offset: 0x04) (R/ 32) Status Register -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint32_t DONE:1; /*!< bit: 0 Operation done */ 76 uint32_t HCR:1; /*!< bit: 1 Hold Core reset */ 77 uint32_t BERR:1; /*!< bit: 2 Bus error */ 78 uint32_t FAIL:1; /*!< bit: 3 Failure */ 79 uint32_t LCK:1; /*!< bit: 4 Lock */ 80 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 81 uint32_t EN:1; /*!< bit: 8 Enabled */ 82 uint32_t PROT:1; /*!< bit: 9 Protected */ 83 uint32_t DBGP:1; /*!< bit: 10 Debugger Present */ 84 uint32_t :13; /*!< bit: 11..23 Reserved */ 85 uint32_t STATE:3; /*!< bit: 24..26 State */ 86 uint32_t :5; /*!< bit: 27..31 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 uint32_t reg; /*!< Type used for register access */ 89 } SMAP_SR_Type; 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 #define SMAP_SR_OFFSET 0x04 /**< \brief (SMAP_SR offset) Status Register */ 93 #define SMAP_SR_RESETVALUE _U_(0x00000000); /**< \brief (SMAP_SR reset_value) Status Register */ 94 95 #define SMAP_SR_DONE_Pos 0 /**< \brief (SMAP_SR) Operation done */ 96 #define SMAP_SR_DONE (_U_(0x1) << SMAP_SR_DONE_Pos) 97 #define SMAP_SR_HCR_Pos 1 /**< \brief (SMAP_SR) Hold Core reset */ 98 #define SMAP_SR_HCR (_U_(0x1) << SMAP_SR_HCR_Pos) 99 #define SMAP_SR_BERR_Pos 2 /**< \brief (SMAP_SR) Bus error */ 100 #define SMAP_SR_BERR (_U_(0x1) << SMAP_SR_BERR_Pos) 101 #define SMAP_SR_FAIL_Pos 3 /**< \brief (SMAP_SR) Failure */ 102 #define SMAP_SR_FAIL (_U_(0x1) << SMAP_SR_FAIL_Pos) 103 #define SMAP_SR_LCK_Pos 4 /**< \brief (SMAP_SR) Lock */ 104 #define SMAP_SR_LCK (_U_(0x1) << SMAP_SR_LCK_Pos) 105 #define SMAP_SR_EN_Pos 8 /**< \brief (SMAP_SR) Enabled */ 106 #define SMAP_SR_EN (_U_(0x1) << SMAP_SR_EN_Pos) 107 #define SMAP_SR_PROT_Pos 9 /**< \brief (SMAP_SR) Protected */ 108 #define SMAP_SR_PROT (_U_(0x1) << SMAP_SR_PROT_Pos) 109 #define SMAP_SR_DBGP_Pos 10 /**< \brief (SMAP_SR) Debugger Present */ 110 #define SMAP_SR_DBGP (_U_(0x1) << SMAP_SR_DBGP_Pos) 111 #define SMAP_SR_STATE_Pos 24 /**< \brief (SMAP_SR) State */ 112 #define SMAP_SR_STATE_Msk (_U_(0x7) << SMAP_SR_STATE_Pos) 113 #define SMAP_SR_STATE(value) (SMAP_SR_STATE_Msk & ((value) << SMAP_SR_STATE_Pos)) 114 #define SMAP_SR_MASK _U_(0x0700071F) /**< \brief (SMAP_SR) MASK Register */ 115 116 /* -------- SMAP_SCR : (SMAP Offset: 0x08) ( /W 32) Status Clear Register -------- */ 117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 118 typedef union { 119 struct { 120 uint32_t DONE:1; /*!< bit: 0 Done */ 121 uint32_t HCR:1; /*!< bit: 1 Hold Core Register */ 122 uint32_t BERR:1; /*!< bit: 2 Bus error */ 123 uint32_t FAIL:1; /*!< bit: 3 Failure */ 124 uint32_t LCK:1; /*!< bit: 4 Lock error */ 125 uint32_t :27; /*!< bit: 5..31 Reserved */ 126 } bit; /*!< Structure used for bit access */ 127 uint32_t reg; /*!< Type used for register access */ 128 } SMAP_SCR_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 #define SMAP_SCR_OFFSET 0x08 /**< \brief (SMAP_SCR offset) Status Clear Register */ 132 #define SMAP_SCR_RESETVALUE _U_(0x00000000); /**< \brief (SMAP_SCR reset_value) Status Clear Register */ 133 134 #define SMAP_SCR_DONE_Pos 0 /**< \brief (SMAP_SCR) Done */ 135 #define SMAP_SCR_DONE (_U_(0x1) << SMAP_SCR_DONE_Pos) 136 #define SMAP_SCR_HCR_Pos 1 /**< \brief (SMAP_SCR) Hold Core Register */ 137 #define SMAP_SCR_HCR (_U_(0x1) << SMAP_SCR_HCR_Pos) 138 #define SMAP_SCR_BERR_Pos 2 /**< \brief (SMAP_SCR) Bus error */ 139 #define SMAP_SCR_BERR (_U_(0x1) << SMAP_SCR_BERR_Pos) 140 #define SMAP_SCR_FAIL_Pos 3 /**< \brief (SMAP_SCR) Failure */ 141 #define SMAP_SCR_FAIL (_U_(0x1) << SMAP_SCR_FAIL_Pos) 142 #define SMAP_SCR_LCK_Pos 4 /**< \brief (SMAP_SCR) Lock error */ 143 #define SMAP_SCR_LCK (_U_(0x1) << SMAP_SCR_LCK_Pos) 144 #define SMAP_SCR_MASK _U_(0x0000001F) /**< \brief (SMAP_SCR) MASK Register */ 145 146 /* -------- SMAP_ADDR : (SMAP Offset: 0x0C) (R/W 32) Address Register -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 151 uint32_t ADDR:30; /*!< bit: 2..31 Address Value */ 152 } bit; /*!< Structure used for bit access */ 153 uint32_t reg; /*!< Type used for register access */ 154 } SMAP_ADDR_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 #define SMAP_ADDR_OFFSET 0x0C /**< \brief (SMAP_ADDR offset) Address Register */ 158 #define SMAP_ADDR_RESETVALUE _U_(0x00000000); /**< \brief (SMAP_ADDR reset_value) Address Register */ 159 160 #define SMAP_ADDR_ADDR_Pos 2 /**< \brief (SMAP_ADDR) Address Value */ 161 #define SMAP_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << SMAP_ADDR_ADDR_Pos) 162 #define SMAP_ADDR_ADDR(value) (SMAP_ADDR_ADDR_Msk & ((value) << SMAP_ADDR_ADDR_Pos)) 163 #define SMAP_ADDR_MASK _U_(0xFFFFFFFC) /**< \brief (SMAP_ADDR) MASK Register */ 164 165 /* -------- SMAP_LENGTH : (SMAP Offset: 0x10) (R/W 32) Length Register -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { 168 struct { 169 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 170 uint32_t LENGTH:30; /*!< bit: 2..31 Length Register */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } SMAP_LENGTH_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define SMAP_LENGTH_OFFSET 0x10 /**< \brief (SMAP_LENGTH offset) Length Register */ 177 #define SMAP_LENGTH_RESETVALUE _U_(0x00000000); /**< \brief (SMAP_LENGTH reset_value) Length Register */ 178 179 #define SMAP_LENGTH_LENGTH_Pos 2 /**< \brief (SMAP_LENGTH) Length Register */ 180 #define SMAP_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << SMAP_LENGTH_LENGTH_Pos) 181 #define SMAP_LENGTH_LENGTH(value) (SMAP_LENGTH_LENGTH_Msk & ((value) << SMAP_LENGTH_LENGTH_Pos)) 182 #define SMAP_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (SMAP_LENGTH) MASK Register */ 183 184 /* -------- SMAP_DATA : (SMAP Offset: 0x14) (R/W 32) Data Register -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 struct { 188 uint32_t DATA:32; /*!< bit: 0..31 Generic data register */ 189 } bit; /*!< Structure used for bit access */ 190 uint32_t reg; /*!< Type used for register access */ 191 } SMAP_DATA_Type; 192 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 193 194 #define SMAP_DATA_OFFSET 0x14 /**< \brief (SMAP_DATA offset) Data Register */ 195 #define SMAP_DATA_RESETVALUE _U_(0x00000000); /**< \brief (SMAP_DATA reset_value) Data Register */ 196 197 #define SMAP_DATA_DATA_Pos 0 /**< \brief (SMAP_DATA) Generic data register */ 198 #define SMAP_DATA_DATA_Msk (_U_(0xFFFFFFFF) << SMAP_DATA_DATA_Pos) 199 #define SMAP_DATA_DATA(value) (SMAP_DATA_DATA_Msk & ((value) << SMAP_DATA_DATA_Pos)) 200 #define SMAP_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (SMAP_DATA) MASK Register */ 201 202 /* -------- SMAP_VERSION : (SMAP Offset: 0x28) (R/ 32) VERSION register -------- */ 203 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 204 typedef union { 205 struct { 206 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 207 uint32_t :4; /*!< bit: 12..15 Reserved */ 208 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 209 uint32_t :12; /*!< bit: 20..31 Reserved */ 210 } bit; /*!< Structure used for bit access */ 211 uint32_t reg; /*!< Type used for register access */ 212 } SMAP_VERSION_Type; 213 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 214 215 #define SMAP_VERSION_OFFSET 0x28 /**< \brief (SMAP_VERSION offset) VERSION register */ 216 #define SMAP_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (SMAP_VERSION reset_value) VERSION register */ 217 218 #define SMAP_VERSION_VERSION_Pos 0 /**< \brief (SMAP_VERSION) Version number */ 219 #define SMAP_VERSION_VERSION_Msk (_U_(0xFFF) << SMAP_VERSION_VERSION_Pos) 220 #define SMAP_VERSION_VERSION(value) (SMAP_VERSION_VERSION_Msk & ((value) << SMAP_VERSION_VERSION_Pos)) 221 #define SMAP_VERSION_VARIANT_Pos 16 /**< \brief (SMAP_VERSION) Variant number */ 222 #define SMAP_VERSION_VARIANT_Msk (_U_(0xF) << SMAP_VERSION_VARIANT_Pos) 223 #define SMAP_VERSION_VARIANT(value) (SMAP_VERSION_VARIANT_Msk & ((value) << SMAP_VERSION_VARIANT_Pos)) 224 #define SMAP_VERSION_MASK _U_(0x000F0FFF) /**< \brief (SMAP_VERSION) MASK Register */ 225 226 /* -------- SMAP_CIDR : (SMAP Offset: 0xF0) (R/ 32) Chip ID Register -------- */ 227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 228 typedef union { 229 struct { 230 uint32_t VERSION:5; /*!< bit: 0.. 4 Version of the Device */ 231 uint32_t EPROC:3; /*!< bit: 5.. 7 Embedded Processor */ 232 uint32_t NVPSIZ:4; /*!< bit: 8..11 Nonvolatile Program Memory Size */ 233 uint32_t NVPSIZ2:4; /*!< bit: 12..15 Second Nonvolatile Program Memory Size */ 234 uint32_t SRAMSIZ:5; /*!< bit: 16..20 Internal SRAM Size */ 235 uint32_t ARCH:7; /*!< bit: 21..27 Architecture Identifier */ 236 uint32_t NVPTYP:3; /*!< bit: 28..30 Nonvolatile Program Memory Type */ 237 uint32_t EXT:1; /*!< bit: 31 Extension Flag */ 238 } bit; /*!< Structure used for bit access */ 239 uint32_t reg; /*!< Type used for register access */ 240 } SMAP_CIDR_Type; 241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 242 243 #define SMAP_CIDR_OFFSET 0xF0 /**< \brief (SMAP_CIDR offset) Chip ID Register */ 244 245 #define SMAP_CIDR_VERSION_Pos 0 /**< \brief (SMAP_CIDR) Version of the Device */ 246 #define SMAP_CIDR_VERSION_Msk (_U_(0x1F) << SMAP_CIDR_VERSION_Pos) 247 #define SMAP_CIDR_VERSION(value) (SMAP_CIDR_VERSION_Msk & ((value) << SMAP_CIDR_VERSION_Pos)) 248 #define SMAP_CIDR_EPROC_Pos 5 /**< \brief (SMAP_CIDR) Embedded Processor */ 249 #define SMAP_CIDR_EPROC_Msk (_U_(0x7) << SMAP_CIDR_EPROC_Pos) 250 #define SMAP_CIDR_EPROC(value) (SMAP_CIDR_EPROC_Msk & ((value) << SMAP_CIDR_EPROC_Pos)) 251 #define SMAP_CIDR_NVPSIZ_Pos 8 /**< \brief (SMAP_CIDR) Nonvolatile Program Memory Size */ 252 #define SMAP_CIDR_NVPSIZ_Msk (_U_(0xF) << SMAP_CIDR_NVPSIZ_Pos) 253 #define SMAP_CIDR_NVPSIZ(value) (SMAP_CIDR_NVPSIZ_Msk & ((value) << SMAP_CIDR_NVPSIZ_Pos)) 254 #define SMAP_CIDR_NVPSIZ2_Pos 12 /**< \brief (SMAP_CIDR) Second Nonvolatile Program Memory Size */ 255 #define SMAP_CIDR_NVPSIZ2_Msk (_U_(0xF) << SMAP_CIDR_NVPSIZ2_Pos) 256 #define SMAP_CIDR_NVPSIZ2(value) (SMAP_CIDR_NVPSIZ2_Msk & ((value) << SMAP_CIDR_NVPSIZ2_Pos)) 257 #define SMAP_CIDR_SRAMSIZ_Pos 16 /**< \brief (SMAP_CIDR) Internal SRAM Size */ 258 #define SMAP_CIDR_SRAMSIZ_Msk (_U_(0x1F) << SMAP_CIDR_SRAMSIZ_Pos) 259 #define SMAP_CIDR_SRAMSIZ(value) (SMAP_CIDR_SRAMSIZ_Msk & ((value) << SMAP_CIDR_SRAMSIZ_Pos)) 260 #define SMAP_CIDR_ARCH_Pos 21 /**< \brief (SMAP_CIDR) Architecture Identifier */ 261 #define SMAP_CIDR_ARCH_Msk (_U_(0x7F) << SMAP_CIDR_ARCH_Pos) 262 #define SMAP_CIDR_ARCH(value) (SMAP_CIDR_ARCH_Msk & ((value) << SMAP_CIDR_ARCH_Pos)) 263 #define SMAP_CIDR_NVPTYP_Pos 28 /**< \brief (SMAP_CIDR) Nonvolatile Program Memory Type */ 264 #define SMAP_CIDR_NVPTYP_Msk (_U_(0x7) << SMAP_CIDR_NVPTYP_Pos) 265 #define SMAP_CIDR_NVPTYP(value) (SMAP_CIDR_NVPTYP_Msk & ((value) << SMAP_CIDR_NVPTYP_Pos)) 266 #define SMAP_CIDR_EXT_Pos 31 /**< \brief (SMAP_CIDR) Extension Flag */ 267 #define SMAP_CIDR_EXT (_U_(0x1) << SMAP_CIDR_EXT_Pos) 268 #define SMAP_CIDR_MASK _U_(0xFFFFFFFF) /**< \brief (SMAP_CIDR) MASK Register */ 269 270 /* -------- SMAP_EXID : (SMAP Offset: 0xF4) (R/ 32) Chip ID Extension Register -------- */ 271 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 272 typedef union { 273 struct { 274 uint32_t EXID:32; /*!< bit: 0..31 Chip ID Extension */ 275 } bit; /*!< Structure used for bit access */ 276 uint32_t reg; /*!< Type used for register access */ 277 } SMAP_EXID_Type; 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 279 280 #define SMAP_EXID_OFFSET 0xF4 /**< \brief (SMAP_EXID offset) Chip ID Extension Register */ 281 282 #define SMAP_EXID_EXID_Pos 0 /**< \brief (SMAP_EXID) Chip ID Extension */ 283 #define SMAP_EXID_EXID_Msk (_U_(0xFFFFFFFF) << SMAP_EXID_EXID_Pos) 284 #define SMAP_EXID_EXID(value) (SMAP_EXID_EXID_Msk & ((value) << SMAP_EXID_EXID_Pos)) 285 #define SMAP_EXID_MASK _U_(0xFFFFFFFF) /**< \brief (SMAP_EXID) MASK Register */ 286 287 /* -------- SMAP_IDR : (SMAP Offset: 0xFC) (R/ 32) AP Identification register -------- */ 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 289 typedef union { 290 struct { 291 uint32_t APIDV:4; /*!< bit: 0.. 3 AP Identification Variant */ 292 uint32_t APID:4; /*!< bit: 4.. 7 AP Identification */ 293 uint32_t :8; /*!< bit: 8..15 Reserved */ 294 uint32_t CLSS:1; /*!< bit: 16 Class */ 295 uint32_t IC:7; /*!< bit: 17..23 JEP-106 Identity Code */ 296 uint32_t CC:4; /*!< bit: 24..27 JEP-106 Continuation Code */ 297 uint32_t REVISION:4; /*!< bit: 28..31 Revision */ 298 } bit; /*!< Structure used for bit access */ 299 uint32_t reg; /*!< Type used for register access */ 300 } SMAP_IDR_Type; 301 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 302 303 #define SMAP_IDR_OFFSET 0xFC /**< \brief (SMAP_IDR offset) AP Identification register */ 304 #define SMAP_IDR_RESETVALUE _U_(0x003E0000); /**< \brief (SMAP_IDR reset_value) AP Identification register */ 305 306 #define SMAP_IDR_APIDV_Pos 0 /**< \brief (SMAP_IDR) AP Identification Variant */ 307 #define SMAP_IDR_APIDV_Msk (_U_(0xF) << SMAP_IDR_APIDV_Pos) 308 #define SMAP_IDR_APIDV(value) (SMAP_IDR_APIDV_Msk & ((value) << SMAP_IDR_APIDV_Pos)) 309 #define SMAP_IDR_APID_Pos 4 /**< \brief (SMAP_IDR) AP Identification */ 310 #define SMAP_IDR_APID_Msk (_U_(0xF) << SMAP_IDR_APID_Pos) 311 #define SMAP_IDR_APID(value) (SMAP_IDR_APID_Msk & ((value) << SMAP_IDR_APID_Pos)) 312 #define SMAP_IDR_CLSS_Pos 16 /**< \brief (SMAP_IDR) Class */ 313 #define SMAP_IDR_CLSS (_U_(0x1) << SMAP_IDR_CLSS_Pos) 314 #define SMAP_IDR_IC_Pos 17 /**< \brief (SMAP_IDR) JEP-106 Identity Code */ 315 #define SMAP_IDR_IC_Msk (_U_(0x7F) << SMAP_IDR_IC_Pos) 316 #define SMAP_IDR_IC(value) (SMAP_IDR_IC_Msk & ((value) << SMAP_IDR_IC_Pos)) 317 #define SMAP_IDR_CC_Pos 24 /**< \brief (SMAP_IDR) JEP-106 Continuation Code */ 318 #define SMAP_IDR_CC_Msk (_U_(0xF) << SMAP_IDR_CC_Pos) 319 #define SMAP_IDR_CC(value) (SMAP_IDR_CC_Msk & ((value) << SMAP_IDR_CC_Pos)) 320 #define SMAP_IDR_REVISION_Pos 28 /**< \brief (SMAP_IDR) Revision */ 321 #define SMAP_IDR_REVISION_Msk (_U_(0xF) << SMAP_IDR_REVISION_Pos) 322 #define SMAP_IDR_REVISION(value) (SMAP_IDR_REVISION_Msk & ((value) << SMAP_IDR_REVISION_Pos)) 323 #define SMAP_IDR_MASK _U_(0xFFFF00FF) /**< \brief (SMAP_IDR) MASK Register */ 324 325 /** \brief SMAP hardware registers */ 326 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 327 typedef struct { 328 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 329 __I uint32_t SR; /**< \brief Offset: 0x04 (R/ 32) Status Register */ 330 __O uint32_t SCR; /**< \brief Offset: 0x08 ( /W 32) Status Clear Register */ 331 __IO uint32_t ADDR; /**< \brief Offset: 0x0C (R/W 32) Address Register */ 332 __IO uint32_t LENGTH; /**< \brief Offset: 0x10 (R/W 32) Length Register */ 333 __IO uint32_t DATA; /**< \brief Offset: 0x14 (R/W 32) Data Register */ 334 RoReg8 Reserved1[0x10]; 335 __I uint32_t VERSION; /**< \brief Offset: 0x28 (R/ 32) VERSION register */ 336 RoReg8 Reserved2[0xC4]; 337 __I uint32_t CIDR; /**< \brief Offset: 0xF0 (R/ 32) Chip ID Register */ 338 __I uint32_t EXID; /**< \brief Offset: 0xF4 (R/ 32) Chip ID Extension Register */ 339 RoReg8 Reserved3[0x4]; 340 __I uint32_t IDR; /**< \brief Offset: 0xFC (R/ 32) AP Identification register */ 341 } Smap; 342 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 343 344 /*@}*/ 345 346 #endif /* _SAM4L_SMAP_COMPONENT_ */ 347
