1 /** 2 * \file 3 * 4 * \brief Component description for PEVC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_PEVC_COMPONENT_ 30 #define _SAM4L_PEVC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PEVC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_PEVC Peripheral Event Controller */ 36 /*@{*/ 37 38 #define PEVC_I7533 39 #define REV_PEVC 0x200 40 41 /* -------- PEVC_CHSR : (PEVC Offset: 0x000) (R/ 32) Channel Status Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t CHS:32; /*!< bit: 0..31 Channel Status */ 46 } bit; /*!< Structure used for bit access */ 47 uint32_t reg; /*!< Type used for register access */ 48 } PEVC_CHSR_Type; 49 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 50 51 #define PEVC_CHSR_OFFSET 0x000 /**< \brief (PEVC_CHSR offset) Channel Status Register */ 52 #define PEVC_CHSR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_CHSR reset_value) Channel Status Register */ 53 54 #define PEVC_CHSR_CHS_Pos 0 /**< \brief (PEVC_CHSR) Channel Status */ 55 #define PEVC_CHSR_CHS_Msk (_U_(0xFFFFFFFF) << PEVC_CHSR_CHS_Pos) 56 #define PEVC_CHSR_CHS(value) (PEVC_CHSR_CHS_Msk & ((value) << PEVC_CHSR_CHS_Pos)) 57 #define PEVC_CHSR_CHS_0_Val _U_(0x0) /**< \brief (PEVC_CHSR) Channel j Disabled */ 58 #define PEVC_CHSR_CHS_1_Val _U_(0x1) /**< \brief (PEVC_CHSR) Channel j Enabled */ 59 #define PEVC_CHSR_CHS_0 (PEVC_CHSR_CHS_0_Val << PEVC_CHSR_CHS_Pos) 60 #define PEVC_CHSR_CHS_1 (PEVC_CHSR_CHS_1_Val << PEVC_CHSR_CHS_Pos) 61 #define PEVC_CHSR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_CHSR) MASK Register */ 62 63 /* -------- PEVC_CHER : (PEVC Offset: 0x004) ( /W 32) Channel Enable Register -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint32_t CHE:32; /*!< bit: 0..31 Channel Enable */ 68 } bit; /*!< Structure used for bit access */ 69 uint32_t reg; /*!< Type used for register access */ 70 } PEVC_CHER_Type; 71 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define PEVC_CHER_OFFSET 0x004 /**< \brief (PEVC_CHER offset) Channel Enable Register */ 74 #define PEVC_CHER_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_CHER reset_value) Channel Enable Register */ 75 76 #define PEVC_CHER_CHE_Pos 0 /**< \brief (PEVC_CHER) Channel Enable */ 77 #define PEVC_CHER_CHE_Msk (_U_(0xFFFFFFFF) << PEVC_CHER_CHE_Pos) 78 #define PEVC_CHER_CHE(value) (PEVC_CHER_CHE_Msk & ((value) << PEVC_CHER_CHE_Pos)) 79 #define PEVC_CHER_CHE_0_Val _U_(0x0) /**< \brief (PEVC_CHER) No Action */ 80 #define PEVC_CHER_CHE_1_Val _U_(0x1) /**< \brief (PEVC_CHER) Enable Channel j */ 81 #define PEVC_CHER_CHE_0 (PEVC_CHER_CHE_0_Val << PEVC_CHER_CHE_Pos) 82 #define PEVC_CHER_CHE_1 (PEVC_CHER_CHE_1_Val << PEVC_CHER_CHE_Pos) 83 #define PEVC_CHER_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_CHER) MASK Register */ 84 85 /* -------- PEVC_CHDR : (PEVC Offset: 0x008) ( /W 32) Channel Disable Register -------- */ 86 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 87 typedef union { 88 struct { 89 uint32_t CHD:32; /*!< bit: 0..31 Channel Disable */ 90 } bit; /*!< Structure used for bit access */ 91 uint32_t reg; /*!< Type used for register access */ 92 } PEVC_CHDR_Type; 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 #define PEVC_CHDR_OFFSET 0x008 /**< \brief (PEVC_CHDR offset) Channel Disable Register */ 96 #define PEVC_CHDR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_CHDR reset_value) Channel Disable Register */ 97 98 #define PEVC_CHDR_CHD_Pos 0 /**< \brief (PEVC_CHDR) Channel Disable */ 99 #define PEVC_CHDR_CHD_Msk (_U_(0xFFFFFFFF) << PEVC_CHDR_CHD_Pos) 100 #define PEVC_CHDR_CHD(value) (PEVC_CHDR_CHD_Msk & ((value) << PEVC_CHDR_CHD_Pos)) 101 #define PEVC_CHDR_CHD_0_Val _U_(0x0) /**< \brief (PEVC_CHDR) No Action */ 102 #define PEVC_CHDR_CHD_1_Val _U_(0x1) /**< \brief (PEVC_CHDR) Disable Channel j */ 103 #define PEVC_CHDR_CHD_0 (PEVC_CHDR_CHD_0_Val << PEVC_CHDR_CHD_Pos) 104 #define PEVC_CHDR_CHD_1 (PEVC_CHDR_CHD_1_Val << PEVC_CHDR_CHD_Pos) 105 #define PEVC_CHDR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_CHDR) MASK Register */ 106 107 /* -------- PEVC_SEV : (PEVC Offset: 0x010) ( /W 32) Software Event -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { 110 struct { 111 uint32_t SEV:32; /*!< bit: 0..31 Software Event */ 112 } bit; /*!< Structure used for bit access */ 113 uint32_t reg; /*!< Type used for register access */ 114 } PEVC_SEV_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define PEVC_SEV_OFFSET 0x010 /**< \brief (PEVC_SEV offset) Software Event */ 118 #define PEVC_SEV_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_SEV reset_value) Software Event */ 119 120 #define PEVC_SEV_SEV_Pos 0 /**< \brief (PEVC_SEV) Software Event */ 121 #define PEVC_SEV_SEV_Msk (_U_(0xFFFFFFFF) << PEVC_SEV_SEV_Pos) 122 #define PEVC_SEV_SEV(value) (PEVC_SEV_SEV_Msk & ((value) << PEVC_SEV_SEV_Pos)) 123 #define PEVC_SEV_SEV_0_Val _U_(0x0) /**< \brief (PEVC_SEV) No Action */ 124 #define PEVC_SEV_SEV_1_Val _U_(0x1) /**< \brief (PEVC_SEV) CPU forces software event to channel j */ 125 #define PEVC_SEV_SEV_0 (PEVC_SEV_SEV_0_Val << PEVC_SEV_SEV_Pos) 126 #define PEVC_SEV_SEV_1 (PEVC_SEV_SEV_1_Val << PEVC_SEV_SEV_Pos) 127 #define PEVC_SEV_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_SEV) MASK Register */ 128 129 /* -------- PEVC_BUSY : (PEVC Offset: 0x014) (R/ 32) Channel / User Busy -------- */ 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 131 typedef union { 132 struct { 133 uint32_t BUSY:32; /*!< bit: 0..31 Channel Status */ 134 } bit; /*!< Structure used for bit access */ 135 uint32_t reg; /*!< Type used for register access */ 136 } PEVC_BUSY_Type; 137 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 138 139 #define PEVC_BUSY_OFFSET 0x014 /**< \brief (PEVC_BUSY offset) Channel / User Busy */ 140 #define PEVC_BUSY_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_BUSY reset_value) Channel / User Busy */ 141 142 #define PEVC_BUSY_BUSY_Pos 0 /**< \brief (PEVC_BUSY) Channel Status */ 143 #define PEVC_BUSY_BUSY_Msk (_U_(0xFFFFFFFF) << PEVC_BUSY_BUSY_Pos) 144 #define PEVC_BUSY_BUSY(value) (PEVC_BUSY_BUSY_Msk & ((value) << PEVC_BUSY_BUSY_Pos)) 145 #define PEVC_BUSY_BUSY_0_Val _U_(0x0) /**< \brief (PEVC_BUSY) No Action */ 146 #define PEVC_BUSY_BUSY_1_Val _U_(0x1) /**< \brief (PEVC_BUSY) Channel j or User j is Busy */ 147 #define PEVC_BUSY_BUSY_0 (PEVC_BUSY_BUSY_0_Val << PEVC_BUSY_BUSY_Pos) 148 #define PEVC_BUSY_BUSY_1 (PEVC_BUSY_BUSY_1_Val << PEVC_BUSY_BUSY_Pos) 149 #define PEVC_BUSY_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_BUSY) MASK Register */ 150 151 /* -------- PEVC_TRIER : (PEVC Offset: 0x020) ( /W 32) Trigger Interrupt Mask Enable Register -------- */ 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { 154 struct { 155 uint32_t TRIE:32; /*!< bit: 0..31 Trigger Interrupt Enable */ 156 } bit; /*!< Structure used for bit access */ 157 uint32_t reg; /*!< Type used for register access */ 158 } PEVC_TRIER_Type; 159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 160 161 #define PEVC_TRIER_OFFSET 0x020 /**< \brief (PEVC_TRIER offset) Trigger Interrupt Mask Enable Register */ 162 #define PEVC_TRIER_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_TRIER reset_value) Trigger Interrupt Mask Enable Register */ 163 164 #define PEVC_TRIER_TRIE_Pos 0 /**< \brief (PEVC_TRIER) Trigger Interrupt Enable */ 165 #define PEVC_TRIER_TRIE_Msk (_U_(0xFFFFFFFF) << PEVC_TRIER_TRIE_Pos) 166 #define PEVC_TRIER_TRIE(value) (PEVC_TRIER_TRIE_Msk & ((value) << PEVC_TRIER_TRIE_Pos)) 167 #define PEVC_TRIER_TRIE_0_Val _U_(0x0) /**< \brief (PEVC_TRIER) No Action */ 168 #define PEVC_TRIER_TRIE_1_Val _U_(0x1) /**< \brief (PEVC_TRIER) Enable Trigger j Interrupt */ 169 #define PEVC_TRIER_TRIE_0 (PEVC_TRIER_TRIE_0_Val << PEVC_TRIER_TRIE_Pos) 170 #define PEVC_TRIER_TRIE_1 (PEVC_TRIER_TRIE_1_Val << PEVC_TRIER_TRIE_Pos) 171 #define PEVC_TRIER_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_TRIER) MASK Register */ 172 173 /* -------- PEVC_TRIDR : (PEVC Offset: 0x024) ( /W 32) Trigger Interrupt Mask Disable Register -------- */ 174 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 175 typedef union { 176 struct { 177 uint32_t TRID:32; /*!< bit: 0..31 Trigger Interrupt Disable */ 178 } bit; /*!< Structure used for bit access */ 179 uint32_t reg; /*!< Type used for register access */ 180 } PEVC_TRIDR_Type; 181 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 183 #define PEVC_TRIDR_OFFSET 0x024 /**< \brief (PEVC_TRIDR offset) Trigger Interrupt Mask Disable Register */ 184 #define PEVC_TRIDR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_TRIDR reset_value) Trigger Interrupt Mask Disable Register */ 185 186 #define PEVC_TRIDR_TRID_Pos 0 /**< \brief (PEVC_TRIDR) Trigger Interrupt Disable */ 187 #define PEVC_TRIDR_TRID_Msk (_U_(0xFFFFFFFF) << PEVC_TRIDR_TRID_Pos) 188 #define PEVC_TRIDR_TRID(value) (PEVC_TRIDR_TRID_Msk & ((value) << PEVC_TRIDR_TRID_Pos)) 189 #define PEVC_TRIDR_TRID_0_Val _U_(0x0) /**< \brief (PEVC_TRIDR) No Action */ 190 #define PEVC_TRIDR_TRID_1_Val _U_(0x1) /**< \brief (PEVC_TRIDR) Disable Trigger j Interrupt */ 191 #define PEVC_TRIDR_TRID_0 (PEVC_TRIDR_TRID_0_Val << PEVC_TRIDR_TRID_Pos) 192 #define PEVC_TRIDR_TRID_1 (PEVC_TRIDR_TRID_1_Val << PEVC_TRIDR_TRID_Pos) 193 #define PEVC_TRIDR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_TRIDR) MASK Register */ 194 195 /* -------- PEVC_TRIMR : (PEVC Offset: 0x028) (R/ 32) Trigger Interrupt Mask Register -------- */ 196 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 197 typedef union { 198 struct { 199 uint32_t TRIM:32; /*!< bit: 0..31 Trigger Interrupt Mask */ 200 } bit; /*!< Structure used for bit access */ 201 uint32_t reg; /*!< Type used for register access */ 202 } PEVC_TRIMR_Type; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define PEVC_TRIMR_OFFSET 0x028 /**< \brief (PEVC_TRIMR offset) Trigger Interrupt Mask Register */ 206 #define PEVC_TRIMR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_TRIMR reset_value) Trigger Interrupt Mask Register */ 207 208 #define PEVC_TRIMR_TRIM_Pos 0 /**< \brief (PEVC_TRIMR) Trigger Interrupt Mask */ 209 #define PEVC_TRIMR_TRIM_Msk (_U_(0xFFFFFFFF) << PEVC_TRIMR_TRIM_Pos) 210 #define PEVC_TRIMR_TRIM(value) (PEVC_TRIMR_TRIM_Msk & ((value) << PEVC_TRIMR_TRIM_Pos)) 211 #define PEVC_TRIMR_TRIM_0_Val _U_(0x0) /**< \brief (PEVC_TRIMR) Trigger j Interrupt Disabled */ 212 #define PEVC_TRIMR_TRIM_1_Val _U_(0x1) /**< \brief (PEVC_TRIMR) Trigger j Interrupt Enabled */ 213 #define PEVC_TRIMR_TRIM_0 (PEVC_TRIMR_TRIM_0_Val << PEVC_TRIMR_TRIM_Pos) 214 #define PEVC_TRIMR_TRIM_1 (PEVC_TRIMR_TRIM_1_Val << PEVC_TRIMR_TRIM_Pos) 215 #define PEVC_TRIMR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_TRIMR) MASK Register */ 216 217 /* -------- PEVC_TRSR : (PEVC Offset: 0x030) (R/ 32) Trigger Status Register -------- */ 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 219 typedef union { 220 struct { 221 uint32_t TRS:32; /*!< bit: 0..31 Trigger Interrupt Status */ 222 } bit; /*!< Structure used for bit access */ 223 uint32_t reg; /*!< Type used for register access */ 224 } PEVC_TRSR_Type; 225 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 226 227 #define PEVC_TRSR_OFFSET 0x030 /**< \brief (PEVC_TRSR offset) Trigger Status Register */ 228 #define PEVC_TRSR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_TRSR reset_value) Trigger Status Register */ 229 230 #define PEVC_TRSR_TRS_Pos 0 /**< \brief (PEVC_TRSR) Trigger Interrupt Status */ 231 #define PEVC_TRSR_TRS_Msk (_U_(0xFFFFFFFF) << PEVC_TRSR_TRS_Pos) 232 #define PEVC_TRSR_TRS(value) (PEVC_TRSR_TRS_Msk & ((value) << PEVC_TRSR_TRS_Pos)) 233 #define PEVC_TRSR_TRS_0_Val _U_(0x0) /**< \brief (PEVC_TRSR) Channel j did not send out an Event in the past */ 234 #define PEVC_TRSR_TRS_1_Val _U_(0x1) /**< \brief (PEVC_TRSR) Channel j did send out an Event in the past */ 235 #define PEVC_TRSR_TRS_0 (PEVC_TRSR_TRS_0_Val << PEVC_TRSR_TRS_Pos) 236 #define PEVC_TRSR_TRS_1 (PEVC_TRSR_TRS_1_Val << PEVC_TRSR_TRS_Pos) 237 #define PEVC_TRSR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_TRSR) MASK Register */ 238 239 /* -------- PEVC_TRSCR : (PEVC Offset: 0x034) ( /W 32) Trigger Status Clear Register -------- */ 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 241 typedef union { 242 struct { 243 uint32_t TRSC:32; /*!< bit: 0..31 Trigger Interrupt Status Clear */ 244 } bit; /*!< Structure used for bit access */ 245 uint32_t reg; /*!< Type used for register access */ 246 } PEVC_TRSCR_Type; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 #define PEVC_TRSCR_OFFSET 0x034 /**< \brief (PEVC_TRSCR offset) Trigger Status Clear Register */ 250 #define PEVC_TRSCR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_TRSCR reset_value) Trigger Status Clear Register */ 251 252 #define PEVC_TRSCR_TRSC_Pos 0 /**< \brief (PEVC_TRSCR) Trigger Interrupt Status Clear */ 253 #define PEVC_TRSCR_TRSC_Msk (_U_(0xFFFFFFFF) << PEVC_TRSCR_TRSC_Pos) 254 #define PEVC_TRSCR_TRSC(value) (PEVC_TRSCR_TRSC_Msk & ((value) << PEVC_TRSCR_TRSC_Pos)) 255 #define PEVC_TRSCR_TRSC_0_Val _U_(0x0) /**< \brief (PEVC_TRSCR) No Action */ 256 #define PEVC_TRSCR_TRSC_1_Val _U_(0x1) /**< \brief (PEVC_TRSCR) Clear TRSR[j] */ 257 #define PEVC_TRSCR_TRSC_0 (PEVC_TRSCR_TRSC_0_Val << PEVC_TRSCR_TRSC_Pos) 258 #define PEVC_TRSCR_TRSC_1 (PEVC_TRSCR_TRSC_1_Val << PEVC_TRSCR_TRSC_Pos) 259 #define PEVC_TRSCR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_TRSCR) MASK Register */ 260 261 /* -------- PEVC_OVIER : (PEVC Offset: 0x040) ( /W 32) Overrun Interrupt Mask Enable Register -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint32_t OVIE:32; /*!< bit: 0..31 Overrun Interrupt Enable */ 266 } bit; /*!< Structure used for bit access */ 267 uint32_t reg; /*!< Type used for register access */ 268 } PEVC_OVIER_Type; 269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 270 271 #define PEVC_OVIER_OFFSET 0x040 /**< \brief (PEVC_OVIER offset) Overrun Interrupt Mask Enable Register */ 272 #define PEVC_OVIER_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_OVIER reset_value) Overrun Interrupt Mask Enable Register */ 273 274 #define PEVC_OVIER_OVIE_Pos 0 /**< \brief (PEVC_OVIER) Overrun Interrupt Enable */ 275 #define PEVC_OVIER_OVIE_Msk (_U_(0xFFFFFFFF) << PEVC_OVIER_OVIE_Pos) 276 #define PEVC_OVIER_OVIE(value) (PEVC_OVIER_OVIE_Msk & ((value) << PEVC_OVIER_OVIE_Pos)) 277 #define PEVC_OVIER_OVIE_0_Val _U_(0x0) /**< \brief (PEVC_OVIER) No Action */ 278 #define PEVC_OVIER_OVIE_1_Val _U_(0x1) /**< \brief (PEVC_OVIER) Enable Overrun Interrupt for Channel j */ 279 #define PEVC_OVIER_OVIE_0 (PEVC_OVIER_OVIE_0_Val << PEVC_OVIER_OVIE_Pos) 280 #define PEVC_OVIER_OVIE_1 (PEVC_OVIER_OVIE_1_Val << PEVC_OVIER_OVIE_Pos) 281 #define PEVC_OVIER_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_OVIER) MASK Register */ 282 283 /* -------- PEVC_OVIDR : (PEVC Offset: 0x044) ( /W 32) Overrun Interrupt Mask Disable Register -------- */ 284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 285 typedef union { 286 struct { 287 uint32_t OVID:32; /*!< bit: 0..31 Overrun Interrupt Disable */ 288 } bit; /*!< Structure used for bit access */ 289 uint32_t reg; /*!< Type used for register access */ 290 } PEVC_OVIDR_Type; 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 292 293 #define PEVC_OVIDR_OFFSET 0x044 /**< \brief (PEVC_OVIDR offset) Overrun Interrupt Mask Disable Register */ 294 #define PEVC_OVIDR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_OVIDR reset_value) Overrun Interrupt Mask Disable Register */ 295 296 #define PEVC_OVIDR_OVID_Pos 0 /**< \brief (PEVC_OVIDR) Overrun Interrupt Disable */ 297 #define PEVC_OVIDR_OVID_Msk (_U_(0xFFFFFFFF) << PEVC_OVIDR_OVID_Pos) 298 #define PEVC_OVIDR_OVID(value) (PEVC_OVIDR_OVID_Msk & ((value) << PEVC_OVIDR_OVID_Pos)) 299 #define PEVC_OVIDR_OVID_0_Val _U_(0x0) /**< \brief (PEVC_OVIDR) No Action */ 300 #define PEVC_OVIDR_OVID_1_Val _U_(0x1) /**< \brief (PEVC_OVIDR) Enable Overrun Interrupt for Channel j */ 301 #define PEVC_OVIDR_OVID_0 (PEVC_OVIDR_OVID_0_Val << PEVC_OVIDR_OVID_Pos) 302 #define PEVC_OVIDR_OVID_1 (PEVC_OVIDR_OVID_1_Val << PEVC_OVIDR_OVID_Pos) 303 #define PEVC_OVIDR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_OVIDR) MASK Register */ 304 305 /* -------- PEVC_OVIMR : (PEVC Offset: 0x048) (R/ 32) Overrun Interrupt Mask Register -------- */ 306 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 307 typedef union { 308 struct { 309 uint32_t OVIM:32; /*!< bit: 0..31 Overrun Interrupt Mask */ 310 } bit; /*!< Structure used for bit access */ 311 uint32_t reg; /*!< Type used for register access */ 312 } PEVC_OVIMR_Type; 313 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 315 #define PEVC_OVIMR_OFFSET 0x048 /**< \brief (PEVC_OVIMR offset) Overrun Interrupt Mask Register */ 316 #define PEVC_OVIMR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_OVIMR reset_value) Overrun Interrupt Mask Register */ 317 318 #define PEVC_OVIMR_OVIM_Pos 0 /**< \brief (PEVC_OVIMR) Overrun Interrupt Mask */ 319 #define PEVC_OVIMR_OVIM_Msk (_U_(0xFFFFFFFF) << PEVC_OVIMR_OVIM_Pos) 320 #define PEVC_OVIMR_OVIM(value) (PEVC_OVIMR_OVIM_Msk & ((value) << PEVC_OVIMR_OVIM_Pos)) 321 #define PEVC_OVIMR_OVIM_0_Val _U_(0x0) /**< \brief (PEVC_OVIMR) Overrun Interrupt for Channel j Disabled */ 322 #define PEVC_OVIMR_OVIM_1_Val _U_(0x1) /**< \brief (PEVC_OVIMR) Overrun Interrupt for Channel j Enabled */ 323 #define PEVC_OVIMR_OVIM_0 (PEVC_OVIMR_OVIM_0_Val << PEVC_OVIMR_OVIM_Pos) 324 #define PEVC_OVIMR_OVIM_1 (PEVC_OVIMR_OVIM_1_Val << PEVC_OVIMR_OVIM_Pos) 325 #define PEVC_OVIMR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_OVIMR) MASK Register */ 326 327 /* -------- PEVC_OVSR : (PEVC Offset: 0x050) (R/ 32) Overrun Status Register -------- */ 328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 329 typedef union { 330 struct { 331 uint32_t OVS:32; /*!< bit: 0..31 Overrun Interrupt Status */ 332 } bit; /*!< Structure used for bit access */ 333 uint32_t reg; /*!< Type used for register access */ 334 } PEVC_OVSR_Type; 335 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 336 337 #define PEVC_OVSR_OFFSET 0x050 /**< \brief (PEVC_OVSR offset) Overrun Status Register */ 338 #define PEVC_OVSR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_OVSR reset_value) Overrun Status Register */ 339 340 #define PEVC_OVSR_OVS_Pos 0 /**< \brief (PEVC_OVSR) Overrun Interrupt Status */ 341 #define PEVC_OVSR_OVS_Msk (_U_(0xFFFFFFFF) << PEVC_OVSR_OVS_Pos) 342 #define PEVC_OVSR_OVS(value) (PEVC_OVSR_OVS_Msk & ((value) << PEVC_OVSR_OVS_Pos)) 343 #define PEVC_OVSR_OVS_0_Val _U_(0x0) /**< \brief (PEVC_OVSR) No Overrun occured on Channel j */ 344 #define PEVC_OVSR_OVS_1_Val _U_(0x1) /**< \brief (PEVC_OVSR) Overrun occured on Channel j */ 345 #define PEVC_OVSR_OVS_0 (PEVC_OVSR_OVS_0_Val << PEVC_OVSR_OVS_Pos) 346 #define PEVC_OVSR_OVS_1 (PEVC_OVSR_OVS_1_Val << PEVC_OVSR_OVS_Pos) 347 #define PEVC_OVSR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_OVSR) MASK Register */ 348 349 /* -------- PEVC_OVSCR : (PEVC Offset: 0x054) ( /W 32) Overrun Status Clear Register -------- */ 350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 351 typedef union { 352 struct { 353 uint32_t OVSC:32; /*!< bit: 0..31 Overrun Interrupt Status Clear */ 354 } bit; /*!< Structure used for bit access */ 355 uint32_t reg; /*!< Type used for register access */ 356 } PEVC_OVSCR_Type; 357 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 358 359 #define PEVC_OVSCR_OFFSET 0x054 /**< \brief (PEVC_OVSCR offset) Overrun Status Clear Register */ 360 #define PEVC_OVSCR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_OVSCR reset_value) Overrun Status Clear Register */ 361 362 #define PEVC_OVSCR_OVSC_Pos 0 /**< \brief (PEVC_OVSCR) Overrun Interrupt Status Clear */ 363 #define PEVC_OVSCR_OVSC_Msk (_U_(0xFFFFFFFF) << PEVC_OVSCR_OVSC_Pos) 364 #define PEVC_OVSCR_OVSC(value) (PEVC_OVSCR_OVSC_Msk & ((value) << PEVC_OVSCR_OVSC_Pos)) 365 #define PEVC_OVSCR_OVSC_0_Val _U_(0x0) /**< \brief (PEVC_OVSCR) No Action */ 366 #define PEVC_OVSCR_OVSC_1_Val _U_(0x1) /**< \brief (PEVC_OVSCR) Clear Overrun Status Bit j */ 367 #define PEVC_OVSCR_OVSC_0 (PEVC_OVSCR_OVSC_0_Val << PEVC_OVSCR_OVSC_Pos) 368 #define PEVC_OVSCR_OVSC_1 (PEVC_OVSCR_OVSC_1_Val << PEVC_OVSCR_OVSC_Pos) 369 #define PEVC_OVSCR_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_OVSCR) MASK Register */ 370 371 /* -------- PEVC_CHMX : (PEVC Offset: 0x100) (R/W 32) CHMX Channel Multiplexer -------- */ 372 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 373 typedef union { 374 struct { 375 uint32_t EVMX:6; /*!< bit: 0.. 5 Event Multiplexer */ 376 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 377 uint32_t SMX:1; /*!< bit: 8 Software Event Multiplexer */ 378 uint32_t :23; /*!< bit: 9..31 Reserved */ 379 } bit; /*!< Structure used for bit access */ 380 uint32_t reg; /*!< Type used for register access */ 381 } PEVC_CHMX_Type; 382 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 383 384 #define PEVC_CHMX_OFFSET 0x100 /**< \brief (PEVC_CHMX offset) Channel Multiplexer */ 385 #define PEVC_CHMX_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_CHMX reset_value) Channel Multiplexer */ 386 387 #define PEVC_CHMX_EVMX_Pos 0 /**< \brief (PEVC_CHMX) Event Multiplexer */ 388 #define PEVC_CHMX_EVMX_Msk (_U_(0x3F) << PEVC_CHMX_EVMX_Pos) 389 #define PEVC_CHMX_EVMX(value) (PEVC_CHMX_EVMX_Msk & ((value) << PEVC_CHMX_EVMX_Pos)) 390 #define PEVC_CHMX_EVMX_0_Val _U_(0x0) /**< \brief (PEVC_CHMX) Event 0 */ 391 #define PEVC_CHMX_EVMX_1_Val _U_(0x1) /**< \brief (PEVC_CHMX) Event 1 */ 392 #define PEVC_CHMX_EVMX_0 (PEVC_CHMX_EVMX_0_Val << PEVC_CHMX_EVMX_Pos) 393 #define PEVC_CHMX_EVMX_1 (PEVC_CHMX_EVMX_1_Val << PEVC_CHMX_EVMX_Pos) 394 #define PEVC_CHMX_SMX_Pos 8 /**< \brief (PEVC_CHMX) Software Event Multiplexer */ 395 #define PEVC_CHMX_SMX (_U_(0x1) << PEVC_CHMX_SMX_Pos) 396 #define PEVC_CHMX_SMX_0_Val _U_(0x0) /**< \brief (PEVC_CHMX) Hardware events */ 397 #define PEVC_CHMX_SMX_1_Val _U_(0x1) /**< \brief (PEVC_CHMX) Software event */ 398 #define PEVC_CHMX_SMX_0 (PEVC_CHMX_SMX_0_Val << PEVC_CHMX_SMX_Pos) 399 #define PEVC_CHMX_SMX_1 (PEVC_CHMX_SMX_1_Val << PEVC_CHMX_SMX_Pos) 400 #define PEVC_CHMX_MASK _U_(0x0000013F) /**< \brief (PEVC_CHMX) MASK Register */ 401 402 /* -------- PEVC_EVS : (PEVC Offset: 0x200) (R/W 32) EVS Event Shaper -------- */ 403 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 404 typedef union { 405 struct { 406 uint32_t EN:1; /*!< bit: 0 Event Shaper Enable */ 407 uint32_t :15; /*!< bit: 1..15 Reserved */ 408 uint32_t IGFR:1; /*!< bit: 16 Input Glitch Filter Rise */ 409 uint32_t IGFF:1; /*!< bit: 17 Input Glitch Filter Fall */ 410 uint32_t IGFON:1; /*!< bit: 18 Input Glitch Filter Status */ 411 uint32_t :13; /*!< bit: 19..31 Reserved */ 412 } bit; /*!< Structure used for bit access */ 413 uint32_t reg; /*!< Type used for register access */ 414 } PEVC_EVS_Type; 415 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 416 417 #define PEVC_EVS_OFFSET 0x200 /**< \brief (PEVC_EVS offset) Event Shaper */ 418 #define PEVC_EVS_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_EVS reset_value) Event Shaper */ 419 420 #define PEVC_EVS_EN_Pos 0 /**< \brief (PEVC_EVS) Event Shaper Enable */ 421 #define PEVC_EVS_EN (_U_(0x1) << PEVC_EVS_EN_Pos) 422 #define PEVC_EVS_EN_0_Val _U_(0x0) /**< \brief (PEVC_EVS) No Action */ 423 #define PEVC_EVS_EN_1_Val _U_(0x1) /**< \brief (PEVC_EVS) Event Shaper enable */ 424 #define PEVC_EVS_EN_0 (PEVC_EVS_EN_0_Val << PEVC_EVS_EN_Pos) 425 #define PEVC_EVS_EN_1 (PEVC_EVS_EN_1_Val << PEVC_EVS_EN_Pos) 426 #define PEVC_EVS_IGFR_Pos 16 /**< \brief (PEVC_EVS) Input Glitch Filter Rise */ 427 #define PEVC_EVS_IGFR (_U_(0x1) << PEVC_EVS_IGFR_Pos) 428 #define PEVC_EVS_IGFR_0_Val _U_(0x0) /**< \brief (PEVC_EVS) No Action */ 429 #define PEVC_EVS_IGFR_1_Val _U_(0x1) /**< \brief (PEVC_EVS) Input Glitch Filter : a rising edge on event input will raise trigger output */ 430 #define PEVC_EVS_IGFR_0 (PEVC_EVS_IGFR_0_Val << PEVC_EVS_IGFR_Pos) 431 #define PEVC_EVS_IGFR_1 (PEVC_EVS_IGFR_1_Val << PEVC_EVS_IGFR_Pos) 432 #define PEVC_EVS_IGFF_Pos 17 /**< \brief (PEVC_EVS) Input Glitch Filter Fall */ 433 #define PEVC_EVS_IGFF (_U_(0x1) << PEVC_EVS_IGFF_Pos) 434 #define PEVC_EVS_IGFF_0_Val _U_(0x0) /**< \brief (PEVC_EVS) No Action */ 435 #define PEVC_EVS_IGFF_1_Val _U_(0x1) /**< \brief (PEVC_EVS) Input Glitch Filter : a falling edge on event input will raise trigger output */ 436 #define PEVC_EVS_IGFF_0 (PEVC_EVS_IGFF_0_Val << PEVC_EVS_IGFF_Pos) 437 #define PEVC_EVS_IGFF_1 (PEVC_EVS_IGFF_1_Val << PEVC_EVS_IGFF_Pos) 438 #define PEVC_EVS_IGFON_Pos 18 /**< \brief (PEVC_EVS) Input Glitch Filter Status */ 439 #define PEVC_EVS_IGFON (_U_(0x1) << PEVC_EVS_IGFON_Pos) 440 #define PEVC_EVS_MASK _U_(0x00070001) /**< \brief (PEVC_EVS) MASK Register */ 441 442 /* -------- PEVC_IGFDR : (PEVC Offset: 0x300) (R/W 32) Input Glitch Filter Divider Register -------- */ 443 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 444 typedef union { 445 struct { 446 uint32_t IGFDR:4; /*!< bit: 0.. 3 Input Glitch Filter Divider Register */ 447 uint32_t :28; /*!< bit: 4..31 Reserved */ 448 } bit; /*!< Structure used for bit access */ 449 uint32_t reg; /*!< Type used for register access */ 450 } PEVC_IGFDR_Type; 451 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 452 453 #define PEVC_IGFDR_OFFSET 0x300 /**< \brief (PEVC_IGFDR offset) Input Glitch Filter Divider Register */ 454 #define PEVC_IGFDR_RESETVALUE _U_(0x00000000); /**< \brief (PEVC_IGFDR reset_value) Input Glitch Filter Divider Register */ 455 456 #define PEVC_IGFDR_IGFDR_Pos 0 /**< \brief (PEVC_IGFDR) Input Glitch Filter Divider Register */ 457 #define PEVC_IGFDR_IGFDR_Msk (_U_(0xF) << PEVC_IGFDR_IGFDR_Pos) 458 #define PEVC_IGFDR_IGFDR(value) (PEVC_IGFDR_IGFDR_Msk & ((value) << PEVC_IGFDR_IGFDR_Pos)) 459 #define PEVC_IGFDR_MASK _U_(0x0000000F) /**< \brief (PEVC_IGFDR) MASK Register */ 460 461 /* -------- PEVC_PARAMETER : (PEVC Offset: 0x3F8) (R/ 32) Parameter -------- */ 462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 463 typedef union { 464 struct { 465 uint32_t IGF_COUNT:8; /*!< bit: 0.. 7 Number of Input Glitch Filters */ 466 uint32_t EVS_COUNT:8; /*!< bit: 8..15 Number of Event Shapers */ 467 uint32_t EVIN:8; /*!< bit: 16..23 Number of Event Inputs / Generators */ 468 uint32_t TRIGOUT:8; /*!< bit: 24..31 Number of Trigger Outputs / Channels / Users */ 469 } bit; /*!< Structure used for bit access */ 470 uint32_t reg; /*!< Type used for register access */ 471 } PEVC_PARAMETER_Type; 472 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 473 474 #define PEVC_PARAMETER_OFFSET 0x3F8 /**< \brief (PEVC_PARAMETER offset) Parameter */ 475 #define PEVC_PARAMETER_RESETVALUE _U_(0x14061824); /**< \brief (PEVC_PARAMETER reset_value) Parameter */ 476 477 #define PEVC_PARAMETER_IGF_COUNT_Pos 0 /**< \brief (PEVC_PARAMETER) Number of Input Glitch Filters */ 478 #define PEVC_PARAMETER_IGF_COUNT_Msk (_U_(0xFF) << PEVC_PARAMETER_IGF_COUNT_Pos) 479 #define PEVC_PARAMETER_IGF_COUNT(value) (PEVC_PARAMETER_IGF_COUNT_Msk & ((value) << PEVC_PARAMETER_IGF_COUNT_Pos)) 480 #define PEVC_PARAMETER_EVS_COUNT_Pos 8 /**< \brief (PEVC_PARAMETER) Number of Event Shapers */ 481 #define PEVC_PARAMETER_EVS_COUNT_Msk (_U_(0xFF) << PEVC_PARAMETER_EVS_COUNT_Pos) 482 #define PEVC_PARAMETER_EVS_COUNT(value) (PEVC_PARAMETER_EVS_COUNT_Msk & ((value) << PEVC_PARAMETER_EVS_COUNT_Pos)) 483 #define PEVC_PARAMETER_EVIN_Pos 16 /**< \brief (PEVC_PARAMETER) Number of Event Inputs / Generators */ 484 #define PEVC_PARAMETER_EVIN_Msk (_U_(0xFF) << PEVC_PARAMETER_EVIN_Pos) 485 #define PEVC_PARAMETER_EVIN(value) (PEVC_PARAMETER_EVIN_Msk & ((value) << PEVC_PARAMETER_EVIN_Pos)) 486 #define PEVC_PARAMETER_TRIGOUT_Pos 24 /**< \brief (PEVC_PARAMETER) Number of Trigger Outputs / Channels / Users */ 487 #define PEVC_PARAMETER_TRIGOUT_Msk (_U_(0xFF) << PEVC_PARAMETER_TRIGOUT_Pos) 488 #define PEVC_PARAMETER_TRIGOUT(value) (PEVC_PARAMETER_TRIGOUT_Msk & ((value) << PEVC_PARAMETER_TRIGOUT_Pos)) 489 #define PEVC_PARAMETER_MASK _U_(0xFFFFFFFF) /**< \brief (PEVC_PARAMETER) MASK Register */ 490 491 /* -------- PEVC_VERSION : (PEVC Offset: 0x3FC) (R/ 32) Version -------- */ 492 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 493 typedef union { 494 struct { 495 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 496 uint32_t :4; /*!< bit: 12..15 Reserved */ 497 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 498 uint32_t :12; /*!< bit: 20..31 Reserved */ 499 } bit; /*!< Structure used for bit access */ 500 uint32_t reg; /*!< Type used for register access */ 501 } PEVC_VERSION_Type; 502 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 503 504 #define PEVC_VERSION_OFFSET 0x3FC /**< \brief (PEVC_VERSION offset) Version */ 505 #define PEVC_VERSION_RESETVALUE _U_(0x00000200); /**< \brief (PEVC_VERSION reset_value) Version */ 506 507 #define PEVC_VERSION_VERSION_Pos 0 /**< \brief (PEVC_VERSION) Version Number */ 508 #define PEVC_VERSION_VERSION_Msk (_U_(0xFFF) << PEVC_VERSION_VERSION_Pos) 509 #define PEVC_VERSION_VERSION(value) (PEVC_VERSION_VERSION_Msk & ((value) << PEVC_VERSION_VERSION_Pos)) 510 #define PEVC_VERSION_VARIANT_Pos 16 /**< \brief (PEVC_VERSION) Variant Number */ 511 #define PEVC_VERSION_VARIANT_Msk (_U_(0xF) << PEVC_VERSION_VARIANT_Pos) 512 #define PEVC_VERSION_VARIANT(value) (PEVC_VERSION_VARIANT_Msk & ((value) << PEVC_VERSION_VARIANT_Pos)) 513 #define PEVC_VERSION_MASK _U_(0x000F0FFF) /**< \brief (PEVC_VERSION) MASK Register */ 514 515 /** \brief PevcChmx hardware registers */ 516 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 517 typedef union { 518 struct { 519 __IO PEVC_CHMX_Type CHMX; /**< \brief Offset: 0x000 (R/W 32) Channel Multiplexer */ 520 } bf; 521 struct { 522 RwReg PEVC_CHMX; /**< \brief (PEVC Offset: 0x000) Channel Multiplexer */ 523 } reg; 524 } PevcChmx; 525 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 /** \brief PevcEvs hardware registers */ 528 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 529 typedef union { 530 struct { 531 __IO PEVC_EVS_Type EVS; /**< \brief Offset: 0x000 (R/W 32) Event Shaper */ 532 } bf; 533 struct { 534 RwReg PEVC_EVS; /**< \brief (PEVC Offset: 0x000) Event Shaper */ 535 } reg; 536 } PevcEvs; 537 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 538 539 /** \brief PEVC hardware registers */ 540 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 541 typedef struct { 542 __I uint32_t CHSR; /**< \brief Offset: 0x000 (R/ 32) Channel Status Register */ 543 __O uint32_t CHER; /**< \brief Offset: 0x004 ( /W 32) Channel Enable Register */ 544 __O uint32_t CHDR; /**< \brief Offset: 0x008 ( /W 32) Channel Disable Register */ 545 RoReg8 Reserved1[0x4]; 546 __O uint32_t SEV; /**< \brief Offset: 0x010 ( /W 32) Software Event */ 547 __I uint32_t BUSY; /**< \brief Offset: 0x014 (R/ 32) Channel / User Busy */ 548 RoReg8 Reserved2[0x8]; 549 __O uint32_t TRIER; /**< \brief Offset: 0x020 ( /W 32) Trigger Interrupt Mask Enable Register */ 550 __O uint32_t TRIDR; /**< \brief Offset: 0x024 ( /W 32) Trigger Interrupt Mask Disable Register */ 551 __I uint32_t TRIMR; /**< \brief Offset: 0x028 (R/ 32) Trigger Interrupt Mask Register */ 552 RoReg8 Reserved3[0x4]; 553 __I uint32_t TRSR; /**< \brief Offset: 0x030 (R/ 32) Trigger Status Register */ 554 __O uint32_t TRSCR; /**< \brief Offset: 0x034 ( /W 32) Trigger Status Clear Register */ 555 RoReg8 Reserved4[0x8]; 556 __O uint32_t OVIER; /**< \brief Offset: 0x040 ( /W 32) Overrun Interrupt Mask Enable Register */ 557 __O uint32_t OVIDR; /**< \brief Offset: 0x044 ( /W 32) Overrun Interrupt Mask Disable Register */ 558 __I uint32_t OVIMR; /**< \brief Offset: 0x048 (R/ 32) Overrun Interrupt Mask Register */ 559 RoReg8 Reserved5[0x4]; 560 __I uint32_t OVSR; /**< \brief Offset: 0x050 (R/ 32) Overrun Status Register */ 561 __O uint32_t OVSCR; /**< \brief Offset: 0x054 ( /W 32) Overrun Status Clear Register */ 562 RoReg8 Reserved6[0xA8]; 563 __IO uint32_t Chmx[19]; /**< \brief Offset: 0x100 PevcChmx groups [TRIGOUT_BITS] */ 564 RoReg8 Reserved7[0xB4]; 565 __IO uint32_t Evs[31]; /**< \brief Offset: 0x200 PevcEvs groups [EVIN_BITS] */ 566 RoReg8 Reserved8[0x84]; 567 __IO uint32_t IGFDR; /**< \brief Offset: 0x300 (R/W 32) Input Glitch Filter Divider Register */ 568 RoReg8 Reserved9[0xF4]; 569 __I uint32_t PARAMETER; /**< \brief Offset: 0x3F8 (R/ 32) Parameter */ 570 __I uint32_t VERSION; /**< \brief Offset: 0x3FC (R/ 32) Version */ 571 } Pevc; 572 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 573 574 /*@}*/ 575 576 #endif /* _SAM4L_PEVC_COMPONENT_ */ 577
