1 /** 2 * \file 3 * 4 * \brief Component description for PARC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_PARC_COMPONENT_ 30 #define _SAM4L_PARC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PARC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_PARC Parallel Capture */ 36 /*@{*/ 37 38 #define PARC_I7570 39 #define REV_PARC 0x100 40 41 /* -------- PARC_CFG : (PARC Offset: 0x00) (R/W 32) Configuration Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t DSIZE:2; /*!< bit: 0.. 1 Data Size */ 46 uint32_t SMODE:2; /*!< bit: 2.. 3 Sampling Mode */ 47 uint32_t EMODE:1; /*!< bit: 4 Events Mode */ 48 uint32_t EDGE:1; /*!< bit: 5 Sampling Edge Select */ 49 uint32_t HALF:1; /*!< bit: 6 Half Capture */ 50 uint32_t ODD:1; /*!< bit: 7 Odd Capture */ 51 uint32_t :24; /*!< bit: 8..31 Reserved */ 52 } bit; /*!< Structure used for bit access */ 53 uint32_t reg; /*!< Type used for register access */ 54 } PARC_CFG_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 #define PARC_CFG_OFFSET 0x00 /**< \brief (PARC_CFG offset) Configuration Register */ 58 #define PARC_CFG_RESETVALUE _U_(0x00000000); /**< \brief (PARC_CFG reset_value) Configuration Register */ 59 60 #define PARC_CFG_DSIZE_Pos 0 /**< \brief (PARC_CFG) Data Size */ 61 #define PARC_CFG_DSIZE_Msk (_U_(0x3) << PARC_CFG_DSIZE_Pos) 62 #define PARC_CFG_DSIZE(value) (PARC_CFG_DSIZE_Msk & ((value) << PARC_CFG_DSIZE_Pos)) 63 #define PARC_CFG_SMODE_Pos 2 /**< \brief (PARC_CFG) Sampling Mode */ 64 #define PARC_CFG_SMODE_Msk (_U_(0x3) << PARC_CFG_SMODE_Pos) 65 #define PARC_CFG_SMODE(value) (PARC_CFG_SMODE_Msk & ((value) << PARC_CFG_SMODE_Pos)) 66 #define PARC_CFG_EMODE_Pos 4 /**< \brief (PARC_CFG) Events Mode */ 67 #define PARC_CFG_EMODE (_U_(0x1) << PARC_CFG_EMODE_Pos) 68 #define PARC_CFG_EDGE_Pos 5 /**< \brief (PARC_CFG) Sampling Edge Select */ 69 #define PARC_CFG_EDGE (_U_(0x1) << PARC_CFG_EDGE_Pos) 70 #define PARC_CFG_HALF_Pos 6 /**< \brief (PARC_CFG) Half Capture */ 71 #define PARC_CFG_HALF (_U_(0x1) << PARC_CFG_HALF_Pos) 72 #define PARC_CFG_ODD_Pos 7 /**< \brief (PARC_CFG) Odd Capture */ 73 #define PARC_CFG_ODD (_U_(0x1) << PARC_CFG_ODD_Pos) 74 #define PARC_CFG_MASK _U_(0x000000FF) /**< \brief (PARC_CFG) MASK Register */ 75 76 /* -------- PARC_CR : (PARC Offset: 0x04) (R/W 32) Control Register -------- */ 77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 78 typedef union { 79 struct { 80 uint32_t EN:1; /*!< bit: 0 Enable */ 81 uint32_t DIS:1; /*!< bit: 1 Disable */ 82 uint32_t START:1; /*!< bit: 2 Start Capture */ 83 uint32_t STOP:1; /*!< bit: 3 Stop Capture */ 84 uint32_t :28; /*!< bit: 4..31 Reserved */ 85 } bit; /*!< Structure used for bit access */ 86 uint32_t reg; /*!< Type used for register access */ 87 } PARC_CR_Type; 88 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 89 90 #define PARC_CR_OFFSET 0x04 /**< \brief (PARC_CR offset) Control Register */ 91 #define PARC_CR_RESETVALUE _U_(0x00000000); /**< \brief (PARC_CR reset_value) Control Register */ 92 93 #define PARC_CR_EN_Pos 0 /**< \brief (PARC_CR) Enable */ 94 #define PARC_CR_EN (_U_(0x1) << PARC_CR_EN_Pos) 95 #define PARC_CR_DIS_Pos 1 /**< \brief (PARC_CR) Disable */ 96 #define PARC_CR_DIS (_U_(0x1) << PARC_CR_DIS_Pos) 97 #define PARC_CR_START_Pos 2 /**< \brief (PARC_CR) Start Capture */ 98 #define PARC_CR_START (_U_(0x1) << PARC_CR_START_Pos) 99 #define PARC_CR_STOP_Pos 3 /**< \brief (PARC_CR) Stop Capture */ 100 #define PARC_CR_STOP (_U_(0x1) << PARC_CR_STOP_Pos) 101 #define PARC_CR_MASK _U_(0x0000000F) /**< \brief (PARC_CR) MASK Register */ 102 103 /* -------- PARC_IER : (PARC Offset: 0x08) ( /W 32) Interrupt Enable Register -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 108 uint32_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Enable */ 109 uint32_t OVR:1; /*!< bit: 3 Overrun Interrupt Enable */ 110 uint32_t :28; /*!< bit: 4..31 Reserved */ 111 } bit; /*!< Structure used for bit access */ 112 uint32_t reg; /*!< Type used for register access */ 113 } PARC_IER_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define PARC_IER_OFFSET 0x08 /**< \brief (PARC_IER offset) Interrupt Enable Register */ 117 #define PARC_IER_RESETVALUE _U_(0x00000000); /**< \brief (PARC_IER reset_value) Interrupt Enable Register */ 118 119 #define PARC_IER_DRDY_Pos 2 /**< \brief (PARC_IER) Data Ready Interrupt Enable */ 120 #define PARC_IER_DRDY (_U_(0x1) << PARC_IER_DRDY_Pos) 121 #define PARC_IER_OVR_Pos 3 /**< \brief (PARC_IER) Overrun Interrupt Enable */ 122 #define PARC_IER_OVR (_U_(0x1) << PARC_IER_OVR_Pos) 123 #define PARC_IER_MASK _U_(0x0000000C) /**< \brief (PARC_IER) MASK Register */ 124 125 /* -------- PARC_IDR : (PARC Offset: 0x0C) ( /W 32) Interrupt Disable Register -------- */ 126 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 127 typedef union { 128 struct { 129 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 130 uint32_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Disable */ 131 uint32_t OVR:1; /*!< bit: 3 Overrun Interrupt Disable */ 132 uint32_t :28; /*!< bit: 4..31 Reserved */ 133 } bit; /*!< Structure used for bit access */ 134 uint32_t reg; /*!< Type used for register access */ 135 } PARC_IDR_Type; 136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 #define PARC_IDR_OFFSET 0x0C /**< \brief (PARC_IDR offset) Interrupt Disable Register */ 139 #define PARC_IDR_RESETVALUE _U_(0x00000000); /**< \brief (PARC_IDR reset_value) Interrupt Disable Register */ 140 141 #define PARC_IDR_DRDY_Pos 2 /**< \brief (PARC_IDR) Data Ready Interrupt Disable */ 142 #define PARC_IDR_DRDY (_U_(0x1) << PARC_IDR_DRDY_Pos) 143 #define PARC_IDR_OVR_Pos 3 /**< \brief (PARC_IDR) Overrun Interrupt Disable */ 144 #define PARC_IDR_OVR (_U_(0x1) << PARC_IDR_OVR_Pos) 145 #define PARC_IDR_MASK _U_(0x0000000C) /**< \brief (PARC_IDR) MASK Register */ 146 147 /* -------- PARC_IMR : (PARC Offset: 0x10) (R/ 32) Interrupt Mask Register -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 152 uint32_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Mask */ 153 uint32_t OVR:1; /*!< bit: 3 Overrun Interrupt Mask */ 154 uint32_t :28; /*!< bit: 4..31 Reserved */ 155 } bit; /*!< Structure used for bit access */ 156 uint32_t reg; /*!< Type used for register access */ 157 } PARC_IMR_Type; 158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 159 160 #define PARC_IMR_OFFSET 0x10 /**< \brief (PARC_IMR offset) Interrupt Mask Register */ 161 #define PARC_IMR_RESETVALUE _U_(0x00000000); /**< \brief (PARC_IMR reset_value) Interrupt Mask Register */ 162 163 #define PARC_IMR_DRDY_Pos 2 /**< \brief (PARC_IMR) Data Ready Interrupt Mask */ 164 #define PARC_IMR_DRDY (_U_(0x1) << PARC_IMR_DRDY_Pos) 165 #define PARC_IMR_OVR_Pos 3 /**< \brief (PARC_IMR) Overrun Interrupt Mask */ 166 #define PARC_IMR_OVR (_U_(0x1) << PARC_IMR_OVR_Pos) 167 #define PARC_IMR_MASK _U_(0x0000000C) /**< \brief (PARC_IMR) MASK Register */ 168 169 /* -------- PARC_SR : (PARC Offset: 0x14) (R/ 32) Status Register -------- */ 170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 171 typedef union { 172 struct { 173 uint32_t EN:1; /*!< bit: 0 Enable Status */ 174 uint32_t CS:1; /*!< bit: 1 Capture Status */ 175 uint32_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Status */ 176 uint32_t OVR:1; /*!< bit: 3 Overrun Interrupt Status */ 177 uint32_t :28; /*!< bit: 4..31 Reserved */ 178 } bit; /*!< Structure used for bit access */ 179 uint32_t reg; /*!< Type used for register access */ 180 } PARC_SR_Type; 181 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 183 #define PARC_SR_OFFSET 0x14 /**< \brief (PARC_SR offset) Status Register */ 184 #define PARC_SR_RESETVALUE _U_(0x00000000); /**< \brief (PARC_SR reset_value) Status Register */ 185 186 #define PARC_SR_EN_Pos 0 /**< \brief (PARC_SR) Enable Status */ 187 #define PARC_SR_EN (_U_(0x1) << PARC_SR_EN_Pos) 188 #define PARC_SR_CS_Pos 1 /**< \brief (PARC_SR) Capture Status */ 189 #define PARC_SR_CS (_U_(0x1) << PARC_SR_CS_Pos) 190 #define PARC_SR_DRDY_Pos 2 /**< \brief (PARC_SR) Data Ready Interrupt Status */ 191 #define PARC_SR_DRDY (_U_(0x1) << PARC_SR_DRDY_Pos) 192 #define PARC_SR_OVR_Pos 3 /**< \brief (PARC_SR) Overrun Interrupt Status */ 193 #define PARC_SR_OVR (_U_(0x1) << PARC_SR_OVR_Pos) 194 #define PARC_SR_MASK _U_(0x0000000F) /**< \brief (PARC_SR) MASK Register */ 195 196 /* -------- PARC_ICR : (PARC Offset: 0x18) ( /W 32) Interrupt Status Clear Register -------- */ 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 198 typedef union { 199 struct { 200 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 201 uint32_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Status Clear */ 202 uint32_t OVR:1; /*!< bit: 3 Overrun Interrupt Status Clear */ 203 uint32_t :28; /*!< bit: 4..31 Reserved */ 204 } bit; /*!< Structure used for bit access */ 205 uint32_t reg; /*!< Type used for register access */ 206 } PARC_ICR_Type; 207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 208 209 #define PARC_ICR_OFFSET 0x18 /**< \brief (PARC_ICR offset) Interrupt Status Clear Register */ 210 #define PARC_ICR_RESETVALUE _U_(0x00000000); /**< \brief (PARC_ICR reset_value) Interrupt Status Clear Register */ 211 212 #define PARC_ICR_DRDY_Pos 2 /**< \brief (PARC_ICR) Data Ready Interrupt Status Clear */ 213 #define PARC_ICR_DRDY (_U_(0x1) << PARC_ICR_DRDY_Pos) 214 #define PARC_ICR_OVR_Pos 3 /**< \brief (PARC_ICR) Overrun Interrupt Status Clear */ 215 #define PARC_ICR_OVR (_U_(0x1) << PARC_ICR_OVR_Pos) 216 #define PARC_ICR_MASK _U_(0x0000000C) /**< \brief (PARC_ICR) MASK Register */ 217 218 /* -------- PARC_RHR : (PARC Offset: 0x1C) (R/ 32) Receive Holding Register -------- */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef union { 221 struct { 222 uint32_t CDATA:32; /*!< bit: 0..31 Captured Data */ 223 } bit; /*!< Structure used for bit access */ 224 uint32_t reg; /*!< Type used for register access */ 225 } PARC_RHR_Type; 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 227 228 #define PARC_RHR_OFFSET 0x1C /**< \brief (PARC_RHR offset) Receive Holding Register */ 229 #define PARC_RHR_RESETVALUE _U_(0x00000000); /**< \brief (PARC_RHR reset_value) Receive Holding Register */ 230 231 #define PARC_RHR_CDATA_Pos 0 /**< \brief (PARC_RHR) Captured Data */ 232 #define PARC_RHR_CDATA_Msk (_U_(0xFFFFFFFF) << PARC_RHR_CDATA_Pos) 233 #define PARC_RHR_CDATA(value) (PARC_RHR_CDATA_Msk & ((value) << PARC_RHR_CDATA_Pos)) 234 #define PARC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PARC_RHR) MASK Register */ 235 236 /* -------- PARC_VERSION : (PARC Offset: 0x20) (R/ 32) Version Register -------- */ 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 238 typedef union { 239 struct { 240 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 241 uint32_t :4; /*!< bit: 12..15 Reserved */ 242 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 243 uint32_t :12; /*!< bit: 20..31 Reserved */ 244 } bit; /*!< Structure used for bit access */ 245 uint32_t reg; /*!< Type used for register access */ 246 } PARC_VERSION_Type; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 #define PARC_VERSION_OFFSET 0x20 /**< \brief (PARC_VERSION offset) Version Register */ 250 #define PARC_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (PARC_VERSION reset_value) Version Register */ 251 252 #define PARC_VERSION_VERSION_Pos 0 /**< \brief (PARC_VERSION) Version Number */ 253 #define PARC_VERSION_VERSION_Msk (_U_(0xFFF) << PARC_VERSION_VERSION_Pos) 254 #define PARC_VERSION_VERSION(value) (PARC_VERSION_VERSION_Msk & ((value) << PARC_VERSION_VERSION_Pos)) 255 #define PARC_VERSION_VARIANT_Pos 16 /**< \brief (PARC_VERSION) Variant Number */ 256 #define PARC_VERSION_VARIANT_Msk (_U_(0xF) << PARC_VERSION_VARIANT_Pos) 257 #define PARC_VERSION_VARIANT(value) (PARC_VERSION_VARIANT_Msk & ((value) << PARC_VERSION_VARIANT_Pos)) 258 #define PARC_VERSION_MASK _U_(0x000F0FFF) /**< \brief (PARC_VERSION) MASK Register */ 259 260 /** \brief PARC hardware registers */ 261 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 262 typedef struct { 263 __IO uint32_t CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration Register */ 264 __IO uint32_t CR; /**< \brief Offset: 0x04 (R/W 32) Control Register */ 265 __O uint32_t IER; /**< \brief Offset: 0x08 ( /W 32) Interrupt Enable Register */ 266 __O uint32_t IDR; /**< \brief Offset: 0x0C ( /W 32) Interrupt Disable Register */ 267 __I uint32_t IMR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Mask Register */ 268 __I uint32_t SR; /**< \brief Offset: 0x14 (R/ 32) Status Register */ 269 __O uint32_t ICR; /**< \brief Offset: 0x18 ( /W 32) Interrupt Status Clear Register */ 270 __I uint32_t RHR; /**< \brief Offset: 0x1C (R/ 32) Receive Holding Register */ 271 __I uint32_t VERSION; /**< \brief Offset: 0x20 (R/ 32) Version Register */ 272 } Parc; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 /*@}*/ 276 277 #endif /* _SAM4L_PARC_COMPONENT_ */ 278
