1 /** 2 * \file 3 * 4 * \brief Component description for LCDCA 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_LCDCA_COMPONENT_ 30 #define _SAM4L_LCDCA_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR LCDCA */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_LCDCA LCD Controller */ 36 /*@{*/ 37 38 #define LCDCA_I7572 39 #define REV_LCDCA 0x100 40 41 /* -------- LCDCA_CR : (LCDCA Offset: 0x00) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t DIS:1; /*!< bit: 0 Disable */ 46 uint32_t EN:1; /*!< bit: 1 Enable */ 47 uint32_t FC0DIS:1; /*!< bit: 2 Frame Counter 0 Disable */ 48 uint32_t FC0EN:1; /*!< bit: 3 Frame Counter 0 Enable */ 49 uint32_t FC1DIS:1; /*!< bit: 4 Frame Counter 1 Disable */ 50 uint32_t FC1EN:1; /*!< bit: 5 Frame Counter 1 Enable */ 51 uint32_t FC2DIS:1; /*!< bit: 6 Frame Counter 2 Disable */ 52 uint32_t FC2EN:1; /*!< bit: 7 Frame Counter 2 Enable */ 53 uint32_t CDM:1; /*!< bit: 8 Clear Display Memory */ 54 uint32_t WDIS:1; /*!< bit: 9 Wake up Disable */ 55 uint32_t WEN:1; /*!< bit: 10 Wake up Enable */ 56 uint32_t BSTART:1; /*!< bit: 11 Blinking Start */ 57 uint32_t BSTOP:1; /*!< bit: 12 Blinking Stop */ 58 uint32_t CSTART:1; /*!< bit: 13 Circular Shift Start */ 59 uint32_t CSTOP:1; /*!< bit: 14 Circular Shift Stop */ 60 uint32_t :17; /*!< bit: 15..31 Reserved */ 61 } bit; /*!< Structure used for bit access */ 62 uint32_t reg; /*!< Type used for register access */ 63 } LCDCA_CR_Type; 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 #define LCDCA_CR_OFFSET 0x00 /**< \brief (LCDCA_CR offset) Control Register */ 67 #define LCDCA_CR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_CR reset_value) Control Register */ 68 69 #define LCDCA_CR_DIS_Pos 0 /**< \brief (LCDCA_CR) Disable */ 70 #define LCDCA_CR_DIS (_U_(0x1) << LCDCA_CR_DIS_Pos) 71 #define LCDCA_CR_EN_Pos 1 /**< \brief (LCDCA_CR) Enable */ 72 #define LCDCA_CR_EN (_U_(0x1) << LCDCA_CR_EN_Pos) 73 #define LCDCA_CR_FC0DIS_Pos 2 /**< \brief (LCDCA_CR) Frame Counter 0 Disable */ 74 #define LCDCA_CR_FC0DIS (_U_(0x1) << LCDCA_CR_FC0DIS_Pos) 75 #define LCDCA_CR_FC0EN_Pos 3 /**< \brief (LCDCA_CR) Frame Counter 0 Enable */ 76 #define LCDCA_CR_FC0EN (_U_(0x1) << LCDCA_CR_FC0EN_Pos) 77 #define LCDCA_CR_FC1DIS_Pos 4 /**< \brief (LCDCA_CR) Frame Counter 1 Disable */ 78 #define LCDCA_CR_FC1DIS (_U_(0x1) << LCDCA_CR_FC1DIS_Pos) 79 #define LCDCA_CR_FC1EN_Pos 5 /**< \brief (LCDCA_CR) Frame Counter 1 Enable */ 80 #define LCDCA_CR_FC1EN (_U_(0x1) << LCDCA_CR_FC1EN_Pos) 81 #define LCDCA_CR_FC2DIS_Pos 6 /**< \brief (LCDCA_CR) Frame Counter 2 Disable */ 82 #define LCDCA_CR_FC2DIS (_U_(0x1) << LCDCA_CR_FC2DIS_Pos) 83 #define LCDCA_CR_FC2EN_Pos 7 /**< \brief (LCDCA_CR) Frame Counter 2 Enable */ 84 #define LCDCA_CR_FC2EN (_U_(0x1) << LCDCA_CR_FC2EN_Pos) 85 #define LCDCA_CR_CDM_Pos 8 /**< \brief (LCDCA_CR) Clear Display Memory */ 86 #define LCDCA_CR_CDM (_U_(0x1) << LCDCA_CR_CDM_Pos) 87 #define LCDCA_CR_WDIS_Pos 9 /**< \brief (LCDCA_CR) Wake up Disable */ 88 #define LCDCA_CR_WDIS (_U_(0x1) << LCDCA_CR_WDIS_Pos) 89 #define LCDCA_CR_WEN_Pos 10 /**< \brief (LCDCA_CR) Wake up Enable */ 90 #define LCDCA_CR_WEN (_U_(0x1) << LCDCA_CR_WEN_Pos) 91 #define LCDCA_CR_BSTART_Pos 11 /**< \brief (LCDCA_CR) Blinking Start */ 92 #define LCDCA_CR_BSTART (_U_(0x1) << LCDCA_CR_BSTART_Pos) 93 #define LCDCA_CR_BSTOP_Pos 12 /**< \brief (LCDCA_CR) Blinking Stop */ 94 #define LCDCA_CR_BSTOP (_U_(0x1) << LCDCA_CR_BSTOP_Pos) 95 #define LCDCA_CR_CSTART_Pos 13 /**< \brief (LCDCA_CR) Circular Shift Start */ 96 #define LCDCA_CR_CSTART (_U_(0x1) << LCDCA_CR_CSTART_Pos) 97 #define LCDCA_CR_CSTOP_Pos 14 /**< \brief (LCDCA_CR) Circular Shift Stop */ 98 #define LCDCA_CR_CSTOP (_U_(0x1) << LCDCA_CR_CSTOP_Pos) 99 #define LCDCA_CR_MASK _U_(0x00007FFF) /**< \brief (LCDCA_CR) MASK Register */ 100 101 /* -------- LCDCA_CFG : (LCDCA Offset: 0x04) (R/W 32) Configuration Register -------- */ 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 103 typedef union { 104 struct { 105 uint32_t XBIAS:1; /*!< bit: 0 External Bias Generation */ 106 uint32_t WMOD:1; /*!< bit: 1 Waveform Mode */ 107 uint32_t BLANK:1; /*!< bit: 2 Blank LCD */ 108 uint32_t LOCK:1; /*!< bit: 3 Lock */ 109 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 110 uint32_t DUTY:2; /*!< bit: 8.. 9 Duty Select */ 111 uint32_t :6; /*!< bit: 10..15 Reserved */ 112 uint32_t FCST:6; /*!< bit: 16..21 Fine Contrast */ 113 uint32_t :2; /*!< bit: 22..23 Reserved */ 114 uint32_t NSU:6; /*!< bit: 24..29 Number of Segment Terminals in Use */ 115 uint32_t :2; /*!< bit: 30..31 Reserved */ 116 } bit; /*!< Structure used for bit access */ 117 uint32_t reg; /*!< Type used for register access */ 118 } LCDCA_CFG_Type; 119 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 #define LCDCA_CFG_OFFSET 0x04 /**< \brief (LCDCA_CFG offset) Configuration Register */ 122 #define LCDCA_CFG_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_CFG reset_value) Configuration Register */ 123 124 #define LCDCA_CFG_XBIAS_Pos 0 /**< \brief (LCDCA_CFG) External Bias Generation */ 125 #define LCDCA_CFG_XBIAS (_U_(0x1) << LCDCA_CFG_XBIAS_Pos) 126 #define LCDCA_CFG_WMOD_Pos 1 /**< \brief (LCDCA_CFG) Waveform Mode */ 127 #define LCDCA_CFG_WMOD (_U_(0x1) << LCDCA_CFG_WMOD_Pos) 128 #define LCDCA_CFG_BLANK_Pos 2 /**< \brief (LCDCA_CFG) Blank LCD */ 129 #define LCDCA_CFG_BLANK (_U_(0x1) << LCDCA_CFG_BLANK_Pos) 130 #define LCDCA_CFG_LOCK_Pos 3 /**< \brief (LCDCA_CFG) Lock */ 131 #define LCDCA_CFG_LOCK (_U_(0x1) << LCDCA_CFG_LOCK_Pos) 132 #define LCDCA_CFG_DUTY_Pos 8 /**< \brief (LCDCA_CFG) Duty Select */ 133 #define LCDCA_CFG_DUTY_Msk (_U_(0x3) << LCDCA_CFG_DUTY_Pos) 134 #define LCDCA_CFG_DUTY(value) (LCDCA_CFG_DUTY_Msk & ((value) << LCDCA_CFG_DUTY_Pos)) 135 #define LCDCA_CFG_FCST_Pos 16 /**< \brief (LCDCA_CFG) Fine Contrast */ 136 #define LCDCA_CFG_FCST_Msk (_U_(0x3F) << LCDCA_CFG_FCST_Pos) 137 #define LCDCA_CFG_FCST(value) (LCDCA_CFG_FCST_Msk & ((value) << LCDCA_CFG_FCST_Pos)) 138 #define LCDCA_CFG_NSU_Pos 24 /**< \brief (LCDCA_CFG) Number of Segment Terminals in Use */ 139 #define LCDCA_CFG_NSU_Msk (_U_(0x3F) << LCDCA_CFG_NSU_Pos) 140 #define LCDCA_CFG_NSU(value) (LCDCA_CFG_NSU_Msk & ((value) << LCDCA_CFG_NSU_Pos)) 141 #define LCDCA_CFG_MASK _U_(0x3F3F030F) /**< \brief (LCDCA_CFG) MASK Register */ 142 143 /* -------- LCDCA_TIM : (LCDCA Offset: 0x08) (R/W 32) Timing Register -------- */ 144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 145 typedef union { 146 struct { 147 uint32_t PRESC:1; /*!< bit: 0 LCD Prescaler Select */ 148 uint32_t CLKDIV:3; /*!< bit: 1.. 3 LCD Clock Division */ 149 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 150 uint32_t FC0:5; /*!< bit: 8..12 Frame Counter 0 */ 151 uint32_t FC0PB:1; /*!< bit: 13 Frame Counter 0 Prescaler Bypass */ 152 uint32_t :2; /*!< bit: 14..15 Reserved */ 153 uint32_t FC1:5; /*!< bit: 16..20 Frame Counter 1 */ 154 uint32_t :3; /*!< bit: 21..23 Reserved */ 155 uint32_t FC2:5; /*!< bit: 24..28 Frame Counter 2 */ 156 uint32_t :3; /*!< bit: 29..31 Reserved */ 157 } bit; /*!< Structure used for bit access */ 158 uint32_t reg; /*!< Type used for register access */ 159 } LCDCA_TIM_Type; 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 #define LCDCA_TIM_OFFSET 0x08 /**< \brief (LCDCA_TIM offset) Timing Register */ 163 #define LCDCA_TIM_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_TIM reset_value) Timing Register */ 164 165 #define LCDCA_TIM_PRESC_Pos 0 /**< \brief (LCDCA_TIM) LCD Prescaler Select */ 166 #define LCDCA_TIM_PRESC (_U_(0x1) << LCDCA_TIM_PRESC_Pos) 167 #define LCDCA_TIM_CLKDIV_Pos 1 /**< \brief (LCDCA_TIM) LCD Clock Division */ 168 #define LCDCA_TIM_CLKDIV_Msk (_U_(0x7) << LCDCA_TIM_CLKDIV_Pos) 169 #define LCDCA_TIM_CLKDIV(value) (LCDCA_TIM_CLKDIV_Msk & ((value) << LCDCA_TIM_CLKDIV_Pos)) 170 #define LCDCA_TIM_FC0_Pos 8 /**< \brief (LCDCA_TIM) Frame Counter 0 */ 171 #define LCDCA_TIM_FC0_Msk (_U_(0x1F) << LCDCA_TIM_FC0_Pos) 172 #define LCDCA_TIM_FC0(value) (LCDCA_TIM_FC0_Msk & ((value) << LCDCA_TIM_FC0_Pos)) 173 #define LCDCA_TIM_FC0PB_Pos 13 /**< \brief (LCDCA_TIM) Frame Counter 0 Prescaler Bypass */ 174 #define LCDCA_TIM_FC0PB (_U_(0x1) << LCDCA_TIM_FC0PB_Pos) 175 #define LCDCA_TIM_FC1_Pos 16 /**< \brief (LCDCA_TIM) Frame Counter 1 */ 176 #define LCDCA_TIM_FC1_Msk (_U_(0x1F) << LCDCA_TIM_FC1_Pos) 177 #define LCDCA_TIM_FC1(value) (LCDCA_TIM_FC1_Msk & ((value) << LCDCA_TIM_FC1_Pos)) 178 #define LCDCA_TIM_FC2_Pos 24 /**< \brief (LCDCA_TIM) Frame Counter 2 */ 179 #define LCDCA_TIM_FC2_Msk (_U_(0x1F) << LCDCA_TIM_FC2_Pos) 180 #define LCDCA_TIM_FC2(value) (LCDCA_TIM_FC2_Msk & ((value) << LCDCA_TIM_FC2_Pos)) 181 #define LCDCA_TIM_MASK _U_(0x1F1F3F0F) /**< \brief (LCDCA_TIM) MASK Register */ 182 183 /* -------- LCDCA_SR : (LCDCA Offset: 0x0C) (R/ 32) Status Register -------- */ 184 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 185 typedef union { 186 struct { 187 uint32_t FC0R:1; /*!< bit: 0 Frame Counter 0 Rollover */ 188 uint32_t FC0S:1; /*!< bit: 1 Frame Counter 0 Status */ 189 uint32_t FC1S:1; /*!< bit: 2 Frame Counter 1 Status */ 190 uint32_t FC2S:1; /*!< bit: 3 Frame Counter 2 Status */ 191 uint32_t EN:1; /*!< bit: 4 LCDCA Status */ 192 uint32_t WEN:1; /*!< bit: 5 Wake up Status */ 193 uint32_t BLKS:1; /*!< bit: 6 Blink Status */ 194 uint32_t CSRS:1; /*!< bit: 7 Circular Shift Register Status */ 195 uint32_t CPS:1; /*!< bit: 8 Charge Pump Status */ 196 uint32_t :23; /*!< bit: 9..31 Reserved */ 197 } bit; /*!< Structure used for bit access */ 198 uint32_t reg; /*!< Type used for register access */ 199 } LCDCA_SR_Type; 200 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 201 202 #define LCDCA_SR_OFFSET 0x0C /**< \brief (LCDCA_SR offset) Status Register */ 203 #define LCDCA_SR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_SR reset_value) Status Register */ 204 205 #define LCDCA_SR_FC0R_Pos 0 /**< \brief (LCDCA_SR) Frame Counter 0 Rollover */ 206 #define LCDCA_SR_FC0R (_U_(0x1) << LCDCA_SR_FC0R_Pos) 207 #define LCDCA_SR_FC0S_Pos 1 /**< \brief (LCDCA_SR) Frame Counter 0 Status */ 208 #define LCDCA_SR_FC0S (_U_(0x1) << LCDCA_SR_FC0S_Pos) 209 #define LCDCA_SR_FC1S_Pos 2 /**< \brief (LCDCA_SR) Frame Counter 1 Status */ 210 #define LCDCA_SR_FC1S (_U_(0x1) << LCDCA_SR_FC1S_Pos) 211 #define LCDCA_SR_FC2S_Pos 3 /**< \brief (LCDCA_SR) Frame Counter 2 Status */ 212 #define LCDCA_SR_FC2S (_U_(0x1) << LCDCA_SR_FC2S_Pos) 213 #define LCDCA_SR_EN_Pos 4 /**< \brief (LCDCA_SR) LCDCA Status */ 214 #define LCDCA_SR_EN (_U_(0x1) << LCDCA_SR_EN_Pos) 215 #define LCDCA_SR_WEN_Pos 5 /**< \brief (LCDCA_SR) Wake up Status */ 216 #define LCDCA_SR_WEN (_U_(0x1) << LCDCA_SR_WEN_Pos) 217 #define LCDCA_SR_BLKS_Pos 6 /**< \brief (LCDCA_SR) Blink Status */ 218 #define LCDCA_SR_BLKS (_U_(0x1) << LCDCA_SR_BLKS_Pos) 219 #define LCDCA_SR_CSRS_Pos 7 /**< \brief (LCDCA_SR) Circular Shift Register Status */ 220 #define LCDCA_SR_CSRS (_U_(0x1) << LCDCA_SR_CSRS_Pos) 221 #define LCDCA_SR_CPS_Pos 8 /**< \brief (LCDCA_SR) Charge Pump Status */ 222 #define LCDCA_SR_CPS (_U_(0x1) << LCDCA_SR_CPS_Pos) 223 #define LCDCA_SR_MASK _U_(0x000001FF) /**< \brief (LCDCA_SR) MASK Register */ 224 225 /* -------- LCDCA_SCR : (LCDCA Offset: 0x10) ( /W 32) Status Clear Register -------- */ 226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 227 typedef union { 228 struct { 229 uint32_t FC0R:1; /*!< bit: 0 Frame Counter 0 Rollover */ 230 uint32_t :31; /*!< bit: 1..31 Reserved */ 231 } bit; /*!< Structure used for bit access */ 232 uint32_t reg; /*!< Type used for register access */ 233 } LCDCA_SCR_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define LCDCA_SCR_OFFSET 0x10 /**< \brief (LCDCA_SCR offset) Status Clear Register */ 237 #define LCDCA_SCR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_SCR reset_value) Status Clear Register */ 238 239 #define LCDCA_SCR_FC0R_Pos 0 /**< \brief (LCDCA_SCR) Frame Counter 0 Rollover */ 240 #define LCDCA_SCR_FC0R (_U_(0x1) << LCDCA_SCR_FC0R_Pos) 241 #define LCDCA_SCR_MASK _U_(0x00000001) /**< \brief (LCDCA_SCR) MASK Register */ 242 243 /* -------- LCDCA_DRL0 : (LCDCA Offset: 0x14) (R/W 32) Data Register Low 0 -------- */ 244 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 245 typedef union { 246 struct { 247 uint32_t DATA:32; /*!< bit: 0..31 Segments Value */ 248 } bit; /*!< Structure used for bit access */ 249 uint32_t reg; /*!< Type used for register access */ 250 } LCDCA_DRL0_Type; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #define LCDCA_DRL0_OFFSET 0x14 /**< \brief (LCDCA_DRL0 offset) Data Register Low 0 */ 254 #define LCDCA_DRL0_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRL0 reset_value) Data Register Low 0 */ 255 256 #define LCDCA_DRL0_DATA_Pos 0 /**< \brief (LCDCA_DRL0) Segments Value */ 257 #define LCDCA_DRL0_DATA_Msk (_U_(0xFFFFFFFF) << LCDCA_DRL0_DATA_Pos) 258 #define LCDCA_DRL0_DATA(value) (LCDCA_DRL0_DATA_Msk & ((value) << LCDCA_DRL0_DATA_Pos)) 259 #define LCDCA_DRL0_MASK _U_(0xFFFFFFFF) /**< \brief (LCDCA_DRL0) MASK Register */ 260 261 /* -------- LCDCA_DRH0 : (LCDCA Offset: 0x18) (R/W 32) Data Register High 0 -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint32_t DATA:8; /*!< bit: 0.. 7 Segments Value */ 266 uint32_t :24; /*!< bit: 8..31 Reserved */ 267 } bit; /*!< Structure used for bit access */ 268 uint32_t reg; /*!< Type used for register access */ 269 } LCDCA_DRH0_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define LCDCA_DRH0_OFFSET 0x18 /**< \brief (LCDCA_DRH0 offset) Data Register High 0 */ 273 #define LCDCA_DRH0_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRH0 reset_value) Data Register High 0 */ 274 275 #define LCDCA_DRH0_DATA_Pos 0 /**< \brief (LCDCA_DRH0) Segments Value */ 276 #define LCDCA_DRH0_DATA_Msk (_U_(0xFF) << LCDCA_DRH0_DATA_Pos) 277 #define LCDCA_DRH0_DATA(value) (LCDCA_DRH0_DATA_Msk & ((value) << LCDCA_DRH0_DATA_Pos)) 278 #define LCDCA_DRH0_MASK _U_(0x000000FF) /**< \brief (LCDCA_DRH0) MASK Register */ 279 280 /* -------- LCDCA_DRL1 : (LCDCA Offset: 0x1C) (R/W 32) Data Register Low 1 -------- */ 281 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 282 typedef union { 283 struct { 284 uint32_t DATA:32; /*!< bit: 0..31 Segments Value */ 285 } bit; /*!< Structure used for bit access */ 286 uint32_t reg; /*!< Type used for register access */ 287 } LCDCA_DRL1_Type; 288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 289 290 #define LCDCA_DRL1_OFFSET 0x1C /**< \brief (LCDCA_DRL1 offset) Data Register Low 1 */ 291 #define LCDCA_DRL1_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRL1 reset_value) Data Register Low 1 */ 292 293 #define LCDCA_DRL1_DATA_Pos 0 /**< \brief (LCDCA_DRL1) Segments Value */ 294 #define LCDCA_DRL1_DATA_Msk (_U_(0xFFFFFFFF) << LCDCA_DRL1_DATA_Pos) 295 #define LCDCA_DRL1_DATA(value) (LCDCA_DRL1_DATA_Msk & ((value) << LCDCA_DRL1_DATA_Pos)) 296 #define LCDCA_DRL1_MASK _U_(0xFFFFFFFF) /**< \brief (LCDCA_DRL1) MASK Register */ 297 298 /* -------- LCDCA_DRH1 : (LCDCA Offset: 0x20) (R/W 32) Data Register High 1 -------- */ 299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 300 typedef union { 301 struct { 302 uint32_t DATA:8; /*!< bit: 0.. 7 Segments Value */ 303 uint32_t :24; /*!< bit: 8..31 Reserved */ 304 } bit; /*!< Structure used for bit access */ 305 uint32_t reg; /*!< Type used for register access */ 306 } LCDCA_DRH1_Type; 307 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 308 309 #define LCDCA_DRH1_OFFSET 0x20 /**< \brief (LCDCA_DRH1 offset) Data Register High 1 */ 310 #define LCDCA_DRH1_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRH1 reset_value) Data Register High 1 */ 311 312 #define LCDCA_DRH1_DATA_Pos 0 /**< \brief (LCDCA_DRH1) Segments Value */ 313 #define LCDCA_DRH1_DATA_Msk (_U_(0xFF) << LCDCA_DRH1_DATA_Pos) 314 #define LCDCA_DRH1_DATA(value) (LCDCA_DRH1_DATA_Msk & ((value) << LCDCA_DRH1_DATA_Pos)) 315 #define LCDCA_DRH1_MASK _U_(0x000000FF) /**< \brief (LCDCA_DRH1) MASK Register */ 316 317 /* -------- LCDCA_DRL2 : (LCDCA Offset: 0x24) (R/W 32) Data Register Low 2 -------- */ 318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 319 typedef union { 320 struct { 321 uint32_t DATA:32; /*!< bit: 0..31 Segments Value */ 322 } bit; /*!< Structure used for bit access */ 323 uint32_t reg; /*!< Type used for register access */ 324 } LCDCA_DRL2_Type; 325 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 326 327 #define LCDCA_DRL2_OFFSET 0x24 /**< \brief (LCDCA_DRL2 offset) Data Register Low 2 */ 328 #define LCDCA_DRL2_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRL2 reset_value) Data Register Low 2 */ 329 330 #define LCDCA_DRL2_DATA_Pos 0 /**< \brief (LCDCA_DRL2) Segments Value */ 331 #define LCDCA_DRL2_DATA_Msk (_U_(0xFFFFFFFF) << LCDCA_DRL2_DATA_Pos) 332 #define LCDCA_DRL2_DATA(value) (LCDCA_DRL2_DATA_Msk & ((value) << LCDCA_DRL2_DATA_Pos)) 333 #define LCDCA_DRL2_MASK _U_(0xFFFFFFFF) /**< \brief (LCDCA_DRL2) MASK Register */ 334 335 /* -------- LCDCA_DRH2 : (LCDCA Offset: 0x28) (R/W 32) Data Register High 2 -------- */ 336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 337 typedef union { 338 struct { 339 uint32_t DATA:8; /*!< bit: 0.. 7 Segments Value */ 340 uint32_t :24; /*!< bit: 8..31 Reserved */ 341 } bit; /*!< Structure used for bit access */ 342 uint32_t reg; /*!< Type used for register access */ 343 } LCDCA_DRH2_Type; 344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 345 346 #define LCDCA_DRH2_OFFSET 0x28 /**< \brief (LCDCA_DRH2 offset) Data Register High 2 */ 347 #define LCDCA_DRH2_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRH2 reset_value) Data Register High 2 */ 348 349 #define LCDCA_DRH2_DATA_Pos 0 /**< \brief (LCDCA_DRH2) Segments Value */ 350 #define LCDCA_DRH2_DATA_Msk (_U_(0xFF) << LCDCA_DRH2_DATA_Pos) 351 #define LCDCA_DRH2_DATA(value) (LCDCA_DRH2_DATA_Msk & ((value) << LCDCA_DRH2_DATA_Pos)) 352 #define LCDCA_DRH2_MASK _U_(0x000000FF) /**< \brief (LCDCA_DRH2) MASK Register */ 353 354 /* -------- LCDCA_DRL3 : (LCDCA Offset: 0x2C) (R/W 32) Data Register Low 3 -------- */ 355 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 356 typedef union { 357 struct { 358 uint32_t DATA:32; /*!< bit: 0..31 Segments Value */ 359 } bit; /*!< Structure used for bit access */ 360 uint32_t reg; /*!< Type used for register access */ 361 } LCDCA_DRL3_Type; 362 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 363 364 #define LCDCA_DRL3_OFFSET 0x2C /**< \brief (LCDCA_DRL3 offset) Data Register Low 3 */ 365 #define LCDCA_DRL3_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRL3 reset_value) Data Register Low 3 */ 366 367 #define LCDCA_DRL3_DATA_Pos 0 /**< \brief (LCDCA_DRL3) Segments Value */ 368 #define LCDCA_DRL3_DATA_Msk (_U_(0xFFFFFFFF) << LCDCA_DRL3_DATA_Pos) 369 #define LCDCA_DRL3_DATA(value) (LCDCA_DRL3_DATA_Msk & ((value) << LCDCA_DRL3_DATA_Pos)) 370 #define LCDCA_DRL3_MASK _U_(0xFFFFFFFF) /**< \brief (LCDCA_DRL3) MASK Register */ 371 372 /* -------- LCDCA_DRH3 : (LCDCA Offset: 0x30) (R/W 32) Data Register High 3 -------- */ 373 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 374 typedef union { 375 struct { 376 uint32_t DATA:8; /*!< bit: 0.. 7 Segments Value */ 377 uint32_t :24; /*!< bit: 8..31 Reserved */ 378 } bit; /*!< Structure used for bit access */ 379 uint32_t reg; /*!< Type used for register access */ 380 } LCDCA_DRH3_Type; 381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 382 383 #define LCDCA_DRH3_OFFSET 0x30 /**< \brief (LCDCA_DRH3 offset) Data Register High 3 */ 384 #define LCDCA_DRH3_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_DRH3 reset_value) Data Register High 3 */ 385 386 #define LCDCA_DRH3_DATA_Pos 0 /**< \brief (LCDCA_DRH3) Segments Value */ 387 #define LCDCA_DRH3_DATA_Msk (_U_(0xFF) << LCDCA_DRH3_DATA_Pos) 388 #define LCDCA_DRH3_DATA(value) (LCDCA_DRH3_DATA_Msk & ((value) << LCDCA_DRH3_DATA_Pos)) 389 #define LCDCA_DRH3_MASK _U_(0x000000FF) /**< \brief (LCDCA_DRH3) MASK Register */ 390 391 /* -------- LCDCA_IADR : (LCDCA Offset: 0x34) ( /W 32) Indirect Access Data Register -------- */ 392 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 393 typedef union { 394 struct { 395 uint32_t DATA:8; /*!< bit: 0.. 7 Segments Value */ 396 uint32_t DMASK:8; /*!< bit: 8..15 Data Mask */ 397 uint32_t OFF:5; /*!< bit: 16..20 Byte Offset */ 398 uint32_t :11; /*!< bit: 21..31 Reserved */ 399 } bit; /*!< Structure used for bit access */ 400 uint32_t reg; /*!< Type used for register access */ 401 } LCDCA_IADR_Type; 402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 403 404 #define LCDCA_IADR_OFFSET 0x34 /**< \brief (LCDCA_IADR offset) Indirect Access Data Register */ 405 #define LCDCA_IADR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_IADR reset_value) Indirect Access Data Register */ 406 407 #define LCDCA_IADR_DATA_Pos 0 /**< \brief (LCDCA_IADR) Segments Value */ 408 #define LCDCA_IADR_DATA_Msk (_U_(0xFF) << LCDCA_IADR_DATA_Pos) 409 #define LCDCA_IADR_DATA(value) (LCDCA_IADR_DATA_Msk & ((value) << LCDCA_IADR_DATA_Pos)) 410 #define LCDCA_IADR_DMASK_Pos 8 /**< \brief (LCDCA_IADR) Data Mask */ 411 #define LCDCA_IADR_DMASK_Msk (_U_(0xFF) << LCDCA_IADR_DMASK_Pos) 412 #define LCDCA_IADR_DMASK(value) (LCDCA_IADR_DMASK_Msk & ((value) << LCDCA_IADR_DMASK_Pos)) 413 #define LCDCA_IADR_OFF_Pos 16 /**< \brief (LCDCA_IADR) Byte Offset */ 414 #define LCDCA_IADR_OFF_Msk (_U_(0x1F) << LCDCA_IADR_OFF_Pos) 415 #define LCDCA_IADR_OFF(value) (LCDCA_IADR_OFF_Msk & ((value) << LCDCA_IADR_OFF_Pos)) 416 #define LCDCA_IADR_MASK _U_(0x001FFFFF) /**< \brief (LCDCA_IADR) MASK Register */ 417 418 /* -------- LCDCA_BCFG : (LCDCA Offset: 0x38) (R/W 32) Blink Configuration Register -------- */ 419 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 420 typedef union { 421 struct { 422 uint32_t MODE:1; /*!< bit: 0 Blinking Mode */ 423 uint32_t FCS:2; /*!< bit: 1.. 2 Frame Counter Selection */ 424 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 425 uint32_t BSS0:4; /*!< bit: 8..11 Blink Segment Selection 0 */ 426 uint32_t BSS1:4; /*!< bit: 12..15 Blink Segment Selection 1 */ 427 uint32_t :16; /*!< bit: 16..31 Reserved */ 428 } bit; /*!< Structure used for bit access */ 429 uint32_t reg; /*!< Type used for register access */ 430 } LCDCA_BCFG_Type; 431 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 432 433 #define LCDCA_BCFG_OFFSET 0x38 /**< \brief (LCDCA_BCFG offset) Blink Configuration Register */ 434 #define LCDCA_BCFG_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_BCFG reset_value) Blink Configuration Register */ 435 436 #define LCDCA_BCFG_MODE_Pos 0 /**< \brief (LCDCA_BCFG) Blinking Mode */ 437 #define LCDCA_BCFG_MODE (_U_(0x1) << LCDCA_BCFG_MODE_Pos) 438 #define LCDCA_BCFG_FCS_Pos 1 /**< \brief (LCDCA_BCFG) Frame Counter Selection */ 439 #define LCDCA_BCFG_FCS_Msk (_U_(0x3) << LCDCA_BCFG_FCS_Pos) 440 #define LCDCA_BCFG_FCS(value) (LCDCA_BCFG_FCS_Msk & ((value) << LCDCA_BCFG_FCS_Pos)) 441 #define LCDCA_BCFG_BSS0_Pos 8 /**< \brief (LCDCA_BCFG) Blink Segment Selection 0 */ 442 #define LCDCA_BCFG_BSS0_Msk (_U_(0xF) << LCDCA_BCFG_BSS0_Pos) 443 #define LCDCA_BCFG_BSS0(value) (LCDCA_BCFG_BSS0_Msk & ((value) << LCDCA_BCFG_BSS0_Pos)) 444 #define LCDCA_BCFG_BSS1_Pos 12 /**< \brief (LCDCA_BCFG) Blink Segment Selection 1 */ 445 #define LCDCA_BCFG_BSS1_Msk (_U_(0xF) << LCDCA_BCFG_BSS1_Pos) 446 #define LCDCA_BCFG_BSS1(value) (LCDCA_BCFG_BSS1_Msk & ((value) << LCDCA_BCFG_BSS1_Pos)) 447 #define LCDCA_BCFG_MASK _U_(0x0000FF07) /**< \brief (LCDCA_BCFG) MASK Register */ 448 449 /* -------- LCDCA_CSRCFG : (LCDCA Offset: 0x3C) (R/W 32) Circular Shift Register Configuration -------- */ 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 451 typedef union { 452 struct { 453 uint32_t DIR:1; /*!< bit: 0 Direction */ 454 uint32_t FCS:2; /*!< bit: 1.. 2 Frame Counter Selection */ 455 uint32_t SIZE:3; /*!< bit: 3.. 5 Size */ 456 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 457 uint32_t DATA:8; /*!< bit: 8..15 Circular Shift Register Value */ 458 uint32_t :16; /*!< bit: 16..31 Reserved */ 459 } bit; /*!< Structure used for bit access */ 460 uint32_t reg; /*!< Type used for register access */ 461 } LCDCA_CSRCFG_Type; 462 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 463 464 #define LCDCA_CSRCFG_OFFSET 0x3C /**< \brief (LCDCA_CSRCFG offset) Circular Shift Register Configuration */ 465 #define LCDCA_CSRCFG_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_CSRCFG reset_value) Circular Shift Register Configuration */ 466 467 #define LCDCA_CSRCFG_DIR_Pos 0 /**< \brief (LCDCA_CSRCFG) Direction */ 468 #define LCDCA_CSRCFG_DIR (_U_(0x1) << LCDCA_CSRCFG_DIR_Pos) 469 #define LCDCA_CSRCFG_FCS_Pos 1 /**< \brief (LCDCA_CSRCFG) Frame Counter Selection */ 470 #define LCDCA_CSRCFG_FCS_Msk (_U_(0x3) << LCDCA_CSRCFG_FCS_Pos) 471 #define LCDCA_CSRCFG_FCS(value) (LCDCA_CSRCFG_FCS_Msk & ((value) << LCDCA_CSRCFG_FCS_Pos)) 472 #define LCDCA_CSRCFG_SIZE_Pos 3 /**< \brief (LCDCA_CSRCFG) Size */ 473 #define LCDCA_CSRCFG_SIZE_Msk (_U_(0x7) << LCDCA_CSRCFG_SIZE_Pos) 474 #define LCDCA_CSRCFG_SIZE(value) (LCDCA_CSRCFG_SIZE_Msk & ((value) << LCDCA_CSRCFG_SIZE_Pos)) 475 #define LCDCA_CSRCFG_DATA_Pos 8 /**< \brief (LCDCA_CSRCFG) Circular Shift Register Value */ 476 #define LCDCA_CSRCFG_DATA_Msk (_U_(0xFF) << LCDCA_CSRCFG_DATA_Pos) 477 #define LCDCA_CSRCFG_DATA(value) (LCDCA_CSRCFG_DATA_Msk & ((value) << LCDCA_CSRCFG_DATA_Pos)) 478 #define LCDCA_CSRCFG_MASK _U_(0x0000FF3F) /**< \brief (LCDCA_CSRCFG) MASK Register */ 479 480 /* -------- LCDCA_CMCFG : (LCDCA Offset: 0x40) (R/W 32) Character Mapping Configuration Register -------- */ 481 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 482 typedef union { 483 struct { 484 uint32_t DREV:1; /*!< bit: 0 Digit Reverse Mode */ 485 uint32_t TDG:2; /*!< bit: 1.. 2 Type of Digit */ 486 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 487 uint32_t STSEG:6; /*!< bit: 8..13 Start Segment */ 488 uint32_t :18; /*!< bit: 14..31 Reserved */ 489 } bit; /*!< Structure used for bit access */ 490 uint32_t reg; /*!< Type used for register access */ 491 } LCDCA_CMCFG_Type; 492 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 493 494 #define LCDCA_CMCFG_OFFSET 0x40 /**< \brief (LCDCA_CMCFG offset) Character Mapping Configuration Register */ 495 #define LCDCA_CMCFG_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_CMCFG reset_value) Character Mapping Configuration Register */ 496 497 #define LCDCA_CMCFG_DREV_Pos 0 /**< \brief (LCDCA_CMCFG) Digit Reverse Mode */ 498 #define LCDCA_CMCFG_DREV (_U_(0x1) << LCDCA_CMCFG_DREV_Pos) 499 #define LCDCA_CMCFG_TDG_Pos 1 /**< \brief (LCDCA_CMCFG) Type of Digit */ 500 #define LCDCA_CMCFG_TDG_Msk (_U_(0x3) << LCDCA_CMCFG_TDG_Pos) 501 #define LCDCA_CMCFG_TDG(value) (LCDCA_CMCFG_TDG_Msk & ((value) << LCDCA_CMCFG_TDG_Pos)) 502 #define LCDCA_CMCFG_STSEG_Pos 8 /**< \brief (LCDCA_CMCFG) Start Segment */ 503 #define LCDCA_CMCFG_STSEG_Msk (_U_(0x3F) << LCDCA_CMCFG_STSEG_Pos) 504 #define LCDCA_CMCFG_STSEG(value) (LCDCA_CMCFG_STSEG_Msk & ((value) << LCDCA_CMCFG_STSEG_Pos)) 505 #define LCDCA_CMCFG_MASK _U_(0x00003F07) /**< \brief (LCDCA_CMCFG) MASK Register */ 506 507 /* -------- LCDCA_CMDR : (LCDCA Offset: 0x44) ( /W 32) Character Mapping Data Register -------- */ 508 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 509 typedef union { 510 struct { 511 uint32_t ASCII:7; /*!< bit: 0.. 6 ASCII Code */ 512 uint32_t :25; /*!< bit: 7..31 Reserved */ 513 } bit; /*!< Structure used for bit access */ 514 uint32_t reg; /*!< Type used for register access */ 515 } LCDCA_CMDR_Type; 516 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 517 518 #define LCDCA_CMDR_OFFSET 0x44 /**< \brief (LCDCA_CMDR offset) Character Mapping Data Register */ 519 #define LCDCA_CMDR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_CMDR reset_value) Character Mapping Data Register */ 520 521 #define LCDCA_CMDR_ASCII_Pos 0 /**< \brief (LCDCA_CMDR) ASCII Code */ 522 #define LCDCA_CMDR_ASCII_Msk (_U_(0x7F) << LCDCA_CMDR_ASCII_Pos) 523 #define LCDCA_CMDR_ASCII(value) (LCDCA_CMDR_ASCII_Msk & ((value) << LCDCA_CMDR_ASCII_Pos)) 524 #define LCDCA_CMDR_MASK _U_(0x0000007F) /**< \brief (LCDCA_CMDR) MASK Register */ 525 526 /* -------- LCDCA_ACMCFG : (LCDCA Offset: 0x48) (R/W 32) Automated Character Mapping Configuration Register -------- */ 527 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 528 typedef union { 529 struct { 530 uint32_t EN:1; /*!< bit: 0 Enable */ 531 uint32_t FCS:2; /*!< bit: 1.. 2 Frame Counter Selection */ 532 uint32_t MODE:1; /*!< bit: 3 Mode (sequential or scrolling) */ 533 uint32_t DREV:1; /*!< bit: 4 Digit Reverse */ 534 uint32_t TDG:2; /*!< bit: 5.. 6 Type of Digit */ 535 uint32_t :1; /*!< bit: 7 Reserved */ 536 uint32_t STSEG:6; /*!< bit: 8..13 Start Segment */ 537 uint32_t :2; /*!< bit: 14..15 Reserved */ 538 uint32_t STEPS:8; /*!< bit: 16..23 Scrolling Steps */ 539 uint32_t DIGN:4; /*!< bit: 24..27 Digit Number */ 540 uint32_t :4; /*!< bit: 28..31 Reserved */ 541 } bit; /*!< Structure used for bit access */ 542 uint32_t reg; /*!< Type used for register access */ 543 } LCDCA_ACMCFG_Type; 544 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 545 546 #define LCDCA_ACMCFG_OFFSET 0x48 /**< \brief (LCDCA_ACMCFG offset) Automated Character Mapping Configuration Register */ 547 #define LCDCA_ACMCFG_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_ACMCFG reset_value) Automated Character Mapping Configuration Register */ 548 549 #define LCDCA_ACMCFG_EN_Pos 0 /**< \brief (LCDCA_ACMCFG) Enable */ 550 #define LCDCA_ACMCFG_EN (_U_(0x1) << LCDCA_ACMCFG_EN_Pos) 551 #define LCDCA_ACMCFG_FCS_Pos 1 /**< \brief (LCDCA_ACMCFG) Frame Counter Selection */ 552 #define LCDCA_ACMCFG_FCS_Msk (_U_(0x3) << LCDCA_ACMCFG_FCS_Pos) 553 #define LCDCA_ACMCFG_FCS(value) (LCDCA_ACMCFG_FCS_Msk & ((value) << LCDCA_ACMCFG_FCS_Pos)) 554 #define LCDCA_ACMCFG_MODE_Pos 3 /**< \brief (LCDCA_ACMCFG) Mode (sequential or scrolling) */ 555 #define LCDCA_ACMCFG_MODE (_U_(0x1) << LCDCA_ACMCFG_MODE_Pos) 556 #define LCDCA_ACMCFG_DREV_Pos 4 /**< \brief (LCDCA_ACMCFG) Digit Reverse */ 557 #define LCDCA_ACMCFG_DREV (_U_(0x1) << LCDCA_ACMCFG_DREV_Pos) 558 #define LCDCA_ACMCFG_TDG_Pos 5 /**< \brief (LCDCA_ACMCFG) Type of Digit */ 559 #define LCDCA_ACMCFG_TDG_Msk (_U_(0x3) << LCDCA_ACMCFG_TDG_Pos) 560 #define LCDCA_ACMCFG_TDG(value) (LCDCA_ACMCFG_TDG_Msk & ((value) << LCDCA_ACMCFG_TDG_Pos)) 561 #define LCDCA_ACMCFG_STSEG_Pos 8 /**< \brief (LCDCA_ACMCFG) Start Segment */ 562 #define LCDCA_ACMCFG_STSEG_Msk (_U_(0x3F) << LCDCA_ACMCFG_STSEG_Pos) 563 #define LCDCA_ACMCFG_STSEG(value) (LCDCA_ACMCFG_STSEG_Msk & ((value) << LCDCA_ACMCFG_STSEG_Pos)) 564 #define LCDCA_ACMCFG_STEPS_Pos 16 /**< \brief (LCDCA_ACMCFG) Scrolling Steps */ 565 #define LCDCA_ACMCFG_STEPS_Msk (_U_(0xFF) << LCDCA_ACMCFG_STEPS_Pos) 566 #define LCDCA_ACMCFG_STEPS(value) (LCDCA_ACMCFG_STEPS_Msk & ((value) << LCDCA_ACMCFG_STEPS_Pos)) 567 #define LCDCA_ACMCFG_DIGN_Pos 24 /**< \brief (LCDCA_ACMCFG) Digit Number */ 568 #define LCDCA_ACMCFG_DIGN_Msk (_U_(0xF) << LCDCA_ACMCFG_DIGN_Pos) 569 #define LCDCA_ACMCFG_DIGN(value) (LCDCA_ACMCFG_DIGN_Msk & ((value) << LCDCA_ACMCFG_DIGN_Pos)) 570 #define LCDCA_ACMCFG_MASK _U_(0x0FFF3F7F) /**< \brief (LCDCA_ACMCFG) MASK Register */ 571 572 /* -------- LCDCA_ACMDR : (LCDCA Offset: 0x4C) ( /W 32) Automated Character Mapping Data Register -------- */ 573 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 574 typedef union { 575 struct { 576 uint32_t ASCII:7; /*!< bit: 0.. 6 ASCII Code */ 577 uint32_t :25; /*!< bit: 7..31 Reserved */ 578 } bit; /*!< Structure used for bit access */ 579 uint32_t reg; /*!< Type used for register access */ 580 } LCDCA_ACMDR_Type; 581 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 582 583 #define LCDCA_ACMDR_OFFSET 0x4C /**< \brief (LCDCA_ACMDR offset) Automated Character Mapping Data Register */ 584 #define LCDCA_ACMDR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_ACMDR reset_value) Automated Character Mapping Data Register */ 585 586 #define LCDCA_ACMDR_ASCII_Pos 0 /**< \brief (LCDCA_ACMDR) ASCII Code */ 587 #define LCDCA_ACMDR_ASCII_Msk (_U_(0x7F) << LCDCA_ACMDR_ASCII_Pos) 588 #define LCDCA_ACMDR_ASCII(value) (LCDCA_ACMDR_ASCII_Msk & ((value) << LCDCA_ACMDR_ASCII_Pos)) 589 #define LCDCA_ACMDR_MASK _U_(0x0000007F) /**< \brief (LCDCA_ACMDR) MASK Register */ 590 591 /* -------- LCDCA_ABMCFG : (LCDCA Offset: 0x50) (R/W 32) Automated Bit Mapping Configuration Register -------- */ 592 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 593 typedef union { 594 struct { 595 uint32_t EN:1; /*!< bit: 0 Enable */ 596 uint32_t FCS:2; /*!< bit: 1.. 2 Frame Counter Selection */ 597 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 598 uint32_t SIZE:5; /*!< bit: 8..12 Size */ 599 uint32_t :19; /*!< bit: 13..31 Reserved */ 600 } bit; /*!< Structure used for bit access */ 601 uint32_t reg; /*!< Type used for register access */ 602 } LCDCA_ABMCFG_Type; 603 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 604 605 #define LCDCA_ABMCFG_OFFSET 0x50 /**< \brief (LCDCA_ABMCFG offset) Automated Bit Mapping Configuration Register */ 606 #define LCDCA_ABMCFG_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_ABMCFG reset_value) Automated Bit Mapping Configuration Register */ 607 608 #define LCDCA_ABMCFG_EN_Pos 0 /**< \brief (LCDCA_ABMCFG) Enable */ 609 #define LCDCA_ABMCFG_EN (_U_(0x1) << LCDCA_ABMCFG_EN_Pos) 610 #define LCDCA_ABMCFG_FCS_Pos 1 /**< \brief (LCDCA_ABMCFG) Frame Counter Selection */ 611 #define LCDCA_ABMCFG_FCS_Msk (_U_(0x3) << LCDCA_ABMCFG_FCS_Pos) 612 #define LCDCA_ABMCFG_FCS(value) (LCDCA_ABMCFG_FCS_Msk & ((value) << LCDCA_ABMCFG_FCS_Pos)) 613 #define LCDCA_ABMCFG_SIZE_Pos 8 /**< \brief (LCDCA_ABMCFG) Size */ 614 #define LCDCA_ABMCFG_SIZE_Msk (_U_(0x1F) << LCDCA_ABMCFG_SIZE_Pos) 615 #define LCDCA_ABMCFG_SIZE(value) (LCDCA_ABMCFG_SIZE_Msk & ((value) << LCDCA_ABMCFG_SIZE_Pos)) 616 #define LCDCA_ABMCFG_MASK _U_(0x00001F07) /**< \brief (LCDCA_ABMCFG) MASK Register */ 617 618 /* -------- LCDCA_ABMDR : (LCDCA Offset: 0x54) ( /W 32) Automated Bit Mapping Data Register -------- */ 619 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 620 typedef union { 621 struct { 622 uint32_t DATA:8; /*!< bit: 0.. 7 Segments Value */ 623 uint32_t DMASK:8; /*!< bit: 8..15 Data Mask */ 624 uint32_t OFF:5; /*!< bit: 16..20 Byte Offset */ 625 uint32_t :11; /*!< bit: 21..31 Reserved */ 626 } bit; /*!< Structure used for bit access */ 627 uint32_t reg; /*!< Type used for register access */ 628 } LCDCA_ABMDR_Type; 629 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 630 631 #define LCDCA_ABMDR_OFFSET 0x54 /**< \brief (LCDCA_ABMDR offset) Automated Bit Mapping Data Register */ 632 #define LCDCA_ABMDR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_ABMDR reset_value) Automated Bit Mapping Data Register */ 633 634 #define LCDCA_ABMDR_DATA_Pos 0 /**< \brief (LCDCA_ABMDR) Segments Value */ 635 #define LCDCA_ABMDR_DATA_Msk (_U_(0xFF) << LCDCA_ABMDR_DATA_Pos) 636 #define LCDCA_ABMDR_DATA(value) (LCDCA_ABMDR_DATA_Msk & ((value) << LCDCA_ABMDR_DATA_Pos)) 637 #define LCDCA_ABMDR_DMASK_Pos 8 /**< \brief (LCDCA_ABMDR) Data Mask */ 638 #define LCDCA_ABMDR_DMASK_Msk (_U_(0xFF) << LCDCA_ABMDR_DMASK_Pos) 639 #define LCDCA_ABMDR_DMASK(value) (LCDCA_ABMDR_DMASK_Msk & ((value) << LCDCA_ABMDR_DMASK_Pos)) 640 #define LCDCA_ABMDR_OFF_Pos 16 /**< \brief (LCDCA_ABMDR) Byte Offset */ 641 #define LCDCA_ABMDR_OFF_Msk (_U_(0x1F) << LCDCA_ABMDR_OFF_Pos) 642 #define LCDCA_ABMDR_OFF(value) (LCDCA_ABMDR_OFF_Msk & ((value) << LCDCA_ABMDR_OFF_Pos)) 643 #define LCDCA_ABMDR_MASK _U_(0x001FFFFF) /**< \brief (LCDCA_ABMDR) MASK Register */ 644 645 /* -------- LCDCA_IER : (LCDCA Offset: 0x58) ( /W 32) Interrupt Enable Register -------- */ 646 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 647 typedef union { 648 struct { 649 uint32_t FC0R:1; /*!< bit: 0 Frame Counter 0 Rollover */ 650 uint32_t :31; /*!< bit: 1..31 Reserved */ 651 } bit; /*!< Structure used for bit access */ 652 uint32_t reg; /*!< Type used for register access */ 653 } LCDCA_IER_Type; 654 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 655 656 #define LCDCA_IER_OFFSET 0x58 /**< \brief (LCDCA_IER offset) Interrupt Enable Register */ 657 #define LCDCA_IER_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_IER reset_value) Interrupt Enable Register */ 658 659 #define LCDCA_IER_FC0R_Pos 0 /**< \brief (LCDCA_IER) Frame Counter 0 Rollover */ 660 #define LCDCA_IER_FC0R (_U_(0x1) << LCDCA_IER_FC0R_Pos) 661 #define LCDCA_IER_MASK _U_(0x00000001) /**< \brief (LCDCA_IER) MASK Register */ 662 663 /* -------- LCDCA_IDR : (LCDCA Offset: 0x5C) ( /W 32) Interrupt Disable Register -------- */ 664 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 665 typedef union { 666 struct { 667 uint32_t FC0R:1; /*!< bit: 0 Frame Counter 0 Rollover */ 668 uint32_t :31; /*!< bit: 1..31 Reserved */ 669 } bit; /*!< Structure used for bit access */ 670 uint32_t reg; /*!< Type used for register access */ 671 } LCDCA_IDR_Type; 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 673 674 #define LCDCA_IDR_OFFSET 0x5C /**< \brief (LCDCA_IDR offset) Interrupt Disable Register */ 675 #define LCDCA_IDR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_IDR reset_value) Interrupt Disable Register */ 676 677 #define LCDCA_IDR_FC0R_Pos 0 /**< \brief (LCDCA_IDR) Frame Counter 0 Rollover */ 678 #define LCDCA_IDR_FC0R (_U_(0x1) << LCDCA_IDR_FC0R_Pos) 679 #define LCDCA_IDR_MASK _U_(0x00000001) /**< \brief (LCDCA_IDR) MASK Register */ 680 681 /* -------- LCDCA_IMR : (LCDCA Offset: 0x60) (R/ 32) Interrupt Mask Register -------- */ 682 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 683 typedef union { 684 struct { 685 uint32_t FC0R:1; /*!< bit: 0 Frame Counter 0 Rollover */ 686 uint32_t :31; /*!< bit: 1..31 Reserved */ 687 } bit; /*!< Structure used for bit access */ 688 uint32_t reg; /*!< Type used for register access */ 689 } LCDCA_IMR_Type; 690 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 691 692 #define LCDCA_IMR_OFFSET 0x60 /**< \brief (LCDCA_IMR offset) Interrupt Mask Register */ 693 #define LCDCA_IMR_RESETVALUE _U_(0x00000000); /**< \brief (LCDCA_IMR reset_value) Interrupt Mask Register */ 694 695 #define LCDCA_IMR_FC0R_Pos 0 /**< \brief (LCDCA_IMR) Frame Counter 0 Rollover */ 696 #define LCDCA_IMR_FC0R (_U_(0x1) << LCDCA_IMR_FC0R_Pos) 697 #define LCDCA_IMR_MASK _U_(0x00000001) /**< \brief (LCDCA_IMR) MASK Register */ 698 699 /* -------- LCDCA_VERSION : (LCDCA Offset: 0x64) (R/ 32) Version Register -------- */ 700 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 701 typedef union { 702 struct { 703 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 704 uint32_t :4; /*!< bit: 12..15 Reserved */ 705 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 706 uint32_t :12; /*!< bit: 20..31 Reserved */ 707 } bit; /*!< Structure used for bit access */ 708 uint32_t reg; /*!< Type used for register access */ 709 } LCDCA_VERSION_Type; 710 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 711 712 #define LCDCA_VERSION_OFFSET 0x64 /**< \brief (LCDCA_VERSION offset) Version Register */ 713 #define LCDCA_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (LCDCA_VERSION reset_value) Version Register */ 714 715 #define LCDCA_VERSION_VERSION_Pos 0 /**< \brief (LCDCA_VERSION) Version Number */ 716 #define LCDCA_VERSION_VERSION_Msk (_U_(0xFFF) << LCDCA_VERSION_VERSION_Pos) 717 #define LCDCA_VERSION_VERSION(value) (LCDCA_VERSION_VERSION_Msk & ((value) << LCDCA_VERSION_VERSION_Pos)) 718 #define LCDCA_VERSION_VARIANT_Pos 16 /**< \brief (LCDCA_VERSION) Variant Number */ 719 #define LCDCA_VERSION_VARIANT_Msk (_U_(0xF) << LCDCA_VERSION_VARIANT_Pos) 720 #define LCDCA_VERSION_VARIANT(value) (LCDCA_VERSION_VARIANT_Msk & ((value) << LCDCA_VERSION_VARIANT_Pos)) 721 #define LCDCA_VERSION_MASK _U_(0x000F0FFF) /**< \brief (LCDCA_VERSION) MASK Register */ 722 723 /** \brief LCDCA hardware registers */ 724 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 725 typedef struct { 726 __O uint32_t CR; /**< \brief Offset: 0x00 ( /W 32) Control Register */ 727 __IO uint32_t CFG; /**< \brief Offset: 0x04 (R/W 32) Configuration Register */ 728 __IO uint32_t TIM; /**< \brief Offset: 0x08 (R/W 32) Timing Register */ 729 __I uint32_t SR; /**< \brief Offset: 0x0C (R/ 32) Status Register */ 730 __O uint32_t SCR; /**< \brief Offset: 0x10 ( /W 32) Status Clear Register */ 731 __IO uint32_t DRL0; /**< \brief Offset: 0x14 (R/W 32) Data Register Low 0 */ 732 __IO uint32_t DRH0; /**< \brief Offset: 0x18 (R/W 32) Data Register High 0 */ 733 __IO uint32_t DRL1; /**< \brief Offset: 0x1C (R/W 32) Data Register Low 1 */ 734 __IO uint32_t DRH1; /**< \brief Offset: 0x20 (R/W 32) Data Register High 1 */ 735 __IO uint32_t DRL2; /**< \brief Offset: 0x24 (R/W 32) Data Register Low 2 */ 736 __IO uint32_t DRH2; /**< \brief Offset: 0x28 (R/W 32) Data Register High 2 */ 737 __IO uint32_t DRL3; /**< \brief Offset: 0x2C (R/W 32) Data Register Low 3 */ 738 __IO uint32_t DRH3; /**< \brief Offset: 0x30 (R/W 32) Data Register High 3 */ 739 __O uint32_t IADR; /**< \brief Offset: 0x34 ( /W 32) Indirect Access Data Register */ 740 __IO uint32_t BCFG; /**< \brief Offset: 0x38 (R/W 32) Blink Configuration Register */ 741 __IO uint32_t CSRCFG; /**< \brief Offset: 0x3C (R/W 32) Circular Shift Register Configuration */ 742 __IO uint32_t CMCFG; /**< \brief Offset: 0x40 (R/W 32) Character Mapping Configuration Register */ 743 __O uint32_t CMDR; /**< \brief Offset: 0x44 ( /W 32) Character Mapping Data Register */ 744 __IO uint32_t ACMCFG; /**< \brief Offset: 0x48 (R/W 32) Automated Character Mapping Configuration Register */ 745 __O uint32_t ACMDR; /**< \brief Offset: 0x4C ( /W 32) Automated Character Mapping Data Register */ 746 __IO uint32_t ABMCFG; /**< \brief Offset: 0x50 (R/W 32) Automated Bit Mapping Configuration Register */ 747 __O uint32_t ABMDR; /**< \brief Offset: 0x54 ( /W 32) Automated Bit Mapping Data Register */ 748 __O uint32_t IER; /**< \brief Offset: 0x58 ( /W 32) Interrupt Enable Register */ 749 __O uint32_t IDR; /**< \brief Offset: 0x5C ( /W 32) Interrupt Disable Register */ 750 __I uint32_t IMR; /**< \brief Offset: 0x60 (R/ 32) Interrupt Mask Register */ 751 __I uint32_t VERSION; /**< \brief Offset: 0x64 (R/ 32) Version Register */ 752 } Lcdca; 753 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 754 755 /*@}*/ 756 757 #endif /* _SAM4L_LCDCA_COMPONENT_ */ 758
