1 /** 2 * \file 3 * 4 * \brief Component description for CATB 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_CATB_COMPONENT_ 30 #define _SAM4L_CATB_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR CATB */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_CATB Capacitive Touch Module B */ 36 /*@{*/ 37 38 #define CATB_I7567 39 #define REV_CATB 0x100 40 41 /* -------- CATB_CR : (CATB Offset: 0x00) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 Module Enable */ 46 uint32_t RUN:1; /*!< bit: 1 Start Operation */ 47 uint32_t IIDLE:1; /*!< bit: 2 Initialize Idle Value */ 48 uint32_t ETRIG:1; /*!< bit: 3 Event Triggered Operation */ 49 uint32_t INTRES:1; /*!< bit: 4 Internal Resistors */ 50 uint32_t CKSEL:1; /*!< bit: 5 Clock Select */ 51 uint32_t DIFF:1; /*!< bit: 6 Differential Mode */ 52 uint32_t DMAEN:1; /*!< bit: 7 DMA Enable */ 53 uint32_t ESAMPLES:7; /*!< bit: 8..14 Number of Event Samples */ 54 uint32_t :1; /*!< bit: 15 Reserved */ 55 uint32_t CHARGET:4; /*!< bit: 16..19 Charge Time */ 56 uint32_t :11; /*!< bit: 20..30 Reserved */ 57 uint32_t SWRST:1; /*!< bit: 31 Software Reset */ 58 } bit; /*!< Structure used for bit access */ 59 uint32_t reg; /*!< Type used for register access */ 60 } CATB_CR_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define CATB_CR_OFFSET 0x00 /**< \brief (CATB_CR offset) Control Register */ 64 #define CATB_CR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_CR reset_value) Control Register */ 65 66 #define CATB_CR_EN_Pos 0 /**< \brief (CATB_CR) Module Enable */ 67 #define CATB_CR_EN (_U_(0x1) << CATB_CR_EN_Pos) 68 #define CATB_CR_RUN_Pos 1 /**< \brief (CATB_CR) Start Operation */ 69 #define CATB_CR_RUN (_U_(0x1) << CATB_CR_RUN_Pos) 70 #define CATB_CR_IIDLE_Pos 2 /**< \brief (CATB_CR) Initialize Idle Value */ 71 #define CATB_CR_IIDLE (_U_(0x1) << CATB_CR_IIDLE_Pos) 72 #define CATB_CR_ETRIG_Pos 3 /**< \brief (CATB_CR) Event Triggered Operation */ 73 #define CATB_CR_ETRIG (_U_(0x1) << CATB_CR_ETRIG_Pos) 74 #define CATB_CR_INTRES_Pos 4 /**< \brief (CATB_CR) Internal Resistors */ 75 #define CATB_CR_INTRES (_U_(0x1) << CATB_CR_INTRES_Pos) 76 #define CATB_CR_CKSEL_Pos 5 /**< \brief (CATB_CR) Clock Select */ 77 #define CATB_CR_CKSEL (_U_(0x1) << CATB_CR_CKSEL_Pos) 78 #define CATB_CR_DIFF_Pos 6 /**< \brief (CATB_CR) Differential Mode */ 79 #define CATB_CR_DIFF (_U_(0x1) << CATB_CR_DIFF_Pos) 80 #define CATB_CR_DMAEN_Pos 7 /**< \brief (CATB_CR) DMA Enable */ 81 #define CATB_CR_DMAEN (_U_(0x1) << CATB_CR_DMAEN_Pos) 82 #define CATB_CR_ESAMPLES_Pos 8 /**< \brief (CATB_CR) Number of Event Samples */ 83 #define CATB_CR_ESAMPLES_Msk (_U_(0x7F) << CATB_CR_ESAMPLES_Pos) 84 #define CATB_CR_ESAMPLES(value) (CATB_CR_ESAMPLES_Msk & ((value) << CATB_CR_ESAMPLES_Pos)) 85 #define CATB_CR_CHARGET_Pos 16 /**< \brief (CATB_CR) Charge Time */ 86 #define CATB_CR_CHARGET_Msk (_U_(0xF) << CATB_CR_CHARGET_Pos) 87 #define CATB_CR_CHARGET(value) (CATB_CR_CHARGET_Msk & ((value) << CATB_CR_CHARGET_Pos)) 88 #define CATB_CR_SWRST_Pos 31 /**< \brief (CATB_CR) Software Reset */ 89 #define CATB_CR_SWRST (_U_(0x1) << CATB_CR_SWRST_Pos) 90 #define CATB_CR_MASK _U_(0x800F7FFF) /**< \brief (CATB_CR) MASK Register */ 91 92 /* -------- CATB_CNTCR : (CATB Offset: 0x04) (R/W 32) Counter Control Register -------- */ 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 94 typedef union { 95 struct { 96 uint32_t TOP:24; /*!< bit: 0..23 Counter Top Value */ 97 uint32_t SPREAD:4; /*!< bit: 24..27 Spread Spectrum */ 98 uint32_t REPEAT:3; /*!< bit: 28..30 Repeat Measurements */ 99 uint32_t :1; /*!< bit: 31 Reserved */ 100 } bit; /*!< Structure used for bit access */ 101 uint32_t reg; /*!< Type used for register access */ 102 } CATB_CNTCR_Type; 103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define CATB_CNTCR_OFFSET 0x04 /**< \brief (CATB_CNTCR offset) Counter Control Register */ 106 #define CATB_CNTCR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_CNTCR reset_value) Counter Control Register */ 107 108 #define CATB_CNTCR_TOP_Pos 0 /**< \brief (CATB_CNTCR) Counter Top Value */ 109 #define CATB_CNTCR_TOP_Msk (_U_(0xFFFFFF) << CATB_CNTCR_TOP_Pos) 110 #define CATB_CNTCR_TOP(value) (CATB_CNTCR_TOP_Msk & ((value) << CATB_CNTCR_TOP_Pos)) 111 #define CATB_CNTCR_SPREAD_Pos 24 /**< \brief (CATB_CNTCR) Spread Spectrum */ 112 #define CATB_CNTCR_SPREAD_Msk (_U_(0xF) << CATB_CNTCR_SPREAD_Pos) 113 #define CATB_CNTCR_SPREAD(value) (CATB_CNTCR_SPREAD_Msk & ((value) << CATB_CNTCR_SPREAD_Pos)) 114 #define CATB_CNTCR_REPEAT_Pos 28 /**< \brief (CATB_CNTCR) Repeat Measurements */ 115 #define CATB_CNTCR_REPEAT_Msk (_U_(0x7) << CATB_CNTCR_REPEAT_Pos) 116 #define CATB_CNTCR_REPEAT(value) (CATB_CNTCR_REPEAT_Msk & ((value) << CATB_CNTCR_REPEAT_Pos)) 117 #define CATB_CNTCR_MASK _U_(0x7FFFFFFF) /**< \brief (CATB_CNTCR) MASK Register */ 118 119 /* -------- CATB_IDLE : (CATB Offset: 0x08) (R/W 32) Sensor Idle Level -------- */ 120 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 121 typedef union { 122 struct { 123 uint32_t FIDLE:12; /*!< bit: 0..11 Fractional Sensor Idle */ 124 uint32_t RIDLE:16; /*!< bit: 12..27 Integer Sensor Idle */ 125 uint32_t :4; /*!< bit: 28..31 Reserved */ 126 } bit; /*!< Structure used for bit access */ 127 uint32_t reg; /*!< Type used for register access */ 128 } CATB_IDLE_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 #define CATB_IDLE_OFFSET 0x08 /**< \brief (CATB_IDLE offset) Sensor Idle Level */ 132 #define CATB_IDLE_RESETVALUE _U_(0x00000000); /**< \brief (CATB_IDLE reset_value) Sensor Idle Level */ 133 134 #define CATB_IDLE_FIDLE_Pos 0 /**< \brief (CATB_IDLE) Fractional Sensor Idle */ 135 #define CATB_IDLE_FIDLE_Msk (_U_(0xFFF) << CATB_IDLE_FIDLE_Pos) 136 #define CATB_IDLE_FIDLE(value) (CATB_IDLE_FIDLE_Msk & ((value) << CATB_IDLE_FIDLE_Pos)) 137 #define CATB_IDLE_RIDLE_Pos 12 /**< \brief (CATB_IDLE) Integer Sensor Idle */ 138 #define CATB_IDLE_RIDLE_Msk (_U_(0xFFFF) << CATB_IDLE_RIDLE_Pos) 139 #define CATB_IDLE_RIDLE(value) (CATB_IDLE_RIDLE_Msk & ((value) << CATB_IDLE_RIDLE_Pos)) 140 #define CATB_IDLE_MASK _U_(0x0FFFFFFF) /**< \brief (CATB_IDLE) MASK Register */ 141 142 /* -------- CATB_LEVEL : (CATB Offset: 0x0C) (R/ 32) Sensor Relative Level -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint32_t FLEVEL:12; /*!< bit: 0..11 Fractional Sensor Level */ 147 uint32_t RLEVEL:8; /*!< bit: 12..19 Integer Sensor Level */ 148 uint32_t :12; /*!< bit: 20..31 Reserved */ 149 } bit; /*!< Structure used for bit access */ 150 uint32_t reg; /*!< Type used for register access */ 151 } CATB_LEVEL_Type; 152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 153 154 #define CATB_LEVEL_OFFSET 0x0C /**< \brief (CATB_LEVEL offset) Sensor Relative Level */ 155 #define CATB_LEVEL_RESETVALUE _U_(0x00000000); /**< \brief (CATB_LEVEL reset_value) Sensor Relative Level */ 156 157 #define CATB_LEVEL_FLEVEL_Pos 0 /**< \brief (CATB_LEVEL) Fractional Sensor Level */ 158 #define CATB_LEVEL_FLEVEL_Msk (_U_(0xFFF) << CATB_LEVEL_FLEVEL_Pos) 159 #define CATB_LEVEL_FLEVEL(value) (CATB_LEVEL_FLEVEL_Msk & ((value) << CATB_LEVEL_FLEVEL_Pos)) 160 #define CATB_LEVEL_RLEVEL_Pos 12 /**< \brief (CATB_LEVEL) Integer Sensor Level */ 161 #define CATB_LEVEL_RLEVEL_Msk (_U_(0xFF) << CATB_LEVEL_RLEVEL_Pos) 162 #define CATB_LEVEL_RLEVEL(value) (CATB_LEVEL_RLEVEL_Msk & ((value) << CATB_LEVEL_RLEVEL_Pos)) 163 #define CATB_LEVEL_MASK _U_(0x000FFFFF) /**< \brief (CATB_LEVEL) MASK Register */ 164 165 /* -------- CATB_RAW : (CATB Offset: 0x10) (R/ 32) Sensor Raw Value -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { 168 struct { 169 uint32_t :16; /*!< bit: 0..15 Reserved */ 170 uint32_t RAWA:8; /*!< bit: 16..23 Current Sensor Raw Value */ 171 uint32_t RAWB:8; /*!< bit: 24..31 Last Sensor Raw Value */ 172 } bit; /*!< Structure used for bit access */ 173 uint32_t reg; /*!< Type used for register access */ 174 } CATB_RAW_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define CATB_RAW_OFFSET 0x10 /**< \brief (CATB_RAW offset) Sensor Raw Value */ 178 #define CATB_RAW_RESETVALUE _U_(0x00000000); /**< \brief (CATB_RAW reset_value) Sensor Raw Value */ 179 180 #define CATB_RAW_RAWA_Pos 16 /**< \brief (CATB_RAW) Current Sensor Raw Value */ 181 #define CATB_RAW_RAWA_Msk (_U_(0xFF) << CATB_RAW_RAWA_Pos) 182 #define CATB_RAW_RAWA(value) (CATB_RAW_RAWA_Msk & ((value) << CATB_RAW_RAWA_Pos)) 183 #define CATB_RAW_RAWB_Pos 24 /**< \brief (CATB_RAW) Last Sensor Raw Value */ 184 #define CATB_RAW_RAWB_Msk (_U_(0xFF) << CATB_RAW_RAWB_Pos) 185 #define CATB_RAW_RAWB(value) (CATB_RAW_RAWB_Msk & ((value) << CATB_RAW_RAWB_Pos)) 186 #define CATB_RAW_MASK _U_(0xFFFF0000) /**< \brief (CATB_RAW) MASK Register */ 187 188 /* -------- CATB_TIMING : (CATB Offset: 0x14) (R/W 32) Filter Timing Register -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint32_t TLEVEL:12; /*!< bit: 0..11 Relative Level Smoothing */ 193 uint32_t :4; /*!< bit: 12..15 Reserved */ 194 uint32_t TIDLE:12; /*!< bit: 16..27 Idle Smoothening */ 195 uint32_t :4; /*!< bit: 28..31 Reserved */ 196 } bit; /*!< Structure used for bit access */ 197 uint32_t reg; /*!< Type used for register access */ 198 } CATB_TIMING_Type; 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 #define CATB_TIMING_OFFSET 0x14 /**< \brief (CATB_TIMING offset) Filter Timing Register */ 202 #define CATB_TIMING_RESETVALUE _U_(0x00000000); /**< \brief (CATB_TIMING reset_value) Filter Timing Register */ 203 204 #define CATB_TIMING_TLEVEL_Pos 0 /**< \brief (CATB_TIMING) Relative Level Smoothing */ 205 #define CATB_TIMING_TLEVEL_Msk (_U_(0xFFF) << CATB_TIMING_TLEVEL_Pos) 206 #define CATB_TIMING_TLEVEL(value) (CATB_TIMING_TLEVEL_Msk & ((value) << CATB_TIMING_TLEVEL_Pos)) 207 #define CATB_TIMING_TIDLE_Pos 16 /**< \brief (CATB_TIMING) Idle Smoothening */ 208 #define CATB_TIMING_TIDLE_Msk (_U_(0xFFF) << CATB_TIMING_TIDLE_Pos) 209 #define CATB_TIMING_TIDLE(value) (CATB_TIMING_TIDLE_Msk & ((value) << CATB_TIMING_TIDLE_Pos)) 210 #define CATB_TIMING_MASK _U_(0x0FFF0FFF) /**< \brief (CATB_TIMING) MASK Register */ 211 212 /* -------- CATB_THRESH : (CATB Offset: 0x18) (R/W 32) Threshold Register -------- */ 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 214 typedef union { 215 struct { 216 uint32_t FTHRESH:12; /*!< bit: 0..11 Fractional part of Threshold Value */ 217 uint32_t RTHRESH:8; /*!< bit: 12..19 Rational part of Threshold Value */ 218 uint32_t :3; /*!< bit: 20..22 Reserved */ 219 uint32_t DIR:1; /*!< bit: 23 Threshold Direction */ 220 uint32_t LENGTH:5; /*!< bit: 24..28 Threshold Length */ 221 uint32_t :3; /*!< bit: 29..31 Reserved */ 222 } bit; /*!< Structure used for bit access */ 223 uint32_t reg; /*!< Type used for register access */ 224 } CATB_THRESH_Type; 225 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 226 227 #define CATB_THRESH_OFFSET 0x18 /**< \brief (CATB_THRESH offset) Threshold Register */ 228 #define CATB_THRESH_RESETVALUE _U_(0x00000000); /**< \brief (CATB_THRESH reset_value) Threshold Register */ 229 230 #define CATB_THRESH_FTHRESH_Pos 0 /**< \brief (CATB_THRESH) Fractional part of Threshold Value */ 231 #define CATB_THRESH_FTHRESH_Msk (_U_(0xFFF) << CATB_THRESH_FTHRESH_Pos) 232 #define CATB_THRESH_FTHRESH(value) (CATB_THRESH_FTHRESH_Msk & ((value) << CATB_THRESH_FTHRESH_Pos)) 233 #define CATB_THRESH_RTHRESH_Pos 12 /**< \brief (CATB_THRESH) Rational part of Threshold Value */ 234 #define CATB_THRESH_RTHRESH_Msk (_U_(0xFF) << CATB_THRESH_RTHRESH_Pos) 235 #define CATB_THRESH_RTHRESH(value) (CATB_THRESH_RTHRESH_Msk & ((value) << CATB_THRESH_RTHRESH_Pos)) 236 #define CATB_THRESH_DIR_Pos 23 /**< \brief (CATB_THRESH) Threshold Direction */ 237 #define CATB_THRESH_DIR (_U_(0x1) << CATB_THRESH_DIR_Pos) 238 #define CATB_THRESH_LENGTH_Pos 24 /**< \brief (CATB_THRESH) Threshold Length */ 239 #define CATB_THRESH_LENGTH_Msk (_U_(0x1F) << CATB_THRESH_LENGTH_Pos) 240 #define CATB_THRESH_LENGTH(value) (CATB_THRESH_LENGTH_Msk & ((value) << CATB_THRESH_LENGTH_Pos)) 241 #define CATB_THRESH_MASK _U_(0x1F8FFFFF) /**< \brief (CATB_THRESH) MASK Register */ 242 243 /* -------- CATB_PINSEL : (CATB Offset: 0x1C) (R/W 32) Pin Selection Register -------- */ 244 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 245 typedef union { 246 struct { 247 uint32_t PINSEL:8; /*!< bit: 0.. 7 Pin Select */ 248 uint32_t :24; /*!< bit: 8..31 Reserved */ 249 } bit; /*!< Structure used for bit access */ 250 uint32_t reg; /*!< Type used for register access */ 251 } CATB_PINSEL_Type; 252 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 253 254 #define CATB_PINSEL_OFFSET 0x1C /**< \brief (CATB_PINSEL offset) Pin Selection Register */ 255 #define CATB_PINSEL_RESETVALUE _U_(0x00000000); /**< \brief (CATB_PINSEL reset_value) Pin Selection Register */ 256 257 #define CATB_PINSEL_PINSEL_Pos 0 /**< \brief (CATB_PINSEL) Pin Select */ 258 #define CATB_PINSEL_PINSEL_Msk (_U_(0xFF) << CATB_PINSEL_PINSEL_Pos) 259 #define CATB_PINSEL_PINSEL(value) (CATB_PINSEL_PINSEL_Msk & ((value) << CATB_PINSEL_PINSEL_Pos)) 260 #define CATB_PINSEL_MASK _U_(0x000000FF) /**< \brief (CATB_PINSEL) MASK Register */ 261 262 /* -------- CATB_DMA : (CATB Offset: 0x20) (R/W 32) Direct Memory Access Register -------- */ 263 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 264 typedef union { 265 struct { 266 uint32_t DMA:32; /*!< bit: 0..31 Direct Memory Access */ 267 } bit; /*!< Structure used for bit access */ 268 uint32_t reg; /*!< Type used for register access */ 269 } CATB_DMA_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define CATB_DMA_OFFSET 0x20 /**< \brief (CATB_DMA offset) Direct Memory Access Register */ 273 #define CATB_DMA_RESETVALUE _U_(0x00000000); /**< \brief (CATB_DMA reset_value) Direct Memory Access Register */ 274 275 #define CATB_DMA_DMA_Pos 0 /**< \brief (CATB_DMA) Direct Memory Access */ 276 #define CATB_DMA_DMA_Msk (_U_(0xFFFFFFFF) << CATB_DMA_DMA_Pos) 277 #define CATB_DMA_DMA(value) (CATB_DMA_DMA_Msk & ((value) << CATB_DMA_DMA_Pos)) 278 #define CATB_DMA_MASK _U_(0xFFFFFFFF) /**< \brief (CATB_DMA) MASK Register */ 279 280 /* -------- CATB_ISR : (CATB Offset: 0x24) (R/ 32) Interrupt Status Register -------- */ 281 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 282 typedef union { 283 struct { 284 uint32_t SAMPLE:1; /*!< bit: 0 Sample Ready Interrupt Status */ 285 uint32_t INTCH:1; /*!< bit: 1 In-touch Interrupt Status */ 286 uint32_t OUTTCH:1; /*!< bit: 2 Out-of-Touch Interrupt Status */ 287 uint32_t :29; /*!< bit: 3..31 Reserved */ 288 } bit; /*!< Structure used for bit access */ 289 uint32_t reg; /*!< Type used for register access */ 290 } CATB_ISR_Type; 291 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 292 293 #define CATB_ISR_OFFSET 0x24 /**< \brief (CATB_ISR offset) Interrupt Status Register */ 294 #define CATB_ISR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_ISR reset_value) Interrupt Status Register */ 295 296 #define CATB_ISR_SAMPLE_Pos 0 /**< \brief (CATB_ISR) Sample Ready Interrupt Status */ 297 #define CATB_ISR_SAMPLE (_U_(0x1) << CATB_ISR_SAMPLE_Pos) 298 #define CATB_ISR_INTCH_Pos 1 /**< \brief (CATB_ISR) In-touch Interrupt Status */ 299 #define CATB_ISR_INTCH (_U_(0x1) << CATB_ISR_INTCH_Pos) 300 #define CATB_ISR_OUTTCH_Pos 2 /**< \brief (CATB_ISR) Out-of-Touch Interrupt Status */ 301 #define CATB_ISR_OUTTCH (_U_(0x1) << CATB_ISR_OUTTCH_Pos) 302 #define CATB_ISR_MASK _U_(0x00000007) /**< \brief (CATB_ISR) MASK Register */ 303 304 /* -------- CATB_IER : (CATB Offset: 0x28) ( /W 32) Interrupt Enable Register -------- */ 305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 306 typedef union { 307 struct { 308 uint32_t SAMPLE:1; /*!< bit: 0 Sample Ready Interrupt Enable */ 309 uint32_t INTCH:1; /*!< bit: 1 In-touch Interrupt Enable */ 310 uint32_t OUTTCH:1; /*!< bit: 2 Out-of-Touch Interrupt Enable */ 311 uint32_t :29; /*!< bit: 3..31 Reserved */ 312 } bit; /*!< Structure used for bit access */ 313 uint32_t reg; /*!< Type used for register access */ 314 } CATB_IER_Type; 315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 316 317 #define CATB_IER_OFFSET 0x28 /**< \brief (CATB_IER offset) Interrupt Enable Register */ 318 #define CATB_IER_RESETVALUE _U_(0x00000000); /**< \brief (CATB_IER reset_value) Interrupt Enable Register */ 319 320 #define CATB_IER_SAMPLE_Pos 0 /**< \brief (CATB_IER) Sample Ready Interrupt Enable */ 321 #define CATB_IER_SAMPLE (_U_(0x1) << CATB_IER_SAMPLE_Pos) 322 #define CATB_IER_INTCH_Pos 1 /**< \brief (CATB_IER) In-touch Interrupt Enable */ 323 #define CATB_IER_INTCH (_U_(0x1) << CATB_IER_INTCH_Pos) 324 #define CATB_IER_OUTTCH_Pos 2 /**< \brief (CATB_IER) Out-of-Touch Interrupt Enable */ 325 #define CATB_IER_OUTTCH (_U_(0x1) << CATB_IER_OUTTCH_Pos) 326 #define CATB_IER_MASK _U_(0x00000007) /**< \brief (CATB_IER) MASK Register */ 327 328 /* -------- CATB_IDR : (CATB Offset: 0x2C) ( /W 32) Interrupt Disable Register -------- */ 329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 330 typedef union { 331 struct { 332 uint32_t SAMPLE:1; /*!< bit: 0 Sample Ready Interrupt Disable */ 333 uint32_t INTCH:1; /*!< bit: 1 In-touch Interrupt Disable */ 334 uint32_t OUTTCH:1; /*!< bit: 2 Out-of-Touch Interrupt Disable */ 335 uint32_t :29; /*!< bit: 3..31 Reserved */ 336 } bit; /*!< Structure used for bit access */ 337 uint32_t reg; /*!< Type used for register access */ 338 } CATB_IDR_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 #define CATB_IDR_OFFSET 0x2C /**< \brief (CATB_IDR offset) Interrupt Disable Register */ 342 #define CATB_IDR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_IDR reset_value) Interrupt Disable Register */ 343 344 #define CATB_IDR_SAMPLE_Pos 0 /**< \brief (CATB_IDR) Sample Ready Interrupt Disable */ 345 #define CATB_IDR_SAMPLE (_U_(0x1) << CATB_IDR_SAMPLE_Pos) 346 #define CATB_IDR_INTCH_Pos 1 /**< \brief (CATB_IDR) In-touch Interrupt Disable */ 347 #define CATB_IDR_INTCH (_U_(0x1) << CATB_IDR_INTCH_Pos) 348 #define CATB_IDR_OUTTCH_Pos 2 /**< \brief (CATB_IDR) Out-of-Touch Interrupt Disable */ 349 #define CATB_IDR_OUTTCH (_U_(0x1) << CATB_IDR_OUTTCH_Pos) 350 #define CATB_IDR_MASK _U_(0x00000007) /**< \brief (CATB_IDR) MASK Register */ 351 352 /* -------- CATB_IMR : (CATB Offset: 0x30) (R/ 32) Interrupt Mask Register -------- */ 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 typedef union { 355 struct { 356 uint32_t SAMPLE:1; /*!< bit: 0 Sample Ready Interrupt Mask */ 357 uint32_t INTCH:1; /*!< bit: 1 In-touch Interrupt Mask */ 358 uint32_t OUTTCH:1; /*!< bit: 2 Out-of-Touch Interrupt Mask */ 359 uint32_t :29; /*!< bit: 3..31 Reserved */ 360 } bit; /*!< Structure used for bit access */ 361 uint32_t reg; /*!< Type used for register access */ 362 } CATB_IMR_Type; 363 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 364 365 #define CATB_IMR_OFFSET 0x30 /**< \brief (CATB_IMR offset) Interrupt Mask Register */ 366 #define CATB_IMR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_IMR reset_value) Interrupt Mask Register */ 367 368 #define CATB_IMR_SAMPLE_Pos 0 /**< \brief (CATB_IMR) Sample Ready Interrupt Mask */ 369 #define CATB_IMR_SAMPLE (_U_(0x1) << CATB_IMR_SAMPLE_Pos) 370 #define CATB_IMR_INTCH_Pos 1 /**< \brief (CATB_IMR) In-touch Interrupt Mask */ 371 #define CATB_IMR_INTCH (_U_(0x1) << CATB_IMR_INTCH_Pos) 372 #define CATB_IMR_OUTTCH_Pos 2 /**< \brief (CATB_IMR) Out-of-Touch Interrupt Mask */ 373 #define CATB_IMR_OUTTCH (_U_(0x1) << CATB_IMR_OUTTCH_Pos) 374 #define CATB_IMR_MASK _U_(0x00000007) /**< \brief (CATB_IMR) MASK Register */ 375 376 /* -------- CATB_SCR : (CATB Offset: 0x34) ( /W 32) Status Clear Register -------- */ 377 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 378 typedef union { 379 struct { 380 uint32_t SAMPLE:1; /*!< bit: 0 Sample Ready */ 381 uint32_t INTCH:1; /*!< bit: 1 In-touch */ 382 uint32_t OUTTCH:1; /*!< bit: 2 Out-of-Touch */ 383 uint32_t :29; /*!< bit: 3..31 Reserved */ 384 } bit; /*!< Structure used for bit access */ 385 uint32_t reg; /*!< Type used for register access */ 386 } CATB_SCR_Type; 387 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 389 #define CATB_SCR_OFFSET 0x34 /**< \brief (CATB_SCR offset) Status Clear Register */ 390 #define CATB_SCR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_SCR reset_value) Status Clear Register */ 391 392 #define CATB_SCR_SAMPLE_Pos 0 /**< \brief (CATB_SCR) Sample Ready */ 393 #define CATB_SCR_SAMPLE (_U_(0x1) << CATB_SCR_SAMPLE_Pos) 394 #define CATB_SCR_INTCH_Pos 1 /**< \brief (CATB_SCR) In-touch */ 395 #define CATB_SCR_INTCH (_U_(0x1) << CATB_SCR_INTCH_Pos) 396 #define CATB_SCR_OUTTCH_Pos 2 /**< \brief (CATB_SCR) Out-of-Touch */ 397 #define CATB_SCR_OUTTCH (_U_(0x1) << CATB_SCR_OUTTCH_Pos) 398 #define CATB_SCR_MASK _U_(0x00000007) /**< \brief (CATB_SCR) MASK Register */ 399 400 /* -------- CATB_INTCH : (CATB Offset: 0x40) (R/ 32) INTCH In-Touch Status Register -------- */ 401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 402 typedef union { 403 struct { 404 uint32_t INTCH:32; /*!< bit: 0..31 In-Touch */ 405 } bit; /*!< Structure used for bit access */ 406 uint32_t reg; /*!< Type used for register access */ 407 } CATB_INTCH_Type; 408 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 409 410 #define CATB_INTCH_OFFSET 0x40 /**< \brief (CATB_INTCH offset) In-Touch Status Register */ 411 #define CATB_INTCH_RESETVALUE _U_(0x00000000); /**< \brief (CATB_INTCH reset_value) In-Touch Status Register */ 412 413 #define CATB_INTCH_INTCH_Pos 0 /**< \brief (CATB_INTCH) In-Touch */ 414 #define CATB_INTCH_INTCH_Msk (_U_(0xFFFFFFFF) << CATB_INTCH_INTCH_Pos) 415 #define CATB_INTCH_INTCH(value) (CATB_INTCH_INTCH_Msk & ((value) << CATB_INTCH_INTCH_Pos)) 416 #define CATB_INTCH_MASK _U_(0xFFFFFFFF) /**< \brief (CATB_INTCH) MASK Register */ 417 418 /* -------- CATB_INTCHCLR : (CATB Offset: 0x50) ( /W 32) INTCHCLR In-Touch Status Clear Register -------- */ 419 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 420 typedef union { 421 struct { 422 uint32_t INTCHCLR:32; /*!< bit: 0..31 In-Touch Clear */ 423 } bit; /*!< Structure used for bit access */ 424 uint32_t reg; /*!< Type used for register access */ 425 } CATB_INTCHCLR_Type; 426 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 427 428 #define CATB_INTCHCLR_OFFSET 0x50 /**< \brief (CATB_INTCHCLR offset) In-Touch Status Clear Register */ 429 #define CATB_INTCHCLR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_INTCHCLR reset_value) In-Touch Status Clear Register */ 430 431 #define CATB_INTCHCLR_INTCHCLR_Pos 0 /**< \brief (CATB_INTCHCLR) In-Touch Clear */ 432 #define CATB_INTCHCLR_INTCHCLR_Msk (_U_(0xFFFFFFFF) << CATB_INTCHCLR_INTCHCLR_Pos) 433 #define CATB_INTCHCLR_INTCHCLR(value) (CATB_INTCHCLR_INTCHCLR_Msk & ((value) << CATB_INTCHCLR_INTCHCLR_Pos)) 434 #define CATB_INTCHCLR_MASK _U_(0xFFFFFFFF) /**< \brief (CATB_INTCHCLR) MASK Register */ 435 436 /* -------- CATB_OUTTCH : (CATB Offset: 0x60) (R/ 32) OUTTCH Out-of-Touch Status Register -------- */ 437 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 438 typedef union { 439 struct { 440 uint32_t OUTTCH:32; /*!< bit: 0..31 Out-of-Touch */ 441 } bit; /*!< Structure used for bit access */ 442 uint32_t reg; /*!< Type used for register access */ 443 } CATB_OUTTCH_Type; 444 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 445 446 #define CATB_OUTTCH_OFFSET 0x60 /**< \brief (CATB_OUTTCH offset) Out-of-Touch Status Register */ 447 #define CATB_OUTTCH_RESETVALUE _U_(0x00000000); /**< \brief (CATB_OUTTCH reset_value) Out-of-Touch Status Register */ 448 449 #define CATB_OUTTCH_OUTTCH_Pos 0 /**< \brief (CATB_OUTTCH) Out-of-Touch */ 450 #define CATB_OUTTCH_OUTTCH_Msk (_U_(0xFFFFFFFF) << CATB_OUTTCH_OUTTCH_Pos) 451 #define CATB_OUTTCH_OUTTCH(value) (CATB_OUTTCH_OUTTCH_Msk & ((value) << CATB_OUTTCH_OUTTCH_Pos)) 452 #define CATB_OUTTCH_MASK _U_(0xFFFFFFFF) /**< \brief (CATB_OUTTCH) MASK Register */ 453 454 /* -------- CATB_OUTTCHCLR : (CATB Offset: 0x70) ( /W 32) OUTTCHCLR Out-of-Touch Status Clear Register -------- */ 455 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 456 typedef union { 457 struct { 458 uint32_t OUTTCHCLR:32; /*!< bit: 0..31 Out of Touch */ 459 } bit; /*!< Structure used for bit access */ 460 uint32_t reg; /*!< Type used for register access */ 461 } CATB_OUTTCHCLR_Type; 462 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 463 464 #define CATB_OUTTCHCLR_OFFSET 0x70 /**< \brief (CATB_OUTTCHCLR offset) Out-of-Touch Status Clear Register */ 465 #define CATB_OUTTCHCLR_RESETVALUE _U_(0x00000000); /**< \brief (CATB_OUTTCHCLR reset_value) Out-of-Touch Status Clear Register */ 466 467 #define CATB_OUTTCHCLR_OUTTCHCLR_Pos 0 /**< \brief (CATB_OUTTCHCLR) Out of Touch */ 468 #define CATB_OUTTCHCLR_OUTTCHCLR_Msk (_U_(0xFFFFFFFF) << CATB_OUTTCHCLR_OUTTCHCLR_Pos) 469 #define CATB_OUTTCHCLR_OUTTCHCLR(value) (CATB_OUTTCHCLR_OUTTCHCLR_Msk & ((value) << CATB_OUTTCHCLR_OUTTCHCLR_Pos)) 470 #define CATB_OUTTCHCLR_MASK _U_(0xFFFFFFFF) /**< \brief (CATB_OUTTCHCLR) MASK Register */ 471 472 /* -------- CATB_PARAMETER : (CATB Offset: 0xF8) (R/ 32) Parameter Register -------- */ 473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 474 typedef union { 475 struct { 476 uint32_t NPINS:8; /*!< bit: 0.. 7 Number of Pins */ 477 uint32_t NSTATUS:8; /*!< bit: 8..15 Number of Status bits */ 478 uint32_t FRACTIONAL:4; /*!< bit: 16..19 Number of Fractional bits */ 479 uint32_t :12; /*!< bit: 20..31 Reserved */ 480 } bit; /*!< Structure used for bit access */ 481 uint32_t reg; /*!< Type used for register access */ 482 } CATB_PARAMETER_Type; 483 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 484 485 #define CATB_PARAMETER_OFFSET 0xF8 /**< \brief (CATB_PARAMETER offset) Parameter Register */ 486 487 #define CATB_PARAMETER_NPINS_Pos 0 /**< \brief (CATB_PARAMETER) Number of Pins */ 488 #define CATB_PARAMETER_NPINS_Msk (_U_(0xFF) << CATB_PARAMETER_NPINS_Pos) 489 #define CATB_PARAMETER_NPINS(value) (CATB_PARAMETER_NPINS_Msk & ((value) << CATB_PARAMETER_NPINS_Pos)) 490 #define CATB_PARAMETER_NSTATUS_Pos 8 /**< \brief (CATB_PARAMETER) Number of Status bits */ 491 #define CATB_PARAMETER_NSTATUS_Msk (_U_(0xFF) << CATB_PARAMETER_NSTATUS_Pos) 492 #define CATB_PARAMETER_NSTATUS(value) (CATB_PARAMETER_NSTATUS_Msk & ((value) << CATB_PARAMETER_NSTATUS_Pos)) 493 #define CATB_PARAMETER_FRACTIONAL_Pos 16 /**< \brief (CATB_PARAMETER) Number of Fractional bits */ 494 #define CATB_PARAMETER_FRACTIONAL_Msk (_U_(0xF) << CATB_PARAMETER_FRACTIONAL_Pos) 495 #define CATB_PARAMETER_FRACTIONAL(value) (CATB_PARAMETER_FRACTIONAL_Msk & ((value) << CATB_PARAMETER_FRACTIONAL_Pos)) 496 #define CATB_PARAMETER_MASK _U_(0x000FFFFF) /**< \brief (CATB_PARAMETER) MASK Register */ 497 498 /* -------- CATB_VERSION : (CATB Offset: 0xFC) (R/ 32) Version Register -------- */ 499 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 500 typedef union { 501 struct { 502 uint32_t VERSION:12; /*!< bit: 0..11 Version number */ 503 uint32_t :4; /*!< bit: 12..15 Reserved */ 504 uint32_t VARIANT:4; /*!< bit: 16..19 Variant number */ 505 uint32_t :12; /*!< bit: 20..31 Reserved */ 506 } bit; /*!< Structure used for bit access */ 507 uint32_t reg; /*!< Type used for register access */ 508 } CATB_VERSION_Type; 509 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 510 511 #define CATB_VERSION_OFFSET 0xFC /**< \brief (CATB_VERSION offset) Version Register */ 512 #define CATB_VERSION_RESETVALUE _U_(0x00000100); /**< \brief (CATB_VERSION reset_value) Version Register */ 513 514 #define CATB_VERSION_VERSION_Pos 0 /**< \brief (CATB_VERSION) Version number */ 515 #define CATB_VERSION_VERSION_Msk (_U_(0xFFF) << CATB_VERSION_VERSION_Pos) 516 #define CATB_VERSION_VERSION(value) (CATB_VERSION_VERSION_Msk & ((value) << CATB_VERSION_VERSION_Pos)) 517 #define CATB_VERSION_VARIANT_Pos 16 /**< \brief (CATB_VERSION) Variant number */ 518 #define CATB_VERSION_VARIANT_Msk (_U_(0xF) << CATB_VERSION_VARIANT_Pos) 519 #define CATB_VERSION_VARIANT(value) (CATB_VERSION_VARIANT_Msk & ((value) << CATB_VERSION_VARIANT_Pos)) 520 #define CATB_VERSION_MASK _U_(0x000F0FFF) /**< \brief (CATB_VERSION) MASK Register */ 521 522 /** \brief CatbIntch hardware registers */ 523 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 524 typedef union { 525 struct { 526 __I CATB_INTCH_Type INTCH; /**< \brief Offset: 0x00 (R/ 32) In-Touch Status Register */ 527 } bf; 528 struct { 529 RoReg CATB_INTCH; /**< \brief (CATB Offset: 0x00) In-Touch Status Register */ 530 } reg; 531 } CatbIntch; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 /** \brief CatbIntchclr hardware registers */ 535 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 536 typedef union { 537 struct { 538 __O CATB_INTCHCLR_Type INTCHCLR; /**< \brief Offset: 0x00 ( /W 32) In-Touch Status Clear Register */ 539 } bf; 540 struct { 541 WoReg CATB_INTCHCLR; /**< \brief (CATB Offset: 0x00) In-Touch Status Clear Register */ 542 } reg; 543 } CatbIntchclr; 544 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 545 546 /** \brief CatbOuttch hardware registers */ 547 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 548 typedef union { 549 struct { 550 __I CATB_OUTTCH_Type OUTTCH; /**< \brief Offset: 0x00 (R/ 32) Out-of-Touch Status Register */ 551 } bf; 552 struct { 553 RoReg CATB_OUTTCH; /**< \brief (CATB Offset: 0x00) Out-of-Touch Status Register */ 554 } reg; 555 } CatbOuttch; 556 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 557 558 /** \brief CatbOuttchclr hardware registers */ 559 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 560 typedef union { 561 struct { 562 __O CATB_OUTTCHCLR_Type OUTTCHCLR; /**< \brief Offset: 0x00 ( /W 32) Out-of-Touch Status Clear Register */ 563 } bf; 564 struct { 565 WoReg CATB_OUTTCHCLR; /**< \brief (CATB Offset: 0x00) Out-of-Touch Status Clear Register */ 566 } reg; 567 } CatbOuttchclr; 568 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 569 570 /** \brief CATB hardware registers */ 571 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 572 typedef struct { 573 __IO uint32_t CR; /**< \brief Offset: 0x00 (R/W 32) Control Register */ 574 __IO uint32_t CNTCR; /**< \brief Offset: 0x04 (R/W 32) Counter Control Register */ 575 __IO uint32_t IDLE; /**< \brief Offset: 0x08 (R/W 32) Sensor Idle Level */ 576 __I uint32_t LEVEL; /**< \brief Offset: 0x0C (R/ 32) Sensor Relative Level */ 577 __I uint32_t RAW; /**< \brief Offset: 0x10 (R/ 32) Sensor Raw Value */ 578 __IO uint32_t TIMING; /**< \brief Offset: 0x14 (R/W 32) Filter Timing Register */ 579 __IO uint32_t THRESH; /**< \brief Offset: 0x18 (R/W 32) Threshold Register */ 580 __IO uint32_t PINSEL; /**< \brief Offset: 0x1C (R/W 32) Pin Selection Register */ 581 __IO uint32_t DMA; /**< \brief Offset: 0x20 (R/W 32) Direct Memory Access Register */ 582 __I uint32_t ISR; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status Register */ 583 __O uint32_t IER; /**< \brief Offset: 0x28 ( /W 32) Interrupt Enable Register */ 584 __O uint32_t IDR; /**< \brief Offset: 0x2C ( /W 32) Interrupt Disable Register */ 585 __I uint32_t IMR; /**< \brief Offset: 0x30 (R/ 32) Interrupt Mask Register */ 586 __O uint32_t SCR; /**< \brief Offset: 0x34 ( /W 32) Status Clear Register */ 587 RoReg8 Reserved1[0x8]; 588 __I uint32_t Intch[1]; /**< \brief Offset: 0x40 CatbIntch groups [STATUS_REG_NUMBER] */ 589 RoReg8 Reserved2[0xC]; 590 __O uint32_t Intchclr[1]; /**< \brief Offset: 0x50 CatbIntchclr groups [STATUS_REG_NUMBER] */ 591 RoReg8 Reserved3[0xC]; 592 __I uint32_t Outtch[1]; /**< \brief Offset: 0x60 CatbOuttch groups [STATUS_REG_NUMBER] */ 593 RoReg8 Reserved4[0xC]; 594 __O uint32_t Outtchclr[1]; /**< \brief Offset: 0x70 CatbOuttchclr groups [STATUS_REG_NUMBER] */ 595 RoReg8 Reserved5[0x84]; 596 __I uint32_t PARAMETER; /**< \brief Offset: 0xF8 (R/ 32) Parameter Register */ 597 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 598 } Catb; 599 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 600 601 /*@}*/ 602 603 #endif /* _SAM4L_CATB_COMPONENT_ */ 604
