1 /** 2 * \file 3 * 4 * \brief Component description for HCACHE 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_HCACHE_COMPONENT_ 30 #define _SAM4L_HCACHE_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR HCACHE */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_HCACHE Cortex M I&D Cache Controller */ 36 /*@{*/ 37 38 #define HCACHE_I8323 39 #define REV_HCACHE 0x101 40 41 /* -------- HCACHE_CTRL : (HCACHE Offset: 0x08) ( /W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t CEN:1; /*!< bit: 0 Cache Enable */ 46 uint32_t :31; /*!< bit: 1..31 Reserved */ 47 } bit; /*!< Structure used for bit access */ 48 uint32_t reg; /*!< Type used for register access */ 49 } HCACHE_CTRL_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define HCACHE_CTRL_OFFSET 0x08 /**< \brief (HCACHE_CTRL offset) Control Register */ 53 54 #define HCACHE_CTRL_CEN_Pos 0 /**< \brief (HCACHE_CTRL) Cache Enable */ 55 #define HCACHE_CTRL_CEN (_U_(0x1) << HCACHE_CTRL_CEN_Pos) 56 #define HCACHE_CTRL_CEN_NO_Val _U_(0x0) /**< \brief (HCACHE_CTRL) Disable Cache Controller */ 57 #define HCACHE_CTRL_CEN_YES_Val _U_(0x1) /**< \brief (HCACHE_CTRL) Enable Cache Controller */ 58 #define HCACHE_CTRL_CEN_NO (HCACHE_CTRL_CEN_NO_Val << HCACHE_CTRL_CEN_Pos) 59 #define HCACHE_CTRL_CEN_YES (HCACHE_CTRL_CEN_YES_Val << HCACHE_CTRL_CEN_Pos) 60 #define HCACHE_CTRL_MASK _U_(0x00000001) /**< \brief (HCACHE_CTRL) MASK Register */ 61 62 /* -------- HCACHE_SR : (HCACHE Offset: 0x0C) (R/W 32) Status Register -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ 67 uint32_t :31; /*!< bit: 1..31 Reserved */ 68 } bit; /*!< Structure used for bit access */ 69 uint32_t reg; /*!< Type used for register access */ 70 } HCACHE_SR_Type; 71 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define HCACHE_SR_OFFSET 0x0C /**< \brief (HCACHE_SR offset) Status Register */ 74 75 #define HCACHE_SR_CSTS_Pos 0 /**< \brief (HCACHE_SR) Cache Controller Status */ 76 #define HCACHE_SR_CSTS (_U_(0x1) << HCACHE_SR_CSTS_Pos) 77 #define HCACHE_SR_CSTS_DIS_Val _U_(0x0) /**< \brief (HCACHE_SR) Cache Controller Disabled */ 78 #define HCACHE_SR_CSTS_EN_Val _U_(0x1) /**< \brief (HCACHE_SR) Cache Controller Enabled */ 79 #define HCACHE_SR_CSTS_DIS (HCACHE_SR_CSTS_DIS_Val << HCACHE_SR_CSTS_Pos) 80 #define HCACHE_SR_CSTS_EN (HCACHE_SR_CSTS_EN_Val << HCACHE_SR_CSTS_Pos) 81 #define HCACHE_SR_MASK _U_(0x00000001) /**< \brief (HCACHE_SR) MASK Register */ 82 83 /* -------- HCACHE_MAINT0 : (HCACHE Offset: 0x20) ( /W 32) Maintenance Register 0 -------- */ 84 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 85 typedef union { 86 struct { 87 uint32_t INVALL:1; /*!< bit: 0 Cache Controller Invalidate All */ 88 uint32_t :31; /*!< bit: 1..31 Reserved */ 89 } bit; /*!< Structure used for bit access */ 90 uint32_t reg; /*!< Type used for register access */ 91 } HCACHE_MAINT0_Type; 92 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 #define HCACHE_MAINT0_OFFSET 0x20 /**< \brief (HCACHE_MAINT0 offset) Maintenance Register 0 */ 95 96 #define HCACHE_MAINT0_INVALL_Pos 0 /**< \brief (HCACHE_MAINT0) Cache Controller Invalidate All */ 97 #define HCACHE_MAINT0_INVALL (_U_(0x1) << HCACHE_MAINT0_INVALL_Pos) 98 #define HCACHE_MAINT0_INVALL_NO_Val _U_(0x0) /**< \brief (HCACHE_MAINT0) No effect */ 99 #define HCACHE_MAINT0_INVALL_YES_Val _U_(0x1) /**< \brief (HCACHE_MAINT0) Invalidate all cache entries */ 100 #define HCACHE_MAINT0_INVALL_NO (HCACHE_MAINT0_INVALL_NO_Val << HCACHE_MAINT0_INVALL_Pos) 101 #define HCACHE_MAINT0_INVALL_YES (HCACHE_MAINT0_INVALL_YES_Val << HCACHE_MAINT0_INVALL_Pos) 102 #define HCACHE_MAINT0_MASK _U_(0x00000001) /**< \brief (HCACHE_MAINT0) MASK Register */ 103 104 /* -------- HCACHE_MAINT1 : (HCACHE Offset: 0x24) ( /W 32) Maintenance Register 1 -------- */ 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 106 typedef union { 107 struct { 108 uint32_t :4; /*!< bit: 0.. 3 Reserved */ 109 uint32_t INDEX:4; /*!< bit: 4.. 7 Invalidate Index */ 110 uint32_t :24; /*!< bit: 8..31 Reserved */ 111 } bit; /*!< Structure used for bit access */ 112 uint32_t reg; /*!< Type used for register access */ 113 } HCACHE_MAINT1_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define HCACHE_MAINT1_OFFSET 0x24 /**< \brief (HCACHE_MAINT1 offset) Maintenance Register 1 */ 117 118 #define HCACHE_MAINT1_INDEX_Pos 4 /**< \brief (HCACHE_MAINT1) Invalidate Index */ 119 #define HCACHE_MAINT1_INDEX_Msk (_U_(0xF) << HCACHE_MAINT1_INDEX_Pos) 120 #define HCACHE_MAINT1_INDEX(value) (HCACHE_MAINT1_INDEX_Msk & ((value) << HCACHE_MAINT1_INDEX_Pos)) 121 #define HCACHE_MAINT1_MASK _U_(0x000000F0) /**< \brief (HCACHE_MAINT1) MASK Register */ 122 123 /* -------- HCACHE_MCFG : (HCACHE Offset: 0x28) (R/W 32) Monitor Configuration Register -------- */ 124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 125 typedef union { 126 struct { 127 uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ 128 uint32_t :30; /*!< bit: 2..31 Reserved */ 129 } bit; /*!< Structure used for bit access */ 130 uint32_t reg; /*!< Type used for register access */ 131 } HCACHE_MCFG_Type; 132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 133 134 #define HCACHE_MCFG_OFFSET 0x28 /**< \brief (HCACHE_MCFG offset) Monitor Configuration Register */ 135 136 #define HCACHE_MCFG_MODE_Pos 0 /**< \brief (HCACHE_MCFG) Cache Controller Monitor Counter Mode */ 137 #define HCACHE_MCFG_MODE_Msk (_U_(0x3) << HCACHE_MCFG_MODE_Pos) 138 #define HCACHE_MCFG_MODE(value) (HCACHE_MCFG_MODE_Msk & ((value) << HCACHE_MCFG_MODE_Pos)) 139 #define HCACHE_MCFG_MODE_CYCLE_Val _U_(0x0) /**< \brief (HCACHE_MCFG) Cycle Counter */ 140 #define HCACHE_MCFG_MODE_IHIT_Val _U_(0x1) /**< \brief (HCACHE_MCFG) Instruction Hit Counter */ 141 #define HCACHE_MCFG_MODE_DHIT_Val _U_(0x2) /**< \brief (HCACHE_MCFG) Data Hit Counter */ 142 #define HCACHE_MCFG_MODE_CYCLE (HCACHE_MCFG_MODE_CYCLE_Val << HCACHE_MCFG_MODE_Pos) 143 #define HCACHE_MCFG_MODE_IHIT (HCACHE_MCFG_MODE_IHIT_Val << HCACHE_MCFG_MODE_Pos) 144 #define HCACHE_MCFG_MODE_DHIT (HCACHE_MCFG_MODE_DHIT_Val << HCACHE_MCFG_MODE_Pos) 145 #define HCACHE_MCFG_MASK _U_(0x00000003) /**< \brief (HCACHE_MCFG) MASK Register */ 146 147 /* -------- HCACHE_MEN : (HCACHE Offset: 0x2C) (R/W 32) Monitor Enable Register -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t MENABLE:1; /*!< bit: 0 Monitor Enable */ 152 uint32_t :31; /*!< bit: 1..31 Reserved */ 153 } bit; /*!< Structure used for bit access */ 154 uint32_t reg; /*!< Type used for register access */ 155 } HCACHE_MEN_Type; 156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 157 158 #define HCACHE_MEN_OFFSET 0x2C /**< \brief (HCACHE_MEN offset) Monitor Enable Register */ 159 160 #define HCACHE_MEN_MENABLE_Pos 0 /**< \brief (HCACHE_MEN) Monitor Enable */ 161 #define HCACHE_MEN_MENABLE (_U_(0x1) << HCACHE_MEN_MENABLE_Pos) 162 #define HCACHE_MEN_MENABLE_DIS_Val _U_(0x0) /**< \brief (HCACHE_MEN) Disable Monitor Counter */ 163 #define HCACHE_MEN_MENABLE_EN_Val _U_(0x1) /**< \brief (HCACHE_MEN) Enable Monitor Counter */ 164 #define HCACHE_MEN_MENABLE_DIS (HCACHE_MEN_MENABLE_DIS_Val << HCACHE_MEN_MENABLE_Pos) 165 #define HCACHE_MEN_MENABLE_EN (HCACHE_MEN_MENABLE_EN_Val << HCACHE_MEN_MENABLE_Pos) 166 #define HCACHE_MEN_MASK _U_(0x00000001) /**< \brief (HCACHE_MEN) MASK Register */ 167 168 /* -------- HCACHE_MCTRL : (HCACHE Offset: 0x30) ( /W 32) Monitor Control Register -------- */ 169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 170 typedef union { 171 struct { 172 uint32_t SWRST:1; /*!< bit: 0 Monitor Software Reset */ 173 uint32_t :31; /*!< bit: 1..31 Reserved */ 174 } bit; /*!< Structure used for bit access */ 175 uint32_t reg; /*!< Type used for register access */ 176 } HCACHE_MCTRL_Type; 177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 178 179 #define HCACHE_MCTRL_OFFSET 0x30 /**< \brief (HCACHE_MCTRL offset) Monitor Control Register */ 180 181 #define HCACHE_MCTRL_SWRST_Pos 0 /**< \brief (HCACHE_MCTRL) Monitor Software Reset */ 182 #define HCACHE_MCTRL_SWRST (_U_(0x1) << HCACHE_MCTRL_SWRST_Pos) 183 #define HCACHE_MCTRL_SWRST_NO_Val _U_(0x0) /**< \brief (HCACHE_MCTRL) No effect */ 184 #define HCACHE_MCTRL_SWRST_YES_Val _U_(0x1) /**< \brief (HCACHE_MCTRL) Reset event counter register */ 185 #define HCACHE_MCTRL_SWRST_NO (HCACHE_MCTRL_SWRST_NO_Val << HCACHE_MCTRL_SWRST_Pos) 186 #define HCACHE_MCTRL_SWRST_YES (HCACHE_MCTRL_SWRST_YES_Val << HCACHE_MCTRL_SWRST_Pos) 187 #define HCACHE_MCTRL_MASK _U_(0x00000001) /**< \brief (HCACHE_MCTRL) MASK Register */ 188 189 /* -------- HCACHE_MSR : (HCACHE Offset: 0x34) (R/ 32) Monitor Status Register -------- */ 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 191 typedef union { 192 struct { 193 uint32_t EVENTCNT:32; /*!< bit: 0..31 Monitor Event Counter */ 194 } bit; /*!< Structure used for bit access */ 195 uint32_t reg; /*!< Type used for register access */ 196 } HCACHE_MSR_Type; 197 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 198 199 #define HCACHE_MSR_OFFSET 0x34 /**< \brief (HCACHE_MSR offset) Monitor Status Register */ 200 201 #define HCACHE_MSR_EVENTCNT_Pos 0 /**< \brief (HCACHE_MSR) Monitor Event Counter */ 202 #define HCACHE_MSR_EVENTCNT_Msk (_U_(0xFFFFFFFF) << HCACHE_MSR_EVENTCNT_Pos) 203 #define HCACHE_MSR_EVENTCNT(value) (HCACHE_MSR_EVENTCNT_Msk & ((value) << HCACHE_MSR_EVENTCNT_Pos)) 204 #define HCACHE_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (HCACHE_MSR) MASK Register */ 205 206 /* -------- HCACHE_VERSION : (HCACHE Offset: 0xFC) (R/ 32) Version Register -------- */ 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 208 typedef union { 209 struct { 210 uint32_t VERSION:12; /*!< bit: 0..11 VERSION */ 211 uint32_t :4; /*!< bit: 12..15 Reserved */ 212 uint32_t MFN:4; /*!< bit: 16..19 MFN */ 213 uint32_t :12; /*!< bit: 20..31 Reserved */ 214 } bit; /*!< Structure used for bit access */ 215 uint32_t reg; /*!< Type used for register access */ 216 } HCACHE_VERSION_Type; 217 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 218 219 #define HCACHE_VERSION_OFFSET 0xFC /**< \brief (HCACHE_VERSION offset) Version Register */ 220 #define HCACHE_VERSION_RESETVALUE _U_(0x00000101); /**< \brief (HCACHE_VERSION reset_value) Version Register */ 221 222 #define HCACHE_VERSION_VERSION_Pos 0 /**< \brief (HCACHE_VERSION) VERSION */ 223 #define HCACHE_VERSION_VERSION_Msk (_U_(0xFFF) << HCACHE_VERSION_VERSION_Pos) 224 #define HCACHE_VERSION_VERSION(value) (HCACHE_VERSION_VERSION_Msk & ((value) << HCACHE_VERSION_VERSION_Pos)) 225 #define HCACHE_VERSION_MFN_Pos 16 /**< \brief (HCACHE_VERSION) MFN */ 226 #define HCACHE_VERSION_MFN_Msk (_U_(0xF) << HCACHE_VERSION_MFN_Pos) 227 #define HCACHE_VERSION_MFN(value) (HCACHE_VERSION_MFN_Msk & ((value) << HCACHE_VERSION_MFN_Pos)) 228 #define HCACHE_VERSION_MASK _U_(0x000F0FFF) /**< \brief (HCACHE_VERSION) MASK Register */ 229 230 /** \brief HCACHE hardware registers */ 231 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 232 typedef struct { 233 RoReg8 Reserved1[0x8]; 234 __O uint32_t CTRL; /**< \brief Offset: 0x08 ( /W 32) Control Register */ 235 __IO uint32_t SR; /**< \brief Offset: 0x0C (R/W 32) Status Register */ 236 RoReg8 Reserved2[0x10]; 237 __O uint32_t MAINT0; /**< \brief Offset: 0x20 ( /W 32) Maintenance Register 0 */ 238 __O uint32_t MAINT1; /**< \brief Offset: 0x24 ( /W 32) Maintenance Register 1 */ 239 __IO uint32_t MCFG; /**< \brief Offset: 0x28 (R/W 32) Monitor Configuration Register */ 240 __IO uint32_t MEN; /**< \brief Offset: 0x2C (R/W 32) Monitor Enable Register */ 241 __O uint32_t MCTRL; /**< \brief Offset: 0x30 ( /W 32) Monitor Control Register */ 242 __I uint32_t MSR; /**< \brief Offset: 0x34 (R/ 32) Monitor Status Register */ 243 RoReg8 Reserved3[0xC4]; 244 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 245 } Hcache; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 /*@}*/ 249 250 #endif /* _SAM4L_HCACHE_COMPONENT_ */ 251
