1 /** 2 * \file 3 * 4 * \brief Component description for AST 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_AST_COMPONENT_ 30 #define _SAM4L_AST_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR AST */ 34 /* ========================================================================== */ 35 /** \addtogroup SAM4L_AST Asynchronous Timer */ 36 /*@{*/ 37 38 #define AST_I7532 39 #define REV_AST 0x311 40 41 /* -------- AST_CR : (AST Offset: 0x00) (R/W 32) Control Register -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t EN:1; /*!< bit: 0 Enable */ 46 uint32_t PCLR:1; /*!< bit: 1 Prescaler Clear */ 47 uint32_t CAL:1; /*!< bit: 2 Calendar mode */ 48 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 49 uint32_t CA0:1; /*!< bit: 8 Clear on Alarm 0 */ 50 uint32_t CA1:1; /*!< bit: 9 Clear on Alarm 1 */ 51 uint32_t :6; /*!< bit: 10..15 Reserved */ 52 uint32_t PSEL:5; /*!< bit: 16..20 Prescaler Select */ 53 uint32_t :11; /*!< bit: 21..31 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 uint32_t reg; /*!< Type used for register access */ 56 } AST_CR_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define AST_CR_OFFSET 0x00 /**< \brief (AST_CR offset) Control Register */ 60 #define AST_CR_RESETVALUE _U_(0x00000000); /**< \brief (AST_CR reset_value) Control Register */ 61 62 #define AST_CR_EN_Pos 0 /**< \brief (AST_CR) Enable */ 63 #define AST_CR_EN (_U_(0x1) << AST_CR_EN_Pos) 64 #define AST_CR_EN_0_Val _U_(0x0) /**< \brief (AST_CR) The AST is disabled. */ 65 #define AST_CR_EN_1_Val _U_(0x1) /**< \brief (AST_CR) The AST is enabled */ 66 #define AST_CR_EN_0 (AST_CR_EN_0_Val << AST_CR_EN_Pos) 67 #define AST_CR_EN_1 (AST_CR_EN_1_Val << AST_CR_EN_Pos) 68 #define AST_CR_PCLR_Pos 1 /**< \brief (AST_CR) Prescaler Clear */ 69 #define AST_CR_PCLR (_U_(0x1) << AST_CR_PCLR_Pos) 70 #define AST_CR_CAL_Pos 2 /**< \brief (AST_CR) Calendar mode */ 71 #define AST_CR_CAL (_U_(0x1) << AST_CR_CAL_Pos) 72 #define AST_CR_CA0_Pos 8 /**< \brief (AST_CR) Clear on Alarm 0 */ 73 #define AST_CR_CA0 (_U_(0x1) << AST_CR_CA0_Pos) 74 #define AST_CR_CA1_Pos 9 /**< \brief (AST_CR) Clear on Alarm 1 */ 75 #define AST_CR_CA1 (_U_(0x1) << AST_CR_CA1_Pos) 76 #define AST_CR_PSEL_Pos 16 /**< \brief (AST_CR) Prescaler Select */ 77 #define AST_CR_PSEL_Msk (_U_(0x1F) << AST_CR_PSEL_Pos) 78 #define AST_CR_PSEL(value) (AST_CR_PSEL_Msk & ((value) << AST_CR_PSEL_Pos)) 79 #define AST_CR_MASK _U_(0x001F0307) /**< \brief (AST_CR) MASK Register */ 80 81 /* -------- AST_CV : (AST Offset: 0x04) (R/W 32) Counter Value -------- */ 82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 83 typedef union { 84 struct { 85 uint32_t VALUE:32; /*!< bit: 0..31 AST Value */ 86 } bit; /*!< Structure used for bit access */ 87 uint32_t reg; /*!< Type used for register access */ 88 } AST_CV_Type; 89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 91 #define AST_CV_OFFSET 0x04 /**< \brief (AST_CV offset) Counter Value */ 92 #define AST_CV_RESETVALUE _U_(0x00000000); /**< \brief (AST_CV reset_value) Counter Value */ 93 94 #define AST_CV_VALUE_Pos 0 /**< \brief (AST_CV) AST Value */ 95 #define AST_CV_VALUE_Msk (_U_(0xFFFFFFFF) << AST_CV_VALUE_Pos) 96 #define AST_CV_VALUE(value) (AST_CV_VALUE_Msk & ((value) << AST_CV_VALUE_Pos)) 97 #define AST_CV_MASK _U_(0xFFFFFFFF) /**< \brief (AST_CV) MASK Register */ 98 99 /* -------- AST_SR : (AST Offset: 0x08) (R/ 32) Status Register -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint32_t OVF:1; /*!< bit: 0 Overflow */ 104 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 105 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 106 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 107 uint32_t :6; /*!< bit: 10..15 Reserved */ 108 uint32_t PER0:1; /*!< bit: 16 Periodic 0 */ 109 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 110 uint32_t :6; /*!< bit: 18..23 Reserved */ 111 uint32_t BUSY:1; /*!< bit: 24 AST Busy */ 112 uint32_t READY:1; /*!< bit: 25 AST Ready */ 113 uint32_t :2; /*!< bit: 26..27 Reserved */ 114 uint32_t CLKBUSY:1; /*!< bit: 28 Clock Busy */ 115 uint32_t CLKRDY:1; /*!< bit: 29 Clock Ready */ 116 uint32_t :2; /*!< bit: 30..31 Reserved */ 117 } bit; /*!< Structure used for bit access */ 118 uint32_t reg; /*!< Type used for register access */ 119 } AST_SR_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 #define AST_SR_OFFSET 0x08 /**< \brief (AST_SR offset) Status Register */ 123 #define AST_SR_RESETVALUE _U_(0x00000000); /**< \brief (AST_SR reset_value) Status Register */ 124 125 #define AST_SR_OVF_Pos 0 /**< \brief (AST_SR) Overflow */ 126 #define AST_SR_OVF (_U_(0x1) << AST_SR_OVF_Pos) 127 #define AST_SR_ALARM0_Pos 8 /**< \brief (AST_SR) Alarm 0 */ 128 #define AST_SR_ALARM0 (_U_(0x1) << AST_SR_ALARM0_Pos) 129 #define AST_SR_ALARM1_Pos 9 /**< \brief (AST_SR) Alarm 1 */ 130 #define AST_SR_ALARM1 (_U_(0x1) << AST_SR_ALARM1_Pos) 131 #define AST_SR_PER0_Pos 16 /**< \brief (AST_SR) Periodic 0 */ 132 #define AST_SR_PER0 (_U_(0x1) << AST_SR_PER0_Pos) 133 #define AST_SR_PER1_Pos 17 /**< \brief (AST_SR) Periodic 1 */ 134 #define AST_SR_PER1 (_U_(0x1) << AST_SR_PER1_Pos) 135 #define AST_SR_BUSY_Pos 24 /**< \brief (AST_SR) AST Busy */ 136 #define AST_SR_BUSY (_U_(0x1) << AST_SR_BUSY_Pos) 137 #define AST_SR_BUSY_0_Val _U_(0x0) /**< \brief (AST_SR) The AST accepts writes to CV, WER, DTR, SCR, AR, PIR and CR */ 138 #define AST_SR_BUSY_1_Val _U_(0x1) /**< \brief (AST_SR) The AST is busy and will discard writes to CV, WER, DTR, SCR, AR, PIR and CR */ 139 #define AST_SR_BUSY_0 (AST_SR_BUSY_0_Val << AST_SR_BUSY_Pos) 140 #define AST_SR_BUSY_1 (AST_SR_BUSY_1_Val << AST_SR_BUSY_Pos) 141 #define AST_SR_READY_Pos 25 /**< \brief (AST_SR) AST Ready */ 142 #define AST_SR_READY (_U_(0x1) << AST_SR_READY_Pos) 143 #define AST_SR_CLKBUSY_Pos 28 /**< \brief (AST_SR) Clock Busy */ 144 #define AST_SR_CLKBUSY (_U_(0x1) << AST_SR_CLKBUSY_Pos) 145 #define AST_SR_CLKBUSY_0_Val _U_(0x0) /**< \brief (AST_SR) The clock is ready and can be changed */ 146 #define AST_SR_CLKBUSY_1_Val _U_(0x1) /**< \brief (AST_SR) CEN has been written and the clock is busy */ 147 #define AST_SR_CLKBUSY_0 (AST_SR_CLKBUSY_0_Val << AST_SR_CLKBUSY_Pos) 148 #define AST_SR_CLKBUSY_1 (AST_SR_CLKBUSY_1_Val << AST_SR_CLKBUSY_Pos) 149 #define AST_SR_CLKRDY_Pos 29 /**< \brief (AST_SR) Clock Ready */ 150 #define AST_SR_CLKRDY (_U_(0x1) << AST_SR_CLKRDY_Pos) 151 #define AST_SR_MASK _U_(0x33030301) /**< \brief (AST_SR) MASK Register */ 152 153 /* -------- AST_SCR : (AST Offset: 0x0C) ( /W 32) Status Clear Register -------- */ 154 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 155 typedef union { 156 struct { 157 uint32_t OVF:1; /*!< bit: 0 Overflow */ 158 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 159 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 160 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 161 uint32_t :6; /*!< bit: 10..15 Reserved */ 162 uint32_t PER0:1; /*!< bit: 16 Periodic 0 */ 163 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 164 uint32_t :7; /*!< bit: 18..24 Reserved */ 165 uint32_t READY:1; /*!< bit: 25 AST Ready */ 166 uint32_t :3; /*!< bit: 26..28 Reserved */ 167 uint32_t CLKRDY:1; /*!< bit: 29 Clock Ready */ 168 uint32_t :2; /*!< bit: 30..31 Reserved */ 169 } bit; /*!< Structure used for bit access */ 170 uint32_t reg; /*!< Type used for register access */ 171 } AST_SCR_Type; 172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 173 174 #define AST_SCR_OFFSET 0x0C /**< \brief (AST_SCR offset) Status Clear Register */ 175 #define AST_SCR_RESETVALUE _U_(0x00000000); /**< \brief (AST_SCR reset_value) Status Clear Register */ 176 177 #define AST_SCR_OVF_Pos 0 /**< \brief (AST_SCR) Overflow */ 178 #define AST_SCR_OVF (_U_(0x1) << AST_SCR_OVF_Pos) 179 #define AST_SCR_ALARM0_Pos 8 /**< \brief (AST_SCR) Alarm 0 */ 180 #define AST_SCR_ALARM0 (_U_(0x1) << AST_SCR_ALARM0_Pos) 181 #define AST_SCR_ALARM1_Pos 9 /**< \brief (AST_SCR) Alarm 1 */ 182 #define AST_SCR_ALARM1 (_U_(0x1) << AST_SCR_ALARM1_Pos) 183 #define AST_SCR_PER0_Pos 16 /**< \brief (AST_SCR) Periodic 0 */ 184 #define AST_SCR_PER0 (_U_(0x1) << AST_SCR_PER0_Pos) 185 #define AST_SCR_PER1_Pos 17 /**< \brief (AST_SCR) Periodic 1 */ 186 #define AST_SCR_PER1 (_U_(0x1) << AST_SCR_PER1_Pos) 187 #define AST_SCR_READY_Pos 25 /**< \brief (AST_SCR) AST Ready */ 188 #define AST_SCR_READY (_U_(0x1) << AST_SCR_READY_Pos) 189 #define AST_SCR_CLKRDY_Pos 29 /**< \brief (AST_SCR) Clock Ready */ 190 #define AST_SCR_CLKRDY (_U_(0x1) << AST_SCR_CLKRDY_Pos) 191 #define AST_SCR_MASK _U_(0x22030301) /**< \brief (AST_SCR) MASK Register */ 192 193 /* -------- AST_IER : (AST Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */ 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 195 typedef union { 196 struct { 197 uint32_t OVF:1; /*!< bit: 0 Overflow */ 198 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 199 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 200 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 201 uint32_t :6; /*!< bit: 10..15 Reserved */ 202 uint32_t PER0:1; /*!< bit: 16 Periodic 0 */ 203 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 204 uint32_t :7; /*!< bit: 18..24 Reserved */ 205 uint32_t READY:1; /*!< bit: 25 AST Ready */ 206 uint32_t :3; /*!< bit: 26..28 Reserved */ 207 uint32_t CLKRDY:1; /*!< bit: 29 Clock Ready */ 208 uint32_t :2; /*!< bit: 30..31 Reserved */ 209 } bit; /*!< Structure used for bit access */ 210 uint32_t reg; /*!< Type used for register access */ 211 } AST_IER_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 #define AST_IER_OFFSET 0x10 /**< \brief (AST_IER offset) Interrupt Enable Register */ 215 #define AST_IER_RESETVALUE _U_(0x00000000); /**< \brief (AST_IER reset_value) Interrupt Enable Register */ 216 217 #define AST_IER_OVF_Pos 0 /**< \brief (AST_IER) Overflow */ 218 #define AST_IER_OVF (_U_(0x1) << AST_IER_OVF_Pos) 219 #define AST_IER_OVF_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 220 #define AST_IER_OVF_1_Val _U_(0x1) /**< \brief (AST_IER) Enable Interrupt. */ 221 #define AST_IER_OVF_0 (AST_IER_OVF_0_Val << AST_IER_OVF_Pos) 222 #define AST_IER_OVF_1 (AST_IER_OVF_1_Val << AST_IER_OVF_Pos) 223 #define AST_IER_ALARM0_Pos 8 /**< \brief (AST_IER) Alarm 0 */ 224 #define AST_IER_ALARM0 (_U_(0x1) << AST_IER_ALARM0_Pos) 225 #define AST_IER_ALARM0_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 226 #define AST_IER_ALARM0_1_Val _U_(0x1) /**< \brief (AST_IER) Enable interrupt */ 227 #define AST_IER_ALARM0_0 (AST_IER_ALARM0_0_Val << AST_IER_ALARM0_Pos) 228 #define AST_IER_ALARM0_1 (AST_IER_ALARM0_1_Val << AST_IER_ALARM0_Pos) 229 #define AST_IER_ALARM1_Pos 9 /**< \brief (AST_IER) Alarm 1 */ 230 #define AST_IER_ALARM1 (_U_(0x1) << AST_IER_ALARM1_Pos) 231 #define AST_IER_ALARM1_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 232 #define AST_IER_ALARM1_1_Val _U_(0x1) /**< \brief (AST_IER) Enable interrupt */ 233 #define AST_IER_ALARM1_0 (AST_IER_ALARM1_0_Val << AST_IER_ALARM1_Pos) 234 #define AST_IER_ALARM1_1 (AST_IER_ALARM1_1_Val << AST_IER_ALARM1_Pos) 235 #define AST_IER_PER0_Pos 16 /**< \brief (AST_IER) Periodic 0 */ 236 #define AST_IER_PER0 (_U_(0x1) << AST_IER_PER0_Pos) 237 #define AST_IER_PER0_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 238 #define AST_IER_PER0_1_Val _U_(0x1) /**< \brief (AST_IER) Enable interrupt */ 239 #define AST_IER_PER0_0 (AST_IER_PER0_0_Val << AST_IER_PER0_Pos) 240 #define AST_IER_PER0_1 (AST_IER_PER0_1_Val << AST_IER_PER0_Pos) 241 #define AST_IER_PER1_Pos 17 /**< \brief (AST_IER) Periodic 1 */ 242 #define AST_IER_PER1 (_U_(0x1) << AST_IER_PER1_Pos) 243 #define AST_IER_PER1_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 244 #define AST_IER_PER1_1_Val _U_(0x1) /**< \brief (AST_IER) Enable interrupt */ 245 #define AST_IER_PER1_0 (AST_IER_PER1_0_Val << AST_IER_PER1_Pos) 246 #define AST_IER_PER1_1 (AST_IER_PER1_1_Val << AST_IER_PER1_Pos) 247 #define AST_IER_READY_Pos 25 /**< \brief (AST_IER) AST Ready */ 248 #define AST_IER_READY (_U_(0x1) << AST_IER_READY_Pos) 249 #define AST_IER_READY_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 250 #define AST_IER_READY_1_Val _U_(0x1) /**< \brief (AST_IER) Enable interrupt */ 251 #define AST_IER_READY_0 (AST_IER_READY_0_Val << AST_IER_READY_Pos) 252 #define AST_IER_READY_1 (AST_IER_READY_1_Val << AST_IER_READY_Pos) 253 #define AST_IER_CLKRDY_Pos 29 /**< \brief (AST_IER) Clock Ready */ 254 #define AST_IER_CLKRDY (_U_(0x1) << AST_IER_CLKRDY_Pos) 255 #define AST_IER_CLKRDY_0_Val _U_(0x0) /**< \brief (AST_IER) No effect */ 256 #define AST_IER_CLKRDY_1_Val _U_(0x1) /**< \brief (AST_IER) Enable interrupt */ 257 #define AST_IER_CLKRDY_0 (AST_IER_CLKRDY_0_Val << AST_IER_CLKRDY_Pos) 258 #define AST_IER_CLKRDY_1 (AST_IER_CLKRDY_1_Val << AST_IER_CLKRDY_Pos) 259 #define AST_IER_MASK _U_(0x22030301) /**< \brief (AST_IER) MASK Register */ 260 261 /* -------- AST_IDR : (AST Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { 264 struct { 265 uint32_t OVF:1; /*!< bit: 0 Overflow */ 266 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 267 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 268 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 269 uint32_t :6; /*!< bit: 10..15 Reserved */ 270 uint32_t PER0:1; /*!< bit: 16 Periodic 0 */ 271 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 272 uint32_t :7; /*!< bit: 18..24 Reserved */ 273 uint32_t READY:1; /*!< bit: 25 AST Ready */ 274 uint32_t :3; /*!< bit: 26..28 Reserved */ 275 uint32_t CLKRDY:1; /*!< bit: 29 Clock Ready */ 276 uint32_t :2; /*!< bit: 30..31 Reserved */ 277 } bit; /*!< Structure used for bit access */ 278 uint32_t reg; /*!< Type used for register access */ 279 } AST_IDR_Type; 280 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 #define AST_IDR_OFFSET 0x14 /**< \brief (AST_IDR offset) Interrupt Disable Register */ 283 #define AST_IDR_RESETVALUE _U_(0x00000000); /**< \brief (AST_IDR reset_value) Interrupt Disable Register */ 284 285 #define AST_IDR_OVF_Pos 0 /**< \brief (AST_IDR) Overflow */ 286 #define AST_IDR_OVF (_U_(0x1) << AST_IDR_OVF_Pos) 287 #define AST_IDR_OVF_0_Val _U_(0x0) /**< \brief (AST_IDR) No effect */ 288 #define AST_IDR_OVF_1_Val _U_(0x1) /**< \brief (AST_IDR) Disable Interrupt. */ 289 #define AST_IDR_OVF_0 (AST_IDR_OVF_0_Val << AST_IDR_OVF_Pos) 290 #define AST_IDR_OVF_1 (AST_IDR_OVF_1_Val << AST_IDR_OVF_Pos) 291 #define AST_IDR_ALARM0_Pos 8 /**< \brief (AST_IDR) Alarm 0 */ 292 #define AST_IDR_ALARM0 (_U_(0x1) << AST_IDR_ALARM0_Pos) 293 #define AST_IDR_ALARM0_0_Val _U_(0x0) /**< \brief (AST_IDR) No effect */ 294 #define AST_IDR_ALARM0_1_Val _U_(0x1) /**< \brief (AST_IDR) Disable interrupt */ 295 #define AST_IDR_ALARM0_0 (AST_IDR_ALARM0_0_Val << AST_IDR_ALARM0_Pos) 296 #define AST_IDR_ALARM0_1 (AST_IDR_ALARM0_1_Val << AST_IDR_ALARM0_Pos) 297 #define AST_IDR_ALARM1_Pos 9 /**< \brief (AST_IDR) Alarm 1 */ 298 #define AST_IDR_ALARM1 (_U_(0x1) << AST_IDR_ALARM1_Pos) 299 #define AST_IDR_ALARM1_0_Val _U_(0x0) /**< \brief (AST_IDR) No effect */ 300 #define AST_IDR_ALARM1_1_Val _U_(0x1) /**< \brief (AST_IDR) Disable interrupt */ 301 #define AST_IDR_ALARM1_0 (AST_IDR_ALARM1_0_Val << AST_IDR_ALARM1_Pos) 302 #define AST_IDR_ALARM1_1 (AST_IDR_ALARM1_1_Val << AST_IDR_ALARM1_Pos) 303 #define AST_IDR_PER0_Pos 16 /**< \brief (AST_IDR) Periodic 0 */ 304 #define AST_IDR_PER0 (_U_(0x1) << AST_IDR_PER0_Pos) 305 #define AST_IDR_PER0_0_Val _U_(0x0) /**< \brief (AST_IDR) No effet */ 306 #define AST_IDR_PER0_1_Val _U_(0x1) /**< \brief (AST_IDR) Disalbe interrupt */ 307 #define AST_IDR_PER0_0 (AST_IDR_PER0_0_Val << AST_IDR_PER0_Pos) 308 #define AST_IDR_PER0_1 (AST_IDR_PER0_1_Val << AST_IDR_PER0_Pos) 309 #define AST_IDR_PER1_Pos 17 /**< \brief (AST_IDR) Periodic 1 */ 310 #define AST_IDR_PER1 (_U_(0x1) << AST_IDR_PER1_Pos) 311 #define AST_IDR_PER1_0_Val _U_(0x0) /**< \brief (AST_IDR) No effect */ 312 #define AST_IDR_PER1_1_Val _U_(0x1) /**< \brief (AST_IDR) Disable interrupt */ 313 #define AST_IDR_PER1_0 (AST_IDR_PER1_0_Val << AST_IDR_PER1_Pos) 314 #define AST_IDR_PER1_1 (AST_IDR_PER1_1_Val << AST_IDR_PER1_Pos) 315 #define AST_IDR_READY_Pos 25 /**< \brief (AST_IDR) AST Ready */ 316 #define AST_IDR_READY (_U_(0x1) << AST_IDR_READY_Pos) 317 #define AST_IDR_READY_0_Val _U_(0x0) /**< \brief (AST_IDR) No effect */ 318 #define AST_IDR_READY_1_Val _U_(0x1) /**< \brief (AST_IDR) Disable interrupt */ 319 #define AST_IDR_READY_0 (AST_IDR_READY_0_Val << AST_IDR_READY_Pos) 320 #define AST_IDR_READY_1 (AST_IDR_READY_1_Val << AST_IDR_READY_Pos) 321 #define AST_IDR_CLKRDY_Pos 29 /**< \brief (AST_IDR) Clock Ready */ 322 #define AST_IDR_CLKRDY (_U_(0x1) << AST_IDR_CLKRDY_Pos) 323 #define AST_IDR_CLKRDY_0_Val _U_(0x0) /**< \brief (AST_IDR) No effect */ 324 #define AST_IDR_CLKRDY_1_Val _U_(0x1) /**< \brief (AST_IDR) Disable interrupt */ 325 #define AST_IDR_CLKRDY_0 (AST_IDR_CLKRDY_0_Val << AST_IDR_CLKRDY_Pos) 326 #define AST_IDR_CLKRDY_1 (AST_IDR_CLKRDY_1_Val << AST_IDR_CLKRDY_Pos) 327 #define AST_IDR_MASK _U_(0x22030301) /**< \brief (AST_IDR) MASK Register */ 328 329 /* -------- AST_IMR : (AST Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 331 typedef union { 332 struct { 333 uint32_t OVF:1; /*!< bit: 0 Overflow */ 334 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 335 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 336 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 337 uint32_t :6; /*!< bit: 10..15 Reserved */ 338 uint32_t PER0:1; /*!< bit: 16 Periodic 0 */ 339 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 340 uint32_t :7; /*!< bit: 18..24 Reserved */ 341 uint32_t READY:1; /*!< bit: 25 AST Ready */ 342 uint32_t :3; /*!< bit: 26..28 Reserved */ 343 uint32_t CLKRDY:1; /*!< bit: 29 Clock Ready */ 344 uint32_t :2; /*!< bit: 30..31 Reserved */ 345 } bit; /*!< Structure used for bit access */ 346 uint32_t reg; /*!< Type used for register access */ 347 } AST_IMR_Type; 348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define AST_IMR_OFFSET 0x18 /**< \brief (AST_IMR offset) Interrupt Mask Register */ 351 #define AST_IMR_RESETVALUE _U_(0x00000000); /**< \brief (AST_IMR reset_value) Interrupt Mask Register */ 352 353 #define AST_IMR_OVF_Pos 0 /**< \brief (AST_IMR) Overflow */ 354 #define AST_IMR_OVF (_U_(0x1) << AST_IMR_OVF_Pos) 355 #define AST_IMR_OVF_0_Val _U_(0x0) /**< \brief (AST_IMR) Interrupt is disabled */ 356 #define AST_IMR_OVF_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled. */ 357 #define AST_IMR_OVF_0 (AST_IMR_OVF_0_Val << AST_IMR_OVF_Pos) 358 #define AST_IMR_OVF_1 (AST_IMR_OVF_1_Val << AST_IMR_OVF_Pos) 359 #define AST_IMR_ALARM0_Pos 8 /**< \brief (AST_IMR) Alarm 0 */ 360 #define AST_IMR_ALARM0 (_U_(0x1) << AST_IMR_ALARM0_Pos) 361 #define AST_IMR_ALARM0_0_Val _U_(0x0) /**< \brief (AST_IMR) Interupt is disabled */ 362 #define AST_IMR_ALARM0_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled */ 363 #define AST_IMR_ALARM0_0 (AST_IMR_ALARM0_0_Val << AST_IMR_ALARM0_Pos) 364 #define AST_IMR_ALARM0_1 (AST_IMR_ALARM0_1_Val << AST_IMR_ALARM0_Pos) 365 #define AST_IMR_ALARM1_Pos 9 /**< \brief (AST_IMR) Alarm 1 */ 366 #define AST_IMR_ALARM1 (_U_(0x1) << AST_IMR_ALARM1_Pos) 367 #define AST_IMR_ALARM1_0_Val _U_(0x0) /**< \brief (AST_IMR) Interrupt is disabled */ 368 #define AST_IMR_ALARM1_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled */ 369 #define AST_IMR_ALARM1_0 (AST_IMR_ALARM1_0_Val << AST_IMR_ALARM1_Pos) 370 #define AST_IMR_ALARM1_1 (AST_IMR_ALARM1_1_Val << AST_IMR_ALARM1_Pos) 371 #define AST_IMR_PER0_Pos 16 /**< \brief (AST_IMR) Periodic 0 */ 372 #define AST_IMR_PER0 (_U_(0x1) << AST_IMR_PER0_Pos) 373 #define AST_IMR_PER0_0_Val _U_(0x0) /**< \brief (AST_IMR) Interrupt is disabled */ 374 #define AST_IMR_PER0_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled */ 375 #define AST_IMR_PER0_0 (AST_IMR_PER0_0_Val << AST_IMR_PER0_Pos) 376 #define AST_IMR_PER0_1 (AST_IMR_PER0_1_Val << AST_IMR_PER0_Pos) 377 #define AST_IMR_PER1_Pos 17 /**< \brief (AST_IMR) Periodic 1 */ 378 #define AST_IMR_PER1 (_U_(0x1) << AST_IMR_PER1_Pos) 379 #define AST_IMR_PER1_0_Val _U_(0x0) /**< \brief (AST_IMR) Interrupt is disabled */ 380 #define AST_IMR_PER1_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled */ 381 #define AST_IMR_PER1_0 (AST_IMR_PER1_0_Val << AST_IMR_PER1_Pos) 382 #define AST_IMR_PER1_1 (AST_IMR_PER1_1_Val << AST_IMR_PER1_Pos) 383 #define AST_IMR_READY_Pos 25 /**< \brief (AST_IMR) AST Ready */ 384 #define AST_IMR_READY (_U_(0x1) << AST_IMR_READY_Pos) 385 #define AST_IMR_READY_0_Val _U_(0x0) /**< \brief (AST_IMR) Interrupt is disabled */ 386 #define AST_IMR_READY_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled */ 387 #define AST_IMR_READY_0 (AST_IMR_READY_0_Val << AST_IMR_READY_Pos) 388 #define AST_IMR_READY_1 (AST_IMR_READY_1_Val << AST_IMR_READY_Pos) 389 #define AST_IMR_CLKRDY_Pos 29 /**< \brief (AST_IMR) Clock Ready */ 390 #define AST_IMR_CLKRDY (_U_(0x1) << AST_IMR_CLKRDY_Pos) 391 #define AST_IMR_CLKRDY_0_Val _U_(0x0) /**< \brief (AST_IMR) Interrupt is disabled */ 392 #define AST_IMR_CLKRDY_1_Val _U_(0x1) /**< \brief (AST_IMR) Interrupt is enabled */ 393 #define AST_IMR_CLKRDY_0 (AST_IMR_CLKRDY_0_Val << AST_IMR_CLKRDY_Pos) 394 #define AST_IMR_CLKRDY_1 (AST_IMR_CLKRDY_1_Val << AST_IMR_CLKRDY_Pos) 395 #define AST_IMR_MASK _U_(0x22030301) /**< \brief (AST_IMR) MASK Register */ 396 397 /* -------- AST_WER : (AST Offset: 0x1C) (R/W 32) Wake Enable Register -------- */ 398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 399 typedef union { 400 struct { 401 uint32_t OVF:1; /*!< bit: 0 Overflow */ 402 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 403 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 404 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 405 uint32_t :6; /*!< bit: 10..15 Reserved */ 406 uint32_t PER0:1; /*!< bit: 16 Periodic 0 */ 407 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 408 uint32_t :14; /*!< bit: 18..31 Reserved */ 409 } bit; /*!< Structure used for bit access */ 410 uint32_t reg; /*!< Type used for register access */ 411 } AST_WER_Type; 412 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 413 414 #define AST_WER_OFFSET 0x1C /**< \brief (AST_WER offset) Wake Enable Register */ 415 #define AST_WER_RESETVALUE _U_(0x00000000); /**< \brief (AST_WER reset_value) Wake Enable Register */ 416 417 #define AST_WER_OVF_Pos 0 /**< \brief (AST_WER) Overflow */ 418 #define AST_WER_OVF (_U_(0x1) << AST_WER_OVF_Pos) 419 #define AST_WER_OVF_0_Val _U_(0x0) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */ 420 #define AST_WER_OVF_1_Val _U_(0x1) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */ 421 #define AST_WER_OVF_0 (AST_WER_OVF_0_Val << AST_WER_OVF_Pos) 422 #define AST_WER_OVF_1 (AST_WER_OVF_1_Val << AST_WER_OVF_Pos) 423 #define AST_WER_ALARM0_Pos 8 /**< \brief (AST_WER) Alarm 0 */ 424 #define AST_WER_ALARM0 (_U_(0x1) << AST_WER_ALARM0_Pos) 425 #define AST_WER_ALARM0_0_Val _U_(0x0) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */ 426 #define AST_WER_ALARM0_1_Val _U_(0x1) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */ 427 #define AST_WER_ALARM0_0 (AST_WER_ALARM0_0_Val << AST_WER_ALARM0_Pos) 428 #define AST_WER_ALARM0_1 (AST_WER_ALARM0_1_Val << AST_WER_ALARM0_Pos) 429 #define AST_WER_ALARM1_Pos 9 /**< \brief (AST_WER) Alarm 1 */ 430 #define AST_WER_ALARM1 (_U_(0x1) << AST_WER_ALARM1_Pos) 431 #define AST_WER_ALARM1_0_Val _U_(0x0) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */ 432 #define AST_WER_ALARM1_1_Val _U_(0x1) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */ 433 #define AST_WER_ALARM1_0 (AST_WER_ALARM1_0_Val << AST_WER_ALARM1_Pos) 434 #define AST_WER_ALARM1_1 (AST_WER_ALARM1_1_Val << AST_WER_ALARM1_Pos) 435 #define AST_WER_PER0_Pos 16 /**< \brief (AST_WER) Periodic 0 */ 436 #define AST_WER_PER0 (_U_(0x1) << AST_WER_PER0_Pos) 437 #define AST_WER_PER0_0_Val _U_(0x0) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */ 438 #define AST_WER_PER0_1_Val _U_(0x1) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */ 439 #define AST_WER_PER0_0 (AST_WER_PER0_0_Val << AST_WER_PER0_Pos) 440 #define AST_WER_PER0_1 (AST_WER_PER0_1_Val << AST_WER_PER0_Pos) 441 #define AST_WER_PER1_Pos 17 /**< \brief (AST_WER) Periodic 1 */ 442 #define AST_WER_PER1 (_U_(0x1) << AST_WER_PER1_Pos) 443 #define AST_WER_PER1_0_Val _U_(0x0) /**< \brief (AST_WER) The corresponing event will not wake up the CPU from sleep mode */ 444 #define AST_WER_PER1_1_Val _U_(0x1) /**< \brief (AST_WER) The corresponding event will wake up the CPU from sleep mode */ 445 #define AST_WER_PER1_0 (AST_WER_PER1_0_Val << AST_WER_PER1_Pos) 446 #define AST_WER_PER1_1 (AST_WER_PER1_1_Val << AST_WER_PER1_Pos) 447 #define AST_WER_MASK _U_(0x00030301) /**< \brief (AST_WER) MASK Register */ 448 449 /* -------- AST_AR0 : (AST Offset: 0x20) (R/W 32) Alarm Register 0 -------- */ 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 451 typedef union { 452 struct { 453 uint32_t VALUE:32; /*!< bit: 0..31 Alarm Value */ 454 } bit; /*!< Structure used for bit access */ 455 uint32_t reg; /*!< Type used for register access */ 456 } AST_AR0_Type; 457 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 458 459 #define AST_AR0_OFFSET 0x20 /**< \brief (AST_AR0 offset) Alarm Register 0 */ 460 #define AST_AR0_RESETVALUE _U_(0x00000000); /**< \brief (AST_AR0 reset_value) Alarm Register 0 */ 461 462 #define AST_AR0_VALUE_Pos 0 /**< \brief (AST_AR0) Alarm Value */ 463 #define AST_AR0_VALUE_Msk (_U_(0xFFFFFFFF) << AST_AR0_VALUE_Pos) 464 #define AST_AR0_VALUE(value) (AST_AR0_VALUE_Msk & ((value) << AST_AR0_VALUE_Pos)) 465 #define AST_AR0_MASK _U_(0xFFFFFFFF) /**< \brief (AST_AR0) MASK Register */ 466 467 /* -------- AST_AR1 : (AST Offset: 0x24) (R/W 32) Alarm Register 1 -------- */ 468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 469 typedef union { 470 struct { 471 uint32_t VALUE:32; /*!< bit: 0..31 Alarm Value */ 472 } bit; /*!< Structure used for bit access */ 473 uint32_t reg; /*!< Type used for register access */ 474 } AST_AR1_Type; 475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 476 477 #define AST_AR1_OFFSET 0x24 /**< \brief (AST_AR1 offset) Alarm Register 1 */ 478 #define AST_AR1_RESETVALUE _U_(0x00000000); /**< \brief (AST_AR1 reset_value) Alarm Register 1 */ 479 480 #define AST_AR1_VALUE_Pos 0 /**< \brief (AST_AR1) Alarm Value */ 481 #define AST_AR1_VALUE_Msk (_U_(0xFFFFFFFF) << AST_AR1_VALUE_Pos) 482 #define AST_AR1_VALUE(value) (AST_AR1_VALUE_Msk & ((value) << AST_AR1_VALUE_Pos)) 483 #define AST_AR1_MASK _U_(0xFFFFFFFF) /**< \brief (AST_AR1) MASK Register */ 484 485 /* -------- AST_PIR0 : (AST Offset: 0x30) (R/W 32) Periodic Interval Register 0 -------- */ 486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 487 typedef union { 488 struct { 489 uint32_t INSEL:5; /*!< bit: 0.. 4 Interval Select */ 490 uint32_t :27; /*!< bit: 5..31 Reserved */ 491 } bit; /*!< Structure used for bit access */ 492 uint32_t reg; /*!< Type used for register access */ 493 } AST_PIR0_Type; 494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 495 496 #define AST_PIR0_OFFSET 0x30 /**< \brief (AST_PIR0 offset) Periodic Interval Register 0 */ 497 #define AST_PIR0_RESETVALUE _U_(0x00000000); /**< \brief (AST_PIR0 reset_value) Periodic Interval Register 0 */ 498 499 #define AST_PIR0_INSEL_Pos 0 /**< \brief (AST_PIR0) Interval Select */ 500 #define AST_PIR0_INSEL_Msk (_U_(0x1F) << AST_PIR0_INSEL_Pos) 501 #define AST_PIR0_INSEL(value) (AST_PIR0_INSEL_Msk & ((value) << AST_PIR0_INSEL_Pos)) 502 #define AST_PIR0_MASK _U_(0x0000001F) /**< \brief (AST_PIR0) MASK Register */ 503 504 /* -------- AST_PIR1 : (AST Offset: 0x34) (R/W 32) Periodic Interval Register 1 -------- */ 505 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 506 typedef union { 507 struct { 508 uint32_t INSEL:5; /*!< bit: 0.. 4 Interval Select */ 509 uint32_t :27; /*!< bit: 5..31 Reserved */ 510 } bit; /*!< Structure used for bit access */ 511 uint32_t reg; /*!< Type used for register access */ 512 } AST_PIR1_Type; 513 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 514 515 #define AST_PIR1_OFFSET 0x34 /**< \brief (AST_PIR1 offset) Periodic Interval Register 1 */ 516 #define AST_PIR1_RESETVALUE _U_(0x00000000); /**< \brief (AST_PIR1 reset_value) Periodic Interval Register 1 */ 517 518 #define AST_PIR1_INSEL_Pos 0 /**< \brief (AST_PIR1) Interval Select */ 519 #define AST_PIR1_INSEL_Msk (_U_(0x1F) << AST_PIR1_INSEL_Pos) 520 #define AST_PIR1_INSEL(value) (AST_PIR1_INSEL_Msk & ((value) << AST_PIR1_INSEL_Pos)) 521 #define AST_PIR1_MASK _U_(0x0000001F) /**< \brief (AST_PIR1) MASK Register */ 522 523 /* -------- AST_CLOCK : (AST Offset: 0x40) (R/W 32) Clock Control Register -------- */ 524 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 525 typedef union { 526 struct { 527 uint32_t CEN:1; /*!< bit: 0 Clock Enable */ 528 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 529 uint32_t CSSEL:3; /*!< bit: 8..10 Clock Source Selection */ 530 uint32_t :21; /*!< bit: 11..31 Reserved */ 531 } bit; /*!< Structure used for bit access */ 532 uint32_t reg; /*!< Type used for register access */ 533 } AST_CLOCK_Type; 534 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 535 536 #define AST_CLOCK_OFFSET 0x40 /**< \brief (AST_CLOCK offset) Clock Control Register */ 537 #define AST_CLOCK_RESETVALUE _U_(0x00000000); /**< \brief (AST_CLOCK reset_value) Clock Control Register */ 538 539 #define AST_CLOCK_CEN_Pos 0 /**< \brief (AST_CLOCK) Clock Enable */ 540 #define AST_CLOCK_CEN (_U_(0x1) << AST_CLOCK_CEN_Pos) 541 #define AST_CLOCK_CEN_0_Val _U_(0x0) /**< \brief (AST_CLOCK) The clock is disabled */ 542 #define AST_CLOCK_CEN_1_Val _U_(0x1) /**< \brief (AST_CLOCK) The clock is enabled */ 543 #define AST_CLOCK_CEN_0 (AST_CLOCK_CEN_0_Val << AST_CLOCK_CEN_Pos) 544 #define AST_CLOCK_CEN_1 (AST_CLOCK_CEN_1_Val << AST_CLOCK_CEN_Pos) 545 #define AST_CLOCK_CSSEL_Pos 8 /**< \brief (AST_CLOCK) Clock Source Selection */ 546 #define AST_CLOCK_CSSEL_Msk (_U_(0x7) << AST_CLOCK_CSSEL_Pos) 547 #define AST_CLOCK_CSSEL(value) (AST_CLOCK_CSSEL_Msk & ((value) << AST_CLOCK_CSSEL_Pos)) 548 #define AST_CLOCK_CSSEL_SLOWCLOCK_Val _U_(0x0) /**< \brief (AST_CLOCK) Slow clock */ 549 #define AST_CLOCK_CSSEL_32KHZCLK_Val _U_(0x1) /**< \brief (AST_CLOCK) 32 kHz clock */ 550 #define AST_CLOCK_CSSEL_PBCLOCK_Val _U_(0x2) /**< \brief (AST_CLOCK) PB clock */ 551 #define AST_CLOCK_CSSEL_GCLK_Val _U_(0x3) /**< \brief (AST_CLOCK) Generic clock */ 552 #define AST_CLOCK_CSSEL_1KHZCLK_Val _U_(0x4) /**< \brief (AST_CLOCK) 1kHz clock from 32 kHz oscillator */ 553 #define AST_CLOCK_CSSEL_SLOWCLOCK (AST_CLOCK_CSSEL_SLOWCLOCK_Val << AST_CLOCK_CSSEL_Pos) 554 #define AST_CLOCK_CSSEL_32KHZCLK (AST_CLOCK_CSSEL_32KHZCLK_Val << AST_CLOCK_CSSEL_Pos) 555 #define AST_CLOCK_CSSEL_PBCLOCK (AST_CLOCK_CSSEL_PBCLOCK_Val << AST_CLOCK_CSSEL_Pos) 556 #define AST_CLOCK_CSSEL_GCLK (AST_CLOCK_CSSEL_GCLK_Val << AST_CLOCK_CSSEL_Pos) 557 #define AST_CLOCK_CSSEL_1KHZCLK (AST_CLOCK_CSSEL_1KHZCLK_Val << AST_CLOCK_CSSEL_Pos) 558 #define AST_CLOCK_MASK _U_(0x00000701) /**< \brief (AST_CLOCK) MASK Register */ 559 560 /* -------- AST_DTR : (AST Offset: 0x44) (R/W 32) Digital Tuner Register -------- */ 561 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 562 typedef union { 563 struct { 564 uint32_t EXP:5; /*!< bit: 0.. 4 EXP */ 565 uint32_t ADD:1; /*!< bit: 5 ADD */ 566 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 567 uint32_t VALUE:8; /*!< bit: 8..15 VALUE */ 568 uint32_t :16; /*!< bit: 16..31 Reserved */ 569 } bit; /*!< Structure used for bit access */ 570 uint32_t reg; /*!< Type used for register access */ 571 } AST_DTR_Type; 572 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 573 574 #define AST_DTR_OFFSET 0x44 /**< \brief (AST_DTR offset) Digital Tuner Register */ 575 #define AST_DTR_RESETVALUE _U_(0x00000000); /**< \brief (AST_DTR reset_value) Digital Tuner Register */ 576 577 #define AST_DTR_EXP_Pos 0 /**< \brief (AST_DTR) EXP */ 578 #define AST_DTR_EXP_Msk (_U_(0x1F) << AST_DTR_EXP_Pos) 579 #define AST_DTR_EXP(value) (AST_DTR_EXP_Msk & ((value) << AST_DTR_EXP_Pos)) 580 #define AST_DTR_ADD_Pos 5 /**< \brief (AST_DTR) ADD */ 581 #define AST_DTR_ADD (_U_(0x1) << AST_DTR_ADD_Pos) 582 #define AST_DTR_VALUE_Pos 8 /**< \brief (AST_DTR) VALUE */ 583 #define AST_DTR_VALUE_Msk (_U_(0xFF) << AST_DTR_VALUE_Pos) 584 #define AST_DTR_VALUE(value) (AST_DTR_VALUE_Msk & ((value) << AST_DTR_VALUE_Pos)) 585 #define AST_DTR_MASK _U_(0x0000FF3F) /**< \brief (AST_DTR) MASK Register */ 586 587 /* -------- AST_EVE : (AST Offset: 0x48) ( /W 32) Event Enable Register -------- */ 588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 589 typedef union { 590 struct { 591 uint32_t OVF:1; /*!< bit: 0 Overflow */ 592 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 593 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 594 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 595 uint32_t :6; /*!< bit: 10..15 Reserved */ 596 uint32_t PER0:1; /*!< bit: 16 Perioidc 0 */ 597 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 598 uint32_t :14; /*!< bit: 18..31 Reserved */ 599 } bit; /*!< Structure used for bit access */ 600 uint32_t reg; /*!< Type used for register access */ 601 } AST_EVE_Type; 602 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 603 604 #define AST_EVE_OFFSET 0x48 /**< \brief (AST_EVE offset) Event Enable Register */ 605 #define AST_EVE_RESETVALUE _U_(0x00000000); /**< \brief (AST_EVE reset_value) Event Enable Register */ 606 607 #define AST_EVE_OVF_Pos 0 /**< \brief (AST_EVE) Overflow */ 608 #define AST_EVE_OVF (_U_(0x1) << AST_EVE_OVF_Pos) 609 #define AST_EVE_ALARM0_Pos 8 /**< \brief (AST_EVE) Alarm 0 */ 610 #define AST_EVE_ALARM0 (_U_(0x1) << AST_EVE_ALARM0_Pos) 611 #define AST_EVE_ALARM1_Pos 9 /**< \brief (AST_EVE) Alarm 1 */ 612 #define AST_EVE_ALARM1 (_U_(0x1) << AST_EVE_ALARM1_Pos) 613 #define AST_EVE_PER0_Pos 16 /**< \brief (AST_EVE) Perioidc 0 */ 614 #define AST_EVE_PER0 (_U_(0x1) << AST_EVE_PER0_Pos) 615 #define AST_EVE_PER1_Pos 17 /**< \brief (AST_EVE) Periodic 1 */ 616 #define AST_EVE_PER1 (_U_(0x1) << AST_EVE_PER1_Pos) 617 #define AST_EVE_MASK _U_(0x00030301) /**< \brief (AST_EVE) MASK Register */ 618 619 /* -------- AST_EVD : (AST Offset: 0x4C) ( /W 32) Event Disable Register -------- */ 620 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 621 typedef union { 622 struct { 623 uint32_t OVF:1; /*!< bit: 0 Overflow */ 624 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 625 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 626 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 627 uint32_t :6; /*!< bit: 10..15 Reserved */ 628 uint32_t PER0:1; /*!< bit: 16 Perioidc 0 */ 629 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 630 uint32_t :14; /*!< bit: 18..31 Reserved */ 631 } bit; /*!< Structure used for bit access */ 632 uint32_t reg; /*!< Type used for register access */ 633 } AST_EVD_Type; 634 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 635 636 #define AST_EVD_OFFSET 0x4C /**< \brief (AST_EVD offset) Event Disable Register */ 637 #define AST_EVD_RESETVALUE _U_(0x00000000); /**< \brief (AST_EVD reset_value) Event Disable Register */ 638 639 #define AST_EVD_OVF_Pos 0 /**< \brief (AST_EVD) Overflow */ 640 #define AST_EVD_OVF (_U_(0x1) << AST_EVD_OVF_Pos) 641 #define AST_EVD_ALARM0_Pos 8 /**< \brief (AST_EVD) Alarm 0 */ 642 #define AST_EVD_ALARM0 (_U_(0x1) << AST_EVD_ALARM0_Pos) 643 #define AST_EVD_ALARM1_Pos 9 /**< \brief (AST_EVD) Alarm 1 */ 644 #define AST_EVD_ALARM1 (_U_(0x1) << AST_EVD_ALARM1_Pos) 645 #define AST_EVD_PER0_Pos 16 /**< \brief (AST_EVD) Perioidc 0 */ 646 #define AST_EVD_PER0 (_U_(0x1) << AST_EVD_PER0_Pos) 647 #define AST_EVD_PER1_Pos 17 /**< \brief (AST_EVD) Periodic 1 */ 648 #define AST_EVD_PER1 (_U_(0x1) << AST_EVD_PER1_Pos) 649 #define AST_EVD_MASK _U_(0x00030301) /**< \brief (AST_EVD) MASK Register */ 650 651 /* -------- AST_EVM : (AST Offset: 0x50) (R/ 32) Event Mask Register -------- */ 652 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 653 typedef union { 654 struct { 655 uint32_t OVF:1; /*!< bit: 0 Overflow */ 656 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 657 uint32_t ALARM0:1; /*!< bit: 8 Alarm 0 */ 658 uint32_t ALARM1:1; /*!< bit: 9 Alarm 1 */ 659 uint32_t :6; /*!< bit: 10..15 Reserved */ 660 uint32_t PER0:1; /*!< bit: 16 Perioidc 0 */ 661 uint32_t PER1:1; /*!< bit: 17 Periodic 1 */ 662 uint32_t :14; /*!< bit: 18..31 Reserved */ 663 } bit; /*!< Structure used for bit access */ 664 uint32_t reg; /*!< Type used for register access */ 665 } AST_EVM_Type; 666 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 667 668 #define AST_EVM_OFFSET 0x50 /**< \brief (AST_EVM offset) Event Mask Register */ 669 #define AST_EVM_RESETVALUE _U_(0x00000000); /**< \brief (AST_EVM reset_value) Event Mask Register */ 670 671 #define AST_EVM_OVF_Pos 0 /**< \brief (AST_EVM) Overflow */ 672 #define AST_EVM_OVF (_U_(0x1) << AST_EVM_OVF_Pos) 673 #define AST_EVM_ALARM0_Pos 8 /**< \brief (AST_EVM) Alarm 0 */ 674 #define AST_EVM_ALARM0 (_U_(0x1) << AST_EVM_ALARM0_Pos) 675 #define AST_EVM_ALARM1_Pos 9 /**< \brief (AST_EVM) Alarm 1 */ 676 #define AST_EVM_ALARM1 (_U_(0x1) << AST_EVM_ALARM1_Pos) 677 #define AST_EVM_PER0_Pos 16 /**< \brief (AST_EVM) Perioidc 0 */ 678 #define AST_EVM_PER0 (_U_(0x1) << AST_EVM_PER0_Pos) 679 #define AST_EVM_PER1_Pos 17 /**< \brief (AST_EVM) Periodic 1 */ 680 #define AST_EVM_PER1 (_U_(0x1) << AST_EVM_PER1_Pos) 681 #define AST_EVM_MASK _U_(0x00030301) /**< \brief (AST_EVM) MASK Register */ 682 683 /* -------- AST_CALV : (AST Offset: 0x54) (R/W 32) Calendar Value -------- */ 684 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 685 typedef union { 686 struct { 687 uint32_t SEC:6; /*!< bit: 0.. 5 Second */ 688 uint32_t MIN:6; /*!< bit: 6..11 Minute */ 689 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 690 uint32_t DAY:5; /*!< bit: 17..21 Day */ 691 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 692 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 693 } bit; /*!< Structure used for bit access */ 694 uint32_t reg; /*!< Type used for register access */ 695 } AST_CALV_Type; 696 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 697 698 #define AST_CALV_OFFSET 0x54 /**< \brief (AST_CALV offset) Calendar Value */ 699 #define AST_CALV_RESETVALUE _U_(0x00000000); /**< \brief (AST_CALV reset_value) Calendar Value */ 700 701 #define AST_CALV_SEC_Pos 0 /**< \brief (AST_CALV) Second */ 702 #define AST_CALV_SEC_Msk (_U_(0x3F) << AST_CALV_SEC_Pos) 703 #define AST_CALV_SEC(value) (AST_CALV_SEC_Msk & ((value) << AST_CALV_SEC_Pos)) 704 #define AST_CALV_MIN_Pos 6 /**< \brief (AST_CALV) Minute */ 705 #define AST_CALV_MIN_Msk (_U_(0x3F) << AST_CALV_MIN_Pos) 706 #define AST_CALV_MIN(value) (AST_CALV_MIN_Msk & ((value) << AST_CALV_MIN_Pos)) 707 #define AST_CALV_HOUR_Pos 12 /**< \brief (AST_CALV) Hour */ 708 #define AST_CALV_HOUR_Msk (_U_(0x1F) << AST_CALV_HOUR_Pos) 709 #define AST_CALV_HOUR(value) (AST_CALV_HOUR_Msk & ((value) << AST_CALV_HOUR_Pos)) 710 #define AST_CALV_DAY_Pos 17 /**< \brief (AST_CALV) Day */ 711 #define AST_CALV_DAY_Msk (_U_(0x1F) << AST_CALV_DAY_Pos) 712 #define AST_CALV_DAY(value) (AST_CALV_DAY_Msk & ((value) << AST_CALV_DAY_Pos)) 713 #define AST_CALV_MONTH_Pos 22 /**< \brief (AST_CALV) Month */ 714 #define AST_CALV_MONTH_Msk (_U_(0xF) << AST_CALV_MONTH_Pos) 715 #define AST_CALV_MONTH(value) (AST_CALV_MONTH_Msk & ((value) << AST_CALV_MONTH_Pos)) 716 #define AST_CALV_YEAR_Pos 26 /**< \brief (AST_CALV) Year */ 717 #define AST_CALV_YEAR_Msk (_U_(0x3F) << AST_CALV_YEAR_Pos) 718 #define AST_CALV_YEAR(value) (AST_CALV_YEAR_Msk & ((value) << AST_CALV_YEAR_Pos)) 719 #define AST_CALV_MASK _U_(0xFFFFFFFF) /**< \brief (AST_CALV) MASK Register */ 720 721 /* -------- AST_PARAMETER : (AST Offset: 0xF0) (R/ 32) Parameter Register -------- */ 722 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 723 typedef union { 724 struct { 725 uint32_t DT:1; /*!< bit: 0 Digital Tuner */ 726 uint32_t DTEXPWA:1; /*!< bit: 1 Digital Tuner Exponent Writeable */ 727 uint32_t DTEXPVALUE:5; /*!< bit: 2.. 6 Digital Tuner Exponent Value */ 728 uint32_t :1; /*!< bit: 7 Reserved */ 729 uint32_t NUMAR:2; /*!< bit: 8.. 9 Number of alarm comparators */ 730 uint32_t :2; /*!< bit: 10..11 Reserved */ 731 uint32_t NUMPIR:1; /*!< bit: 12 Number of periodic comparators */ 732 uint32_t :1; /*!< bit: 13 Reserved */ 733 uint32_t PIR0WA:1; /*!< bit: 14 Periodic Interval 0 Writeable */ 734 uint32_t PIR1WA:1; /*!< bit: 15 Periodic Interval 1 Writeable */ 735 uint32_t PER0VALUE:5; /*!< bit: 16..20 Periodic Interval 0 Value */ 736 uint32_t :3; /*!< bit: 21..23 Reserved */ 737 uint32_t PER1VALUE:5; /*!< bit: 24..28 Periodic Interval 1 Value */ 738 uint32_t :3; /*!< bit: 29..31 Reserved */ 739 } bit; /*!< Structure used for bit access */ 740 uint32_t reg; /*!< Type used for register access */ 741 } AST_PARAMETER_Type; 742 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 743 744 #define AST_PARAMETER_OFFSET 0xF0 /**< \brief (AST_PARAMETER offset) Parameter Register */ 745 746 #define AST_PARAMETER_DT_Pos 0 /**< \brief (AST_PARAMETER) Digital Tuner */ 747 #define AST_PARAMETER_DT (_U_(0x1) << AST_PARAMETER_DT_Pos) 748 #define AST_PARAMETER_DT_OFF_Val _U_(0x0) /**< \brief (AST_PARAMETER) Digital tuner off */ 749 #define AST_PARAMETER_DT_ON_Val _U_(0x1) /**< \brief (AST_PARAMETER) Digital tuner on */ 750 #define AST_PARAMETER_DT_OFF (AST_PARAMETER_DT_OFF_Val << AST_PARAMETER_DT_Pos) 751 #define AST_PARAMETER_DT_ON (AST_PARAMETER_DT_ON_Val << AST_PARAMETER_DT_Pos) 752 #define AST_PARAMETER_DTEXPWA_Pos 1 /**< \brief (AST_PARAMETER) Digital Tuner Exponent Writeable */ 753 #define AST_PARAMETER_DTEXPWA (_U_(0x1) << AST_PARAMETER_DTEXPWA_Pos) 754 #define AST_PARAMETER_DTEXPWA_0_Val _U_(0x0) /**< \brief (AST_PARAMETER) Digital tuner exponent is a constant value. Writes to EXP bitfield in DTR will be discarded. */ 755 #define AST_PARAMETER_DTEXPWA_1_Val _U_(0x1) /**< \brief (AST_PARAMETER) Digital tuner exponent is chosen by writing to EXP bitfield in DTR */ 756 #define AST_PARAMETER_DTEXPWA_0 (AST_PARAMETER_DTEXPWA_0_Val << AST_PARAMETER_DTEXPWA_Pos) 757 #define AST_PARAMETER_DTEXPWA_1 (AST_PARAMETER_DTEXPWA_1_Val << AST_PARAMETER_DTEXPWA_Pos) 758 #define AST_PARAMETER_DTEXPVALUE_Pos 2 /**< \brief (AST_PARAMETER) Digital Tuner Exponent Value */ 759 #define AST_PARAMETER_DTEXPVALUE_Msk (_U_(0x1F) << AST_PARAMETER_DTEXPVALUE_Pos) 760 #define AST_PARAMETER_DTEXPVALUE(value) (AST_PARAMETER_DTEXPVALUE_Msk & ((value) << AST_PARAMETER_DTEXPVALUE_Pos)) 761 #define AST_PARAMETER_NUMAR_Pos 8 /**< \brief (AST_PARAMETER) Number of alarm comparators */ 762 #define AST_PARAMETER_NUMAR_Msk (_U_(0x3) << AST_PARAMETER_NUMAR_Pos) 763 #define AST_PARAMETER_NUMAR(value) (AST_PARAMETER_NUMAR_Msk & ((value) << AST_PARAMETER_NUMAR_Pos)) 764 #define AST_PARAMETER_NUMAR_ZERO_Val _U_(0x0) /**< \brief (AST_PARAMETER) No alarm comparators */ 765 #define AST_PARAMETER_NUMAR_ONE_Val _U_(0x1) /**< \brief (AST_PARAMETER) One alarm comparator */ 766 #define AST_PARAMETER_NUMAR_TWO_Val _U_(0x2) /**< \brief (AST_PARAMETER) Two alarm comparators */ 767 #define AST_PARAMETER_NUMAR_ZERO (AST_PARAMETER_NUMAR_ZERO_Val << AST_PARAMETER_NUMAR_Pos) 768 #define AST_PARAMETER_NUMAR_ONE (AST_PARAMETER_NUMAR_ONE_Val << AST_PARAMETER_NUMAR_Pos) 769 #define AST_PARAMETER_NUMAR_TWO (AST_PARAMETER_NUMAR_TWO_Val << AST_PARAMETER_NUMAR_Pos) 770 #define AST_PARAMETER_NUMPIR_Pos 12 /**< \brief (AST_PARAMETER) Number of periodic comparators */ 771 #define AST_PARAMETER_NUMPIR (_U_(0x1) << AST_PARAMETER_NUMPIR_Pos) 772 #define AST_PARAMETER_NUMPIR_ONE_Val _U_(0x0) /**< \brief (AST_PARAMETER) One periodic comparator */ 773 #define AST_PARAMETER_NUMPIR_TWO_Val _U_(0x1) /**< \brief (AST_PARAMETER) Two periodic comparators */ 774 #define AST_PARAMETER_NUMPIR_ONE (AST_PARAMETER_NUMPIR_ONE_Val << AST_PARAMETER_NUMPIR_Pos) 775 #define AST_PARAMETER_NUMPIR_TWO (AST_PARAMETER_NUMPIR_TWO_Val << AST_PARAMETER_NUMPIR_Pos) 776 #define AST_PARAMETER_PIR0WA_Pos 14 /**< \brief (AST_PARAMETER) Periodic Interval 0 Writeable */ 777 #define AST_PARAMETER_PIR0WA (_U_(0x1) << AST_PARAMETER_PIR0WA_Pos) 778 #define AST_PARAMETER_PIR0WA_0_Val _U_(0x0) /**< \brief (AST_PARAMETER) Periodic alarm prescaler 0 tapping is a constant value. Writes to INSEL bitfield in PIR0 will be discarded. */ 779 #define AST_PARAMETER_PIR0WA_1_Val _U_(0x1) /**< \brief (AST_PARAMETER) Periodic alarm prescaler 0 tapping is chosen by writing to INSEL bitfield in PIR0 */ 780 #define AST_PARAMETER_PIR0WA_0 (AST_PARAMETER_PIR0WA_0_Val << AST_PARAMETER_PIR0WA_Pos) 781 #define AST_PARAMETER_PIR0WA_1 (AST_PARAMETER_PIR0WA_1_Val << AST_PARAMETER_PIR0WA_Pos) 782 #define AST_PARAMETER_PIR1WA_Pos 15 /**< \brief (AST_PARAMETER) Periodic Interval 1 Writeable */ 783 #define AST_PARAMETER_PIR1WA (_U_(0x1) << AST_PARAMETER_PIR1WA_Pos) 784 #define AST_PARAMETER_PIR1WA_0_Val _U_(0x0) /**< \brief (AST_PARAMETER) Writes to PIR1 will be discarded */ 785 #define AST_PARAMETER_PIR1WA_1_Val _U_(0x1) /**< \brief (AST_PARAMETER) PIR1 can be written */ 786 #define AST_PARAMETER_PIR1WA_0 (AST_PARAMETER_PIR1WA_0_Val << AST_PARAMETER_PIR1WA_Pos) 787 #define AST_PARAMETER_PIR1WA_1 (AST_PARAMETER_PIR1WA_1_Val << AST_PARAMETER_PIR1WA_Pos) 788 #define AST_PARAMETER_PER0VALUE_Pos 16 /**< \brief (AST_PARAMETER) Periodic Interval 0 Value */ 789 #define AST_PARAMETER_PER0VALUE_Msk (_U_(0x1F) << AST_PARAMETER_PER0VALUE_Pos) 790 #define AST_PARAMETER_PER0VALUE(value) (AST_PARAMETER_PER0VALUE_Msk & ((value) << AST_PARAMETER_PER0VALUE_Pos)) 791 #define AST_PARAMETER_PER1VALUE_Pos 24 /**< \brief (AST_PARAMETER) Periodic Interval 1 Value */ 792 #define AST_PARAMETER_PER1VALUE_Msk (_U_(0x1F) << AST_PARAMETER_PER1VALUE_Pos) 793 #define AST_PARAMETER_PER1VALUE(value) (AST_PARAMETER_PER1VALUE_Msk & ((value) << AST_PARAMETER_PER1VALUE_Pos)) 794 #define AST_PARAMETER_MASK _U_(0x1F1FD37F) /**< \brief (AST_PARAMETER) MASK Register */ 795 796 /* -------- AST_VERSION : (AST Offset: 0xFC) (R/ 32) Version Register -------- */ 797 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 798 typedef union { 799 struct { 800 uint32_t VERSION:12; /*!< bit: 0..11 Version Number */ 801 uint32_t :4; /*!< bit: 12..15 Reserved */ 802 uint32_t VARIANT:4; /*!< bit: 16..19 Variant Number */ 803 uint32_t :12; /*!< bit: 20..31 Reserved */ 804 } bit; /*!< Structure used for bit access */ 805 uint32_t reg; /*!< Type used for register access */ 806 } AST_VERSION_Type; 807 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 808 809 #define AST_VERSION_OFFSET 0xFC /**< \brief (AST_VERSION offset) Version Register */ 810 #define AST_VERSION_RESETVALUE _U_(0x00000311); /**< \brief (AST_VERSION reset_value) Version Register */ 811 812 #define AST_VERSION_VERSION_Pos 0 /**< \brief (AST_VERSION) Version Number */ 813 #define AST_VERSION_VERSION_Msk (_U_(0xFFF) << AST_VERSION_VERSION_Pos) 814 #define AST_VERSION_VERSION(value) (AST_VERSION_VERSION_Msk & ((value) << AST_VERSION_VERSION_Pos)) 815 #define AST_VERSION_VARIANT_Pos 16 /**< \brief (AST_VERSION) Variant Number */ 816 #define AST_VERSION_VARIANT_Msk (_U_(0xF) << AST_VERSION_VARIANT_Pos) 817 #define AST_VERSION_VARIANT(value) (AST_VERSION_VARIANT_Msk & ((value) << AST_VERSION_VARIANT_Pos)) 818 #define AST_VERSION_MASK _U_(0x000F0FFF) /**< \brief (AST_VERSION) MASK Register */ 819 820 /** \brief AST hardware registers */ 821 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 822 typedef struct { 823 __IO uint32_t CR; /**< \brief Offset: 0x00 (R/W 32) Control Register */ 824 __IO uint32_t CV; /**< \brief Offset: 0x04 (R/W 32) Counter Value */ 825 __I uint32_t SR; /**< \brief Offset: 0x08 (R/ 32) Status Register */ 826 __O uint32_t SCR; /**< \brief Offset: 0x0C ( /W 32) Status Clear Register */ 827 __O uint32_t IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable Register */ 828 __O uint32_t IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable Register */ 829 __I uint32_t IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask Register */ 830 __IO uint32_t WER; /**< \brief Offset: 0x1C (R/W 32) Wake Enable Register */ 831 __IO uint32_t AR0; /**< \brief Offset: 0x20 (R/W 32) Alarm Register 0 */ 832 __IO uint32_t AR1; /**< \brief Offset: 0x24 (R/W 32) Alarm Register 1 */ 833 RoReg8 Reserved1[0x8]; 834 __IO uint32_t PIR0; /**< \brief Offset: 0x30 (R/W 32) Periodic Interval Register 0 */ 835 __IO uint32_t PIR1; /**< \brief Offset: 0x34 (R/W 32) Periodic Interval Register 1 */ 836 RoReg8 Reserved2[0x8]; 837 __IO uint32_t CLOCK; /**< \brief Offset: 0x40 (R/W 32) Clock Control Register */ 838 __IO uint32_t DTR; /**< \brief Offset: 0x44 (R/W 32) Digital Tuner Register */ 839 __O uint32_t EVE; /**< \brief Offset: 0x48 ( /W 32) Event Enable Register */ 840 __O uint32_t EVD; /**< \brief Offset: 0x4C ( /W 32) Event Disable Register */ 841 __I uint32_t EVM; /**< \brief Offset: 0x50 (R/ 32) Event Mask Register */ 842 __IO uint32_t CALV; /**< \brief Offset: 0x54 (R/W 32) Calendar Value */ 843 RoReg8 Reserved3[0x98]; 844 __I uint32_t PARAMETER; /**< \brief Offset: 0xF0 (R/ 32) Parameter Register */ 845 RoReg8 Reserved4[0x8]; 846 __I uint32_t VERSION; /**< \brief Offset: 0xFC (R/ 32) Version Register */ 847 } Ast; 848 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 849 850 /*@}*/ 851 852 #endif /* _SAM4L_AST_COMPONENT_ */ 853
