1 /** 2 * \file 3 * 4 * \brief Instance description for AESA 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_AESA_INSTANCE_ 30 #define _SAM4L_AESA_INSTANCE_ 31 32 /* ========== Register definition for AESA peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_AESA_CTRL (0x400B0000) /**< \brief (AESA) Control Register */ 35 #define REG_AESA_MODE (0x400B0004) /**< \brief (AESA) Mode Register */ 36 #define REG_AESA_DATABUFPTR (0x400B0008) /**< \brief (AESA) Data Buffer Pointer Register */ 37 #define REG_AESA_SR (0x400B000C) /**< \brief (AESA) Status Register */ 38 #define REG_AESA_IER (0x400B0010) /**< \brief (AESA) Interrupt Enable Register */ 39 #define REG_AESA_IDR (0x400B0014) /**< \brief (AESA) Interrupt Disable Register */ 40 #define REG_AESA_IMR (0x400B0018) /**< \brief (AESA) Interrupt Mask Register */ 41 #define REG_AESA_KEY0 (0x400B0020) /**< \brief (AESA) Key Register 0 */ 42 #define REG_AESA_KEY1 (0x400B0024) /**< \brief (AESA) Key Register 1 */ 43 #define REG_AESA_KEY2 (0x400B0028) /**< \brief (AESA) Key Register 2 */ 44 #define REG_AESA_KEY3 (0x400B002C) /**< \brief (AESA) Key Register 3 */ 45 #define REG_AESA_KEY4 (0x400B0030) /**< \brief (AESA) Key Register 4 */ 46 #define REG_AESA_KEY5 (0x400B0034) /**< \brief (AESA) Key Register 5 */ 47 #define REG_AESA_KEY6 (0x400B0038) /**< \brief (AESA) Key Register 6 */ 48 #define REG_AESA_KEY7 (0x400B003C) /**< \brief (AESA) Key Register 7 */ 49 #define REG_AESA_INITVECT0 (0x400B0040) /**< \brief (AESA) Initialization Vector Register 0 */ 50 #define REG_AESA_INITVECT1 (0x400B0044) /**< \brief (AESA) Initialization Vector Register 1 */ 51 #define REG_AESA_INITVECT2 (0x400B0048) /**< \brief (AESA) Initialization Vector Register 2 */ 52 #define REG_AESA_INITVECT3 (0x400B004C) /**< \brief (AESA) Initialization Vector Register 3 */ 53 #define REG_AESA_IDATA (0x400B0050) /**< \brief (AESA) Input Data Register */ 54 #define REG_AESA_ODATA (0x400B0060) /**< \brief (AESA) Output Data Register */ 55 #define REG_AESA_DRNGSEED (0x400B0070) /**< \brief (AESA) DRNG Seed Register */ 56 #define REG_AESA_PARAMETER (0x400B00F8) /**< \brief (AESA) Parameter Register */ 57 #define REG_AESA_VERSION (0x400B00FC) /**< \brief (AESA) Version Register */ 58 #else 59 #define REG_AESA_CTRL (*(RwReg *)0x400B0000UL) /**< \brief (AESA) Control Register */ 60 #define REG_AESA_MODE (*(RwReg *)0x400B0004UL) /**< \brief (AESA) Mode Register */ 61 #define REG_AESA_DATABUFPTR (*(RwReg *)0x400B0008UL) /**< \brief (AESA) Data Buffer Pointer Register */ 62 #define REG_AESA_SR (*(RoReg *)0x400B000CUL) /**< \brief (AESA) Status Register */ 63 #define REG_AESA_IER (*(WoReg *)0x400B0010UL) /**< \brief (AESA) Interrupt Enable Register */ 64 #define REG_AESA_IDR (*(WoReg *)0x400B0014UL) /**< \brief (AESA) Interrupt Disable Register */ 65 #define REG_AESA_IMR (*(RoReg *)0x400B0018UL) /**< \brief (AESA) Interrupt Mask Register */ 66 #define REG_AESA_KEY0 (*(WoReg *)0x400B0020UL) /**< \brief (AESA) Key Register 0 */ 67 #define REG_AESA_KEY1 (*(WoReg *)0x400B0024UL) /**< \brief (AESA) Key Register 1 */ 68 #define REG_AESA_KEY2 (*(WoReg *)0x400B0028UL) /**< \brief (AESA) Key Register 2 */ 69 #define REG_AESA_KEY3 (*(WoReg *)0x400B002CUL) /**< \brief (AESA) Key Register 3 */ 70 #define REG_AESA_KEY4 (*(WoReg *)0x400B0030UL) /**< \brief (AESA) Key Register 4 */ 71 #define REG_AESA_KEY5 (*(WoReg *)0x400B0034UL) /**< \brief (AESA) Key Register 5 */ 72 #define REG_AESA_KEY6 (*(WoReg *)0x400B0038UL) /**< \brief (AESA) Key Register 6 */ 73 #define REG_AESA_KEY7 (*(WoReg *)0x400B003CUL) /**< \brief (AESA) Key Register 7 */ 74 #define REG_AESA_INITVECT0 (*(WoReg *)0x400B0040UL) /**< \brief (AESA) Initialization Vector Register 0 */ 75 #define REG_AESA_INITVECT1 (*(WoReg *)0x400B0044UL) /**< \brief (AESA) Initialization Vector Register 1 */ 76 #define REG_AESA_INITVECT2 (*(WoReg *)0x400B0048UL) /**< \brief (AESA) Initialization Vector Register 2 */ 77 #define REG_AESA_INITVECT3 (*(WoReg *)0x400B004CUL) /**< \brief (AESA) Initialization Vector Register 3 */ 78 #define REG_AESA_IDATA (*(WoReg *)0x400B0050UL) /**< \brief (AESA) Input Data Register */ 79 #define REG_AESA_ODATA (*(RoReg *)0x400B0060UL) /**< \brief (AESA) Output Data Register */ 80 #define REG_AESA_DRNGSEED (*(WoReg *)0x400B0070UL) /**< \brief (AESA) DRNG Seed Register */ 81 #define REG_AESA_PARAMETER (*(RoReg *)0x400B00F8UL) /**< \brief (AESA) Parameter Register */ 82 #define REG_AESA_VERSION (*(RoReg *)0x400B00FCUL) /**< \brief (AESA) Version Register */ 83 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 /* ========== Instance parameters for AESA peripheral ========== */ 86 #define AESA_DMAC_ID_RX 87 #define AESA_DMAC_ID_TX 88 #define AESA_GCLK_NUM 4 89 #define AESA_PDCA_ID_RX 17 90 #define AESA_PDCA_ID_TX 36 91 92 #endif /* _SAM4L_AESA_INSTANCE_ */ 93
