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Searched refs:psConfig (Results 1 – 25 of 67) sorted by relevance

123

/hal_ambiq-latest/mcu/apollo4p/hal/
Dam_hal_wdt.c68 am_hal_wdt_config_t *psConfig = pvConfig; in am_hal_wdt_config() local
81 ui32ConfigValue |= _VAL2FLD(WDT_CFG_CLKSEL, psConfig->eClockSource); in am_hal_wdt_config()
82 ui32ConfigValue |= _VAL2FLD(WDT_CFG_INTVAL, psConfig->ui32InterruptValue); in am_hal_wdt_config()
83 ui32ConfigValue |= _VAL2FLD(WDT_CFG_RESVAL, psConfig->ui32ResetValue); in am_hal_wdt_config()
85 if (psConfig->bAlertOnDSPReset) in am_hal_wdt_config()
90 if (psConfig->bResetEnable) in am_hal_wdt_config()
95 if (psConfig->bInterruptEnable) in am_hal_wdt_config()
108 RSTGEN->CFG_b.WDREN = psConfig->bResetEnable; in am_hal_wdt_config()
130 am_hal_wdt_config_dsp_t *psConfig = pvConfig; in dsp_wdt_config() local
138 ui32ConfigValue |= _FLD2VAL(WDT_DSP0CFG_DSP0PMRESVAL, psConfig->ui32PMResetValue); in dsp_wdt_config()
[all …]
Dam_hal_pwrctrl.c1002 am_hal_pwrctrl_mcu_memory_config(am_hal_pwrctrl_mcu_memory_config_t *psConfig) in am_hal_pwrctrl_mcu_memory_config() argument
1009 switch ( psConfig->eCacheCfg ) in am_hal_pwrctrl_mcu_memory_config()
1028 PWRCTRL->MEMPWREN_b.PWRENDTCM = psConfig->eDTCMCfg; in am_hal_pwrctrl_mcu_memory_config()
1033 PWRCTRL->MEMPWREN_b.PWRENNVM0 = psConfig->bEnableNVM0; in am_hal_pwrctrl_mcu_memory_config()
1069 if (psConfig->bRetainCache) in am_hal_pwrctrl_mcu_memory_config()
1081 if (psConfig->bRetainNVM0) in am_hal_pwrctrl_mcu_memory_config()
1093 switch ( psConfig->eRetainDTCM ) in am_hal_pwrctrl_mcu_memory_config()
1120 am_hal_pwrctrl_mcu_memory_config_get(am_hal_pwrctrl_mcu_memory_config_t *psConfig) in am_hal_pwrctrl_mcu_memory_config_get() argument
1129 psConfig->eCacheCfg = AM_HAL_PWRCTRL_CACHE_ALL; in am_hal_pwrctrl_mcu_memory_config_get()
1133 psConfig->eCacheCfg = AM_HAL_PWRCTRL_CACHEB0_ONLY; in am_hal_pwrctrl_mcu_memory_config_get()
[all …]
Dam_hal_pdm.c300 am_hal_pdm_configure(void *pHandle, am_hal_pdm_config_t *psConfig) in am_hal_pdm_configure() argument
313 PDMn(ui32Module)->CORECFG0_b.LRSWAP = psConfig->bLRSwap; in am_hal_pdm_configure()
314 PDMn(ui32Module)->CORECFG0_b.SOFTMUTE = psConfig->bSoftMute; in am_hal_pdm_configure()
316 PDMn(ui32Module)->CORECFG0_b.SCYCLES = psConfig->ui32GainChangeDelay; in am_hal_pdm_configure()
318 PDMn(ui32Module)->CORECFG0_b.HPGAIN = psConfig->ui32HighPassCutoff; in am_hal_pdm_configure()
319 PDMn(ui32Module)->CORECFG0_b.ADCHPD = psConfig->bHighPassEnable; in am_hal_pdm_configure()
321 PDMn(ui32Module)->CORECFG0_b.MCLKDIV = psConfig->ePDMAClkOutDivder; in am_hal_pdm_configure()
322 PDMn(ui32Module)->CORECFG0_b.SINCRATE = psConfig->ui32DecimationRate; in am_hal_pdm_configure()
324 PDMn(ui32Module)->CORECFG0_b.PGAL = psConfig->eLeftGain; in am_hal_pdm_configure()
325 PDMn(ui32Module)->CORECFG0_b.PGAR = psConfig->eRightGain; in am_hal_pdm_configure()
[all …]
Dam_hal_i2s.c250 am_hal_i2s_configure(void *pHandle, am_hal_i2s_config_t *psConfig) in am_hal_i2s_configure() argument
262 if ((pHandle == NULL) || (psConfig == NULL) || (pState->ui32Module >= AM_REG_I2S_NUM_MODULES)) in am_hal_i2s_configure()
277 am_hal_i2s_data_format_t* pI2SData = psConfig->eData; in am_hal_i2s_configure()
278 am_hal_i2s_io_signal_t* pI2SIOCfg = psConfig->eIO; in am_hal_i2s_configure()
316 …uint32_t ui32OEN = (psConfig->eXfer == AM_HAL_I2S_XFER_TX || psConfig->eXfer == AM_HAL_I2S_XFER_RX… in am_hal_i2s_configure()
333 _VAL2FLD(I2S0_I2SIOCFG_MSL, psConfig->eMode) | in am_hal_i2s_configure()
352 if ( psConfig->eMode == AM_HAL_I2S_IO_MODE_MASTER ) in am_hal_i2s_configure()
358 if ( psConfig->eASRC ) in am_hal_i2s_configure()
370 uint32_t clk_sel = psConfig->eClock; in am_hal_i2s_configure()
371 I2Sn(ui32Module)->CLKCFG_b.DIV3 = psConfig->eDiv3; in am_hal_i2s_configure()
[all …]
Dam_hal_pwrctrl.h560 extern uint32_t am_hal_pwrctrl_mcu_memory_config(am_hal_pwrctrl_mcu_memory_config_t *psConfig);
573 extern uint32_t am_hal_pwrctrl_mcu_memory_config_get(am_hal_pwrctrl_mcu_memory_config_t *psConfig);
587 extern uint32_t am_hal_pwrctrl_sram_config(am_hal_pwrctrl_sram_memcfg_t *psConfig);
600 extern uint32_t am_hal_pwrctrl_sram_config_get(am_hal_pwrctrl_sram_memcfg_t *psConfig);
631 am_hal_pwrctrl_dsp_memory_config_t *psConfig);
648 am_hal_pwrctrl_dsp_memory_config_t *psConfig);
Dam_hal_i2s.h504 extern uint32_t am_hal_i2s_configure(void *pHandle, am_hal_i2s_config_t *psConfig);
544 …t am_hal_i2s_interrupt_service(void *pHandle, uint32_t ui32IntMask, am_hal_i2s_config_t* psConfig);
631 extern uint32_t am_hal_i2s_dma_configure(void *pHandle, am_hal_i2s_config_t* psConfig, am_hal_i2s_t…
660 extern uint32_t am_hal_i2s_dma_transfer_continue(void *pHandle, am_hal_i2s_config_t* psConfig, am_h…
/hal_ambiq-latest/mcu/apollo4p/hal/mcu/
Dam_hal_cachectrl.c156 am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig) in am_hal_cachectrl_config() argument
177 _VAL2FLD(CPU_CACHECFG_LRU, psConfig->bLRU) | in am_hal_cachectrl_config()
178 _VAL2FLD(CPU_CACHECFG_CONFIG, psConfig->eDescript) | in am_hal_cachectrl_config()
179 ((psConfig->eMode << CPU_CACHECFG_IENABLE_Pos) & in am_hal_cachectrl_config()
362 am_hal_daxi_config(const am_hal_daxi_config_t *psConfig) in am_hal_daxi_config() argument
366 if (psConfig) in am_hal_daxi_config()
369 _VAL2FLD(CPU_DAXICFG_FLUSHLEVEL, psConfig->eNumFreeBuf) | in am_hal_daxi_config()
370 _VAL2FLD(CPU_DAXICFG_AGINGSENABLE, psConfig->bAgingSEnabled) | in am_hal_daxi_config()
372 _VAL2FLD(CPU_DAXICFG_BUFFERENABLE, psConfig->eNumBuf) | in am_hal_daxi_config()
373 _VAL2FLD(CPU_DAXICFG_AGINGCOUNTER, psConfig->eAgingCounter) | in am_hal_daxi_config()
[all …]
Dam_hal_mpu.c94 am_hal_mpu_region_configure(tMPURegion *psConfig, bool bEnableNow) in am_hal_mpu_region_configure() argument
99 …if (psConfig->ui8RegionNumber > _FLD2VAL( MPU_RBAR_REGION , 0xFFFFFFFF ) ) //(MPU_RBAR_REGION_Msk … in am_hal_mpu_region_configure()
103 …if (psConfig->eAccessPermission > _FLD2VAL( MPU_RASR_AP, 0xFFFFFFFF)) // (MPU_RASR_AP_Msk >> MPU_R… in am_hal_mpu_region_configure()
107 …if (psConfig->ui16SubRegionDisable > _FLD2VAL(MPU_RASR_SRD, 0xFFFFFFFF)) // (MPU_RASR_SRD_Msk >> M… in am_hal_mpu_region_configure()
111 …if (psConfig->ui8Size > _FLD2VAL(MPU_RASR_SIZE, 0xFFFFFFFF)) // (MPU_RASR_SIZE_Msk >> MPU_RASR_SIZ… in am_hal_mpu_region_configure()
121 MPU->RBAR = (psConfig->ui32BaseAddress & MPU_RBAR_ADDR_Msk) | in am_hal_mpu_region_configure()
122 _VAL2FLD(MPU_RBAR_REGION, psConfig->ui8RegionNumber ) | in am_hal_mpu_region_configure()
128 MPU->RASR = _VAL2FLD(MPU_RASR_XN, (uint32_t) psConfig->bExecuteNever ) | in am_hal_mpu_region_configure()
129 _VAL2FLD(MPU_RASR_AP, psConfig->eAccessPermission) | in am_hal_mpu_region_configure()
130 _VAL2FLD(MPU_RASR_SRD, psConfig->ui16SubRegionDisable) | in am_hal_mpu_region_configure()
[all …]
Dam_hal_ios.c341 uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig) in am_hal_ios_configure() argument
356 if ( (psConfig == NULL) || in am_hal_ios_configure()
373 pIOSState->pui8FIFOBase = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32FIFOBase); in am_hal_ios_configure()
374 pIOSState->pui8FIFOEnd = (uint8_t *)(REG_IOSLAVE_BASEADDR + psConfig->ui32RAMBase); in am_hal_ios_configure()
376 pIOSState->ui32FifoBaseOffset = psConfig->ui32FIFOBase; in am_hal_ios_configure()
383 … if ( psConfig->ui32SRAMBufferCap > (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1) ) in am_hal_ios_configure()
385 psConfig->ui32SRAMBufferCap = (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1); in am_hal_ios_configure()
387 am_hal_ios_buffer_init(&g_sSRAMBuffer, psConfig->pui8SRAMBuffer, psConfig->ui32SRAMBufferCap); in am_hal_ios_configure()
392 ui32LRAMConfig = _VAL2FLD(IOSLAVE_FIFOCFG_ROBASE, psConfig->ui32ROBase >> 3); in am_hal_ios_configure()
393 ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOBASE, psConfig->ui32FIFOBase >> 3); in am_hal_ios_configure()
[all …]
Dam_hal_cachectrl.h284 extern uint32_t am_hal_cachectrl_config(const am_hal_cachectrl_config_t *psConfig);
357 extern uint32_t am_hal_daxi_config(const am_hal_daxi_config_t *psConfig);
386 extern uint32_t am_hal_daxi_config_get(am_hal_daxi_config_t *psConfig);
/hal_ambiq-latest/mcu/apollo3p/hal/
Dam_hal_tpiu.c194 am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig) in am_hal_tpiu_configure() argument
199 MCUCTRL->TPIUCTRL |= psConfig->ui32TraceClkIn; in am_hal_tpiu_configure()
204 TPI->SPPR = psConfig->ui32PinProtocol; in am_hal_tpiu_configure()
210 TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); in am_hal_tpiu_configure()
215 TPI->ACPR = psConfig->ui32ClockPrescaler; in am_hal_tpiu_configure()
240 am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) in am_hal_tpiu_enable() argument
245 ui32ITMbitrate = psConfig->ui32SetItmBaud; in am_hal_tpiu_enable()
320 TPI->ACPR = psConfig->ui32ClockPrescaler; in am_hal_tpiu_enable()
326 TPI->SPPR = psConfig->ui32PinProtocol; in am_hal_tpiu_enable()
333 TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); in am_hal_tpiu_enable()
[all …]
Dam_hal_pdm.c331 am_hal_pdm_configure(void *pHandle, const am_hal_pdm_config_t *psConfig) in am_hal_pdm_configure() argument
347 ui32Temp |= _VAL2FLD(PDM_PCFG_SOFTMUTE, psConfig->bSoftMute) in am_hal_pdm_configure()
348 | _VAL2FLD( PDM_PCFG_CYCLES, psConfig->ui32GainChangeDelay) in am_hal_pdm_configure()
349 | _VAL2FLD( PDM_PCFG_HPCUTOFF, psConfig->ui32HighPassCutoff) in am_hal_pdm_configure()
350 | _VAL2FLD( PDM_PCFG_ADCHPD, psConfig->bHighPassEnable) in am_hal_pdm_configure()
351 | _VAL2FLD( PDM_PCFG_SINCRATE, psConfig->ui32DecimationRate) in am_hal_pdm_configure()
352 | _VAL2FLD( PDM_PCFG_MCLKDIV, psConfig->eClkDivider) in am_hal_pdm_configure()
353 | _VAL2FLD( PDM_PCFG_PGALEFT, psConfig->eLeftGain) in am_hal_pdm_configure()
354 | _VAL2FLD( PDM_PCFG_PGARIGHT, psConfig->eRightGain) in am_hal_pdm_configure()
355 | _VAL2FLD( PDM_PCFG_LRSWAP, psConfig->bLRSwap); in am_hal_pdm_configure()
[all …]
Dam_hal_wdt.c85 am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) in am_hal_wdt_init() argument
89 bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; in am_hal_wdt_init()
90 bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; in am_hal_wdt_init()
95 ui16IntCount = psConfig->ui16InterruptCount; in am_hal_wdt_init()
96 ui16ResetCount = psConfig->ui16ResetCount; in am_hal_wdt_init()
102 ui32ConfigVal = psConfig->ui32Config & ~(WDT_CFG_INTVAL_Msk | WDT_CFG_RESVAL_Msk); in am_hal_wdt_init()
150 if ( !(psConfig->ui32Config & WDT_CFG_CLKSEL_Msk) ) in am_hal_wdt_init()
Dam_hal_ios.c336 uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig) in am_hal_ios_configure() argument
351 if ( (psConfig == NULL) || in am_hal_ios_configure()
368 pIOSState->pui8FIFOBase = (uint8_t *)(IOSLAVE_BASE + psConfig->ui32FIFOBase); in am_hal_ios_configure()
369 pIOSState->pui8FIFOEnd = (uint8_t *)(IOSLAVE_BASE + psConfig->ui32RAMBase); in am_hal_ios_configure()
371 pIOSState->ui32FifoBaseOffset = psConfig->ui32FIFOBase; in am_hal_ios_configure()
378 … if ( psConfig->ui32SRAMBufferCap > (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1) ) in am_hal_ios_configure()
380 psConfig->ui32SRAMBufferCap = (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1); in am_hal_ios_configure()
382 am_hal_ios_buffer_init(&g_sSRAMBuffer, psConfig->pui8SRAMBuffer, psConfig->ui32SRAMBufferCap); in am_hal_ios_configure()
387 ui32LRAMConfig = _VAL2FLD(IOSLAVE_FIFOCFG_ROBASE, psConfig->ui32ROBase >> 3); in am_hal_ios_configure()
388 ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOBASE, psConfig->ui32FIFOBase >> 3); in am_hal_ios_configure()
[all …]
Dam_hal_adc.c332 am_hal_adc_config_t *psConfig) in am_hal_adc_configure() argument
354 ui32Config |= _VAL2FLD(ADC_CFG_CLKSEL, psConfig->eClock); in am_hal_adc_configure()
359 ui32Config |= _VAL2FLD(ADC_CFG_TRIGPOL, psConfig->ePolarity); in am_hal_adc_configure()
364 ui32Config |= _VAL2FLD(ADC_CFG_TRIGSEL, psConfig->eTrigger); in am_hal_adc_configure()
369 ui32Config |= _VAL2FLD(ADC_CFG_REFSEL, psConfig->eReference); in am_hal_adc_configure()
379 ui32Config |= _VAL2FLD(ADC_CFG_CKMODE, psConfig->eClockMode); in am_hal_adc_configure()
384 ui32Config |= _VAL2FLD(ADC_CFG_LPMODE, psConfig->ePowerMode); in am_hal_adc_configure()
389 ui32Config |= _VAL2FLD(ADC_CFG_RPTEN, psConfig->eRepeat); in am_hal_adc_configure()
Dam_hal_uart.c367 am_hal_uart_configure(void *pHandle, const am_hal_uart_config_t *psConfig) in am_hal_uart_configure() argument
426 ui32ErrorStatus = config_baudrate(ui32Module, psConfig->ui32BaudRate, in am_hal_uart_configure()
436 UARTn(ui32Module)->CR |= psConfig->ui32FlowControl; in am_hal_uart_configure()
438 UARTn(ui32Module)->IFLS = psConfig->ui32FifoLevels; in am_hal_uart_configure()
440 UARTn(ui32Module)->LCRH = (psConfig->ui32DataBits | in am_hal_uart_configure()
441 psConfig->ui32Parity | in am_hal_uart_configure()
442 psConfig->ui32StopBits | in am_hal_uart_configure()
460 psConfig->pui8TxBuffer, in am_hal_uart_configure()
461 psConfig->ui32TxBufferSize, in am_hal_uart_configure()
462 psConfig->pui8RxBuffer, in am_hal_uart_configure()
[all …]
Dam_hal_scard.c485 am_hal_scard_configure(void *pHandle, am_hal_scard_config_t *psConfig) in am_hal_scard_configure() argument
513 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_BAUDRATE, &psConfig->ui32Fidi); in am_hal_scard_configure()
519 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PROTOCOL, &psConfig->ui32Protocol); in am_hal_scard_configure()
520 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_CARD_FORMAT, &psConfig->ui32Direction); in am_hal_scard_configure()
521 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PARITY, &psConfig->ui32Parity); in am_hal_scard_configure()
522 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_GUARDTIME, &psConfig->ui32GuardTime); in am_hal_scard_configure()
523 SCARDn(ui32Module)->UCR1_b.CLKIOV = psConfig->ui32ClkLevel; in am_hal_scard_configure()
534 psConfig->pui8TxBuffer, in am_hal_scard_configure()
535 psConfig->ui32TxBufferSize, in am_hal_scard_configure()
536 psConfig->pui8RxBuffer, in am_hal_scard_configure()
[all …]
/hal_ambiq-latest/mcu/apollo3/hal/
Dam_hal_tpiu.c194 am_hal_tpiu_configure(am_hal_tpiu_config_t *psConfig) in am_hal_tpiu_configure() argument
199 MCUCTRL->TPIUCTRL |= psConfig->ui32TraceClkIn; in am_hal_tpiu_configure()
204 TPI->SPPR = psConfig->ui32PinProtocol; in am_hal_tpiu_configure()
210 TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); in am_hal_tpiu_configure()
215 TPI->ACPR = psConfig->ui32ClockPrescaler; in am_hal_tpiu_configure()
240 am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig) in am_hal_tpiu_enable() argument
245 ui32ITMbitrate = psConfig->ui32SetItmBaud; in am_hal_tpiu_enable()
320 TPI->ACPR = psConfig->ui32ClockPrescaler; in am_hal_tpiu_enable()
326 TPI->SPPR = psConfig->ui32PinProtocol; in am_hal_tpiu_enable()
333 TPI->CSPSR = (1 << (psConfig->ui32ParallelPortSize - 1)); in am_hal_tpiu_enable()
[all …]
Dam_hal_pdm.c331 am_hal_pdm_configure(void *pHandle, const am_hal_pdm_config_t *psConfig) in am_hal_pdm_configure() argument
347 ui32Temp |= _VAL2FLD(PDM_PCFG_SOFTMUTE, psConfig->bSoftMute) in am_hal_pdm_configure()
348 | _VAL2FLD( PDM_PCFG_CYCLES, psConfig->ui32GainChangeDelay) in am_hal_pdm_configure()
349 | _VAL2FLD( PDM_PCFG_HPCUTOFF, psConfig->ui32HighPassCutoff) in am_hal_pdm_configure()
350 | _VAL2FLD( PDM_PCFG_ADCHPD, psConfig->bHighPassEnable) in am_hal_pdm_configure()
351 | _VAL2FLD( PDM_PCFG_SINCRATE, psConfig->ui32DecimationRate) in am_hal_pdm_configure()
352 | _VAL2FLD( PDM_PCFG_MCLKDIV, psConfig->eClkDivider) in am_hal_pdm_configure()
353 | _VAL2FLD( PDM_PCFG_PGALEFT, psConfig->eLeftGain) in am_hal_pdm_configure()
354 | _VAL2FLD( PDM_PCFG_PGARIGHT, psConfig->eRightGain) in am_hal_pdm_configure()
355 | _VAL2FLD( PDM_PCFG_LRSWAP, psConfig->bLRSwap); in am_hal_pdm_configure()
[all …]
Dam_hal_wdt.c85 am_hal_wdt_init(const am_hal_wdt_config_t *psConfig) in am_hal_wdt_init() argument
89 bool bResetEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_RESET; in am_hal_wdt_init()
90 bool bInterruptEnabled = psConfig->ui32Config & AM_HAL_WDT_ENABLE_INTERRUPT; in am_hal_wdt_init()
95 ui16IntCount = psConfig->ui16InterruptCount; in am_hal_wdt_init()
96 ui16ResetCount = psConfig->ui16ResetCount; in am_hal_wdt_init()
102 ui32ConfigVal = psConfig->ui32Config & ~(WDT_CFG_INTVAL_Msk | WDT_CFG_RESVAL_Msk); in am_hal_wdt_init()
150 if ( !(psConfig->ui32Config & WDT_CFG_CLKSEL_Msk) ) in am_hal_wdt_init()
Dam_hal_ios.c336 uint32_t am_hal_ios_configure(void *pHandle, am_hal_ios_config_t *psConfig) in am_hal_ios_configure() argument
351 if ( (psConfig == NULL) || in am_hal_ios_configure()
368 pIOSState->pui8FIFOBase = (uint8_t *)(IOSLAVE_BASE + psConfig->ui32FIFOBase); in am_hal_ios_configure()
369 pIOSState->pui8FIFOEnd = (uint8_t *)(IOSLAVE_BASE + psConfig->ui32RAMBase); in am_hal_ios_configure()
371 pIOSState->ui32FifoBaseOffset = psConfig->ui32FIFOBase; in am_hal_ios_configure()
378 … if ( psConfig->ui32SRAMBufferCap > (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1) ) in am_hal_ios_configure()
380 psConfig->ui32SRAMBufferCap = (AM_HAL_IOS_MAX_SW_FIFO_SIZE - pIOSState->ui32HwFifoSize + 1); in am_hal_ios_configure()
382 am_hal_ios_buffer_init(&g_sSRAMBuffer, psConfig->pui8SRAMBuffer, psConfig->ui32SRAMBufferCap); in am_hal_ios_configure()
387 ui32LRAMConfig = _VAL2FLD(IOSLAVE_FIFOCFG_ROBASE, psConfig->ui32ROBase >> 3); in am_hal_ios_configure()
388 ui32LRAMConfig |= _VAL2FLD(IOSLAVE_FIFOCFG_FIFOBASE, psConfig->ui32FIFOBase >> 3); in am_hal_ios_configure()
[all …]
Dam_hal_adc.c332 am_hal_adc_config_t *psConfig) in am_hal_adc_configure() argument
354 ui32Config |= _VAL2FLD(ADC_CFG_CLKSEL, psConfig->eClock); in am_hal_adc_configure()
359 ui32Config |= _VAL2FLD(ADC_CFG_TRIGPOL, psConfig->ePolarity); in am_hal_adc_configure()
364 ui32Config |= _VAL2FLD(ADC_CFG_TRIGSEL, psConfig->eTrigger); in am_hal_adc_configure()
369 ui32Config |= _VAL2FLD(ADC_CFG_REFSEL, psConfig->eReference); in am_hal_adc_configure()
379 ui32Config |= _VAL2FLD(ADC_CFG_CKMODE, psConfig->eClockMode); in am_hal_adc_configure()
384 ui32Config |= _VAL2FLD(ADC_CFG_LPMODE, psConfig->ePowerMode); in am_hal_adc_configure()
389 ui32Config |= _VAL2FLD(ADC_CFG_RPTEN, psConfig->eRepeat); in am_hal_adc_configure()
Dam_hal_ctimer.c529 am_hal_ctimer_config_t *psConfig) in am_hal_ctimer_config() argument
547 ui32ConfigVal = ( (psConfig->ui32TimerAConfig) | in am_hal_ctimer_config()
548 (psConfig->ui32TimerBConfig << 16) ); in am_hal_ctimer_config()
553 ui32ConfigVal |= psConfig->ui32Link ? AM_HAL_CTIMER_LINK : 0; in am_hal_ctimer_config()
578 if ( ( psConfig->ui32TimerAConfig != 0 ) || psConfig->ui32Link ) in am_hal_ctimer_config()
581 ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, psConfig->ui32TimerAConfig); in am_hal_ctimer_config()
583 else if ( psConfig->ui32TimerBConfig != 0) in am_hal_ctimer_config()
586 ui32ClkSrc = _FLD2VAL(CTIMER_CTRL0_TMRA0CLK, psConfig->ui32TimerBConfig); in am_hal_ctimer_config()
Dam_hal_uart.c367 am_hal_uart_configure(void *pHandle, const am_hal_uart_config_t *psConfig) in am_hal_uart_configure() argument
426 ui32ErrorStatus = config_baudrate(ui32Module, psConfig->ui32BaudRate, in am_hal_uart_configure()
436 UARTn(ui32Module)->CR |= psConfig->ui32FlowControl; in am_hal_uart_configure()
438 UARTn(ui32Module)->IFLS = psConfig->ui32FifoLevels; in am_hal_uart_configure()
440 UARTn(ui32Module)->LCRH = (psConfig->ui32DataBits | in am_hal_uart_configure()
441 psConfig->ui32Parity | in am_hal_uart_configure()
442 psConfig->ui32StopBits | in am_hal_uart_configure()
460 psConfig->pui8TxBuffer, in am_hal_uart_configure()
461 psConfig->ui32TxBufferSize, in am_hal_uart_configure()
462 psConfig->pui8RxBuffer, in am_hal_uart_configure()
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Dam_hal_scard.c485 am_hal_scard_configure(void *pHandle, am_hal_scard_config_t *psConfig) in am_hal_scard_configure() argument
513 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_BAUDRATE, &psConfig->ui32Fidi); in am_hal_scard_configure()
519 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PROTOCOL, &psConfig->ui32Protocol); in am_hal_scard_configure()
520 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_CARD_FORMAT, &psConfig->ui32Direction); in am_hal_scard_configure()
521 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_PARITY, &psConfig->ui32Parity); in am_hal_scard_configure()
522 status = am_hal_scard_control(pHandle, AM_HAL_SCARD_REQ_GUARDTIME, &psConfig->ui32GuardTime); in am_hal_scard_configure()
523 SCARDn(ui32Module)->UCR1_b.CLKIOV = psConfig->ui32ClkLevel; in am_hal_scard_configure()
534 psConfig->pui8TxBuffer, in am_hal_scard_configure()
535 psConfig->ui32TxBufferSize, in am_hal_scard_configure()
536 psConfig->pui8RxBuffer, in am_hal_scard_configure()
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