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Searched refs:ePeripheral (Results 1 – 8 of 8) sorted by relevance

/hal_ambiq-latest/mcu/apollo4p/hal/
Dam_hal_access.c185 am_hal_access_periph_e ePeripheral) in am_hal_access_check() argument
189 if (AM_HAL_ACCESS_ALLOWED(psAccess, ePeripheral) && in am_hal_access_check()
190 !AM_HAL_ACCESS_SHARED(psAccess, ePeripheral)) in am_hal_access_check()
194 else if (AM_HAL_ACCESS_ALLOWED(psAccess, ePeripheral) && in am_hal_access_check()
195 AM_HAL_ACCESS_CLAIMED(psAccess, ePeripheral)) in am_hal_access_check()
212 am_hal_access_periph_e ePeripheral, in am_hal_access_get() argument
219 if (am_hal_access_check(psAccess, ePeripheral)) in am_hal_access_get()
227 else if (AM_HAL_ACCESS_ALLOWED(psAccess, ePeripheral)) in am_hal_access_get()
250 if (AM_HAL_ACCESS_AVAILABLE(psAccess, ePeripheral)) in am_hal_access_get()
252 AM_HAL_ACCESS_CLAIM(psAccess, ePeripheral); in am_hal_access_get()
[all …]
Dam_hal_pwrctrl.c483 am_get_pwrctrl(struct am_pwr_s *pwr_ctrl, uint32_t ePeripheral) in am_get_pwrctrl() argument
485 if ( pwr_ctrl == NULL || ePeripheral >= AM_HAL_PWRCTRL_PERIPH_MAX ) in am_get_pwrctrl()
490 *pwr_ctrl = am_hal_pwrctrl_peripheral_control[ePeripheral]; in am_get_pwrctrl()
506 am_get_pwrctrl(struct am_pwr_s *pwr_ctrl, uint32_t ePeripheral) in am_get_pwrctrl() argument
510 if (pwr_ctrl == NULL || ePeripheral >= AM_HAL_PWRCTRL_PERIPH_MAX) in am_get_pwrctrl()
515 if (ePeripheral < AM_HAL_PWRCTRL_PERIPH_AUDREC) in am_get_pwrctrl()
519 pwr_ctrl->ui32PeriphEnable = 1 << ePeripheral; in am_get_pwrctrl()
520 pwr_ctrl->ui32PeriphStatus = 1 << ePeripheral; in am_get_pwrctrl()
524 shift_pos = (ePeripheral - AM_HAL_PWRCTRL_PERIPH_AUDREC); in am_get_pwrctrl()
525 if (ePeripheral > AM_HAL_PWRCTRL_PERIPH_I2S1) in am_get_pwrctrl()
[all …]
Dam_hal_pwrctrl.h662 extern uint32_t am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral);
676 extern uint32_t am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral);
691 extern uint32_t am_hal_pwrctrl_periph_enabled(am_hal_pwrctrl_periph_e ePeripheral,
Dam_hal_access.h232 am_hal_access_periph_e ePeripheral,
250 am_hal_access_periph_e ePeripheral,
/hal_ambiq-latest/mcu/apollo3/hal/
Dam_hal_pwrctrl.c281 am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral) in am_hal_pwrctrl_periph_enable() argument
287 PWRCTRL->DEVPWREN |= am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; in am_hal_pwrctrl_periph_enable()
294 … if ((PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0) in am_hal_pwrctrl_periph_enable()
303 … if ((PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0) in am_hal_pwrctrl_periph_enable()
313 PWRCTRL->DEVPWREN &= ~am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; in am_hal_pwrctrl_periph_enable()
329 pwrctrl_periph_disable_msk_check(am_hal_pwrctrl_periph_e ePeripheral) in pwrctrl_periph_disable_msk_check() argument
334 switch (am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) in pwrctrl_periph_disable_msk_check()
337 …sk & HCPA_MASK) > 0) && ((HCPxMask & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnab… in pwrctrl_periph_disable_msk_check()
344 …sk & HCPB_MASK) > 0) && ((HCPxMask & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnab… in pwrctrl_periph_disable_msk_check()
351 …sk & HCPC_MASK) > 0) && ((HCPxMask & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnab… in pwrctrl_periph_disable_msk_check()
[all …]
Dam_hal_pwrctrl.h139 extern uint32_t am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral);
153 extern uint32_t am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral);
169 am_hal_pwrctrl_periph_e ePeripheral, uint32_t *pui32Enabled);
/hal_ambiq-latest/mcu/apollo3p/hal/
Dam_hal_pwrctrl.c297 am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral) in am_hal_pwrctrl_periph_enable() argument
303 PWRCTRL->DEVPWREN |= am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; in am_hal_pwrctrl_periph_enable()
310 … if ((PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0) in am_hal_pwrctrl_periph_enable()
319 … if ((PWRCTRL->DEVPWRSTATUS & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) > 0) in am_hal_pwrctrl_periph_enable()
329 PWRCTRL->DEVPWREN &= ~am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnable; in am_hal_pwrctrl_periph_enable()
344 pwrctrl_periph_disable_msk_check(am_hal_pwrctrl_periph_e ePeripheral) in pwrctrl_periph_disable_msk_check() argument
349 switch (am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphStatus) in pwrctrl_periph_disable_msk_check()
352 …HCPA_MASK) > 0) && ((HCPxMSPIxMask & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnab… in pwrctrl_periph_disable_msk_check()
359 …HCPB_MASK) > 0) && ((HCPxMSPIxMask & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnab… in pwrctrl_periph_disable_msk_check()
366 …HCPC_MASK) > 0) && ((HCPxMSPIxMask & am_hal_pwrctrl_peripheral_control[ePeripheral].ui32PeriphEnab… in pwrctrl_periph_disable_msk_check()
[all …]
Dam_hal_pwrctrl.h164 extern uint32_t am_hal_pwrctrl_periph_enable(am_hal_pwrctrl_periph_e ePeripheral);
178 extern uint32_t am_hal_pwrctrl_periph_disable(am_hal_pwrctrl_periph_e ePeripheral);
194 am_hal_pwrctrl_periph_e ePeripheral, uint32_t *pui32Enabled);