Home
last modified time | relevance | path

Searched refs:am_hal_ble_plf_reg_read (Results 1 – 5 of 5) sorted by relevance

/hal_ambiq-latest/mcu/apollo3/hal/
Dam_hal_ble.c1466 am_hal_ble_plf_reg_read(pBLE, 0x43000004, &ui32LockValue); in am_hal_ble_trim_set()
1483 am_hal_ble_plf_reg_read(pBLE, ui32BleCoreAddress, &ui32ReadVal); in am_hal_ble_trim_set()
2901 am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_B0, &rc32k_clock); in am_hal_ble_check_32k_clock()
2905 am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_A1, &rc32k_clock); in am_hal_ble_check_32k_clock()
2925 am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value) in am_hal_ble_plf_reg_read() function
3145 am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); in am_hal_ble_transmitter_modex_set()
3151 am_hal_ble_plf_reg_read(pBLE, 0x52000008, &temp); in am_hal_ble_transmitter_modex_set()
3153 am_hal_ble_plf_reg_read(pBLE, 0x52000000, &RegValueSTCR); in am_hal_ble_transmitter_modex_set()
3157 am_hal_ble_plf_reg_read(pBLE, 0x45800070, &RegValueBACKCR); in am_hal_ble_transmitter_modex_set()
3191 am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); in am_hal_ble_sleep_set()
[all …]
Dam_hal_ble.h892 extern uint32_t am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value);
/hal_ambiq-latest/mcu/apollo3p/hal/
Dam_hal_ble.c1360 am_hal_ble_plf_reg_read(pBLE, 0x43000004, &ui32LockValue); in am_hal_ble_trim_set()
1377 am_hal_ble_plf_reg_read(pBLE, ui32BleCoreAddress, &ui32ReadVal); in am_hal_ble_trim_set()
2795 am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_32K_CLOCK_ADDR_B0, &rc32k_clock); in am_hal_ble_check_32k_clock()
2819 am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value) in am_hal_ble_plf_reg_read() function
3039 am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); in am_hal_ble_transmitter_modex_set()
3045 am_hal_ble_plf_reg_read(pBLE, 0x52000008, &temp); in am_hal_ble_transmitter_modex_set()
3047 am_hal_ble_plf_reg_read(pBLE, 0x52000000, &RegValueSTCR); in am_hal_ble_transmitter_modex_set()
3051 am_hal_ble_plf_reg_read(pBLE, 0x45800070, &RegValueBACKCR); in am_hal_ble_transmitter_modex_set()
3086 am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); in am_hal_ble_sleep_set()
3126 am_hal_ble_plf_reg_read(pBLE, AM_HAL_BLE_IP_RAM_SLEEP_ENABLE_ADDR_B0, &sleepenable); in am_hal_ble_sleep_get()
[all …]
Dam_hal_ble.h804 extern uint32_t am_hal_ble_plf_reg_read(void *pHandle, uint32_t ui32Address, uint32_t *pui32Value);
/hal_ambiq-latest/utils/
Dam_util_ble.c250 am_hal_ble_plf_reg_read(pBLE, 0x43000004, &RegValueMCGR); in am_util_ble_crystal_trim_set()
666 am_hal_ble_plf_reg_read(pBLE, 0x20006874, &temp); in am_util_ble_read_modex_value()
670 am_hal_ble_plf_reg_read(pBLE, 0x20006070, &temp); in am_util_ble_read_modex_value()