1 /*
2  * Copyright (c) 2024, Ambiq Micro, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  *
31  * @file     apollo3.h
32  * @brief    CMSIS HeaderFile
33  * @version  1.0
34  * @date     20. May 2024
35  * @note     Generated by SVDConv V3.3.42 on Monday, 20.05.2024 14:22:08
36  *           from File './apollo3.svd',
37  *           last modified on Monday, 20.05.2024 19:22:08
38  */
39 
40 
41 
42 /** @addtogroup Ambiq Micro
43   * @{
44   */
45 
46 
47 /** @addtogroup apollo3
48   * @{
49   */
50 
51 
52 #ifndef APOLLO3_H
53 #define APOLLO3_H
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
59 
60 /** @addtogroup Configuration_of_CMSIS
61   * @{
62   */
63 
64 
65 
66 /* =========================================================================================================================== */
67 /* ================                                Interrupt Number Definition                                ================ */
68 /* =========================================================================================================================== */
69 
70 typedef enum {
71 /* =======================================  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
72   Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
73   NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
74   HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
75   MemoryManagement_IRQn     = -12,              /*!< -12  Memory Management, MPU mismatch, including Access Violation
76                                                      and No Match                                                              */
77   BusFault_IRQn             = -11,              /*!< -11  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
78                                                      related Fault                                                             */
79   UsageFault_IRQn           = -10,              /*!< -10  Usage Fault, i.e. Undef Instruction, Illegal State Transition        */
80   SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
81   DebugMonitor_IRQn         =  -4,              /*!< -4 Debug Monitor                                                          */
82   PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
83   SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
84 /* ==========================================  apollo3 Specific Interrupt Numbers  =========================================== */
85   BROWNOUT_IRQn             =   0,              /*!< 0  BROWNOUT_IRQ                                                           */
86   WDT_IRQn                  =   1,              /*!< 1  WDT_IRQ                                                                */
87   RTC_IRQn                  =   2,              /*!< 2  RTC_IRQ                                                                */
88   VCOMP_IRQn                =   3,              /*!< 3  VCOMP_IRQ                                                              */
89   IOSLAVE_IRQn              =   4,              /*!< 4  IOSLAVE_IRQ                                                            */
90   IOSLAVEACC_IRQn           =   5,              /*!< 5  IOSLAVEACC_IRQ                                                         */
91   IOMSTR0_IRQn              =   6,              /*!< 6  IOMSTR0_IRQ                                                            */
92   IOMSTR1_IRQn              =   7,              /*!< 7  IOMSTR1_IRQ                                                            */
93   IOMSTR2_IRQn              =   8,              /*!< 8  IOMSTR2_IRQ                                                            */
94   IOMSTR3_IRQn              =   9,              /*!< 9  IOMSTR3_IRQ                                                            */
95   IOMSTR4_IRQn              =  10,              /*!< 10 IOMSTR4_IRQ                                                            */
96   IOMSTR5_IRQn              =  11,              /*!< 11 IOMSTR5_IRQ                                                            */
97   BLE_IRQn                  =  12,              /*!< 12 BLE_IRQ                                                                */
98   GPIO_IRQn                 =  13,              /*!< 13 GPIO_IRQ                                                               */
99   CTIMER_IRQn               =  14,              /*!< 14 CTIMER_IRQ                                                             */
100   UART0_IRQn                =  15,              /*!< 15 UART0_IRQ                                                              */
101   UART1_IRQn                =  16,              /*!< 16 UART1_IRQ                                                              */
102   SCARD_IRQn                =  17,              /*!< 17 SCARD_IRQ                                                              */
103   ADC_IRQn                  =  18,              /*!< 18 ADC_IRQ                                                                */
104   PDM_IRQn                  =  19,              /*!< 19 PDM_IRQ                                                                */
105   MSPI0_IRQn                =  20,              /*!< 20 MSPI0_IRQ                                                              */
106   STIMER_IRQn               =  22,              /*!< 22 STIMER_IRQ                                                             */
107   STIMER_CMPR0_IRQn         =  23,              /*!< 23 STIMER_CMPR0_IRQ                                                       */
108   STIMER_CMPR1_IRQn         =  24,              /*!< 24 STIMER_CMPR1_IRQ                                                       */
109   STIMER_CMPR2_IRQn         =  25,              /*!< 25 STIMER_CMPR2_IRQ                                                       */
110   STIMER_CMPR3_IRQn         =  26,              /*!< 26 STIMER_CMPR3_IRQ                                                       */
111   STIMER_CMPR4_IRQn         =  27,              /*!< 27 STIMER_CMPR4_IRQ                                                       */
112   STIMER_CMPR5_IRQn         =  28,              /*!< 28 STIMER_CMPR5_IRQ                                                       */
113   STIMER_CMPR6_IRQn         =  29,              /*!< 29 STIMER_CMPR6_IRQ                                                       */
114   STIMER_CMPR7_IRQn         =  30,              /*!< 30 STIMER_CMPR7_IRQ                                                       */
115   CLKGEN_IRQn               =  31,              /*!< 31 CLKGEN_IRQ                                                             */
116   MAX_IRQn                  =  32               /*!< 32 Not a valid IRQ. The maximum IRQ is this value - 1.                    */
117 } IRQn_Type;
118 
119 
120 
121 /* =========================================================================================================================== */
122 /* ================                           Processor and Core Peripheral Section                           ================ */
123 /* =========================================================================================================================== */
124 
125 /* ===========================  Configuration of the ARM Cortex-M4 Processor and Core Peripherals  =========================== */
126 #define __CM4_REV                 0x0100U       /*!< CM4 Core Revision                                                         */
127 #define __NVIC_PRIO_BITS               3        /*!< Number of Bits used for Priority Levels                                   */
128 #define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
129 #define __VTOR_PRESENT                 1        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
130 #define __MPU_PRESENT                  1        /*!< MPU present                                                               */
131 #define __FPU_PRESENT                  1        /*!< FPU present                                                               */
132 #define __FPU_DP                       0        /*!< Double Precision FPU                                                      */
133 #define __DSP_PRESENT                  0        /*!< DSP extension present                                                     */
134 #define __ICACHE_PRESENT               0        /*!< Instruction Cache present                                                 */
135 #define __DCACHE_PRESENT               0        /*!< Data Cache present                                                        */
136 #define __ITCM_PRESENT                 1        /*!< Instruction TCM present                                                   */
137 #define __DTCM_PRESENT                 1        /*!< Data TCM present                                                          */
138 #define __SAUREGION_PRESENT            0        /*!< SAU region present                                                        */
139 #define __PMU_PRESENT                  0        /*!< PMU present                                                               */
140 #define __PMU_NUM_EVENTCNT             0        /*!< PMU Event Counters                                                        */
141 
142 
143 /** @} */ /* End of group Configuration_of_CMSIS */
144 
145 #include "core_cm4.h"                           /*!< ARM Cortex-M4 processor and core peripherals                              */
146 #include "system_apollo3.h"                     /*!< apollo3 System                                                            */
147 
148 #ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
149   #define __IM   __I
150 #endif
151 #ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
152   #define __OM   __O
153 #endif
154 #ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
155   #define __IOM  __IO
156 #endif
157 
158 
159 /* ========================================  Start of section using anonymous unions  ======================================== */
160 #if defined (__CC_ARM)
161   #pragma push
162   #pragma anon_unions
163 #elif defined (__ICCARM__)
164   #pragma language=extended
165 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
166   #pragma clang diagnostic push
167   #pragma clang diagnostic ignored "-Wc11-extensions"
168   #pragma clang diagnostic ignored "-Wreserved-id-macro"
169   #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
170   #pragma clang diagnostic ignored "-Wnested-anon-types"
171 #elif defined (__GNUC__)
172   /* anonymous unions are enabled by default */
173 #elif defined (__TMS470__)
174   /* anonymous unions are enabled by default */
175 #elif defined (__TASKING__)
176   #pragma warning 586
177 #elif defined (__CSMC__)
178   /* anonymous unions are enabled by default */
179 #else
180   #warning Not supported compiler type
181 #endif
182 
183 
184 /* =========================================================================================================================== */
185 /* ================                            Device Specific Peripheral Section                             ================ */
186 /* =========================================================================================================================== */
187 
188 
189 /** @addtogroup Device_Peripheral_peripherals
190   * @{
191   */
192 
193 
194 
195 /* =========================================================================================================================== */
196 /* ================                                            ADC                                            ================ */
197 /* =========================================================================================================================== */
198 
199 
200 /**
201   * @brief Analog Digital Converter Control (ADC)
202   */
203 
204 typedef struct {                                /*!< (@ 0x50010000) ADC Structure                                              */
205 
206   union {
207     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The ADC Configuration Register contains the software
208                                                                     control for selecting the clock frequency
209                                                                     used for the SAR conversions, the trigger
210                                                                     polarity, the trigger select, the reference
211                                                                     voltage select, the low power mode, the
212                                                                     operating mode (single scan per trigger
213                                                                     vs. repeating mode) and ADC enable.                        */
214 
215     struct {
216       __IOM uint32_t ADCEN      : 1;            /*!< [0..0] This bit enables the ADC module. While the ADC is enabled,
217                                                      the ADCCFG and SLOT Configuration register settings must
218                                                      remain stable and unchanged. All configuration register
219                                                      settings, slot configuration settings and window comparison
220                                                      settings should be written prior to setting the ADCEN bit
221                                                      to '1'.                                                                   */
222             uint32_t            : 1;
223       __IOM uint32_t RPTEN      : 1;            /*!< [2..2] This bit enables Repeating Scan Mode.                              */
224       __IOM uint32_t LPMODE     : 1;            /*!< [3..3] Select power mode to enter between active scans.                   */
225       __IOM uint32_t CKMODE     : 1;            /*!< [4..4] Clock mode register                                                */
226             uint32_t            : 3;
227       __IOM uint32_t REFSEL     : 2;            /*!< [9..8] Select the ADC reference voltage.                                  */
228             uint32_t            : 2;
229       __IOM uint32_t DFIFORDEN  : 1;            /*!< [12..12] Destructive FIFO Read Enable. Setting this will enable
230                                                      FIFO pop upon reading the FIFOPR register.                                */
231             uint32_t            : 3;
232       __IOM uint32_t TRIGSEL    : 3;            /*!< [18..16] Select the ADC trigger source.                                   */
233       __IOM uint32_t TRIGPOL    : 1;            /*!< [19..19] This bit selects the ADC trigger polarity for external
234                                                      off chip triggers.                                                        */
235             uint32_t            : 4;
236       __IOM uint32_t CLKSEL     : 2;            /*!< [25..24] Select the source and frequency for the ADC clock.
237                                                      All values not enumerated below are undefined.                            */
238             uint32_t            : 6;
239     } CFG_b;
240   } ;
241 
242   union {
243     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) This register indicates the basic power status
244                                                                     for the ADC. For detailed power status,
245                                                                     see the power control power status register.
246                                                                     ADC power mode 0 indicates the ADC is in
247                                                                     it's full power state and is ready to process
248                                                                     scans. ADC Power mode 1 indicates the ADC
249                                                                     enabled and in a low power state.                          */
250 
251     struct {
252       __IOM uint32_t PWDSTAT    : 1;            /*!< [0..0] Indicates the power-status of the ADC.                             */
253             uint32_t            : 31;
254     } STAT_b;
255   } ;
256 
257   union {
258     __IOM uint32_t SWT;                         /*!< (@ 0x00000008) This register enables initiating an ADC scan
259                                                                     through software.                                          */
260 
261     struct {
262       __IOM uint32_t SWT        : 8;            /*!< [7..0] Writing 0x37 to this register generates a software trigger.        */
263             uint32_t            : 24;
264     } SWT_b;
265   } ;
266 
267   union {
268     __IOM uint32_t SL0CFG;                      /*!< (@ 0x0000000C) Slot 0 Configuration Register                              */
269 
270     struct {
271       __IOM uint32_t SLEN0      : 1;            /*!< [0..0] This bit enables slot 0 for ADC conversions.                       */
272       __IOM uint32_t WCEN0      : 1;            /*!< [1..1] This bit enables the window compare function for slot
273                                                      0.                                                                        */
274             uint32_t            : 6;
275       __IOM uint32_t CHSEL0     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
276             uint32_t            : 4;
277       __IOM uint32_t PRMODE0    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
278             uint32_t            : 6;
279       __IOM uint32_t ADSEL0     : 3;            /*!< [26..24] Select the number of measurements to average in the
280                                                      accumulate divide module for this slot.                                   */
281             uint32_t            : 5;
282     } SL0CFG_b;
283   } ;
284 
285   union {
286     __IOM uint32_t SL1CFG;                      /*!< (@ 0x00000010) Slot 1 Configuration Register                              */
287 
288     struct {
289       __IOM uint32_t SLEN1      : 1;            /*!< [0..0] This bit enables slot 1 for ADC conversions.                       */
290       __IOM uint32_t WCEN1      : 1;            /*!< [1..1] This bit enables the window compare function for slot
291                                                      1.                                                                        */
292             uint32_t            : 6;
293       __IOM uint32_t CHSEL1     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
294             uint32_t            : 4;
295       __IOM uint32_t PRMODE1    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
296             uint32_t            : 6;
297       __IOM uint32_t ADSEL1     : 3;            /*!< [26..24] Select the number of measurements to average in the
298                                                      accumulate divide module for this slot.                                   */
299             uint32_t            : 5;
300     } SL1CFG_b;
301   } ;
302 
303   union {
304     __IOM uint32_t SL2CFG;                      /*!< (@ 0x00000014) Slot 2 Configuration Register                              */
305 
306     struct {
307       __IOM uint32_t SLEN2      : 1;            /*!< [0..0] This bit enables slot 2 for ADC conversions.                       */
308       __IOM uint32_t WCEN2      : 1;            /*!< [1..1] This bit enables the window compare function for slot
309                                                      2.                                                                        */
310             uint32_t            : 6;
311       __IOM uint32_t CHSEL2     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
312             uint32_t            : 4;
313       __IOM uint32_t PRMODE2    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
314             uint32_t            : 6;
315       __IOM uint32_t ADSEL2     : 3;            /*!< [26..24] Select the number of measurements to average in the
316                                                      accumulate divide module for this slot.                                   */
317             uint32_t            : 5;
318     } SL2CFG_b;
319   } ;
320 
321   union {
322     __IOM uint32_t SL3CFG;                      /*!< (@ 0x00000018) Slot 3 Configuration Register                              */
323 
324     struct {
325       __IOM uint32_t SLEN3      : 1;            /*!< [0..0] This bit enables slot 3 for ADC conversions.                       */
326       __IOM uint32_t WCEN3      : 1;            /*!< [1..1] This bit enables the window compare function for slot
327                                                      3.                                                                        */
328             uint32_t            : 6;
329       __IOM uint32_t CHSEL3     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
330             uint32_t            : 4;
331       __IOM uint32_t PRMODE3    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
332             uint32_t            : 6;
333       __IOM uint32_t ADSEL3     : 3;            /*!< [26..24] Select the number of measurements to average in the
334                                                      accumulate divide module for this slot.                                   */
335             uint32_t            : 5;
336     } SL3CFG_b;
337   } ;
338 
339   union {
340     __IOM uint32_t SL4CFG;                      /*!< (@ 0x0000001C) Slot 4 Configuration Register                              */
341 
342     struct {
343       __IOM uint32_t SLEN4      : 1;            /*!< [0..0] This bit enables slot 4 for ADC conversions.                       */
344       __IOM uint32_t WCEN4      : 1;            /*!< [1..1] This bit enables the window compare function for slot
345                                                      4.                                                                        */
346             uint32_t            : 6;
347       __IOM uint32_t CHSEL4     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
348             uint32_t            : 4;
349       __IOM uint32_t PRMODE4    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
350             uint32_t            : 6;
351       __IOM uint32_t ADSEL4     : 3;            /*!< [26..24] Select the number of measurements to average in the
352                                                      accumulate divide module for this slot.                                   */
353             uint32_t            : 5;
354     } SL4CFG_b;
355   } ;
356 
357   union {
358     __IOM uint32_t SL5CFG;                      /*!< (@ 0x00000020) Slot 5 Configuration Register                              */
359 
360     struct {
361       __IOM uint32_t SLEN5      : 1;            /*!< [0..0] This bit enables slot 5 for ADC conversions.                       */
362       __IOM uint32_t WCEN5      : 1;            /*!< [1..1] This bit enables the window compare function for slot
363                                                      5.                                                                        */
364             uint32_t            : 6;
365       __IOM uint32_t CHSEL5     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
366             uint32_t            : 4;
367       __IOM uint32_t PRMODE5    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
368             uint32_t            : 6;
369       __IOM uint32_t ADSEL5     : 3;            /*!< [26..24] Select number of measurements to average in the accumulate
370                                                      divide module for this slot.                                              */
371             uint32_t            : 5;
372     } SL5CFG_b;
373   } ;
374 
375   union {
376     __IOM uint32_t SL6CFG;                      /*!< (@ 0x00000024) Slot 6 Configuration Register                              */
377 
378     struct {
379       __IOM uint32_t SLEN6      : 1;            /*!< [0..0] This bit enables slot 6 for ADC conversions.                       */
380       __IOM uint32_t WCEN6      : 1;            /*!< [1..1] This bit enables the window compare function for slot
381                                                      6.                                                                        */
382             uint32_t            : 6;
383       __IOM uint32_t CHSEL6     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
384             uint32_t            : 4;
385       __IOM uint32_t PRMODE6    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
386             uint32_t            : 6;
387       __IOM uint32_t ADSEL6     : 3;            /*!< [26..24] Select the number of measurements to average in the
388                                                      accumulate divide module for this slot.                                   */
389             uint32_t            : 5;
390     } SL6CFG_b;
391   } ;
392 
393   union {
394     __IOM uint32_t SL7CFG;                      /*!< (@ 0x00000028) Slot 7 Configuration Register                              */
395 
396     struct {
397       __IOM uint32_t SLEN7      : 1;            /*!< [0..0] This bit enables slot 7 for ADC conversions.                       */
398       __IOM uint32_t WCEN7      : 1;            /*!< [1..1] This bit enables the window compare function for slot
399                                                      7.                                                                        */
400             uint32_t            : 6;
401       __IOM uint32_t CHSEL7     : 4;            /*!< [11..8] Select one of the 14 channel inputs for this slot.                */
402             uint32_t            : 4;
403       __IOM uint32_t PRMODE7    : 2;            /*!< [17..16] Set the Precision Mode For Slot.                                 */
404             uint32_t            : 6;
405       __IOM uint32_t ADSEL7     : 3;            /*!< [26..24] Select the number of measurements to average in the
406                                                      accumulate divide module for this slot.                                   */
407             uint32_t            : 5;
408     } SL7CFG_b;
409   } ;
410 
411   union {
412     __IOM uint32_t WULIM;                       /*!< (@ 0x0000002C) Window Comparator Upper Limits Register                    */
413 
414     struct {
415       __IOM uint32_t ULIM       : 20;           /*!< [19..0] Sets the upper limit for the window comparator.                   */
416             uint32_t            : 12;
417     } WULIM_b;
418   } ;
419 
420   union {
421     __IOM uint32_t WLLIM;                       /*!< (@ 0x00000030) Window Comparator Lower Limits Register                    */
422 
423     struct {
424       __IOM uint32_t LLIM       : 20;           /*!< [19..0] Sets the lower limit for the window comparator.                   */
425             uint32_t            : 12;
426     } WLLIM_b;
427   } ;
428 
429   union {
430     __IOM uint32_t SCWLIM;                      /*!< (@ 0x00000034) Scale Window Comparator Limits                             */
431 
432     struct {
433       __IOM uint32_t SCWLIMEN   : 1;            /*!< [0..0] Scale the window limits compare values per precision
434                                                      mode. When set to 0x0 (default), the values in the 20-bit
435                                                      limits registers will compare directly with the FIFO values
436                                                      regardless of the precision mode the slot is configured
437                                                      to. When set to 0x1, the compare values will be divided
438                                                      by the difference in precision bits while performing the
439                                                      window limit comparisons.                                                 */
440             uint32_t            : 31;
441     } SCWLIM_b;
442   } ;
443 
444   union {
445     __IOM uint32_t FIFO;                        /*!< (@ 0x00000038) The ADC FIFO Register contains the slot number
446                                                                     and FIFO data for the oldest conversion
447                                                                     data in the FIFO. The COUNT field indicates
448                                                                     the total number of valid entries in the
449                                                                     FIFO. A write to this register will pop
450                                                                     one of the FIFO entries off the FIFO and
451                                                                     decrease the COUNT by 1 if the COUNT is
452                                                                     greater than zero.                                         */
453 
454     struct {
455       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
456       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
457       __IOM uint32_t SLOTNUM    : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
458       __IOM uint32_t RSVD       : 1;            /*!< [31..31] RESERVED.                                                        */
459     } FIFO_b;
460   } ;
461 
462   union {
463     __IOM uint32_t FIFOPR;                      /*!< (@ 0x0000003C) This is a Pop Read mirrored copy of the ADCFIFO
464                                                                     register with the only difference being
465                                                                     that reading this register will result in
466                                                                     a simultaneous FIFO POP which is also achieved
467                                                                     by writing to the ADCFIFO Register. Note:
468                                                                     The DFIFORDEN bit must be set in the CFG
469                                                                     register for the the destructive read to
470                                                                     be enabled.                                                */
471 
472     struct {
473       __IOM uint32_t DATA       : 20;           /*!< [19..0] Oldest data in the FIFO.                                          */
474       __IOM uint32_t COUNT      : 8;            /*!< [27..20] Number of valid entries in the ADC FIFO.                         */
475       __IOM uint32_t SLOTNUMPR  : 3;            /*!< [30..28] Slot number associated with this FIFO data.                      */
476       __IOM uint32_t RSVDPR     : 1;            /*!< [31..31] RESERVED.                                                        */
477     } FIFOPR_b;
478   } ;
479   __IM  uint32_t  RESERVED[112];
480 
481   union {
482     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
483                                                                     to generate the corresponding interrupt.                   */
484 
485     struct {
486       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
487       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
488       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
489       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
490       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
491       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
492       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
493       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
494             uint32_t            : 24;
495     } INTEN_b;
496   } ;
497 
498   union {
499     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
500                                                                     cause of a recent interrupt.                               */
501 
502     struct {
503       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
504       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
505       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
506       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
507       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
508       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
509       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
510       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
511             uint32_t            : 24;
512     } INTSTAT_b;
513   } ;
514 
515   union {
516     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
517                                                                     the interrupt status associated with that
518                                                                     bit.                                                       */
519 
520     struct {
521       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
522       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
523       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
524       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
525       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
526       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
527       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
528       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
529             uint32_t            : 24;
530     } INTCLR_b;
531   } ;
532 
533   union {
534     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
535                                                                     generate an interrupt from this module.
536                                                                     (Generally used for testing purposes).                     */
537 
538     struct {
539       __IOM uint32_t CNVCMP     : 1;            /*!< [0..0] ADC conversion complete interrupt.                                 */
540       __IOM uint32_t SCNCMP     : 1;            /*!< [1..1] ADC scan complete interrupt.                                       */
541       __IOM uint32_t FIFOOVR1   : 1;            /*!< [2..2] FIFO 75 percent full interrupt.                                    */
542       __IOM uint32_t FIFOOVR2   : 1;            /*!< [3..3] FIFO 100 percent full interrupt.                                   */
543       __IOM uint32_t WCEXC      : 1;            /*!< [4..4] Window comparator voltage excursion interrupt.                     */
544       __IOM uint32_t WCINC      : 1;            /*!< [5..5] Window comparator voltage incursion interrupt.                     */
545       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Transfer Complete                                              */
546       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Condition                                                */
547             uint32_t            : 24;
548     } INTSET_b;
549   } ;
550   __IM  uint32_t  RESERVED1[12];
551 
552   union {
553     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable Register                                */
554 
555     struct {
556       __IOM uint32_t DFIFO75    : 1;            /*!< [0..0] Trigger DMA upon FIFO 75 percent Full                              */
557       __IOM uint32_t DFIFOFULL  : 1;            /*!< [1..1] Trigger DMA upon FIFO 100 percent Full                             */
558             uint32_t            : 30;
559     } DMATRIGEN_b;
560   } ;
561 
562   union {
563     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status Register                                */
564 
565     struct {
566       __IOM uint32_t D75STAT    : 1;            /*!< [0..0] Triggered DMA from FIFO 75 percent Full                            */
567       __IOM uint32_t DFULLSTAT  : 1;            /*!< [1..1] Triggered DMA from FIFO 100 percent Full                           */
568             uint32_t            : 30;
569     } DMATRIGSTAT_b;
570   } ;
571   __IM  uint32_t  RESERVED2[14];
572 
573   union {
574     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration Register                                 */
575 
576     struct {
577       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
578             uint32_t            : 1;
579       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
580             uint32_t            : 5;
581       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
582       __IOM uint32_t DMADYNPRI  : 1;            /*!< [9..9] Enables dynamic priority based on FIFO fullness. When
583                                                      FIFO is full, priority is automatically set to HIGH. Otherwise,
584                                                      DMAPRI is used.                                                           */
585             uint32_t            : 6;
586       __IOM uint32_t DMAHONSTAT : 1;            /*!< [16..16] Halt New ADC conversions until DMA Status DMAERR and
587                                                      DMACPL Cleared.                                                           */
588       __IOM uint32_t DMAMSK     : 1;            /*!< [17..17] Mask the FIFOCNT and SLOTNUM when transferring FIFO
589                                                      contents to memory                                                        */
590       __IOM uint32_t DPWROFF    : 1;            /*!< [18..18] Power Off the ADC System upon DMACPL.                            */
591             uint32_t            : 13;
592     } DMACFG_b;
593   } ;
594   __IM  uint32_t  RESERVED3;
595 
596   union {
597     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
598 
599     struct {
600             uint32_t            : 2;
601       __IOM uint32_t TOTCOUNT   : 16;           /*!< [17..2] Total Transfer Count                                              */
602             uint32_t            : 14;
603     } DMATOTCOUNT_b;
604   } ;
605 
606   union {
607     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address Register                                */
608 
609     struct {
610       __IOM uint32_t LTARGADDR  : 19;           /*!< [18..0] DMA Target Address                                                */
611       __IOM uint32_t UTARGADDR  : 13;           /*!< [31..19] SRAM Target                                                      */
612     } DMATARGADDR_b;
613   } ;
614 
615   union {
616     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status Register                                        */
617 
618     struct {
619       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
620       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
621       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
622             uint32_t            : 29;
623     } DMASTAT_b;
624   } ;
625 } ADC_Type;                                     /*!< Size = 660 (0x294)                                                        */
626 
627 
628 
629 /* =========================================================================================================================== */
630 /* ================                                          APBDMA                                           ================ */
631 /* =========================================================================================================================== */
632 
633 
634 /**
635   * @brief APB DMA Register Interfaces (APBDMA)
636   */
637 
638 typedef struct {                                /*!< (@ 0x40011000) APBDMA Structure                                           */
639 
640   union {
641     __IOM uint32_t BBVALUE;                     /*!< (@ 0x00000000) Control Register                                           */
642 
643     struct {
644       __IOM uint32_t DATAOUT    : 8;            /*!< [7..0] Data Output Values                                                 */
645             uint32_t            : 8;
646       __IOM uint32_t PIN        : 8;            /*!< [23..16] PIO values                                                       */
647             uint32_t            : 8;
648     } BBVALUE_b;
649   } ;
650 
651   union {
652     __IOM uint32_t BBSETCLEAR;                  /*!< (@ 0x00000004) Set/Clear Register                                         */
653 
654     struct {
655       __IOM uint32_t SET        : 8;            /*!< [7..0] Write 1 to set PIO value (set higher priority then clear
656                                                      if both bits are set)                                                     */
657             uint32_t            : 8;
658       __IOM uint32_t CLEAR      : 8;            /*!< [23..16] Write 1 to clear PIO value                                       */
659             uint32_t            : 8;
660     } BBSETCLEAR_b;
661   } ;
662 
663   union {
664     __IOM uint32_t BBINPUT;                     /*!< (@ 0x00000008) PIO Input Values                                           */
665 
666     struct {
667       __IOM uint32_t DATAIN     : 8;            /*!< [7..0] PIO values                                                         */
668             uint32_t            : 24;
669     } BBINPUT_b;
670   } ;
671   __IM  uint32_t  RESERVED[5];
672 
673   union {
674     __IOM uint32_t DEBUGDATA;                   /*!< (@ 0x00000020) PIO Input Values                                           */
675 
676     struct {
677       __IOM uint32_t DEBUGDATA  : 32;           /*!< [31..0] Debug Data                                                        */
678     } DEBUGDATA_b;
679   } ;
680   __IM  uint32_t  RESERVED1[7];
681 
682   union {
683     __IOM uint32_t DEBUG;                       /*!< (@ 0x00000040) PIO Input Values                                           */
684 
685     struct {
686       __IOM uint32_t DEBUGEN    : 4;            /*!< [3..0] Debug Enable                                                       */
687             uint32_t            : 28;
688     } DEBUG_b;
689   } ;
690 } APBDMA_Type;                                  /*!< Size = 68 (0x44)                                                          */
691 
692 
693 
694 /* =========================================================================================================================== */
695 /* ================                                           BLEIF                                           ================ */
696 /* =========================================================================================================================== */
697 
698 
699 /**
700   * @brief BLE Interface (BLEIF)
701   */
702 
703 typedef struct {                                /*!< (@ 0x5000C000) BLEIF Structure                                            */
704 
705   union {
706     __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both input and
707                                                                     output FIFOs. The state of the FIFO is not
708                                                                     disturbed by reading these locations (i.e.,
709                                                                     no POP will occur). FIFO0 is accessible
710                                                                     from addresses 0x0 - 0x1C, and is used for
711                                                                     data output from the IOM to external devices.
712                                                                     These FIFO locations can be read and written
713                                                                     directly.FIFO locations 0x20 - 0x3C provide
714                                                                     read only access to the input FIFO. These
715                                                                     FIFO locations cannot be directly written
716                                                                     by the MCU, and are updated only by the
717                                                                     internal hardware                                          */
718 
719     struct {
720       __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
721                                                      valid information.                                                        */
722     } FIFO_b;
723   } ;
724   __IM  uint32_t  RESERVED[63];
725 
726   union {
727     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
728                                                                     within the FIFO as seen from the internal
729                                                                     state machines. FIFO0 is dedicated to outgoing
730                                                                     transactions and FIFO1 is dedicated to incoming
731                                                                     transactions. All counts are specified in
732                                                                     units of bytes.                                            */
733 
734     struct {
735       __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
736                                                      0 (written by MCU, read by interface)                                     */
737       __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
738                                                      FIFO 0 (written by MCU, read by interface)                                */
739       __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
740                                                      (written by interface, read by MCU)                                       */
741       __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
742                                                      in FIFO 1 (written by interface, read by MCU)                             */
743     } FIFOPTR_b;
744   } ;
745 
746   union {
747     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
748                                                                     transactions. The threshold values are used
749                                                                     to assert the interrupt if enabled, and
750                                                                     also used during DMA to set the transfer
751                                                                     size as a result of DMATHR trigger.The WTHR
752                                                                     is used to indicate when there are more
753                                                                     than WTHR bytes of open FIFO locations available
754                                                                     in the outgoing FIFO (FIFO0). The intended
755                                                                     use to invoke an interrupt or DMA transfer
756                                                                     that will refill the FIFO with a byte count
757                                                                     up to this value.The RTHR is used to indicate
758                                                                     when t                                                     */
759 
760     struct {
761       __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
762                                                      the read FIFO level from activating the threshold interrupt.
763                                                      If this field is non-zero, it will trigger a threshold
764                                                      interrupt when the read FIFO contains FIFORTHR valid bytes
765                                                      of data, as indicated by the FIFO1SIZ field. This is intended
766                                                      to signal when a data transfer of FIFORTHR bytes can be
767                                                      done from the IOM module to the host via the read FIFO
768                                                      to support large IOM read operations.                                     */
769             uint32_t            : 2;
770       __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
771                                                      the write FIFO level from activating the threshold interrupt.
772                                                      If this field is non-zero, it will trigger a threshold
773                                                      interrupt when the write FIFO contains FIFOWTHR free bytes,
774                                                      as indicated by the FIFO0REM field. This is intended to
775                                                      signal when a transfer of FIFOWTHR bytes can be done from
776                                                      the host to the IOM write FIFO to support large IOM write
777                                                      operations.                                                               */
778             uint32_t            : 18;
779     } FIFOTHR_b;
780   } ;
781 
782   union {
783     __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
784                                                                     incoming FIFO (FIFO1) when read, if POPWR
785                                                                     is not active. If POPWR is active, a write
786                                                                     to this register is needed to advance the
787                                                                     internal FIFO pointer.                                     */
788 
789     struct {
790       __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
791                                                      the current read pointer on reads. If the POPWR control
792                                                      bit in the FIFOCTRL register is reset (0), the FIFO read
793                                                      pointer will be advanced by one word as a result of the
794                                                      read.If the POPWR bit is set (1), the FIFO read pointer
795                                                      will only be advanced after a write operation to this register.
796                                                      The write data is ignored for this register.If less than
797                                                      a even word multiple is available, and the command is completed,
798                                                      the module will return the word containing                                */
799     } FIFOPOP_b;
800   } ;
801 
802   union {
803     __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
804                                                                     advance the internal write pointer.                        */
805 
806     struct {
807       __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
808                                                      and will cause a push event to occur to the next open slot
809                                                      within the FIFORAM. Writing to this register will cause
810                                                      the write point to increment by 1 word(4 bytes).                          */
811     } FIFOPUSH_b;
812   } ;
813 
814   union {
815     __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
816                                                                     FIFOs. Contains fields used to control the
817                                                                     operation of the POP register, and also
818                                                                     controls to reset the internal pointers
819                                                                     of the FIFOs.                                              */
820 
821     struct {
822       __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
823                                                      FIFO read operations. A value of '1' will prevent a pop
824                                                      event on a read operation, and will require a write to
825                                                      the FIFOPOP register to create a pop event.A value of '0'
826                                                      in this register will allow a pop event to occur on the
827                                                      read of the FIFOPOP register, and may cause inadvertent
828                                                      FIFO pops when used in a debugging mode.                                  */
829       __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the FIFO. Write to 0 to reset
830                                                      FIFO, and then write to 1 to remove the reset.                            */
831             uint32_t            : 30;
832     } FIFOCTRL_b;
833   } ;
834 
835   union {
836     __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
837                                                                     and write pointers. This register is read
838                                                                     only and can be used along with the FIFO
839                                                                     direct access method to determine the next
840                                                                     data to be used for input and output functions.            */
841 
842     struct {
843       __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
844                                                      outgoing FIFO (FIFO0), which is used during write operations
845                                                      to external devices.                                                      */
846             uint32_t            : 4;
847       __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
848                                                      FIFO (FIFO1), which is used to store read data returned
849                                                      from external devices during a read operation.                            */
850             uint32_t            : 20;
851     } FIFOLOC_b;
852   } ;
853   __IM  uint32_t  RESERVED1[58];
854 
855   union {
856     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000200) Provides clock related controls used internal
857                                                                     to the BLEIF module, and enablement of 32KHz
858                                                                     clock to the BLE Core module. The internal
859                                                                     clock sourced is selected via the FSEL and
860                                                                     can be further divided by 3 using the DIV3
861                                                                     control.This register is also used to enable
862                                                                     the clock, which must be done prior to performing
863                                                                     any IO transactions.                                       */
864 
865     struct {
866       __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
867                                                      to executing any IO operations.                                           */
868             uint32_t            : 7;
869       __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
870       __IOM uint32_t CLK32KEN   : 1;            /*!< [11..11] Enable for the 32Khz clock to the BLE module                     */
871       __IOM uint32_t DIV3       : 1;            /*!< [12..12] Enable of the divide by 3 of the source IOCLK.                   */
872             uint32_t            : 19;
873     } CLKCFG_b;
874   } ;
875   __IM  uint32_t  RESERVED2[2];
876 
877   union {
878     __IOM uint32_t CMD;                         /*!< (@ 0x0000020C) Writes to this register will start an IO transaction,
879                                                                     as well as set various parameters for the
880                                                                     command itself. Reads will return the command
881                                                                     value written to the CMD register.To read
882                                                                     the number of bytes that have yet to be
883                                                                     transferred, refer to the CTSIZE field within
884                                                                     the CMDSTAT register.                                      */
885 
886     struct {
887       __IOM uint32_t CMD        : 5;            /*!< [4..0] Command for submodule.                                             */
888       __IOM uint32_t OFFSETCNT  : 2;            /*!< [6..5] Number of offset bytes to use for the command - 0, 1,
889                                                      2, 3 are valid selections. The second (byte 1) and third
890                                                      byte (byte 2) are read from the OFFSETHI register, and
891                                                      the low order byte is pulled from this register in the
892                                                      OFFSETLO field.Offset bytes are transmitted highest byte
893                                                      first. E.g., if OFFSETCNT == 3, OFFSETHI[15:8] will be
894                                                      transmitted first, then OFFSETHI[7:0] then OFFSETLO.If
895                                                      OFFSETCNT == 2, OFFSETHI[7:0] will be transmitted, then
896                                                      OFFSETLO.If OFFSETCNT == 1, only OFFSETLO will be transmitted             */
897       __IOM uint32_t CONT       : 1;            /*!< [7..7] Continue to hold the bus after the current transaction
898                                                      if set to a 1 with a new command issued.                                  */
899       __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
900                                                      is not included in this size.                                             */
901       __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information                           */
902             uint32_t            : 2;
903       __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
904                                                      be used in the transaction. The number of offset bytes
905                                                      to use is set with bits 1:0 of the command. Offset bytes
906                                                      are transferred starting from the highest byte first.                     */
907     } CMD_b;
908   } ;
909 
910   union {
911     __IOM uint32_t CMDRPT;                      /*!< (@ 0x00000210) Will repeat the next command for CMDRPT number
912                                                                     of times. If CMDRPT is set to 1, the next
913                                                                     command will be done 2 times in series.
914                                                                     A repeat count of up to 31 is possible.
915                                                                     Each command will be done as a separate
916                                                                     command, but the data willbe treated as
917                                                                     packed, and aligned to byte boundaries.
918                                                                     This differs when executing separate commands
919                                                                     without the CMDRPT set, as the data for
920                                                                     each transaction is word aligned and any
921                                                                     unused byte locations will be filled with
922                                                                     0 for read operations, ordiscarded                         */
923 
924     struct {
925       __IOM uint32_t CMDRPT     : 5;            /*!< [4..0] Count of number of times to repeat the next command.               */
926             uint32_t            : 27;
927     } CMDRPT_b;
928   } ;
929 
930   union {
931     __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000214) Provides the high order bytes of 2 or 3 byte
932                                                                     offset transactions of the current command.
933                                                                     Usage of these bytes is dependent on the
934                                                                     OFFSETCNT field in the CMD register. If
935                                                                     the OFFSETCNT == 3, the data located at
936                                                                     OFFSETHI[15:0] will first be transmitted,followed
937                                                                     by OFFSETHI[7:0], followed by OFFSETLO (in
938                                                                     the CMD register) prior to sending or receiving
939                                                                     any transaction data (if programed via TSIZE
940                                                                     field in the CMD register).The offset bytes
941                                                                     are always transmitted MSB first for all
942                                                                     modules.                                                   */
943 
944     struct {
945       __IOM uint32_t OFFSETHI   : 16;           /*!< [15..0] Holds the high order bytes of the 2 or 3 byte offset
946                                                      phase of a transaction.                                                   */
947             uint32_t            : 16;
948     } OFFSETHI_b;
949   } ;
950 
951   union {
952     __IOM uint32_t CMDSTAT;                     /*!< (@ 0x00000218) Provides status on the execution of the command
953                                                                     currently in progress. The fields in this
954                                                                     register will reflect the real time status
955                                                                     of the internal state machines and data
956                                                                     transfers within the IOM.These are read
957                                                                     only fields and writes to the registers
958                                                                     are ignored.                                               */
959 
960     struct {
961       __IOM uint32_t CCMD       : 5;            /*!< [4..0] current command that is being executed                             */
962       __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
963       __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
964                                                      with this command. This field will count down to zero.                    */
965             uint32_t            : 12;
966     } CMDSTAT_b;
967   } ;
968   __IM  uint32_t  RESERVED3;
969 
970   union {
971     __IOM uint32_t INTEN;                       /*!< (@ 0x00000220) Set bits in this register to allow this module
972                                                                     to generate the corresponding interrupt.                   */
973 
974     struct {
975       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
976                                                      operation has completed. For repeated commands, this will
977                                                      only be asserted when the final repeated command is completed.            */
978       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
979                                                      when the number of free bytes in the write FIFO equals
980                                                      or exceeds the WTHR field.For read operations, asserted
981                                                      when the number of valid bytes in the read FIFO equals
982                                                      of exceeds the value set in the RTHR field.                               */
983       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
984                                                      is done to a empty read FIFO.                                             */
985       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
986                                                      tries to write to a full FIFO. The current operation does
987                                                      not stop.                                                                 */
988       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
989                                                      the B2M_STATE signal from the BLE Core.                                   */
990       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
991                                                      a overflow or underflow event                                             */
992       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
993                                                      written when an active command is in progress.                            */
994       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
995                                                      from the BLE Core is asserted, indicating the availability
996                                                      of read data from the BLE Core.                                           */
997       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
998                                                      signal from the BLE Core is asserted, indicating that SPI
999                                                      writes can be done to the BLE Core.Transfers to the BLE
1000                                                      Core should only be done when this signal is high.                        */
1001       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1002                                                      and the DMA submodule is returned into the idle state                     */
1003       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1004                                                      DMA command. The DMA error could occur when the memory
1005                                                      access specified in the DMA operation is not available
1006                                                      or incorrectly specified.                                                 */
1007       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1008                                                      in the PAUSEEN register. The interrupt is posted when the
1009                                                      event is enabled within the PAUSEEN register, the mask
1010                                                      is active in the CQIRQMASK field and the event occurs.                    */
1011       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1012                                                      with the register address bit 0 set to 1. The low address
1013                                                      bits in the CQ address fields are unused and bit 0 can
1014                                                      be used to trigger an interrupt to indicate when this register
1015                                                      write is performed by the CQ operation.                                   */
1016       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1017                                                      occurs, the system will stop processing and halt operations
1018                                                      to allow software to take recovery actions                                */
1019       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1020                                                      sleep state                                                               */
1021       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1022                                                      into the active state Revision B: Falling BLE Core IRQ
1023                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1024                                                      is deasserted (1 -> 0)                                                    */
1025       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1026                                                      into shutdown state Revision B: Falling BLE Core Status
1027                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1028                                                      Core is deasserted (1 -> 0)                                               */
1029             uint32_t            : 15;
1030     } INTEN_b;
1031   } ;
1032 
1033   union {
1034     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000224) Read bits from this register to discover the
1035                                                                     cause of a recent interrupt.                               */
1036 
1037     struct {
1038       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
1039                                                      operation has completed. For repeated commands, this will
1040                                                      only be asserted when the final repeated command is completed.            */
1041       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
1042                                                      when the number of free bytes in the write FIFO equals
1043                                                      or exceeds the WTHR field.For read operations, asserted
1044                                                      when the number of valid bytes in the read FIFO equals
1045                                                      of exceeds the value set in the RTHR field.                               */
1046       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
1047                                                      is done to a empty read FIFO.                                             */
1048       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
1049                                                      tries to write to a full FIFO. The current operation does
1050                                                      not stop.                                                                 */
1051       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
1052                                                      the B2M_STATE signal from the BLE Core.                                   */
1053       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
1054                                                      a overflow or underflow event                                             */
1055       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
1056                                                      written when an active command is in progress.                            */
1057       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
1058                                                      from the BLE Core is asserted, indicating the availability
1059                                                      of read data from the BLE Core.                                           */
1060       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1061                                                      signal from the BLE Core is asserted, indicating that SPI
1062                                                      writes can be done to the BLE Core.Transfers to the BLE
1063                                                      Core should only be done when this signal is high.                        */
1064       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1065                                                      and the DMA submodule is returned into the idle state                     */
1066       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1067                                                      DMA command. The DMA error could occur when the memory
1068                                                      access specified in the DMA operation is not available
1069                                                      or incorrectly specified.                                                 */
1070       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1071                                                      in the PAUSEEN register. The interrupt is posted when the
1072                                                      event is enabled within the PAUSEEN register, the mask
1073                                                      is active in the CQIRQMASK field and the event occurs.                    */
1074       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1075                                                      with the register address bit 0 set to 1. The low address
1076                                                      bits in the CQ address fields are unused and bit 0 can
1077                                                      be used to trigger an interrupt to indicate when this register
1078                                                      write is performed by the CQ operation.                                   */
1079       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1080                                                      occurs, the system will stop processing and halt operations
1081                                                      to allow software to take recovery actions                                */
1082       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1083                                                      sleep state                                                               */
1084       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1085                                                      into the active state Revision B: Falling BLE Core IRQ
1086                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1087                                                      is deasserted (1 -> 0)                                                    */
1088       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1089                                                      into shutdown state Revision B: Falling BLE Core Status
1090                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1091                                                      Core is deasserted (1 -> 0)                                               */
1092             uint32_t            : 15;
1093     } INTSTAT_b;
1094   } ;
1095 
1096   union {
1097     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000228) Write a 1 to a bit in this register to clear
1098                                                                     the interrupt status associated with that
1099                                                                     bit.                                                       */
1100 
1101     struct {
1102       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
1103                                                      operation has completed. For repeated commands, this will
1104                                                      only be asserted when the final repeated command is completed.            */
1105       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
1106                                                      when the number of free bytes in the write FIFO equals
1107                                                      or exceeds the WTHR field.For read operations, asserted
1108                                                      when the number of valid bytes in the read FIFO equals
1109                                                      of exceeds the value set in the RTHR field.                               */
1110       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
1111                                                      is done to a empty read FIFO.                                             */
1112       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
1113                                                      tries to write to a full FIFO. The current operation does
1114                                                      not stop.                                                                 */
1115       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
1116                                                      the B2M_STATE signal from the BLE Core.                                   */
1117       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
1118                                                      a overflow or underflow event                                             */
1119       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
1120                                                      written when an active command is in progress.                            */
1121       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
1122                                                      from the BLE Core is asserted, indicating the availability
1123                                                      of read data from the BLE Core.                                           */
1124       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1125                                                      signal from the BLE Core is asserted, indicating that SPI
1126                                                      writes can be done to the BLE Core.Transfers to the BLE
1127                                                      Core should only be done when this signal is high.                        */
1128       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1129                                                      and the DMA submodule is returned into the idle state                     */
1130       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1131                                                      DMA command. The DMA error could occur when the memory
1132                                                      access specified in the DMA operation is not available
1133                                                      or incorrectly specified.                                                 */
1134       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1135                                                      in the PAUSEEN register. The interrupt is posted when the
1136                                                      event is enabled within the PAUSEEN register, the mask
1137                                                      is active in the CQIRQMASK field and the event occurs.                    */
1138       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1139                                                      with the register address bit 0 set to 1. The low address
1140                                                      bits in the CQ address fields are unused and bit 0 can
1141                                                      be used to trigger an interrupt to indicate when this register
1142                                                      write is performed by the CQ operation.                                   */
1143       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1144                                                      occurs, the system will stop processing and halt operations
1145                                                      to allow software to take recovery actions                                */
1146       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1147                                                      sleep state                                                               */
1148       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1149                                                      into the active state Revision B: Falling BLE Core IRQ
1150                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1151                                                      is deasserted (1 -> 0)                                                    */
1152       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1153                                                      into shutdown state Revision B: Falling BLE Core Status
1154                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1155                                                      Core is deasserted (1 -> 0)                                               */
1156             uint32_t            : 15;
1157     } INTCLR_b;
1158   } ;
1159 
1160   union {
1161     __IOM uint32_t INTSET;                      /*!< (@ 0x0000022C) Write a 1 to a bit in this register to instantly
1162                                                                     generate an interrupt from this module.
1163                                                                     (Generally used for testing purposes).                     */
1164 
1165     struct {
1166       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
1167                                                      operation has completed. For repeated commands, this will
1168                                                      only be asserted when the final repeated command is completed.            */
1169       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
1170                                                      when the number of free bytes in the write FIFO equals
1171                                                      or exceeds the WTHR field.For read operations, asserted
1172                                                      when the number of valid bytes in the read FIFO equals
1173                                                      of exceeds the value set in the RTHR field.                               */
1174       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. Asserted when a pop operation
1175                                                      is done to a empty read FIFO.                                             */
1176       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
1177                                                      tries to write to a full FIFO. The current operation does
1178                                                      not stop.                                                                 */
1179       __IOM uint32_t B2MST      : 1;            /*!< [4..4] B2M State change interrupt. Asserted on any change in
1180                                                      the B2M_STATE signal from the BLE Core.                                   */
1181       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
1182                                                      a overflow or underflow event                                             */
1183       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
1184                                                      written when an active command is in progress.                            */
1185       __IOM uint32_t BLECIRQ    : 1;            /*!< [7..7] BLE Core IRQ signal. Asserted when the BLE_IRQ signal
1186                                                      from the BLE Core is asserted, indicating the availability
1187                                                      of read data from the BLE Core.                                           */
1188       __IOM uint32_t BLECSSTAT  : 1;            /*!< [8..8] BLE Core SPI Status interrupt. Asserted when the SPI_STATUS
1189                                                      signal from the BLE Core is asserted, indicating that SPI
1190                                                      writes can be done to the BLE Core.Transfers to the BLE
1191                                                      Core should only be done when this signal is high.                        */
1192       __IOM uint32_t DCMP       : 1;            /*!< [9..9] DMA Complete. Processing of the DMA operation has completed
1193                                                      and the DMA submodule is returned into the idle state                     */
1194       __IOM uint32_t DERR       : 1;            /*!< [10..10] DMA Error encountered during the processing of the
1195                                                      DMA command. The DMA error could occur when the memory
1196                                                      access specified in the DMA operation is not available
1197                                                      or incorrectly specified.                                                 */
1198       __IOM uint32_t CQPAUSED   : 1;            /*!< [11..11] Command queue is paused due to an active event enabled
1199                                                      in the PAUSEEN register. The interrupt is posted when the
1200                                                      event is enabled within the PAUSEEN register, the mask
1201                                                      is active in the CQIRQMASK field and the event occurs.                    */
1202       __IOM uint32_t CQUPD      : 1;            /*!< [12..12] Command queue write operation executed a register write
1203                                                      with the register address bit 0 set to 1. The low address
1204                                                      bits in the CQ address fields are unused and bit 0 can
1205                                                      be used to trigger an interrupt to indicate when this register
1206                                                      write is performed by the CQ operation.                                   */
1207       __IOM uint32_t CQERR      : 1;            /*!< [13..13] Command queue error during processing. When an error
1208                                                      occurs, the system will stop processing and halt operations
1209                                                      to allow software to take recovery actions                                */
1210       __IOM uint32_t B2MSLEEP   : 1;            /*!< [14..14] The B2M_STATE from the BLE Core transitioned into the
1211                                                      sleep state                                                               */
1212       __IOM uint32_t B2MACTIVE  : 1;            /*!< [15..15] Revision A: The B2M_STATE from the BLE Core transitioned
1213                                                      into the active state Revision B: Falling BLE Core IRQ
1214                                                      signal. Asserted when the BLE_IRQ signal from the BLE Core
1215                                                      is deasserted (1 -> 0)                                                    */
1216       __IOM uint32_t B2MSHUTDN  : 1;            /*!< [16..16] Revision A: The B2M_STATE from the BLE Core transitioned
1217                                                      into shutdown state Revision B: Falling BLE Core Status
1218                                                      signal. Asserted when the BLE_STATUS signal from the BLE
1219                                                      Core is deasserted (1 -> 0)                                               */
1220             uint32_t            : 15;
1221     } INTSET_b;
1222   } ;
1223 
1224   union {
1225     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000230) Provides control on which event will trigger
1226                                                                     the DMA transfer after the DMA operation
1227                                                                     is setup and enabled. The trigger event
1228                                                                     will cause a number of bytes (depending
1229                                                                     on trigger event) to betransferred via the
1230                                                                     DMA operation, and can be used to adjust
1231                                                                     the latency of data to/from the IOM module
1232                                                                     to/from the DMA target. DMA transfers are
1233                                                                     broken into smaller transfers internally
1234                                                                     of up to16 bytes each, and multiple trigger
1235                                                                     events can be used to complete the entire
1236                                                                     programmed DMA transfer.                                   */
1237 
1238     struct {
1239       __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
1240                                                      of the DMA when a command is completed. When this event
1241                                                      is triggered, the number of words transferred will be the
1242                                                      lesser of the remaining TOTCOUNT bytes, or the number of
1243                                                      bytes in the FIFO when the command completed. If this is
1244                                                      disabled, and the number of bytes in the FIFO is equal
1245                                                      or greater than the TOTCOUNT bytes, a transfer of TOTCOUNT
1246                                                      bytes will be done to ensure read data is stored when the
1247                                                      DMA is completed.                                                         */
1248       __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
1249                                                      (IOM writes), the trigger will assert when the write FIFO
1250                                                      has (WTHR/4) number of words free in the write FIFO, and
1251                                                      will transfer (WTHR/4) number of wordsor, if the number
1252                                                      of words left to transfer is less than the WTHR value,
1253                                                      will transfer the remaining byte count.For P2M DMA operations,
1254                                                      the trigger will assert when the read FIFO has (RTHR/4)
1255                                                      words available in the read FIFO, and will transfer (RTHR/4)
1256                                                      words to SRAM. This trigger will NOT asser                                */
1257             uint32_t            : 30;
1258     } DMATRIGEN_b;
1259   } ;
1260 
1261   union {
1262     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000234) Provides the status of trigger events that have
1263                                                                     occurred for the transaction. Some of the
1264                                                                     bits are read only and some can be reset
1265                                                                     via a write of 0.                                          */
1266 
1267     struct {
1268       __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
1269                                                      only and can be cleared by disabling the DCMDCMP trigger
1270                                                      enable or by disabling DMA.                                               */
1271       __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
1272                                                      be cleared by disabling the DTHR trigger enable or by disabling
1273                                                      DMA.                                                                      */
1274       __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
1275                                                      in the FIFO was enough to complete the DMA operation (greater
1276                                                      than or equal to current TOTCOUNT) when the command completed.
1277                                                      This trigger is default active when the DCMDCMP trigger
1278                                                      isdisabled and there is enough data in the FIFO to complete
1279                                                      the DMA operation.                                                        */
1280             uint32_t            : 29;
1281     } DMATRIGSTAT_b;
1282   } ;
1283 
1284   union {
1285     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000238) Configuration control of the DMA process, including
1286                                                                     the direction of DMA, and enablement of
1287                                                                     DMA                                                        */
1288 
1289     struct {
1290       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
1291                                                      operation. This should be the last DMA related register
1292                                                      set prior to issuing the command                                          */
1293       __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
1294             uint32_t            : 6;
1295       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
1296       __IOM uint32_t DPWROFF    : 1;            /*!< [9..9] Power off module after DMA is complete. If this bit is
1297                                                      active, the module will request to power off the supply
1298                                                      it is attached to. If there are other units still requiring
1299                                                      power from the same domain, power down will not be performed.             */
1300             uint32_t            : 22;
1301     } DMACFG_b;
1302   } ;
1303 
1304   union {
1305     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x0000023C) Contains the number of bytes to be transferred
1306                                                                     for this DMA transaction. This register
1307                                                                     is decremented as the data is transferred,
1308                                                                     and will be 0 at the completion of the DMA
1309                                                                     operation.                                                 */
1310 
1311     struct {
1312       __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occurred.
1313                                                      Bit is read only and can be cleared by disabling the DTHR
1314                                                      trigger enable or by disabling DMA.                                       */
1315             uint32_t            : 20;
1316     } DMATOTCOUNT_b;
1317   } ;
1318 
1319   union {
1320     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000240) The source or destination address internal the
1321                                                                     SRAM for the DMA data. For write operations,
1322                                                                     this can only be SRAM data (ADDR bit 28
1323                                                                     = 1); For read operations, this can be either
1324                                                                     SRAM or FLASH (ADDR bit 28 = 0)                            */
1325 
1326     struct {
1327       __IOM uint32_t TARGADDR   : 20;           /*!< [19..0] Bits [19:0] of the target byte address for source of
1328                                                      DMA (either read or write). The address can be any byte
1329                                                      alignment, and does not have to be word aligned. In cases
1330                                                      of non-word aligned addresses, the DMA logic will take
1331                                                      care for ensuring only the target bytes are read/written.                 */
1332             uint32_t            : 8;
1333       __IOM uint32_t TARGADDR28 : 1;            /*!< [28..28] Bit 28 of the target byte address for source of DMA
1334                                                      (either read or write). In cases of non-word aligned addresses,
1335                                                      the DMA logic will take care for ensuring only the target
1336                                                      bytes are read/written.Setting to '1' will select the SRAM.
1337                                                      Setting to '0' will select the flash                                      */
1338             uint32_t            : 3;
1339     } DMATARGADDR_b;
1340   } ;
1341 
1342   union {
1343     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000244) Status of the DMA operation currently in progress.         */
1344 
1345     struct {
1346       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
1347                                                      a DMA transfer is active. The DMA transfer may be waiting
1348                                                      on data, transferring data, or waiting for priority.All
1349                                                      of these will be indicated with a 1. A 0 will indicate
1350                                                      that the DMA is fully complete and no further transactions
1351                                                      will be done. This bit is read only.                                      */
1352       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
1353                                                      operation. This bit can be cleared by writing to 0.                       */
1354       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
1355                                                      was encountered during the DMA operation.                                 */
1356             uint32_t            : 29;
1357     } DMASTAT_b;
1358   } ;
1359 
1360   union {
1361     __IOM uint32_t CQCFG;                       /*!< (@ 0x00000248) Controls parameters and options for execution
1362                                                                     of the command queue operation. To enable
1363                                                                     command queue, create this in memory, set
1364                                                                     the address, and enable it with a write
1365                                                                     to CQEN                                                    */
1366 
1367     struct {
1368       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
1369                                                      of the command queue and fetches of address/data pairs
1370                                                      will proceed from the word address within the CQADDR register.
1371                                                      Can be disabledusing a CQ executed write to this bit as
1372                                                      well.                                                                     */
1373       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request.                */
1374             uint32_t            : 30;
1375     } CQCFG_b;
1376   } ;
1377 
1378   union {
1379     __IOM uint32_t CQADDR;                      /*!< (@ 0x0000024C) The SRAM address which will be fetched next execution
1380                                                                     of the CQ operation. This register is updated
1381                                                                     as the CQ operation progresses, and is the
1382                                                                     live version of the register. The register
1383                                                                     can also bewritten by the Command Queue
1384                                                                     operation itself, allowing the relocation
1385                                                                     of successive CQ fetches. In this case,
1386                                                                     the new CQ address will be used for the
1387                                                                     next CQ address/data fetch                                 */
1388 
1389     struct {
1390             uint32_t            : 2;
1391       __IOM uint32_t CQADDR     : 18;           /*!< [19..2] Bits 19:2 of target byte address for source of CQ (read
1392                                                      only). The buffer must be aligned on a word boundary                      */
1393             uint32_t            : 8;
1394       __IOM uint32_t CQADDR28   : 1;            /*!< [28..28] Bit 28 of target byte address for source of CQ (read
1395                                                      only). Used to denote Flash (0) or SRAM (1) access                        */
1396             uint32_t            : 3;
1397     } CQADDR_b;
1398   } ;
1399 
1400   union {
1401     __IOM uint32_t CQSTAT;                      /*!< (@ 0x00000250) Provides the status of the command queue operation.
1402                                                                     If the command queue is disabled, these
1403                                                                     bits will be cleared. The bits are read
1404                                                                     only                                                       */
1405 
1406     struct {
1407       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
1408                                                      indicate that a CQ transfer is active and this will remain
1409                                                      active even when paused waiting for external event.                       */
1410       __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
1411       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing error. This active high bit
1412                                                      signals that an error was encountered during the CQ operation.            */
1413             uint32_t            : 29;
1414     } CQSTAT_b;
1415   } ;
1416 
1417   union {
1418     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x00000254) Provides the current status of the SWFLAGS (bits
1419                                                                     7:0) and the hardware generated flags (15:8).
1420                                                                     A '1' will pause the CQ operation if it
1421                                                                     the same bit is enabled in the CQPAUSEEN
1422                                                                     register                                                   */
1423 
1424     struct {
1425       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
1426                                                      controllable and bits [15:8] are hardware status.                         */
1427       __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Provides for a per-bit mask of the flags used to invoke
1428                                                      an interrupt. A '1' in the bit position will enable the
1429                                                      pause event to trigger the interrupt, if the CQWT_int interrupt
1430                                                      is enabled.Bits definitions are the same as CQPAUSE                       */
1431     } CQFLAGS_b;
1432   } ;
1433 
1434   union {
1435     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x00000258) Set/Clear the command queue software pause flags
1436                                                                     on a per-bit basis. Contains 3 fields, allowing
1437                                                                     for setting, clearing or toggling the value
1438                                                                     in the software flags. Priority when the
1439                                                                     same bitis enabled in each field is toggle,
1440                                                                     then set, then clear.                                      */
1441 
1442     struct {
1443       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
1444                                                      SWFLAG with a '1' in the corresponding bit position of
1445                                                      this field                                                                */
1446       __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
1447                                                      SWFLAG with a '1' in the corresponding bit position of
1448                                                      this field                                                                */
1449       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
1450                                                      with a '1' in the corresponding bit position of this field                */
1451             uint32_t            : 8;
1452     } CQSETCLEAR_b;
1453   } ;
1454 
1455   union {
1456     __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x0000025C) Enables a flag to pause an active command queue
1457                                                                     operation. If a bit is '1' and the corresponding
1458                                                                     bit in the CQFLAG register is '1', CQ processing
1459                                                                     will halt until either value is changed
1460                                                                     to '0'.                                                    */
1461 
1462     struct {
1463       __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
1464                                                      when active                                                               */
1465             uint32_t            : 16;
1466     } CQPAUSEEN_b;
1467   } ;
1468 
1469   union {
1470     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x00000260) Current index value, targeted to be written by
1471                                                                     register write operations within the command
1472                                                                     queue. This is compared to the CQENDIDX
1473                                                                     and will stop the CQ operation if bit 15
1474                                                                     of the CQPAUSEEN is '1' andthis current
1475                                                                     index equals the CQENDIDX register value.
1476                                                                     This will only pause when the values are
1477                                                                     equal.                                                     */
1478 
1479     struct {
1480       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
1481                                                      register field. If the values match, the IDXEQ pause event
1482                                                      will be activated, which will cause the pausing of command
1483                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
1484             uint32_t            : 24;
1485     } CQCURIDX_b;
1486   } ;
1487 
1488   union {
1489     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x00000264) End index value, targeted to be written by software
1490                                                                     to indicate the last valid register pair
1491                                                                     contained within the command queue for register
1492                                                                     write operations within the command queue.This
1493                                                                     is compared to the CQCURIDX and will stop
1494                                                                     the CQ operation if bit 15 of the CQPAUSEEN
1495                                                                     is '1' andthis current index equals the
1496                                                                     CQCURIDX register value. This will only
1497                                                                     pause when the values are equal.                           */
1498 
1499     struct {
1500       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
1501                                                      register field. If the values match, the IDXEQ pause event
1502                                                      will be activated, which will cause the pausing of command
1503                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
1504             uint32_t            : 24;
1505     } CQENDIDX_b;
1506   } ;
1507 
1508   union {
1509     __IOM uint32_t STATUS;                      /*!< (@ 0x00000268) General status of the IOM module command execution.        */
1510 
1511     struct {
1512       __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
1513                                                      indicators. This will always return 0.                                    */
1514       __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
1515                                                      a transaction, or command is complete, but the FIFO pointers
1516                                                      are still synchronizing internally. This bit will go high
1517                                                      atthe start of the transaction, and will go low when the
1518                                                      command is complete, and the data and pointers within the
1519                                                      FIFO have been synchronized.                                              */
1520       __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
1521                                                      - The state machine could be in idle state due to hold-offs
1522                                                      from data availability, or as the command gets propagated
1523                                                      into the logic from the registers.                                        */
1524             uint32_t            : 29;
1525     } STATUS_b;
1526   } ;
1527   __IM  uint32_t  RESERVED4[37];
1528 
1529   union {
1530     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000300) Controls the configuration of the SPI master
1531                                                                     module, including POL/PHA, LSB, flow control,
1532                                                                     and delays for MISO and MOSI                               */
1533 
1534     struct {
1535       __IOM uint32_t SPOL       : 1;            /*!< [0..0] This bit selects SPI polarity.                                     */
1536       __IOM uint32_t SPHA       : 1;            /*!< [1..1] Selects the SPI phase; When 1, will shift the sampling
1537                                                      edge by 1/2 clock.                                                        */
1538       __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Full Duplex mode. Capture read data during writes operations       */
1539             uint32_t            : 13;
1540       __IOM uint32_t WTFC       : 1;            /*!< [16..16] Enables flow control of new write transactions based
1541                                                      on the SPI_STATUS signal from the BLE Core.                               */
1542       __IOM uint32_t RDFC       : 1;            /*!< [17..17] Enables flow control of new read transactions based
1543                                                      on the SPI_STATUS signal from the BLE Core.                               */
1544             uint32_t            : 3;
1545       __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] Selects the write flow control signal polarity. The
1546                                                      transfers are halted when the selected flow control signal
1547                                                      is OPPOSITE polarity of this bit. (For example: WTFCPOL
1548                                                      = 0 will allow a SPI_STATUS=1 to pause transfers).                        */
1549       __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] Selects the read flow control signal polarity. When
1550                                                      set, the clock will be held low until the flow control
1551                                                      is deasserted.                                                            */
1552       __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
1553                                                      (1) for the data portion of the SPI transaction. The offset
1554                                                      bytes are always transmitted MSB first.                                   */
1555       __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
1556                                                      gives more hold time on the input data.                                   */
1557       __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
1558                                                      give more hold time on the output data.                                   */
1559       __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Bit is deprecated. setting it will have no effect.               */
1560             uint32_t            : 1;
1561     } MSPICFG_b;
1562   } ;
1563 
1564   union {
1565     __IOM uint32_t BLECFG;                      /*!< (@ 0x00000304) Provides control of isolation and IO signals
1566                                                                     between the interface module and the BLE
1567                                                                     Core.                                                      */
1568 
1569     struct {
1570       __IOM uint32_t PWRSMEN    : 1;            /*!< [0..0] Enable the power state machine for automatic sequencing
1571                                                      and control of power states of the BLE Core module.                       */
1572       __IOM uint32_t BLERSTN    : 1;            /*!< [1..1] Reset line to the BLE Core. This will reset the BLE core
1573                                                      when asserted ('0') and must be written to '1' prior to
1574                                                      performing any BTLE related operations to the core.                       */
1575       __IOM uint32_t WAKEUPCTL  : 2;            /*!< [3..2] WAKE signal override. Controls the source of the WAKE
1576                                                      signal to the BLE Core.                                                   */
1577       __IOM uint32_t DCDCFLGCTL : 2;            /*!< [5..4] DCDCFLG signal override. The value of this field will
1578                                                      be sent to the BLE Core when the PWRSM is off. Otherwise,
1579                                                      the value is supplied from internal logic.                                */
1580       __IOM uint32_t BLEHREQCTL : 2;            /*!< [7..6] BLEH power on request override. The value of this field
1581                                                      will be sent to the BLE Core when the PWRSM is off. Otherwise,
1582                                                      the value is supplied from internal logic.                                */
1583       __IOM uint32_t WT4ACTOFF  : 1;            /*!< [8..8] Debug control of BLEIF power state machine. Allows transition
1584                                                      into the active state in the BLEIF state without waiting
1585                                                      for DCDC request from BLE Core.                                           */
1586       __IOM uint32_t MCUFRCSLP  : 1;            /*!< [9..9] Force power state machine to go to the sleep state. Intended
1587                                                      for debug only. Has no effect on the actual BLE Core state,
1588                                                      only the state of the BLEIF interface state machine.                      */
1589       __IOM uint32_t FRCCLK     : 1;            /*!< [10..10] Force the clock in the BLEIF to be always running                */
1590       __IOM uint32_t STAYASLEEP : 1;            /*!< [11..11] Set to prevent the BLE power control module from waking
1591                                                      up the BLE Core after going into power down. To be used
1592                                                      for graceful shutdown, set by software prior to powering
1593                                                      off and will allow assertion of reset from sleep state.                   */
1594       __IOM uint32_t PWRISOCTL  : 2;            /*!< [13..12] Configuration of BLEH isolation control for power related
1595                                                      signals.                                                                  */
1596       __IOM uint32_t SPIISOCTL  : 2;            /*!< [15..14] Configuration of BLEH isolation controls for SPI related
1597                                                      signals.                                                                  */
1598             uint32_t            : 16;
1599     } BLECFG_b;
1600   } ;
1601 
1602   union {
1603     __IOM uint32_t PWRCMD;                      /*!< (@ 0x00000308) Sends power related commands to the power state
1604                                                                     machine in the BLE IF module.                              */
1605 
1606     struct {
1607       __IOM uint32_t WAKEREQ    : 1;            /*!< [0..0] Wake request from the MCU. When asserted (1), the BLE
1608                                                      Interface logic will assert the wakeup request signal to
1609                                                      the BLE Core. Only recognized when in the sleep state                     */
1610       __IOM uint32_t RESTART    : 1;            /*!< [1..1] Restart the BLE Core after going into the shutdown state.
1611                                                      Only valid when in the shutdown state.                                    */
1612             uint32_t            : 30;
1613     } PWRCMD_b;
1614   } ;
1615 
1616   union {
1617     __IOM uint32_t BSTATUS;                     /*!< (@ 0x0000030C) Status of the BLE Core interface signals                   */
1618 
1619     struct {
1620       __IOM uint32_t B2MSTATE   : 3;            /*!< [2..0] State of the BLE Core logic.                                       */
1621       __IOM uint32_t SPISTATUS  : 1;            /*!< [3..3] Value of the SPISTATUS signal from the BLE Core. The
1622                                                      signal is asserted when the BLE Core is able to accept
1623                                                      write data via the SPI interface. Data should be transmitted
1624                                                      to theBLE core only when this signal is 1. The hardware
1625                                                      will automatically wait for this signal prior to performing
1626                                                      a write operation if flow control is active.                              */
1627       __IOM uint32_t DCDCREQ    : 1;            /*!< [4..4] Value of the DCDCREQ signal from the BLE Core. The DCDCREQ
1628                                                      signal is sent from the core to the BLEIF module when the
1629                                                      BLE core requires BLEH power to be active. When activated,
1630                                                      this isindicated by DCDCFLAG going to 1.                                  */
1631       __IOM uint32_t DCDCFLAG   : 1;            /*!< [5..5] Value of the DCDCFLAG signal to the BLE Core. The DCDCFLAG
1632                                                      is a signal to the BLE Core indicating that the BLEH power
1633                                                      is active.                                                                */
1634       __IOM uint32_t WAKEUP     : 1;            /*!< [6..6] Value of the WAKEUP signal to the BLE Core . The WAKEUP
1635                                                      signals is sent from the BLEIF to the BLECORE to request
1636                                                      the BLE Core transition from sleep state to active state.                 */
1637       __IOM uint32_t BLEIRQ     : 1;            /*!< [7..7] Status of the BLEIRQ signal from the BLE Core. A value
1638                                                      of 1 indicates that read data is available in the core
1639                                                      and a read operation needs to be performed.                               */
1640       __IOM uint32_t PWRST      : 3;            /*!< [10..8] Current status of the power state machine                         */
1641       __IOM uint32_t BLEHACK    : 1;            /*!< [11..11] Value of the BLEHACK signal from the power control
1642                                                      unit. If the signal is '1', the BLEH power is active and
1643                                                      ready for use.                                                            */
1644       __IOM uint32_t BLEHREQ    : 1;            /*!< [12..12] Value of the BLEHREQ signal to the power control unit.
1645                                                      The BLEHREQ signal is sent from the BLEIF module to the
1646                                                      power control module to request the BLEH power up. When
1647                                                      the BLEHACK signal is asserted,BLEH power is stable and
1648                                                      ready for use.                                                            */
1649             uint32_t            : 19;
1650     } BSTATUS_b;
1651   } ;
1652   __IM  uint32_t  RESERVED5[64];
1653 
1654   union {
1655     __IOM uint32_t BLEDBG;                      /*!< (@ 0x00000410) Debug control                                              */
1656 
1657     struct {
1658       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting this bit will enable the update
1659                                                      of data within this register, otherwise it is clock gated
1660                                                      for power savings                                                         */
1661       __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
1662                                                      when this bit is '1'. Otherwise, the clock is controlled
1663                                                      with gating from the logic as needed.                                     */
1664       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
1665                                                      when this bit is '1'. Otherwise, the clock is controlled
1666                                                      with gating from the logic as needed.                                     */
1667       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug data                                                        */
1668     } BLEDBG_b;
1669   } ;
1670 } BLEIF_Type;                                   /*!< Size = 1044 (0x414)                                                       */
1671 
1672 
1673 
1674 /* =========================================================================================================================== */
1675 /* ================                                         CACHECTRL                                         ================ */
1676 /* =========================================================================================================================== */
1677 
1678 
1679 /**
1680   * @brief FLASH Cache Controller (CACHECTRL)
1681   */
1682 
1683 typedef struct {                                /*!< (@ 0x40018000) CACHECTRL Structure                                        */
1684 
1685   union {
1686     __IOM uint32_t CACHECFG;                    /*!< (@ 0x00000000) FLASH Cache Control                                        */
1687 
1688     struct {
1689       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Enables the FLASH cache controller and enables power
1690                                                      to the cache SRAMs. The ICACHE_ENABLE and DCACHE_ENABLE
1691                                                      should be set to enable caching for each type of access.                  */
1692       __IOM uint32_t LRU        : 1;            /*!< [1..1] Sets the cache replacement policy. 0=LRR (least recently
1693                                                      replaced), 1=LRU (least recently used). LRR minimizes writes
1694                                                      to the TAG SRAM.                                                          */
1695       __IOM uint32_t ENABLE_NC0 : 1;            /*!< [2..2] Enable Non-cacheable region 0. See NCR0 registers to
1696                                                      define the region.                                                        */
1697       __IOM uint32_t ENABLE_NC1 : 1;            /*!< [3..3] Enable Non-cacheable region 1. See NCR1 registers to
1698                                                      define the region.                                                        */
1699       __IOM uint32_t CONFIG     : 4;            /*!< [7..4] Sets the cache configuration                                       */
1700       __IOM uint32_t ICACHE_ENABLE : 1;         /*!< [8..8] Enable FLASH Instruction Caching                                   */
1701       __IOM uint32_t DCACHE_ENABLE : 1;         /*!< [9..9] Enable FLASH Data Caching                                          */
1702       __IOM uint32_t CACHE_CLKGATE : 1;         /*!< [10..10] Enable clock gating of cache TAG RAM. Software should
1703                                                      enable this bit for optimal power efficiency.                             */
1704       __IOM uint32_t CACHE_LS   : 1;            /*!< [11..11] Enable LS (light sleep) of cache RAMs. Software should
1705                                                      DISABLE this bit since cache activity is too high to benefit
1706                                                      from LS usage.                                                            */
1707             uint32_t            : 8;
1708       __IOM uint32_t DATA_CLKGATE : 1;          /*!< [20..20] Enable aggressive clock gating of entire data array.
1709                                                      This bit should be set to 1 for optimal power efficiency.                 */
1710             uint32_t            : 3;
1711       __IOM uint32_t ENABLE_MONITOR : 1;        /*!< [24..24] Enable Cache Monitoring Stats. Cache monitoring consumes
1712                                                      additional power and should only be enabled when profiling
1713                                                      code and counters will increment when this bit is set.
1714                                                      Counter values will be retained when this is set to 0,
1715                                                      allowing software to enable/disable counting for multiple
1716                                                      code segments.                                                            */
1717             uint32_t            : 7;
1718     } CACHECFG_b;
1719   } ;
1720 
1721   union {
1722     __IOM uint32_t FLASHCFG;                    /*!< (@ 0x00000004) FLASH Control Register                                     */
1723 
1724     struct {
1725       __IOM uint32_t RD_WAIT    : 4;            /*!< [3..0] Sets read waitstates for normal (fast) operation. A value
1726                                                      of 1 is recommended.                                                      */
1727       __IOM uint32_t SEDELAY    : 3;            /*!< [6..4] Sets SE delay (FLASH address setup). A value of 5 is
1728                                                      recommended.                                                              */
1729             uint32_t            : 1;
1730       __IOM uint32_t LPM_RD_WAIT : 4;           /*!< [11..8] Sets FLASH waitstates when in LPM Mode 2 (RD_WAIT in
1731                                                      LPM mode 2 only)                                                          */
1732       __IOM uint32_t LPMMODE    : 2;            /*!< [13..12] Controls FLASH low power modes (control of LPM pin).             */
1733             uint32_t            : 18;
1734     } FLASHCFG_b;
1735   } ;
1736 
1737   union {
1738     __IOM uint32_t CTRL;                        /*!< (@ 0x00000008) Cache Control                                              */
1739 
1740     struct {
1741       __IOM uint32_t INVALIDATE : 1;            /*!< [0..0] Writing a 1 to this bit field invalidates the FLASH cache
1742                                                      contents.                                                                 */
1743       __IOM uint32_t RESET_STAT : 1;            /*!< [1..1] Reset Cache Statistics. When written to a 1, the cache
1744                                                      monitor counters will be cleared. The monitor counters
1745                                                      can be reset only when the CACHECFG.ENABLE_MONITOR bit
1746                                                      is set.                                                                   */
1747       __IOM uint32_t CACHE_READY : 1;           /*!< [2..2] Cache Ready Status (enabled and not processing an invalidate
1748                                                      operation)                                                                */
1749             uint32_t            : 1;
1750       __IOM uint32_t FLASH0_SLM_STATUS : 1;     /*!< [4..4] FLASH Sleep Mode Status. 1 indicates that FLASH0 is in
1751                                                      sleep mode, 0 indicates FLASH0 is in normal mode.                         */
1752       __IOM uint32_t FLASH0_SLM_DISABLE : 1;    /*!< [5..5] Disable FLASH Sleep Mode. Write 1 to wake FLASH0 from
1753                                                      sleep mode (reading the array will also automatically wake
1754                                                      it).                                                                      */
1755       __IOM uint32_t FLASH0_SLM_ENABLE : 1;     /*!< [6..6] Enable FLASH Sleep Mode. Write to 1 to put FLASH0 into
1756                                                      sleep mode. NOTE: there is a 5 us latency after waking
1757                                                      FLASH until the first access will be returned.                            */
1758             uint32_t            : 1;
1759       __IOM uint32_t FLASH1_SLM_STATUS : 1;     /*!< [8..8] FLASH Sleep Mode Status. 1 indicates that FLASH1 is in
1760                                                      sleep mode, 0 indicates FLASH1 is in normal mode.                         */
1761       __IOM uint32_t FLASH1_SLM_DISABLE : 1;    /*!< [9..9] Disable FLASH Sleep Mode. Write 1 to wake FLASH1 from
1762                                                      sleep mode (reading the array will also automatically wake
1763                                                      it).                                                                      */
1764       __IOM uint32_t FLASH1_SLM_ENABLE : 1;     /*!< [10..10] Enable FLASH Sleep Mode. Write to 1 to put FLASH1 into
1765                                                      sleep mode. NOTE: there is a 5 us latency after waking
1766                                                      FLASH until the first access will be returned.                            */
1767             uint32_t            : 21;
1768     } CTRL_b;
1769   } ;
1770   __IM  uint32_t  RESERVED;
1771 
1772   union {
1773     __IOM uint32_t NCR0START;                   /*!< (@ 0x00000010) FLASH Cache Noncacheable Region 0 Start                    */
1774 
1775     struct {
1776             uint32_t            : 4;
1777       __IOM uint32_t ADDR       : 23;           /*!< [26..4] Start address for non-cacheable region 0                          */
1778             uint32_t            : 5;
1779     } NCR0START_b;
1780   } ;
1781 
1782   union {
1783     __IOM uint32_t NCR0END;                     /*!< (@ 0x00000014) FLASH Cache Noncacheable Region 0 End                      */
1784 
1785     struct {
1786             uint32_t            : 4;
1787       __IOM uint32_t ADDR       : 23;           /*!< [26..4] End address for non-cacheable region 0                            */
1788             uint32_t            : 5;
1789     } NCR0END_b;
1790   } ;
1791 
1792   union {
1793     __IOM uint32_t NCR1START;                   /*!< (@ 0x00000018) FLASH Cache Noncacheable Region 1 Start                    */
1794 
1795     struct {
1796             uint32_t            : 4;
1797       __IOM uint32_t ADDR       : 23;           /*!< [26..4] Start address for non-cacheable region 1                          */
1798             uint32_t            : 5;
1799     } NCR1START_b;
1800   } ;
1801 
1802   union {
1803     __IOM uint32_t NCR1END;                     /*!< (@ 0x0000001C) FLASH Cache Noncacheable Region 1 End                      */
1804 
1805     struct {
1806             uint32_t            : 4;
1807       __IOM uint32_t ADDR       : 23;           /*!< [26..4] End address for non-cacheable region 1                            */
1808             uint32_t            : 5;
1809     } NCR1END_b;
1810   } ;
1811   __IM  uint32_t  RESERVED1[8];
1812 
1813   union {
1814     __IOM uint32_t DMON0;                       /*!< (@ 0x00000040) Data Cache Total Accesses                                  */
1815 
1816     struct {
1817       __IOM uint32_t DACCESS_COUNT : 32;        /*!< [31..0] Total accesses to data cache. All performance metrics
1818                                                      should be relative to the number of accesses performed.                   */
1819     } DMON0_b;
1820   } ;
1821 
1822   union {
1823     __IOM uint32_t DMON1;                       /*!< (@ 0x00000044) Data Cache Tag Lookups                                     */
1824 
1825     struct {
1826       __IOM uint32_t DLOOKUP_COUNT : 32;        /*!< [31..0] Total tag lookups from data cache.                                */
1827     } DMON1_b;
1828   } ;
1829 
1830   union {
1831     __IOM uint32_t DMON2;                       /*!< (@ 0x00000048) Data Cache Hits                                            */
1832 
1833     struct {
1834       __IOM uint32_t DHIT_COUNT : 32;           /*!< [31..0] Cache hits from lookup operations.                                */
1835     } DMON2_b;
1836   } ;
1837 
1838   union {
1839     __IOM uint32_t DMON3;                       /*!< (@ 0x0000004C) Data Cache Line Hits                                       */
1840 
1841     struct {
1842       __IOM uint32_t DLINE_COUNT : 32;          /*!< [31..0] Cache hits from line cache                                        */
1843     } DMON3_b;
1844   } ;
1845 
1846   union {
1847     __IOM uint32_t IMON0;                       /*!< (@ 0x00000050) Instruction Cache Total Accesses                           */
1848 
1849     struct {
1850       __IOM uint32_t IACCESS_COUNT : 32;        /*!< [31..0] Total accesses to Instruction cache                               */
1851     } IMON0_b;
1852   } ;
1853 
1854   union {
1855     __IOM uint32_t IMON1;                       /*!< (@ 0x00000054) Instruction Cache Tag Lookups                              */
1856 
1857     struct {
1858       __IOM uint32_t ILOOKUP_COUNT : 32;        /*!< [31..0] Total tag lookups from Instruction cache                          */
1859     } IMON1_b;
1860   } ;
1861 
1862   union {
1863     __IOM uint32_t IMON2;                       /*!< (@ 0x00000058) Instruction Cache Hits                                     */
1864 
1865     struct {
1866       __IOM uint32_t IHIT_COUNT : 32;           /*!< [31..0] Cache hits from lookup operations                                 */
1867     } IMON2_b;
1868   } ;
1869 
1870   union {
1871     __IOM uint32_t IMON3;                       /*!< (@ 0x0000005C) Instruction Cache Line Hits                                */
1872 
1873     struct {
1874       __IOM uint32_t ILINE_COUNT : 32;          /*!< [31..0] Cache hits from line cache                                        */
1875     } IMON3_b;
1876   } ;
1877 } CACHECTRL_Type;                               /*!< Size = 96 (0x60)                                                          */
1878 
1879 
1880 
1881 /* =========================================================================================================================== */
1882 /* ================                                          CLKGEN                                           ================ */
1883 /* =========================================================================================================================== */
1884 
1885 
1886 /**
1887   * @brief Clock Generator (CLKGEN)
1888   */
1889 
1890 typedef struct {                                /*!< (@ 0x40004000) CLKGEN Structure                                           */
1891 
1892   union {
1893     __IOM uint32_t CALXT;                       /*!< (@ 0x00000000) This is the XT Oscillator Calibration value.
1894                                                                     This value allows any derived XT clocks
1895                                                                     to be calibrated. This means that the original
1896                                                                     32KHz version of XT will not be changed,
1897                                                                     but a 16KHz version (divided down version)
1898                                                                     can be modified. This register value will
1899                                                                     add or subtract the number of cycles programmed
1900                                                                     in this register across a 32 seconds interval.
1901                                                                     For example, if a value of 100 is programmed
1902                                                                     in this register, then 100 additional clock
1903                                                                     cycles will be added into a 16KHz clock
1904                                                                     period across                                              */
1905 
1906     struct {
1907       __IOM uint32_t CALXT      : 11;           /*!< [10..0] XT Oscillator calibration value. This register will
1908                                                      enable the hardware to increase or decrease the number
1909                                                      of cycles in a 16KHz clock derived from the original 32KHz
1910                                                      version. The most significant bit is the sign. A '1' is
1911                                                      a reduction, and a '0' is an addition. This calibration
1912                                                      value will add or reduce the number of cycles programmed
1913                                                      here across a 32 second interval. The maximum value that
1914                                                      is effective is from -976 to 975.                                         */
1915             uint32_t            : 21;
1916     } CALXT_b;
1917   } ;
1918 
1919   union {
1920     __IOM uint32_t CALRC;                       /*!< (@ 0x00000004) This is the LFRC Calibration value. Similar to
1921                                                                     the XT calibration, it allows the derived
1922                                                                     LFRC clock to be calibrated. The original
1923                                                                     1024Hz clock source will not change, but
1924                                                                     a 512Hz version (divided down version) can
1925                                                                     be modified. This register will add or subtract
1926                                                                     the number of cycles programmed in this
1927                                                                     register across a 1024 seconds interval.
1928                                                                     For example, if a value of 200 is programmed
1929                                                                     in this register, then 200 additional clocks
1930                                                                     will be added into the 512Hz derived clock
1931                                                                     across a 1024 secon                                        */
1932 
1933     struct {
1934       __IOM uint32_t CALRC      : 18;           /*!< [17..0] LFRC Oscillator calibration value. This register will
1935                                                      enable the hardware to increase or decrease the number
1936                                                      of cycles in a 512 Hz clock derived from the original 1024
1937                                                      version. The most significant bit is the sign. A '1' is
1938                                                      a reduction, and a '0' is an addition. This calibration
1939                                                      value will add or reduce the number of cycles programmed
1940                                                      here across a 32 second interval. The range is from -131072
1941                                                      (decimal) to 131071 (decimal). This register is normally
1942                                                      used in conjunction with ACALCTR register. The CALRC regi                 */
1943             uint32_t            : 14;
1944     } CALRC_b;
1945   } ;
1946 
1947   union {
1948     __IOM uint32_t ACALCTR;                     /*!< (@ 0x00000008) This register can be used for 2 purposes. The
1949                                                                     first is to calibrate the LFRC clock using
1950                                                                     the XT clock source. The second is to measure
1951                                                                     an internal clock signal relative to the
1952                                                                     external clock. In that case, the ACALCTR
1953                                                                     will show the multiple of the external clock
1954                                                                     with respect to the internal clock signal.
1955                                                                     E.g. Fref = Fmeas x ACALCTR. Note that this
1956                                                                     register should not be confused with the
1957                                                                     HFRC Adjustment register, which is separately
1958                                                                     defined in CLKGEN_HFADJ register.                          */
1959 
1960     struct {
1961       __IOM uint32_t ACALCTR    : 24;           /*!< [23..0] Autocalibration Counter result. Bits 17 down to 0 of
1962                                                      this is feed directly to the CALRC register if ACAL register
1963                                                      in OCTRL register is set to 1024SEC or 512SEC.                            */
1964             uint32_t            : 8;
1965     } ACALCTR_b;
1966   } ;
1967 
1968   union {
1969     __IOM uint32_t OCTRL;                       /*!< (@ 0x0000000C) This register includes controls for autocalibration
1970                                                                     in addition to the RTC oscillator controls.                */
1971 
1972     struct {
1973       __IOM uint32_t STOPXT     : 1;            /*!< [0..0] Stop the XT Oscillator to the RTC                                  */
1974       __IOM uint32_t STOPRC     : 1;            /*!< [1..1] Stop the LFRC Oscillator to the RTC                                */
1975             uint32_t            : 4;
1976       __IOM uint32_t FOS        : 1;            /*!< [6..6] Oscillator switch on failure function. If this is set,
1977                                                      then LFRC clock source will switch from XT to RC.                         */
1978       __IOM uint32_t OSEL       : 1;            /*!< [7..7] Selects the RTC oscillator (1 => LFRC, 0 => XT)                    */
1979       __IOM uint32_t ACAL       : 3;            /*!< [10..8] Autocalibration control. This selects the source to
1980                                                      be used in the autocalibration flow. This flow can also
1981                                                      be used to measure an internal clock against an external
1982                                                      clock source, with the external clock normally used as
1983                                                      the reference.                                                            */
1984             uint32_t            : 21;
1985     } OCTRL_b;
1986   } ;
1987 
1988   union {
1989     __IOM uint32_t CLKOUT;                      /*!< (@ 0x00000010) This register enables the CLKOUT to the GPIOs,
1990                                                                     and selects the clock source to that.                      */
1991 
1992     struct {
1993       __IOM uint32_t CKSEL      : 6;            /*!< [5..0] CLKOUT signal select                                               */
1994             uint32_t            : 1;
1995       __IOM uint32_t CKEN       : 1;            /*!< [7..7] Enable the CLKOUT signal                                           */
1996             uint32_t            : 24;
1997     } CLKOUT_b;
1998   } ;
1999 
2000   union {
2001     __IOM uint32_t CLKKEY;                      /*!< (@ 0x00000014) This controls the write access to the CCTRL register.
2002                                                                     This prevents customers from accidentally
2003                                                                     setting the HFRC clocks to be half of what
2004                                                                     they are set to.                                           */
2005 
2006     struct {
2007       __IOM uint32_t CLKKEY     : 32;           /*!< [31..0] Key register value.                                               */
2008     } CLKKEY_b;
2009   } ;
2010 
2011   union {
2012     __IOM uint32_t CCTRL;                       /*!< (@ 0x00000018) This register controls the main divider for HFRC
2013                                                                     clock. If this is set, all internal HFRC
2014                                                                     clock sources are divided by 2.                            */
2015 
2016     struct {
2017       __IOM uint32_t CORESEL    : 1;            /*!< [0..0] Core Clock divisor                                                 */
2018             uint32_t            : 31;
2019     } CCTRL_b;
2020   } ;
2021 
2022   union {
2023     __IOM uint32_t STATUS;                      /*!< (@ 0x0000001C) This register provides status to the XT oscillator
2024                                                                     and the source of the RTC.                                 */
2025 
2026     struct {
2027       __IOM uint32_t OMODE      : 1;            /*!< [0..0] Current RTC oscillator (1 => LFRC, 0 => XT). After an
2028                                                      RTC oscillator change, it may take up to 2 seconds for
2029                                                      this field to reflect the new oscillator.                                 */
2030       __IOM uint32_t OSCF       : 1;            /*!< [1..1] XT Oscillator is enabled but not oscillating                       */
2031             uint32_t            : 30;
2032     } STATUS_b;
2033   } ;
2034 
2035   union {
2036     __IOM uint32_t HFADJ;                       /*!< (@ 0x00000020) This register controls the HFRC adjustment. The
2037                                                                     HFRC clock can change with temperature and
2038                                                                     process corners, and this register controls
2039                                                                     the HFRC adjustment logic which reduces
2040                                                                     the fluctuations to the clock.                             */
2041 
2042     struct {
2043       __IOM uint32_t HFADJEN    : 1;            /*!< [0..0] HFRC adjustment control                                            */
2044       __IOM uint32_t HFADJCK    : 3;            /*!< [3..1] Repeat period for HFRC adjustment                                  */
2045             uint32_t            : 4;
2046       __IOM uint32_t HFXTADJ    : 12;           /*!< [19..8] Target HFRC adjustment value.                                     */
2047       __IOM uint32_t HFWARMUP   : 1;            /*!< [20..20] XT warm-up period for HFRC adjustment                            */
2048       __IOM uint32_t HFADJGAIN  : 3;            /*!< [23..21] Gain control for HFRC adjustment                                 */
2049             uint32_t            : 8;
2050     } HFADJ_b;
2051   } ;
2052   __IM  uint32_t  RESERVED;
2053 
2054   union {
2055     __IOM uint32_t CLOCKENSTAT;                 /*!< (@ 0x00000028) This register provides the enable status to all
2056                                                                     the peripheral clocks.                                     */
2057 
2058     struct {
2059       __IOM uint32_t CLOCKENSTAT : 32;          /*!< [31..0] Clock enable status                                               */
2060     } CLOCKENSTAT_b;
2061   } ;
2062 
2063   union {
2064     __IOM uint32_t CLOCKEN2STAT;                /*!< (@ 0x0000002C) This is a continuation of the clock enable status.         */
2065 
2066     struct {
2067       __IOM uint32_t CLOCKEN2STAT : 32;         /*!< [31..0] Clock enable status 2                                             */
2068     } CLOCKEN2STAT_b;
2069   } ;
2070 
2071   union {
2072     __IOM uint32_t CLOCKEN3STAT;                /*!< (@ 0x00000030) This is a continuation of the clock enable status.         */
2073 
2074     struct {
2075       __IOM uint32_t CLOCKEN3STAT : 32;         /*!< [31..0] Clock enable status 3                                             */
2076     } CLOCKEN3STAT_b;
2077   } ;
2078 
2079   union {
2080     __IOM uint32_t FREQCTRL;                    /*!< (@ 0x00000034) This register provides the burst control and
2081                                                                     burst status.                                              */
2082 
2083     struct {
2084       __IOM uint32_t BURSTREQ   : 1;            /*!< [0..0] Frequency Burst Enable Request                                     */
2085       __IOM uint32_t BURSTACK   : 1;            /*!< [1..1] Frequency Burst Request Acknowledge. Frequency burst
2086                                                      requested is always acknowledged whether burst is granted
2087                                                      or not depending on feature enable.                                       */
2088       __IOM uint32_t BURSTSTATUS : 1;           /*!< [2..2] This represents frequency burst status.                            */
2089             uint32_t            : 29;
2090     } FREQCTRL_b;
2091   } ;
2092   __IM  uint32_t  RESERVED1;
2093 
2094   union {
2095     __IOM uint32_t BLEBUCKTONADJ;               /*!< (@ 0x0000003C) This is the register control for BLE ton adjustment
2096                                                                     logic.                                                     */
2097 
2098     struct {
2099       __IOM uint32_t TONLOWTHRESHOLD : 10;      /*!< [9..0] TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz)
2100                                                      #15(47KHz) #53(12Khz) #14D(3Khz)                                          */
2101       __IOM uint32_t TONHIGHTHRESHOLD : 10;     /*!< [19..10] TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz)
2102                                                      #2A(47Khz) #A6(12Khz) #29A(3Khz)                                          */
2103       __IOM uint32_t TONADJUSTPERIOD : 2;       /*!< [21..20] TON ADJUST PERIOD                                                */
2104       __IOM uint32_t TONADJUSTEN : 1;           /*!< [22..22] TON ADJUST ENABLE                                                */
2105       __IOM uint32_t ZEROLENDETECTTRIM : 4;     /*!< [26..23] BLEBUCK ZERO LENGTH DETECT TRIM                                  */
2106       __IOM uint32_t ZEROLENDETECTEN : 1;       /*!< [27..27] BLEBUCK ZERO LENGTH DETECT ENABLE                                */
2107             uint32_t            : 4;
2108     } BLEBUCKTONADJ_b;
2109   } ;
2110   __IM  uint32_t  RESERVED2[48];
2111 
2112   union {
2113     __IOM uint32_t INTRPTEN;                    /*!< (@ 0x00000100) Set bits in this register to allow this module
2114                                                                     to generate the corresponding interrupt.                   */
2115 
2116     struct {
2117       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2118       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2119       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2120             uint32_t            : 29;
2121     } INTRPTEN_b;
2122   } ;
2123 
2124   union {
2125     __IOM uint32_t INTRPTSTAT;                  /*!< (@ 0x00000104) Read bits from this register to discover the
2126                                                                     cause of a recent interrupt.                               */
2127 
2128     struct {
2129       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2130       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2131       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2132             uint32_t            : 29;
2133     } INTRPTSTAT_b;
2134   } ;
2135 
2136   union {
2137     __IOM uint32_t INTRPTCLR;                   /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
2138                                                                     the interrupt status associated with that
2139                                                                     bit.                                                       */
2140 
2141     struct {
2142       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2143       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2144       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2145             uint32_t            : 29;
2146     } INTRPTCLR_b;
2147   } ;
2148 
2149   union {
2150     __IOM uint32_t INTRPTSET;                   /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
2151                                                                     generate an interrupt from this module.
2152                                                                     (Generally used for testing purposes).                     */
2153 
2154     struct {
2155       __IOM uint32_t ACF        : 1;            /*!< [0..0] Autocalibration Fail interrupt                                     */
2156       __IOM uint32_t ACC        : 1;            /*!< [1..1] Autocalibration Complete interrupt                                 */
2157       __IOM uint32_t OF         : 1;            /*!< [2..2] XT Oscillator Fail interrupt                                       */
2158             uint32_t            : 29;
2159     } INTRPTSET_b;
2160   } ;
2161 } CLKGEN_Type;                                  /*!< Size = 272 (0x110)                                                        */
2162 
2163 
2164 
2165 /* =========================================================================================================================== */
2166 /* ================                                          CTIMER                                           ================ */
2167 /* =========================================================================================================================== */
2168 
2169 
2170 /**
2171   * @brief Counter/Timer (CTIMER)
2172   */
2173 
2174 typedef struct {                                /*!< (@ 0x40008000) CTIMER Structure                                           */
2175 
2176   union {
2177     __IOM uint32_t TMR0;                        /*!< (@ 0x00000000) This register holds the running time or event
2178                                                                     count for CTIMER 0. This is either for each
2179                                                                     16 bit half or for the whole 32 bit count
2180                                                                     when the pair is linked. If the pair is
2181                                                                     not linked, they can be running on separate
2182                                                                     clocks and are completely independent.                     */
2183 
2184     struct {
2185       __IOM uint32_t CTTMRA0    : 16;           /*!< [15..0] Counter/Timer A0.                                                 */
2186       __IOM uint32_t CTTMRB0    : 16;           /*!< [31..16] Counter/Timer B0.                                                */
2187     } TMR0_b;
2188   } ;
2189 
2190   union {
2191     __IOM uint32_t CMPRA0;                      /*!< (@ 0x00000004) This contains the Compare limits for timer 0
2192                                                                     half A.                                                    */
2193 
2194     struct {
2195       __IOM uint32_t CMPR0A0    : 16;           /*!< [15..0] Counter/Timer A0 Compare Register 0. Holds the lower
2196                                                      limit for timer half A.                                                   */
2197       __IOM uint32_t CMPR1A0    : 16;           /*!< [31..16] Counter/Timer A0 Compare Register 1. Holds the upper
2198                                                      limit for timer half A.                                                   */
2199     } CMPRA0_b;
2200   } ;
2201 
2202   union {
2203     __IOM uint32_t CMPRB0;                      /*!< (@ 0x00000008) This contains the Compare limits for timer 0
2204                                                                     B half.                                                    */
2205 
2206     struct {
2207       __IOM uint32_t CMPR0B0    : 16;           /*!< [15..0] Counter/Timer B0 Compare Register 0. Holds the lower
2208                                                      limit for timer half B.                                                   */
2209       __IOM uint32_t CMPR1B0    : 16;           /*!< [31..16] Counter/Timer B0 Compare Register 1. Holds the upper
2210                                                      limit for timer half B.                                                   */
2211     } CMPRB0_b;
2212   } ;
2213 
2214   union {
2215     __IOM uint32_t CTRL0;                       /*!< (@ 0x0000000C) This includes the Control bit fields for both
2216                                                                     halves of timer 0.                                         */
2217 
2218     struct {
2219       __IOM uint32_t TMRA0EN    : 1;            /*!< [0..0] Counter/Timer A0 Enable bit.                                       */
2220       __IOM uint32_t TMRA0CLK   : 5;            /*!< [5..1] Counter/Timer A0 Clock Select.                                     */
2221       __IOM uint32_t TMRA0FN    : 3;            /*!< [8..6] Counter/Timer A0 Function Select.                                  */
2222       __IOM uint32_t TMRA0IE0   : 1;            /*!< [9..9] Counter/Timer A0 Interrupt Enable bit based on COMPR0.             */
2223       __IOM uint32_t TMRA0IE1   : 1;            /*!< [10..10] Counter/Timer A0 Interrupt Enable bit based on COMPR1.           */
2224       __IOM uint32_t TMRA0CLR   : 1;            /*!< [11..11] Counter/Timer A0 Clear bit.                                      */
2225       __IOM uint32_t TMRA0POL   : 1;            /*!< [12..12] Counter/Timer A0 output polarity.                                */
2226             uint32_t            : 3;
2227       __IOM uint32_t TMRB0EN    : 1;            /*!< [16..16] Counter/Timer B0 Enable bit.                                     */
2228       __IOM uint32_t TMRB0CLK   : 5;            /*!< [21..17] Counter/Timer B0 Clock Select.                                   */
2229       __IOM uint32_t TMRB0FN    : 3;            /*!< [24..22] Counter/Timer B0 Function Select.                                */
2230       __IOM uint32_t TMRB0IE0   : 1;            /*!< [25..25] Counter/Timer B0 Interrupt Enable bit for COMPR0.                */
2231       __IOM uint32_t TMRB0IE1   : 1;            /*!< [26..26] Counter/Timer B0 Interrupt Enable bit for COMPR1.                */
2232       __IOM uint32_t TMRB0CLR   : 1;            /*!< [27..27] Counter/Timer B0 Clear bit.                                      */
2233       __IOM uint32_t TMRB0POL   : 1;            /*!< [28..28] Counter/Timer B0 output polarity.                                */
2234             uint32_t            : 2;
2235       __IOM uint32_t CTLINK0    : 1;            /*!< [31..31] Counter/Timer A0/B0 Link bit.                                    */
2236     } CTRL0_b;
2237   } ;
2238   __IM  uint32_t  RESERVED;
2239 
2240   union {
2241     __IOM uint32_t CMPRAUXA0;                   /*!< (@ 0x00000014) Enhanced compare limits for timer half A. This
2242                                                                     is valid if timer 0 is set to function 4
2243                                                                     and function 5.                                            */
2244 
2245     struct {
2246       __IOM uint32_t CMPR2A0    : 16;           /*!< [15..0] Counter/Timer A0 Compare Register 2. Holds the lower
2247                                                      limit for timer half A.                                                   */
2248       __IOM uint32_t CMPR3A0    : 16;           /*!< [31..16] Counter/Timer A0 Compare Register 3. Holds the upper
2249                                                      limit for timer half A.                                                   */
2250     } CMPRAUXA0_b;
2251   } ;
2252 
2253   union {
2254     __IOM uint32_t CMPRAUXB0;                   /*!< (@ 0x00000018) Enhanced compare limits for timer half B. This
2255                                                                     is valid if timer 0 is set to function 4
2256                                                                     and function 5.                                            */
2257 
2258     struct {
2259       __IOM uint32_t CMPR2B0    : 16;           /*!< [15..0] Counter/Timer B0 Compare Register 2. Holds the lower
2260                                                      limit for timer half B.                                                   */
2261       __IOM uint32_t CMPR3B0    : 16;           /*!< [31..16] Counter/Timer B0 Compare Register 3. Holds the upper
2262                                                      limit for timer half B.                                                   */
2263     } CMPRAUXB0_b;
2264   } ;
2265 
2266   union {
2267     __IOM uint32_t AUX0;                        /*!< (@ 0x0000001C) Control bit fields for both halves of timer 0.             */
2268 
2269     struct {
2270       __IOM uint32_t TMRA0LMT   : 7;            /*!< [6..0] Counter/Timer A0 Pattern Limit Count.                              */
2271       __IOM uint32_t TMRA0TRIG  : 4;            /*!< [10..7] Counter/Timer A0 Trigger Select.                                  */
2272       __IOM uint32_t TMRA0NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2273       __IOM uint32_t TMRA0TINV  : 1;            /*!< [12..12] Counter/Timer A0 Invert on trigger.                              */
2274       __IOM uint32_t TMRA0POL23 : 1;            /*!< [13..13] Counter/Timer A0 Upper output polarity                           */
2275       __IOM uint32_t TMRA0EN23  : 1;            /*!< [14..14] Counter/Timer A0 Upper compare enable.                           */
2276             uint32_t            : 1;
2277       __IOM uint32_t TMRB0LMT   : 6;            /*!< [21..16] Counter/Timer B0 Pattern Limit Count.                            */
2278             uint32_t            : 1;
2279       __IOM uint32_t TMRB0TRIG  : 4;            /*!< [26..23] Counter/Timer B0 Trigger Select.                                 */
2280       __IOM uint32_t TMRB0NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2281       __IOM uint32_t TMRB0TINV  : 1;            /*!< [28..28] Counter/Timer B0 Invert on trigger.                              */
2282       __IOM uint32_t TMRB0POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2283       __IOM uint32_t TMRB0EN23  : 1;            /*!< [30..30] Counter/Timer B0 Upper compare enable.                           */
2284             uint32_t            : 1;
2285     } AUX0_b;
2286   } ;
2287 
2288   union {
2289     __IOM uint32_t TMR1;                        /*!< (@ 0x00000020) This register holds the running time or event
2290                                                                     count for CTIMER 1. This is either for each
2291                                                                     16 bit half or for the whole 32 bit count
2292                                                                     when the pair is linked. If the pair is
2293                                                                     not linked, they can be running on separate
2294                                                                     clocks and are completely independent.                     */
2295 
2296     struct {
2297       __IOM uint32_t CTTMRA1    : 16;           /*!< [15..0] Counter/Timer A1.                                                 */
2298       __IOM uint32_t CTTMRB1    : 16;           /*!< [31..16] Counter/Timer B1.                                                */
2299     } TMR1_b;
2300   } ;
2301 
2302   union {
2303     __IOM uint32_t CMPRA1;                      /*!< (@ 0x00000024) This contains the Compare limits for timer 1
2304                                                                     A half.                                                    */
2305 
2306     struct {
2307       __IOM uint32_t CMPR0A1    : 16;           /*!< [15..0] Counter/Timer A1 Compare Register 0.                              */
2308       __IOM uint32_t CMPR1A1    : 16;           /*!< [31..16] Counter/Timer A1 Compare Register 1.                             */
2309     } CMPRA1_b;
2310   } ;
2311 
2312   union {
2313     __IOM uint32_t CMPRB1;                      /*!< (@ 0x00000028) This contains the Compare limits for timer 1
2314                                                                     B half.                                                    */
2315 
2316     struct {
2317       __IOM uint32_t CMPR0B1    : 16;           /*!< [15..0] Counter/Timer B1 Compare Register 0.                              */
2318       __IOM uint32_t CMPR1B1    : 16;           /*!< [31..16] Counter/Timer B1 Compare Register 1.                             */
2319     } CMPRB1_b;
2320   } ;
2321 
2322   union {
2323     __IOM uint32_t CTRL1;                       /*!< (@ 0x0000002C) This includes the Control bit fields for both
2324                                                                     halves of timer 1.                                         */
2325 
2326     struct {
2327       __IOM uint32_t TMRA1EN    : 1;            /*!< [0..0] Counter/Timer A1 Enable bit.                                       */
2328       __IOM uint32_t TMRA1CLK   : 5;            /*!< [5..1] Counter/Timer A1 Clock Select.                                     */
2329       __IOM uint32_t TMRA1FN    : 3;            /*!< [8..6] Counter/Timer A1 Function Select.                                  */
2330       __IOM uint32_t TMRA1IE0   : 1;            /*!< [9..9] Counter/Timer A1 Interrupt Enable bit based on COMPR0.             */
2331       __IOM uint32_t TMRA1IE1   : 1;            /*!< [10..10] Counter/Timer A1 Interrupt Enable bit based on COMPR1.           */
2332       __IOM uint32_t TMRA1CLR   : 1;            /*!< [11..11] Counter/Timer A1 Clear bit.                                      */
2333       __IOM uint32_t TMRA1POL   : 1;            /*!< [12..12] Counter/Timer A1 output polarity.                                */
2334             uint32_t            : 3;
2335       __IOM uint32_t TMRB1EN    : 1;            /*!< [16..16] Counter/Timer B1 Enable bit.                                     */
2336       __IOM uint32_t TMRB1CLK   : 5;            /*!< [21..17] Counter/Timer B1 Clock Select.                                   */
2337       __IOM uint32_t TMRB1FN    : 3;            /*!< [24..22] Counter/Timer B1 Function Select.                                */
2338       __IOM uint32_t TMRB1IE0   : 1;            /*!< [25..25] Counter/Timer B1 Interrupt Enable bit for COMPR0.                */
2339       __IOM uint32_t TMRB1IE1   : 1;            /*!< [26..26] Counter/Timer B1 Interrupt Enable bit for COMPR1.                */
2340       __IOM uint32_t TMRB1CLR   : 1;            /*!< [27..27] Counter/Timer B1 Clear bit.                                      */
2341       __IOM uint32_t TMRB1POL   : 1;            /*!< [28..28] Counter/Timer B1 output polarity.                                */
2342             uint32_t            : 2;
2343       __IOM uint32_t CTLINK1    : 1;            /*!< [31..31] Counter/Timer A1/B1 Link bit.                                    */
2344     } CTRL1_b;
2345   } ;
2346   __IM  uint32_t  RESERVED1;
2347 
2348   union {
2349     __IOM uint32_t CMPRAUXA1;                   /*!< (@ 0x00000034) Enhanced compare limits for timer half A. This
2350                                                                     is valid if timer 1 is set to function 4
2351                                                                     and function 5.                                            */
2352 
2353     struct {
2354       __IOM uint32_t CMPR2A1    : 16;           /*!< [15..0] Counter/Timer A1 Compare Register 2. Holds the lower
2355                                                      limit for timer half A.                                                   */
2356       __IOM uint32_t CMPR3A1    : 16;           /*!< [31..16] Counter/Timer A1 Compare Register 3. Holds the upper
2357                                                      limit for timer half A.                                                   */
2358     } CMPRAUXA1_b;
2359   } ;
2360 
2361   union {
2362     __IOM uint32_t CMPRAUXB1;                   /*!< (@ 0x00000038) Enhanced compare limits for timer half B. This
2363                                                                     is valid if timer 1 is set to function 4
2364                                                                     and function 5.                                            */
2365 
2366     struct {
2367       __IOM uint32_t CMPR2B1    : 16;           /*!< [15..0] Counter/Timer B1 Compare Register 2. Holds the lower
2368                                                      limit for timer half B.                                                   */
2369       __IOM uint32_t CMPR3B1    : 16;           /*!< [31..16] Counter/Timer B1 Compare Register 3. Holds the upper
2370                                                      limit for timer half B.                                                   */
2371     } CMPRAUXB1_b;
2372   } ;
2373 
2374   union {
2375     __IOM uint32_t AUX1;                        /*!< (@ 0x0000003C) Control bit fields for both halves of timer 0.             */
2376 
2377     struct {
2378       __IOM uint32_t TMRA1LMT   : 7;            /*!< [6..0] Counter/Timer A1 Pattern Limit Count.                              */
2379       __IOM uint32_t TMRA1TRIG  : 4;            /*!< [10..7] Counter/Timer A1 Trigger Select.                                  */
2380       __IOM uint32_t TMRA1NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2381       __IOM uint32_t TMRA1TINV  : 1;            /*!< [12..12] Counter/Timer A1 Invert on trigger.                              */
2382       __IOM uint32_t TMRA1POL23 : 1;            /*!< [13..13] Counter/Timer A1 Upper output polarity                           */
2383       __IOM uint32_t TMRA1EN23  : 1;            /*!< [14..14] Counter/Timer A1 Upper compare enable.                           */
2384             uint32_t            : 1;
2385       __IOM uint32_t TMRB1LMT   : 6;            /*!< [21..16] Counter/Timer B1 Pattern Limit Count.                            */
2386             uint32_t            : 1;
2387       __IOM uint32_t TMRB1TRIG  : 4;            /*!< [26..23] Counter/Timer B1 Trigger Select.                                 */
2388       __IOM uint32_t TMRB1NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2389       __IOM uint32_t TMRB1TINV  : 1;            /*!< [28..28] Counter/Timer B1 Invert on trigger.                              */
2390       __IOM uint32_t TMRB1POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2391       __IOM uint32_t TMRB1EN23  : 1;            /*!< [30..30] Counter/Timer B1 Upper compare enable.                           */
2392             uint32_t            : 1;
2393     } AUX1_b;
2394   } ;
2395 
2396   union {
2397     __IOM uint32_t TMR2;                        /*!< (@ 0x00000040) This register holds the running time or event
2398                                                                     count for CTIMER 2. This is either for each
2399                                                                     16 bit half or for the whole 32 bit count
2400                                                                     when the pair is linked. If the pair is
2401                                                                     not linked, they can be running on separate
2402                                                                     clocks and are completely independent.                     */
2403 
2404     struct {
2405       __IOM uint32_t CTTMRA2    : 16;           /*!< [15..0] Counter/Timer A2.                                                 */
2406       __IOM uint32_t CTTMRB2    : 16;           /*!< [31..16] Counter/Timer B2.                                                */
2407     } TMR2_b;
2408   } ;
2409 
2410   union {
2411     __IOM uint32_t CMPRA2;                      /*!< (@ 0x00000044) This register holds the compare limits for timer
2412                                                                     2 A half.                                                  */
2413 
2414     struct {
2415       __IOM uint32_t CMPR0A2    : 16;           /*!< [15..0] Counter/Timer A2 Compare Register 0.                              */
2416       __IOM uint32_t CMPR1A2    : 16;           /*!< [31..16] Counter/Timer A2 Compare Register 1.                             */
2417     } CMPRA2_b;
2418   } ;
2419 
2420   union {
2421     __IOM uint32_t CMPRB2;                      /*!< (@ 0x00000048) This register holds the compare limits for timer
2422                                                                     2 B half.                                                  */
2423 
2424     struct {
2425       __IOM uint32_t CMPR0B2    : 16;           /*!< [15..0] Counter/Timer B2 Compare Register 0.                              */
2426       __IOM uint32_t CMPR1B2    : 16;           /*!< [31..16] Counter/Timer B2 Compare Register 1.                             */
2427     } CMPRB2_b;
2428   } ;
2429 
2430   union {
2431     __IOM uint32_t CTRL2;                       /*!< (@ 0x0000004C) This register holds the control bit fields for
2432                                                                     both halves of timer 2.                                    */
2433 
2434     struct {
2435       __IOM uint32_t TMRA2EN    : 1;            /*!< [0..0] Counter/Timer A2 Enable bit.                                       */
2436       __IOM uint32_t TMRA2CLK   : 5;            /*!< [5..1] Counter/Timer A2 Clock Select.                                     */
2437       __IOM uint32_t TMRA2FN    : 3;            /*!< [8..6] Counter/Timer A2 Function Select.                                  */
2438       __IOM uint32_t TMRA2IE0   : 1;            /*!< [9..9] Counter/Timer A2 Interrupt Enable bit based on COMPR0.             */
2439       __IOM uint32_t TMRA2IE1   : 1;            /*!< [10..10] Counter/Timer A2 Interrupt Enable bit based on COMPR1.           */
2440       __IOM uint32_t TMRA2CLR   : 1;            /*!< [11..11] Counter/Timer A2 Clear bit.                                      */
2441       __IOM uint32_t TMRA2POL   : 1;            /*!< [12..12] Counter/Timer A2 output polarity.                                */
2442             uint32_t            : 3;
2443       __IOM uint32_t TMRB2EN    : 1;            /*!< [16..16] Counter/Timer B2 Enable bit.                                     */
2444       __IOM uint32_t TMRB2CLK   : 5;            /*!< [21..17] Counter/Timer B2 Clock Select.                                   */
2445       __IOM uint32_t TMRB2FN    : 3;            /*!< [24..22] Counter/Timer B2 Function Select.                                */
2446       __IOM uint32_t TMRB2IE0   : 1;            /*!< [25..25] Counter/Timer B2 Interrupt Enable bit for COMPR0.                */
2447       __IOM uint32_t TMRB2IE1   : 1;            /*!< [26..26] Counter/Timer B2 Interrupt Enable bit for COMPR1.                */
2448       __IOM uint32_t TMRB2CLR   : 1;            /*!< [27..27] Counter/Timer B2 Clear bit.                                      */
2449       __IOM uint32_t TMRB2POL   : 1;            /*!< [28..28] Counter/Timer B2 output polarity.                                */
2450             uint32_t            : 2;
2451       __IOM uint32_t CTLINK2    : 1;            /*!< [31..31] Counter/Timer A2/B2 Link bit.                                    */
2452     } CTRL2_b;
2453   } ;
2454   __IM  uint32_t  RESERVED2;
2455 
2456   union {
2457     __IOM uint32_t CMPRAUXA2;                   /*!< (@ 0x00000054) Enhanced compare limits for timer half A.                  */
2458 
2459     struct {
2460       __IOM uint32_t CMPR2A2    : 16;           /*!< [15..0] Counter/Timer A2 Compare Register 2. Holds the lower
2461                                                      limit for timer half A.                                                   */
2462       __IOM uint32_t CMPR3A2    : 16;           /*!< [31..16] Counter/Timer A2 Compare Register 3. Holds the upper
2463                                                      limit for timer half A.                                                   */
2464     } CMPRAUXA2_b;
2465   } ;
2466 
2467   union {
2468     __IOM uint32_t CMPRAUXB2;                   /*!< (@ 0x00000058) Enhanced compare limits for timer half B.                  */
2469 
2470     struct {
2471       __IOM uint32_t CMPR2B2    : 16;           /*!< [15..0] Counter/Timer B2 Compare Register 2. Holds the lower
2472                                                      limit for timer half B.                                                   */
2473       __IOM uint32_t CMPR3B2    : 16;           /*!< [31..16] Counter/Timer B2 Compare Register 3. Holds the upper
2474                                                      limit for timer half B.                                                   */
2475     } CMPRAUXB2_b;
2476   } ;
2477 
2478   union {
2479     __IOM uint32_t AUX2;                        /*!< (@ 0x0000005C) Control bit fields for both halves of timer 0.             */
2480 
2481     struct {
2482       __IOM uint32_t TMRA2LMT   : 7;            /*!< [6..0] Counter/Timer A2 Pattern Limit Count.                              */
2483       __IOM uint32_t TMRA2TRIG  : 4;            /*!< [10..7] Counter/Timer A2 Trigger Select.                                  */
2484       __IOM uint32_t TMRA2NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2485       __IOM uint32_t TMRA2TINV  : 1;            /*!< [12..12] Counter/Timer A2 Invert on trigger.                              */
2486       __IOM uint32_t TMRA2POL23 : 1;            /*!< [13..13] Counter/Timer A2 Upper output polarity                           */
2487       __IOM uint32_t TMRA2EN23  : 1;            /*!< [14..14] Counter/Timer A2 Upper compare enable.                           */
2488             uint32_t            : 1;
2489       __IOM uint32_t TMRB2LMT   : 6;            /*!< [21..16] Counter/Timer B2 Pattern Limit Count.                            */
2490             uint32_t            : 1;
2491       __IOM uint32_t TMRB2TRIG  : 4;            /*!< [26..23] Counter/Timer B2 Trigger Select.                                 */
2492       __IOM uint32_t TMRB2NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2493       __IOM uint32_t TMRB2TINV  : 1;            /*!< [28..28] Counter/Timer B2 Invert on trigger.                              */
2494       __IOM uint32_t TMRB2POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2495       __IOM uint32_t TMRB2EN23  : 1;            /*!< [30..30] Counter/Timer B2 Upper compare enable.                           */
2496             uint32_t            : 1;
2497     } AUX2_b;
2498   } ;
2499 
2500   union {
2501     __IOM uint32_t TMR3;                        /*!< (@ 0x00000060) Counter/Timer 3                                            */
2502 
2503     struct {
2504       __IOM uint32_t CTTMRA3    : 16;           /*!< [15..0] Counter/Timer A3.                                                 */
2505       __IOM uint32_t CTTMRB3    : 16;           /*!< [31..16] Counter/Timer B3.                                                */
2506     } TMR3_b;
2507   } ;
2508 
2509   union {
2510     __IOM uint32_t CMPRA3;                      /*!< (@ 0x00000064) This register holds the compare limits for timer
2511                                                                     half A.                                                    */
2512 
2513     struct {
2514       __IOM uint32_t CMPR0A3    : 16;           /*!< [15..0] Counter/Timer A3 Compare Register 0.                              */
2515       __IOM uint32_t CMPR1A3    : 16;           /*!< [31..16] Counter/Timer A3 Compare Register 1.                             */
2516     } CMPRA3_b;
2517   } ;
2518 
2519   union {
2520     __IOM uint32_t CMPRB3;                      /*!< (@ 0x00000068) This register holds the compare limits for timer
2521                                                                     half B.                                                    */
2522 
2523     struct {
2524       __IOM uint32_t CMPR0B3    : 16;           /*!< [15..0] Counter/Timer B3 Compare Register 0.                              */
2525       __IOM uint32_t CMPR1B3    : 16;           /*!< [31..16] Counter/Timer B3 Compare Register 1.                             */
2526     } CMPRB3_b;
2527   } ;
2528 
2529   union {
2530     __IOM uint32_t CTRL3;                       /*!< (@ 0x0000006C) This register holds the control bit fields for
2531                                                                     both halves of timer 3.                                    */
2532 
2533     struct {
2534       __IOM uint32_t TMRA3EN    : 1;            /*!< [0..0] Counter/Timer A3 Enable bit.                                       */
2535       __IOM uint32_t TMRA3CLK   : 5;            /*!< [5..1] Counter/Timer A3 Clock Select.                                     */
2536       __IOM uint32_t TMRA3FN    : 3;            /*!< [8..6] Counter/Timer A3 Function Select.                                  */
2537       __IOM uint32_t TMRA3IE0   : 1;            /*!< [9..9] Counter/Timer A3 Interrupt Enable bit based on COMPR0.             */
2538       __IOM uint32_t TMRA3IE1   : 1;            /*!< [10..10] Counter/Timer A3 Interrupt Enable bit based on COMPR1.           */
2539       __IOM uint32_t TMRA3CLR   : 1;            /*!< [11..11] Counter/Timer A3 Clear bit.                                      */
2540       __IOM uint32_t TMRA3POL   : 1;            /*!< [12..12] Counter/Timer A3 output polarity.                                */
2541             uint32_t            : 2;
2542       __IOM uint32_t ADCEN      : 1;            /*!< [15..15] Special Timer A3 enable for ADC function.                        */
2543       __IOM uint32_t TMRB3EN    : 1;            /*!< [16..16] Counter/Timer B3 Enable bit.                                     */
2544       __IOM uint32_t TMRB3CLK   : 5;            /*!< [21..17] Counter/Timer B3 Clock Select.                                   */
2545       __IOM uint32_t TMRB3FN    : 3;            /*!< [24..22] Counter/Timer B3 Function Select.                                */
2546       __IOM uint32_t TMRB3IE0   : 1;            /*!< [25..25] Counter/Timer B3 Interrupt Enable bit for COMPR0.                */
2547       __IOM uint32_t TMRB3IE1   : 1;            /*!< [26..26] Counter/Timer B3 Interrupt Enable bit for COMPR1.                */
2548       __IOM uint32_t TMRB3CLR   : 1;            /*!< [27..27] Counter/Timer B3 Clear bit.                                      */
2549       __IOM uint32_t TMRB3POL   : 1;            /*!< [28..28] Counter/Timer B3 output polarity.                                */
2550             uint32_t            : 2;
2551       __IOM uint32_t CTLINK3    : 1;            /*!< [31..31] Counter/Timer A3/B3 Link bit.                                    */
2552     } CTRL3_b;
2553   } ;
2554   __IM  uint32_t  RESERVED3;
2555 
2556   union {
2557     __IOM uint32_t CMPRAUXA3;                   /*!< (@ 0x00000074) Enhanced compare limits for timer half A.                  */
2558 
2559     struct {
2560       __IOM uint32_t CMPR2A3    : 16;           /*!< [15..0] Counter/Timer A3 Compare Register 2. Holds the lower
2561                                                      limit for timer half A.                                                   */
2562       __IOM uint32_t CMPR3A3    : 16;           /*!< [31..16] Counter/Timer A3 Compare Register 3. Holds the upper
2563                                                      limit for timer half A.                                                   */
2564     } CMPRAUXA3_b;
2565   } ;
2566 
2567   union {
2568     __IOM uint32_t CMPRAUXB3;                   /*!< (@ 0x00000078) Enhanced compare limits for timer half B.                  */
2569 
2570     struct {
2571       __IOM uint32_t CMPR2B3    : 16;           /*!< [15..0] Counter/Timer B3 Compare Register 2. Holds the lower
2572                                                      limit for timer half B.                                                   */
2573       __IOM uint32_t CMPR3B3    : 16;           /*!< [31..16] Counter/Timer B3 Compare Register 3. Holds the upper
2574                                                      limit for timer half B.                                                   */
2575     } CMPRAUXB3_b;
2576   } ;
2577 
2578   union {
2579     __IOM uint32_t AUX3;                        /*!< (@ 0x0000007C) Control bit fields for both halves of timer 0.             */
2580 
2581     struct {
2582       __IOM uint32_t TMRA3LMT   : 7;            /*!< [6..0] Counter/Timer A3 Pattern Limit Count.                              */
2583       __IOM uint32_t TMRA3TRIG  : 4;            /*!< [10..7] Counter/Timer A3 Trigger Select.                                  */
2584       __IOM uint32_t TMRA3NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2585       __IOM uint32_t TMRA3TINV  : 1;            /*!< [12..12] Counter/Timer A3 Invert on trigger.                              */
2586       __IOM uint32_t TMRA3POL23 : 1;            /*!< [13..13] Counter/Timer A3 Upper output polarity                           */
2587       __IOM uint32_t TMRA3EN23  : 1;            /*!< [14..14] Counter/Timer A3 Upper compare enable.                           */
2588             uint32_t            : 1;
2589       __IOM uint32_t TMRB3LMT   : 6;            /*!< [21..16] Counter/Timer B3 Pattern Limit Count.                            */
2590             uint32_t            : 1;
2591       __IOM uint32_t TMRB3TRIG  : 4;            /*!< [26..23] Counter/Timer B3 Trigger Select.                                 */
2592       __IOM uint32_t TMRB3NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2593       __IOM uint32_t TMRB3TINV  : 1;            /*!< [28..28] Counter/Timer B3 Invert on trigger.                              */
2594       __IOM uint32_t TMRB3POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2595       __IOM uint32_t TMRB3EN23  : 1;            /*!< [30..30] Counter/Timer B3 Upper compare enable.                           */
2596             uint32_t            : 1;
2597     } AUX3_b;
2598   } ;
2599 
2600   union {
2601     __IOM uint32_t TMR4;                        /*!< (@ 0x00000080) This register holds the running time or event
2602                                                                     count, either for each 16 bit half or for
2603                                                                     the whole 32 bit count when the pair is
2604                                                                     linked.                                                    */
2605 
2606     struct {
2607       __IOM uint32_t CTTMRA4    : 16;           /*!< [15..0] Counter/Timer A4.                                                 */
2608       __IOM uint32_t CTTMRB4    : 16;           /*!< [31..16] Counter/Timer B4.                                                */
2609     } TMR4_b;
2610   } ;
2611 
2612   union {
2613     __IOM uint32_t CMPRA4;                      /*!< (@ 0x00000084) Compare limits for timer half A.                           */
2614 
2615     struct {
2616       __IOM uint32_t CMPR0A4    : 16;           /*!< [15..0] Counter/Timer A4 Compare Register 0. Holds the lower
2617                                                      limit for timer half A.                                                   */
2618       __IOM uint32_t CMPR1A4    : 16;           /*!< [31..16] Counter/Timer A4 Compare Register 1. Holds the upper
2619                                                      limit for timer half A.                                                   */
2620     } CMPRA4_b;
2621   } ;
2622 
2623   union {
2624     __IOM uint32_t CMPRB4;                      /*!< (@ 0x00000088) Compare limits for timer half B.                           */
2625 
2626     struct {
2627       __IOM uint32_t CMPR0B4    : 16;           /*!< [15..0] Counter/Timer B4 Compare Register 0. Holds the lower
2628                                                      limit for timer half B.                                                   */
2629       __IOM uint32_t CMPR1B4    : 16;           /*!< [31..16] Counter/Timer B4 Compare Register 1. Holds the upper
2630                                                      limit for timer half B.                                                   */
2631     } CMPRB4_b;
2632   } ;
2633 
2634   union {
2635     __IOM uint32_t CTRL4;                       /*!< (@ 0x0000008C) Control bit fields for both halves of timer 4.             */
2636 
2637     struct {
2638       __IOM uint32_t TMRA4EN    : 1;            /*!< [0..0] Counter/Timer A4 Enable bit.                                       */
2639       __IOM uint32_t TMRA4CLK   : 5;            /*!< [5..1] Counter/Timer A4 Clock Select.                                     */
2640       __IOM uint32_t TMRA4FN    : 3;            /*!< [8..6] Counter/Timer A4 Function Select.                                  */
2641       __IOM uint32_t TMRA4IE0   : 1;            /*!< [9..9] Counter/Timer A4 Interrupt Enable bit based on COMPR0.             */
2642       __IOM uint32_t TMRA4IE1   : 1;            /*!< [10..10] Counter/Timer A4 Interrupt Enable bit based on COMPR1.           */
2643       __IOM uint32_t TMRA4CLR   : 1;            /*!< [11..11] Counter/Timer A4 Clear bit.                                      */
2644       __IOM uint32_t TMRA4POL   : 1;            /*!< [12..12] Counter/Timer A4 output polarity.                                */
2645             uint32_t            : 3;
2646       __IOM uint32_t TMRB4EN    : 1;            /*!< [16..16] Counter/Timer B4 Enable bit.                                     */
2647       __IOM uint32_t TMRB4CLK   : 5;            /*!< [21..17] Counter/Timer B4 Clock Select.                                   */
2648       __IOM uint32_t TMRB4FN    : 3;            /*!< [24..22] Counter/Timer B4 Function Select.                                */
2649       __IOM uint32_t TMRB4IE0   : 1;            /*!< [25..25] Counter/Timer B4 Interrupt Enable bit for COMPR0.                */
2650       __IOM uint32_t TMRB4IE1   : 1;            /*!< [26..26] Counter/Timer B4 Interrupt Enable bit for COMPR1.                */
2651       __IOM uint32_t TMRB4CLR   : 1;            /*!< [27..27] Counter/Timer B4 Clear bit.                                      */
2652       __IOM uint32_t TMRB4POL   : 1;            /*!< [28..28] Counter/Timer B4 output polarity.                                */
2653             uint32_t            : 2;
2654       __IOM uint32_t CTLINK4    : 1;            /*!< [31..31] Counter/Timer A4/B4 Link bit.                                    */
2655     } CTRL4_b;
2656   } ;
2657   __IM  uint32_t  RESERVED4;
2658 
2659   union {
2660     __IOM uint32_t CMPRAUXA4;                   /*!< (@ 0x00000094) Enhanced compare limits for timer half A.                  */
2661 
2662     struct {
2663       __IOM uint32_t CMPR2A4    : 16;           /*!< [15..0] Counter/Timer A4 Compare Register 2. Holds the lower
2664                                                      limit for timer half A.                                                   */
2665       __IOM uint32_t CMPR3A4    : 16;           /*!< [31..16] Counter/Timer A4 Compare Register 3. Holds the upper
2666                                                      limit for timer half A.                                                   */
2667     } CMPRAUXA4_b;
2668   } ;
2669 
2670   union {
2671     __IOM uint32_t CMPRAUXB4;                   /*!< (@ 0x00000098) Enhanced compare limits for timer half B.                  */
2672 
2673     struct {
2674       __IOM uint32_t CMPR2B4    : 16;           /*!< [15..0] Counter/Timer B4 Compare Register 2. Holds the lower
2675                                                      limit for timer half B.                                                   */
2676       __IOM uint32_t CMPR3B4    : 16;           /*!< [31..16] Counter/Timer B4 Compare Register 3. Holds the upper
2677                                                      limit for timer half B.                                                   */
2678     } CMPRAUXB4_b;
2679   } ;
2680 
2681   union {
2682     __IOM uint32_t AUX4;                        /*!< (@ 0x0000009C) Control bit fields for both halves of timer 4.             */
2683 
2684     struct {
2685       __IOM uint32_t TMRA4LMT   : 7;            /*!< [6..0] Counter/Timer A4 Pattern Limit Count.                              */
2686       __IOM uint32_t TMRA4TRIG  : 4;            /*!< [10..7] Counter/Timer A4 Trigger Select.                                  */
2687       __IOM uint32_t TMRA4NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2688       __IOM uint32_t TMRA4TINV  : 1;            /*!< [12..12] Counter/Timer A4 Invert on trigger.                              */
2689       __IOM uint32_t TMRA4POL23 : 1;            /*!< [13..13] Counter/Timer A4 Upper output polarity                           */
2690       __IOM uint32_t TMRA4EN23  : 1;            /*!< [14..14] Counter/Timer A4 Upper compare enable.                           */
2691             uint32_t            : 1;
2692       __IOM uint32_t TMRB4LMT   : 6;            /*!< [21..16] Counter/Timer B4 Pattern Limit Count.                            */
2693             uint32_t            : 1;
2694       __IOM uint32_t TMRB4TRIG  : 4;            /*!< [26..23] Counter/Timer B4 Trigger Select.                                 */
2695       __IOM uint32_t TMRB4NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2696       __IOM uint32_t TMRB4TINV  : 1;            /*!< [28..28] Counter/Timer B4 Invert on trigger.                              */
2697       __IOM uint32_t TMRB4POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2698       __IOM uint32_t TMRB4EN23  : 1;            /*!< [30..30] Counter/Timer B4 Upper compare enable.                           */
2699             uint32_t            : 1;
2700     } AUX4_b;
2701   } ;
2702 
2703   union {
2704     __IOM uint32_t TMR5;                        /*!< (@ 0x000000A0) This register holds the running time or event
2705                                                                     count, either for each 16 bit half or for
2706                                                                     the whole 32 bit count when the pair is
2707                                                                     linked.                                                    */
2708 
2709     struct {
2710       __IOM uint32_t CTTMRA5    : 16;           /*!< [15..0] Counter/Timer A5.                                                 */
2711       __IOM uint32_t CTTMRB5    : 16;           /*!< [31..16] Counter/Timer B5.                                                */
2712     } TMR5_b;
2713   } ;
2714 
2715   union {
2716     __IOM uint32_t CMPRA5;                      /*!< (@ 0x000000A4) This register holds the compare limits for timer
2717                                                                     half A.                                                    */
2718 
2719     struct {
2720       __IOM uint32_t CMPR0A5    : 16;           /*!< [15..0] Counter/Timer A5 Compare Register 0.                              */
2721       __IOM uint32_t CMPR1A5    : 16;           /*!< [31..16] Counter/Timer A5 Compare Register 1.                             */
2722     } CMPRA5_b;
2723   } ;
2724 
2725   union {
2726     __IOM uint32_t CMPRB5;                      /*!< (@ 0x000000A8) This register holds the compare limits for timer
2727                                                                     half B.                                                    */
2728 
2729     struct {
2730       __IOM uint32_t CMPR0B5    : 16;           /*!< [15..0] Counter/Timer B5 Compare Register 0.                              */
2731       __IOM uint32_t CMPR1B5    : 16;           /*!< [31..16] Counter/Timer B5 Compare Register 1.                             */
2732     } CMPRB5_b;
2733   } ;
2734 
2735   union {
2736     __IOM uint32_t CTRL5;                       /*!< (@ 0x000000AC) Control bit fields for both halves of timer 0.             */
2737 
2738     struct {
2739       __IOM uint32_t TMRA5EN    : 1;            /*!< [0..0] Counter/Timer A5 Enable bit.                                       */
2740       __IOM uint32_t TMRA5CLK   : 5;            /*!< [5..1] Counter/Timer A5 Clock Select.                                     */
2741       __IOM uint32_t TMRA5FN    : 3;            /*!< [8..6] Counter/Timer A5 Function Select.                                  */
2742       __IOM uint32_t TMRA5IE0   : 1;            /*!< [9..9] Counter/Timer A5 Interrupt Enable bit based on COMPR0.             */
2743       __IOM uint32_t TMRA5IE1   : 1;            /*!< [10..10] Counter/Timer A5 Interrupt Enable bit based on COMPR1.           */
2744       __IOM uint32_t TMRA5CLR   : 1;            /*!< [11..11] Counter/Timer A5 Clear bit.                                      */
2745       __IOM uint32_t TMRA5POL   : 1;            /*!< [12..12] Counter/Timer A5 output polarity.                                */
2746             uint32_t            : 3;
2747       __IOM uint32_t TMRB5EN    : 1;            /*!< [16..16] Counter/Timer B5 Enable bit.                                     */
2748       __IOM uint32_t TMRB5CLK   : 5;            /*!< [21..17] Counter/Timer B5 Clock Select.                                   */
2749       __IOM uint32_t TMRB5FN    : 3;            /*!< [24..22] Counter/Timer B5 Function Select.                                */
2750       __IOM uint32_t TMRB5IE0   : 1;            /*!< [25..25] Counter/Timer B5 Interrupt Enable bit for COMPR0.                */
2751       __IOM uint32_t TMRB5IE1   : 1;            /*!< [26..26] Counter/Timer B5 Interrupt Enable bit for COMPR1.                */
2752       __IOM uint32_t TMRB5CLR   : 1;            /*!< [27..27] Counter/Timer B5 Clear bit.                                      */
2753       __IOM uint32_t TMRB5POL   : 1;            /*!< [28..28] Counter/Timer B5 output polarity.                                */
2754             uint32_t            : 2;
2755       __IOM uint32_t CTLINK5    : 1;            /*!< [31..31] Counter/Timer A5/B5 Link bit.                                    */
2756     } CTRL5_b;
2757   } ;
2758   __IM  uint32_t  RESERVED5;
2759 
2760   union {
2761     __IOM uint32_t CMPRAUXA5;                   /*!< (@ 0x000000B4) Enhanced compare limits for timer half A.                  */
2762 
2763     struct {
2764       __IOM uint32_t CMPR2A5    : 16;           /*!< [15..0] Counter/Timer A5 Compare Register 2. Holds the lower
2765                                                      limit for timer half A.                                                   */
2766       __IOM uint32_t CMPR3A5    : 16;           /*!< [31..16] Counter/Timer A5 Compare Register 3. Holds the upper
2767                                                      limit for timer half A.                                                   */
2768     } CMPRAUXA5_b;
2769   } ;
2770 
2771   union {
2772     __IOM uint32_t CMPRAUXB5;                   /*!< (@ 0x000000B8) Enhanced compare limits for timer half B.                  */
2773 
2774     struct {
2775       __IOM uint32_t CMPR2B5    : 16;           /*!< [15..0] Counter/Timer B5 Compare Register 2. Holds the lower
2776                                                      limit for timer half B.                                                   */
2777       __IOM uint32_t CMPR3B5    : 16;           /*!< [31..16] Counter/Timer B5 Compare Register 3. Holds the upper
2778                                                      limit for timer half B.                                                   */
2779     } CMPRAUXB5_b;
2780   } ;
2781 
2782   union {
2783     __IOM uint32_t AUX5;                        /*!< (@ 0x000000BC) Control bit fields for both halves of timer 0.             */
2784 
2785     struct {
2786       __IOM uint32_t TMRA5LMT   : 7;            /*!< [6..0] Counter/Timer A5 Pattern Limit Count.                              */
2787       __IOM uint32_t TMRA5TRIG  : 4;            /*!< [10..7] Counter/Timer A5 Trigger Select.                                  */
2788       __IOM uint32_t TMRA5NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2789       __IOM uint32_t TMRA5TINV  : 1;            /*!< [12..12] Counter/Timer A5 Invert on trigger.                              */
2790       __IOM uint32_t TMRA5POL23 : 1;            /*!< [13..13] Counter/Timer A5 Upper output polarity                           */
2791       __IOM uint32_t TMRA5EN23  : 1;            /*!< [14..14] Counter/Timer A5 Upper compare enable.                           */
2792             uint32_t            : 1;
2793       __IOM uint32_t TMRB5LMT   : 6;            /*!< [21..16] Counter/Timer B5 Pattern Limit Count.                            */
2794             uint32_t            : 1;
2795       __IOM uint32_t TMRB5TRIG  : 4;            /*!< [26..23] Counter/Timer B5 Trigger Select.                                 */
2796       __IOM uint32_t TMRB5NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2797       __IOM uint32_t TMRB5TINV  : 1;            /*!< [28..28] Counter/Timer B5 Invert on trigger.                              */
2798       __IOM uint32_t TMRB5POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2799       __IOM uint32_t TMRB5EN23  : 1;            /*!< [30..30] Counter/Timer B5 Upper compare enable.                           */
2800             uint32_t            : 1;
2801     } AUX5_b;
2802   } ;
2803 
2804   union {
2805     __IOM uint32_t TMR6;                        /*!< (@ 0x000000C0) Counter/Timer 6                                            */
2806 
2807     struct {
2808       __IOM uint32_t CTTMRA6    : 16;           /*!< [15..0] Counter/Timer A6.                                                 */
2809       __IOM uint32_t CTTMRB6    : 16;           /*!< [31..16] Counter/Timer B6.                                                */
2810     } TMR6_b;
2811   } ;
2812 
2813   union {
2814     __IOM uint32_t CMPRA6;                      /*!< (@ 0x000000C4) This register holds the compare limits for timer
2815                                                                     half A.                                                    */
2816 
2817     struct {
2818       __IOM uint32_t CMPR0A6    : 16;           /*!< [15..0] Counter/Timer A6 Compare Register 0.                              */
2819       __IOM uint32_t CMPR1A6    : 16;           /*!< [31..16] Counter/Timer A6 Compare Register 1.                             */
2820     } CMPRA6_b;
2821   } ;
2822 
2823   union {
2824     __IOM uint32_t CMPRB6;                      /*!< (@ 0x000000C8) This register holds the compare limits for timer
2825                                                                     half B.                                                    */
2826 
2827     struct {
2828       __IOM uint32_t CMPR0B6    : 16;           /*!< [15..0] Counter/Timer B6 Compare Register 0.                              */
2829       __IOM uint32_t CMPR1B6    : 16;           /*!< [31..16] Counter/Timer B6 Compare Register 1.                             */
2830     } CMPRB6_b;
2831   } ;
2832 
2833   union {
2834     __IOM uint32_t CTRL6;                       /*!< (@ 0x000000CC) This register holds the control bit fields for
2835                                                                     both halves of timer 6.                                    */
2836 
2837     struct {
2838       __IOM uint32_t TMRA6EN    : 1;            /*!< [0..0] Counter/Timer A6 Enable bit.                                       */
2839       __IOM uint32_t TMRA6CLK   : 5;            /*!< [5..1] Counter/Timer A6 Clock Select.                                     */
2840       __IOM uint32_t TMRA6FN    : 3;            /*!< [8..6] Counter/Timer A6 Function Select.                                  */
2841       __IOM uint32_t TMRA6IE0   : 1;            /*!< [9..9] Counter/Timer A6 Interrupt Enable bit based on COMPR0.             */
2842       __IOM uint32_t TMRA6IE1   : 1;            /*!< [10..10] Counter/Timer A6 Interrupt Enable bit based on COMPR1.           */
2843       __IOM uint32_t TMRA6CLR   : 1;            /*!< [11..11] Counter/Timer A6 Clear bit.                                      */
2844       __IOM uint32_t TMRA6POL   : 1;            /*!< [12..12] Counter/Timer A6 output polarity.                                */
2845             uint32_t            : 3;
2846       __IOM uint32_t TMRB6EN    : 1;            /*!< [16..16] Counter/Timer B6 Enable bit.                                     */
2847       __IOM uint32_t TMRB6CLK   : 5;            /*!< [21..17] Counter/Timer B6 Clock Select.                                   */
2848       __IOM uint32_t TMRB6FN    : 3;            /*!< [24..22] Counter/Timer B6 Function Select.                                */
2849       __IOM uint32_t TMRB6IE0   : 1;            /*!< [25..25] Counter/Timer B6 Interrupt Enable bit for COMPR0.                */
2850       __IOM uint32_t TMRB6IE1   : 1;            /*!< [26..26] Counter/Timer B6 Interrupt Enable bit for COMPR1.                */
2851       __IOM uint32_t TMRB6CLR   : 1;            /*!< [27..27] Counter/Timer B6 Clear bit.                                      */
2852       __IOM uint32_t TMRB6POL   : 1;            /*!< [28..28] Counter/Timer B6 output polarity.                                */
2853             uint32_t            : 2;
2854       __IOM uint32_t CTLINK6    : 1;            /*!< [31..31] Counter/Timer A6/B6 Link bit.                                    */
2855     } CTRL6_b;
2856   } ;
2857   __IM  uint32_t  RESERVED6;
2858 
2859   union {
2860     __IOM uint32_t CMPRAUXA6;                   /*!< (@ 0x000000D4) Enhanced compare limits for timer half A.                  */
2861 
2862     struct {
2863       __IOM uint32_t CMPR2A6    : 16;           /*!< [15..0] Counter/Timer A6 Compare Register 2. Holds the lower
2864                                                      limit for timer half A.                                                   */
2865       __IOM uint32_t CMPR3A6    : 16;           /*!< [31..16] Counter/Timer A6 Compare Register 3. Holds the upper
2866                                                      limit for timer half A.                                                   */
2867     } CMPRAUXA6_b;
2868   } ;
2869 
2870   union {
2871     __IOM uint32_t CMPRAUXB6;                   /*!< (@ 0x000000D8) Enhanced compare limits for timer half B.                  */
2872 
2873     struct {
2874       __IOM uint32_t CMPR2B6    : 16;           /*!< [15..0] Counter/Timer B6 Compare Register 2. Holds the lower
2875                                                      limit for timer half B.                                                   */
2876       __IOM uint32_t CMPR3B6    : 16;           /*!< [31..16] Counter/Timer B6 Compare Register 3. Holds the upper
2877                                                      limit for timer half B.                                                   */
2878     } CMPRAUXB6_b;
2879   } ;
2880 
2881   union {
2882     __IOM uint32_t AUX6;                        /*!< (@ 0x000000DC) Control bit fields for both halves of timer 0.             */
2883 
2884     struct {
2885       __IOM uint32_t TMRA6LMT   : 7;            /*!< [6..0] Counter/Timer A6 Pattern Limit Count.                              */
2886       __IOM uint32_t TMRA6TRIG  : 4;            /*!< [10..7] Counter/Timer A6 Trigger Select.                                  */
2887       __IOM uint32_t TMRA6NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2888       __IOM uint32_t TMRA6TINV  : 1;            /*!< [12..12] Counter/Timer A6 Invert on trigger.                              */
2889       __IOM uint32_t TMRA6POL23 : 1;            /*!< [13..13] Counter/Timer A6 Upper output polarity                           */
2890       __IOM uint32_t TMRA6EN23  : 1;            /*!< [14..14] Counter/Timer A6 Upper compare enable.                           */
2891             uint32_t            : 1;
2892       __IOM uint32_t TMRB6LMT   : 6;            /*!< [21..16] Counter/Timer B6 Pattern Limit Count.                            */
2893             uint32_t            : 1;
2894       __IOM uint32_t TMRB6TRIG  : 4;            /*!< [26..23] Counter/Timer B6 Trigger Select.                                 */
2895       __IOM uint32_t TMRB6NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2896       __IOM uint32_t TMRB6TINV  : 1;            /*!< [28..28] Counter/Timer B6 Invert on trigger.                              */
2897       __IOM uint32_t TMRB6POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2898       __IOM uint32_t TMRB6EN23  : 1;            /*!< [30..30] Counter/Timer B6 Upper compare enable.                           */
2899             uint32_t            : 1;
2900     } AUX6_b;
2901   } ;
2902 
2903   union {
2904     __IOM uint32_t TMR7;                        /*!< (@ 0x000000E0) Counter/Timer 7                                            */
2905 
2906     struct {
2907       __IOM uint32_t CTTMRA7    : 16;           /*!< [15..0] Counter/Timer A7.                                                 */
2908       __IOM uint32_t CTTMRB7    : 16;           /*!< [31..16] Counter/Timer B7.                                                */
2909     } TMR7_b;
2910   } ;
2911 
2912   union {
2913     __IOM uint32_t CMPRA7;                      /*!< (@ 0x000000E4) This register holds the compare limits for timer
2914                                                                     half A.                                                    */
2915 
2916     struct {
2917       __IOM uint32_t CMPR0A7    : 16;           /*!< [15..0] Counter/Timer A7 Compare Register 0.                              */
2918       __IOM uint32_t CMPR1A7    : 16;           /*!< [31..16] Counter/Timer A7 Compare Register 1.                             */
2919     } CMPRA7_b;
2920   } ;
2921 
2922   union {
2923     __IOM uint32_t CMPRB7;                      /*!< (@ 0x000000E8) This register holds the compare limits for timer
2924                                                                     half B.                                                    */
2925 
2926     struct {
2927       __IOM uint32_t CMPR0B7    : 16;           /*!< [15..0] Counter/Timer B3 Compare Register 0.                              */
2928       __IOM uint32_t CMPR1B7    : 16;           /*!< [31..16] Counter/Timer B3 Compare Register 1.                             */
2929     } CMPRB7_b;
2930   } ;
2931 
2932   union {
2933     __IOM uint32_t CTRL7;                       /*!< (@ 0x000000EC) This register holds the control bit fields for
2934                                                                     both halves of timer 7.                                    */
2935 
2936     struct {
2937       __IOM uint32_t TMRA7EN    : 1;            /*!< [0..0] Counter/Timer A7 Enable bit.                                       */
2938       __IOM uint32_t TMRA7CLK   : 5;            /*!< [5..1] Counter/Timer A7 Clock Select.                                     */
2939       __IOM uint32_t TMRA7FN    : 3;            /*!< [8..6] Counter/Timer A7 Function Select.                                  */
2940       __IOM uint32_t TMRA7IE0   : 1;            /*!< [9..9] Counter/Timer A7 Interrupt Enable bit based on COMPR0.             */
2941       __IOM uint32_t TMRA7IE1   : 1;            /*!< [10..10] Counter/Timer A7 Interrupt Enable bit based on COMPR1.           */
2942       __IOM uint32_t TMRA7CLR   : 1;            /*!< [11..11] Counter/Timer A7 Clear bit.                                      */
2943       __IOM uint32_t TMRA7POL   : 1;            /*!< [12..12] Counter/Timer A7 output polarity.                                */
2944             uint32_t            : 3;
2945       __IOM uint32_t TMRB7EN    : 1;            /*!< [16..16] Counter/Timer B7 Enable bit.                                     */
2946       __IOM uint32_t TMRB7CLK   : 5;            /*!< [21..17] Counter/Timer B7 Clock Select.                                   */
2947       __IOM uint32_t TMRB7FN    : 3;            /*!< [24..22] Counter/Timer B7 Function Select.                                */
2948       __IOM uint32_t TMRB7IE0   : 1;            /*!< [25..25] Counter/Timer B7 Interrupt Enable bit for COMPR0.                */
2949       __IOM uint32_t TMRB7IE1   : 1;            /*!< [26..26] Counter/Timer B7 Interrupt Enable bit for COMPR1.                */
2950       __IOM uint32_t TMRB7CLR   : 1;            /*!< [27..27] Counter/Timer B7 Clear bit.                                      */
2951       __IOM uint32_t TMRB7POL   : 1;            /*!< [28..28] Counter/Timer B7 output polarity.                                */
2952             uint32_t            : 2;
2953       __IOM uint32_t CTLINK7    : 1;            /*!< [31..31] Counter/Timer A7/B7 Link bit.                                    */
2954     } CTRL7_b;
2955   } ;
2956   __IM  uint32_t  RESERVED7;
2957 
2958   union {
2959     __IOM uint32_t CMPRAUXA7;                   /*!< (@ 0x000000F4) Enhanced compare limits for timer half A.                  */
2960 
2961     struct {
2962       __IOM uint32_t CMPR2A7    : 16;           /*!< [15..0] Counter/Timer A7 Compare Register 2. Holds the lower
2963                                                      limit for timer half A.                                                   */
2964       __IOM uint32_t CMPR3A7    : 16;           /*!< [31..16] Counter/Timer A7 Compare Register 3. Holds the upper
2965                                                      limit for timer half A.                                                   */
2966     } CMPRAUXA7_b;
2967   } ;
2968 
2969   union {
2970     __IOM uint32_t CMPRAUXB7;                   /*!< (@ 0x000000F8) Enhanced compare limits for timer half B.                  */
2971 
2972     struct {
2973       __IOM uint32_t CMPR2B7    : 16;           /*!< [15..0] Counter/Timer B7 Compare Register 2. Holds the lower
2974                                                      limit for timer half B.                                                   */
2975       __IOM uint32_t CMPR3B7    : 16;           /*!< [31..16] Counter/Timer B7 Compare Register 3. Holds the upper
2976                                                      limit for timer half B.                                                   */
2977     } CMPRAUXB7_b;
2978   } ;
2979 
2980   union {
2981     __IOM uint32_t AUX7;                        /*!< (@ 0x000000FC) Control bit fields for both halves of timer 0.             */
2982 
2983     struct {
2984       __IOM uint32_t TMRA7LMT   : 7;            /*!< [6..0] Counter/Timer A7 Pattern Limit Count.                              */
2985       __IOM uint32_t TMRA7TRIG  : 4;            /*!< [10..7] Counter/Timer A7 Trigger Select.                                  */
2986       __IOM uint32_t TMRA7NOSYNC : 1;           /*!< [11..11] Source clock synchronization control.                            */
2987       __IOM uint32_t TMRA7TINV  : 1;            /*!< [12..12] Counter/Timer A7 Invert on trigger.                              */
2988       __IOM uint32_t TMRA7POL23 : 1;            /*!< [13..13] Counter/Timer A7 Upper output polarity                           */
2989       __IOM uint32_t TMRA7EN23  : 1;            /*!< [14..14] Counter/Timer A7 Upper compare enable.                           */
2990             uint32_t            : 1;
2991       __IOM uint32_t TMRB7LMT   : 6;            /*!< [21..16] Counter/Timer B7 Pattern Limit Count.                            */
2992             uint32_t            : 1;
2993       __IOM uint32_t TMRB7TRIG  : 4;            /*!< [26..23] Counter/Timer B7 Trigger Select.                                 */
2994       __IOM uint32_t TMRB7NOSYNC : 1;           /*!< [27..27] Source clock synchronization control.                            */
2995       __IOM uint32_t TMRB7TINV  : 1;            /*!< [28..28] Counter/Timer B7 Invert on trigger.                              */
2996       __IOM uint32_t TMRB7POL23 : 1;            /*!< [29..29] Upper output polarity                                            */
2997       __IOM uint32_t TMRB7EN23  : 1;            /*!< [30..30] Counter/Timer B7 Upper compare enable.                           */
2998             uint32_t            : 1;
2999     } AUX7_b;
3000   } ;
3001 
3002   union {
3003     __IOM uint32_t GLOBEN;                      /*!< (@ 0x00000100) Alternate enables for all CTIMERs.                         */
3004 
3005     struct {
3006       __IOM uint32_t ENA0       : 1;            /*!< [0..0] Alternate enable for A0                                            */
3007       __IOM uint32_t ENB0       : 1;            /*!< [1..1] Alternate enable for B0                                            */
3008       __IOM uint32_t ENA1       : 1;            /*!< [2..2] Alternate enable for A1                                            */
3009       __IOM uint32_t ENB1       : 1;            /*!< [3..3] Alternate enable for B1                                            */
3010       __IOM uint32_t ENA2       : 1;            /*!< [4..4] Alternate enable for A2                                            */
3011       __IOM uint32_t ENB2       : 1;            /*!< [5..5] Alternate enable for B2                                            */
3012       __IOM uint32_t ENA3       : 1;            /*!< [6..6] Alternate enable for A3                                            */
3013       __IOM uint32_t ENB3       : 1;            /*!< [7..7] Alternate enable for B3.                                           */
3014       __IOM uint32_t ENA4       : 1;            /*!< [8..8] Alternate enable for A4                                            */
3015       __IOM uint32_t ENB4       : 1;            /*!< [9..9] Alternate enable for B4                                            */
3016       __IOM uint32_t ENA5       : 1;            /*!< [10..10] Alternate enable for A5                                          */
3017       __IOM uint32_t ENB5       : 1;            /*!< [11..11] Alternate enable for B5                                          */
3018       __IOM uint32_t ENA6       : 1;            /*!< [12..12] Alternate enable for A6                                          */
3019       __IOM uint32_t ENB6       : 1;            /*!< [13..13] Alternate enable for B6                                          */
3020       __IOM uint32_t ENA7       : 1;            /*!< [14..14] Alternate enable for A7                                          */
3021       __IOM uint32_t ENB7       : 1;            /*!< [15..15] Alternate enable for B7.                                         */
3022             uint32_t            : 16;
3023     } GLOBEN_b;
3024   } ;
3025 
3026   union {
3027     __IOM uint32_t OUTCFG0;                     /*!< (@ 0x00000104) Pad output configuration 0.                                */
3028 
3029     struct {
3030       __IOM uint32_t CFG0       : 3;            /*!< [2..0] Pad output 0 configuration                                         */
3031       __IOM uint32_t CFG1       : 3;            /*!< [5..3] Pad output 1 configuration                                         */
3032       __IOM uint32_t CFG2       : 3;            /*!< [8..6] Pad output 2 configuration                                         */
3033       __IOM uint32_t CFG3       : 3;            /*!< [11..9] Pad output 3 configuration                                        */
3034       __IOM uint32_t CFG4       : 3;            /*!< [14..12] Pad output 4 configuration                                       */
3035             uint32_t            : 1;
3036       __IOM uint32_t CFG5       : 3;            /*!< [18..16] Pad output 5 configuration                                       */
3037       __IOM uint32_t CFG6       : 3;            /*!< [21..19] Pad output 6 configuration                                       */
3038       __IOM uint32_t CFG7       : 3;            /*!< [24..22] Pad output 7 configuration                                       */
3039       __IOM uint32_t CFG8       : 3;            /*!< [27..25] Pad output 8 configuration                                       */
3040       __IOM uint32_t CFG9       : 3;            /*!< [30..28] Pad output 9 configuration                                       */
3041             uint32_t            : 1;
3042     } OUTCFG0_b;
3043   } ;
3044 
3045   union {
3046     __IOM uint32_t OUTCFG1;                     /*!< (@ 0x00000108) Pad output configuration 1.                                */
3047 
3048     struct {
3049       __IOM uint32_t CFG10      : 3;            /*!< [2..0] Pad output 10 configuration                                        */
3050       __IOM uint32_t CFG11      : 3;            /*!< [5..3] Pad output 11 configuration                                        */
3051       __IOM uint32_t CFG12      : 3;            /*!< [8..6] Pad output 12 configuration                                        */
3052       __IOM uint32_t CFG13      : 3;            /*!< [11..9] Pad output 13 configuration                                       */
3053       __IOM uint32_t CFG14      : 3;            /*!< [14..12] Pad output 14 configuration                                      */
3054             uint32_t            : 1;
3055       __IOM uint32_t CFG15      : 3;            /*!< [18..16] Pad output 15 configuration                                      */
3056       __IOM uint32_t CFG16      : 3;            /*!< [21..19] Pad output 16 configuration                                      */
3057       __IOM uint32_t CFG17      : 3;            /*!< [24..22] Pad output 17 configuration                                      */
3058       __IOM uint32_t CFG18      : 3;            /*!< [27..25] Pad output 18 configuration                                      */
3059       __IOM uint32_t CFG19      : 3;            /*!< [30..28] Pad output 19 configuration                                      */
3060             uint32_t            : 1;
3061     } OUTCFG1_b;
3062   } ;
3063 
3064   union {
3065     __IOM uint32_t OUTCFG2;                     /*!< (@ 0x0000010C) Pad output configuration 2.                                */
3066 
3067     struct {
3068       __IOM uint32_t CFG20      : 3;            /*!< [2..0] Pad output 20 configuration                                        */
3069       __IOM uint32_t CFG21      : 3;            /*!< [5..3] Pad output 21 configuration                                        */
3070       __IOM uint32_t CFG22      : 3;            /*!< [8..6] Pad output 22 configuration                                        */
3071       __IOM uint32_t CFG23      : 3;            /*!< [11..9] Pad output 23 configuration                                       */
3072       __IOM uint32_t CFG24      : 3;            /*!< [14..12] Pad output 24 configuration                                      */
3073             uint32_t            : 1;
3074       __IOM uint32_t CFG25      : 3;            /*!< [18..16] Pad output 25 configuration                                      */
3075       __IOM uint32_t CFG26      : 3;            /*!< [21..19] Pad output 26 configuration                                      */
3076       __IOM uint32_t CFG27      : 3;            /*!< [24..22] Pad output 27 configuration                                      */
3077       __IOM uint32_t CFG28      : 3;            /*!< [27..25] Pad output 28 configuration                                      */
3078       __IOM uint32_t CFG29      : 3;            /*!< [30..28] Pad output 29 configuration                                      */
3079             uint32_t            : 1;
3080     } OUTCFG2_b;
3081   } ;
3082   __IM  uint32_t  RESERVED8;
3083 
3084   union {
3085     __IOM uint32_t OUTCFG3;                     /*!< (@ 0x00000114) Pad output configuration 3.                                */
3086 
3087     struct {
3088       __IOM uint32_t CFG30      : 3;            /*!< [2..0] Pad output 30 configuration                                        */
3089       __IOM uint32_t CFG31      : 3;            /*!< [5..3] Pad output 31 configuration                                        */
3090             uint32_t            : 26;
3091     } OUTCFG3_b;
3092   } ;
3093 
3094   union {
3095     __IOM uint32_t INCFG;                       /*!< (@ 0x00000118) Pad input configuration.                                   */
3096 
3097     struct {
3098       __IOM uint32_t CFGA0      : 1;            /*!< [0..0] CTIMER A0 input configuration                                      */
3099       __IOM uint32_t CFGB0      : 1;            /*!< [1..1] CTIMER B0 input configuration                                      */
3100       __IOM uint32_t CFGA1      : 1;            /*!< [2..2] CTIMER A1 input configuration                                      */
3101       __IOM uint32_t CFGB1      : 1;            /*!< [3..3] CTIMER B1 input configuration                                      */
3102       __IOM uint32_t CFGA2      : 1;            /*!< [4..4] CTIMER A2 input configuration                                      */
3103       __IOM uint32_t CFGB2      : 1;            /*!< [5..5] CTIMER B2 input configuration                                      */
3104       __IOM uint32_t CFGA3      : 1;            /*!< [6..6] CTIMER A3 input configuration                                      */
3105       __IOM uint32_t CFGB3      : 1;            /*!< [7..7] CTIMER B3 input configuration                                      */
3106       __IOM uint32_t CFGA4      : 1;            /*!< [8..8] CTIMER A4 input configuration                                      */
3107       __IOM uint32_t CFGB4      : 1;            /*!< [9..9] CTIMER B4 input configuration                                      */
3108       __IOM uint32_t CFGA5      : 1;            /*!< [10..10] CTIMER A5 input configuration                                    */
3109       __IOM uint32_t CFGB5      : 1;            /*!< [11..11] CTIMER B5 input configuration                                    */
3110       __IOM uint32_t CFGA6      : 1;            /*!< [12..12] CTIMER A6 input configuration                                    */
3111       __IOM uint32_t CFGB6      : 1;            /*!< [13..13] CTIMER B6 input configuration                                    */
3112       __IOM uint32_t CFGA7      : 1;            /*!< [14..14] CTIMER A7 input configuration                                    */
3113       __IOM uint32_t CFGB7      : 1;            /*!< [15..15] CTIMER B7 input configuration                                    */
3114             uint32_t            : 16;
3115     } INCFG_b;
3116   } ;
3117   __IM  uint32_t  RESERVED9[9];
3118 
3119   union {
3120     __IOM uint32_t STCFG;                       /*!< (@ 0x00000140) The STIMER Configuration Register contains the
3121                                                                     software control for selecting the clock
3122                                                                     divider and source feeding the system timer.               */
3123 
3124     struct {
3125       __IOM uint32_t CLKSEL     : 4;            /*!< [3..0] Selects an appropriate clock source and divider to use
3126                                                      for the System Timer clock.                                               */
3127             uint32_t            : 4;
3128       __IOM uint32_t COMPARE_A_EN : 1;          /*!< [8..8] Selects whether compare is enabled for the corresponding
3129                                                      SCMPR register. If compare is enabled, the interrupt status
3130                                                      is set once the comparison is met.                                        */
3131       __IOM uint32_t COMPARE_B_EN : 1;          /*!< [9..9] Selects whether compare is enabled for the corresponding
3132                                                      SCMPR register. If compare is enabled, the interrupt status
3133                                                      is set once the comparison is met.                                        */
3134       __IOM uint32_t COMPARE_C_EN : 1;          /*!< [10..10] Selects whether compare is enabled for the corresponding
3135                                                      SCMPR register. If compare is enabled, the interrupt status
3136                                                      is set once the comparison is met.                                        */
3137       __IOM uint32_t COMPARE_D_EN : 1;          /*!< [11..11] Selects whether compare is enabled for the corresponding
3138                                                      SCMPR register. If compare is enabled, the interrupt status
3139                                                      is set once the comparison is met.                                        */
3140       __IOM uint32_t COMPARE_E_EN : 1;          /*!< [12..12] Selects whether compare is enabled for the corresponding
3141                                                      SCMPR register. If compare is enabled, the interrupt status
3142                                                      is set once the comparison is met.                                        */
3143       __IOM uint32_t COMPARE_F_EN : 1;          /*!< [13..13] Selects whether compare is enabled for the corresponding
3144                                                      SCMPR register. If compare is enabled, the interrupt status
3145                                                      is set once the comparison is met.                                        */
3146       __IOM uint32_t COMPARE_G_EN : 1;          /*!< [14..14] Selects whether compare is enabled for the corresponding
3147                                                      SCMPR register. If compare is enabled, the interrupt status
3148                                                      is set once the comparison is met.                                        */
3149       __IOM uint32_t COMPARE_H_EN : 1;          /*!< [15..15] Selects whether compare is enabled for the corresponding
3150                                                      SCMPR register. If compare is enabled, the interrupt status
3151                                                      is set once the comparison is met.                                        */
3152             uint32_t            : 14;
3153       __IOM uint32_t CLEAR      : 1;            /*!< [30..30] Set this bit to one to clear the System Timer register.
3154                                                      If this bit is set to '1', the system timer register will
3155                                                      stay cleared. It needs to be set to '0' for the system
3156                                                      timer to start running.                                                   */
3157       __IOM uint32_t FREEZE     : 1;            /*!< [31..31] Set this bit to one to freeze the clock input to the
3158                                                      COUNTER register. Once frozen, the value can be safely
3159                                                      written from the MCU. Unfreeze to resume.                                 */
3160     } STCFG_b;
3161   } ;
3162 
3163   union {
3164     __IOM uint32_t STTMR;                       /*!< (@ 0x00000144) The COUNTER Register contains the running count
3165                                                                     of time as maintained by incrementing for
3166                                                                     every rising clock edge of the clock source
3167                                                                     selected in the configuration register.
3168                                                                     It is this counter value that captured in
3169                                                                     the capture registers and it is this counter
3170                                                                     value that is compared against the various
3171                                                                     compare registers. This register cannot
3172                                                                     be written, but can be cleared to 0 for
3173                                                                     a deterministic value. Use the FREEZE bit
3174                                                                     will stop this counter from incrementing.                  */
3175 
3176     struct {
3177       __IOM uint32_t STTMR      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3178     } STTMR_b;
3179   } ;
3180 
3181   union {
3182     __IOM uint32_t CAPTURECONTROL;              /*!< (@ 0x00000148) The STIMER Capture Control Register controls
3183                                                                     each of the 4 capture registers. It selects
3184                                                                     their GPIO pin number for a trigger source,
3185                                                                     enables a capture operation and sets the
3186                                                                     input polarity for the capture. NOTE: 8-bit
3187                                                                     writes can control individual capture registers
3188                                                                     atomically.                                                */
3189 
3190     struct {
3191       __IOM uint32_t CAPTURE0   : 1;            /*!< [0..0] Selects whether capture is enabled for the specified
3192                                                      capture register.                                                         */
3193       __IOM uint32_t CAPTURE1   : 1;            /*!< [1..1] Selects whether capture is enabled for the specified
3194                                                      capture register.                                                         */
3195       __IOM uint32_t CAPTURE2   : 1;            /*!< [2..2] Selects whether capture is enabled for the specified
3196                                                      capture register.                                                         */
3197       __IOM uint32_t CAPTURE3   : 1;            /*!< [3..3] Selects whether capture is enabled for the specified
3198                                                      capture register.                                                         */
3199             uint32_t            : 28;
3200     } CAPTURECONTROL_b;
3201   } ;
3202   __IM  uint32_t  RESERVED10;
3203 
3204   union {
3205     __IOM uint32_t SCMPR0;                      /*!< (@ 0x00000150) The VALUE in this bit field is used to compare
3206                                                                     against the VALUE in the COUNTER register.
3207                                                                     If the match criterion in the configuration
3208                                                                     register is met then a corresponding interrupt
3209                                                                     status bit is set. The match criterion is
3210                                                                     defined as COUNTER equal to COMPARE. To
3211                                                                     establish a desired value in this COMPARE
3212                                                                     register, write the number of ticks in the
3213                                                                     future to this register to indicate when
3214                                                                     to interrupt. The hardware does the addition
3215                                                                     to the COUNTER value in the STIMER clock
3216                                                                     domain so that the ma                                      */
3217 
3218     struct {
3219       __IOM uint32_t SCMPR0     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3220                                                      according to the match criterion, as selected in the COMPARE_A_EN
3221                                                      bit in the REG_CTIMER_STCGF register.                                     */
3222     } SCMPR0_b;
3223   } ;
3224 
3225   union {
3226     __IOM uint32_t SCMPR1;                      /*!< (@ 0x00000154) The VALUE in this bit field is used to compare
3227                                                                     against the VALUE in the COUNTER register.
3228                                                                     If the match criterion in the configuration
3229                                                                     register is met then a corresponding interrupt
3230                                                                     status bit is set. The match criterion is
3231                                                                     defined as COUNTER equal to COMPARE. To
3232                                                                     establish a desired value in this COMPARE
3233                                                                     register, write the number of ticks in the
3234                                                                     future to this register to indicate when
3235                                                                     to interrupt. The hardware does the addition
3236                                                                     to the COUNTER value in the STIMER clock
3237                                                                     domain so that the ma                                      */
3238 
3239     struct {
3240       __IOM uint32_t SCMPR1     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3241                                                      according to the match criterion, as selected in the COMPARE_B_EN
3242                                                      bit in the REG_CTIMER_STCGF register.                                     */
3243     } SCMPR1_b;
3244   } ;
3245 
3246   union {
3247     __IOM uint32_t SCMPR2;                      /*!< (@ 0x00000158) The VALUE in this bit field is used to compare
3248                                                                     against the VALUE in the COUNTER register.
3249                                                                     If the match criterion in the configuration
3250                                                                     register is met then a corresponding interrupt
3251                                                                     status bit is set. The match criterion is
3252                                                                     defined as COUNTER equal to COMPARE. To
3253                                                                     establish a desired value in this COMPARE
3254                                                                     register, write the number of ticks in the
3255                                                                     future to this register to indicate when
3256                                                                     to interrupt. The hardware does the addition
3257                                                                     to the COUNTER value in the STIMER clock
3258                                                                     domain so that the ma                                      */
3259 
3260     struct {
3261       __IOM uint32_t SCMPR2     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3262                                                      according to the match criterion, as selected in the COMPARE_C_EN
3263                                                      bit in the REG_CTIMER_STCGF register.                                     */
3264     } SCMPR2_b;
3265   } ;
3266 
3267   union {
3268     __IOM uint32_t SCMPR3;                      /*!< (@ 0x0000015C) The VALUE in this bit field is used to compare
3269                                                                     against the VALUE in the COUNTER register.
3270                                                                     If the match criterion in the configuration
3271                                                                     register is met then a corresponding interrupt
3272                                                                     status bit is set. The match criterion is
3273                                                                     defined as COUNTER equal to COMPARE. To
3274                                                                     establish a desired value in this COMPARE
3275                                                                     register, write the number of ticks in the
3276                                                                     future to this register to indicate when
3277                                                                     to interrupt. The hardware does the addition
3278                                                                     to the COUNTER value in the STIMER clock
3279                                                                     domain so that the ma                                      */
3280 
3281     struct {
3282       __IOM uint32_t SCMPR3     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3283                                                      according to the match criterion, as selected in the COMPARE_D_EN
3284                                                      bit in the REG_CTIMER_STCGF register.                                     */
3285     } SCMPR3_b;
3286   } ;
3287 
3288   union {
3289     __IOM uint32_t SCMPR4;                      /*!< (@ 0x00000160) The VALUE in this bit field is used to compare
3290                                                                     against the VALUE in the COUNTER register.
3291                                                                     If the match criterion in the configuration
3292                                                                     register is met then a corresponding interrupt
3293                                                                     status bit is set. The match criterion is
3294                                                                     defined as COUNTER equal to COMPARE. To
3295                                                                     establish a desired value in this COMPARE
3296                                                                     register, write the number of ticks in the
3297                                                                     future to this register to indicate when
3298                                                                     to interrupt. The hardware does the addition
3299                                                                     to the COUNTER value in the STIMER clock
3300                                                                     domain so that the ma                                      */
3301 
3302     struct {
3303       __IOM uint32_t SCMPR4     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3304                                                      according to the match criterion, as selected in the COMPARE_E_EN
3305                                                      bit in the REG_CTIMER_STCGF register.                                     */
3306     } SCMPR4_b;
3307   } ;
3308 
3309   union {
3310     __IOM uint32_t SCMPR5;                      /*!< (@ 0x00000164) The VALUE in this bit field is used to compare
3311                                                                     against the VALUE in the COUNTER register.
3312                                                                     If the match criterion in the configuration
3313                                                                     register is met then a corresponding interrupt
3314                                                                     status bit is set. The match criterion is
3315                                                                     defined as COUNTER equal to COMPARE. To
3316                                                                     establish a desired value in this COMPARE
3317                                                                     register, write the number of ticks in the
3318                                                                     future to this register to indicate when
3319                                                                     to interrupt. The hardware does the addition
3320                                                                     to the COUNTER value in the STIMER clock
3321                                                                     domain so that the ma                                      */
3322 
3323     struct {
3324       __IOM uint32_t SCMPR5     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3325                                                      according to the match criterion, as selected in the COMPARE_F_EN
3326                                                      bit in the REG_CTIMER_STCGF register.                                     */
3327     } SCMPR5_b;
3328   } ;
3329 
3330   union {
3331     __IOM uint32_t SCMPR6;                      /*!< (@ 0x00000168) The VALUE in this bit field is used to compare
3332                                                                     against the VALUE in the COUNTER register.
3333                                                                     If the match criterion in the configuration
3334                                                                     register is met then a corresponding interrupt
3335                                                                     status bit is set. The match criterion is
3336                                                                     defined as COUNTER equal to COMPARE. To
3337                                                                     establish a desired value in this COMPARE
3338                                                                     register, write the number of ticks in the
3339                                                                     future to this register to indicate when
3340                                                                     to interrupt. The hardware does the addition
3341                                                                     to the COUNTER value in the STIMER clock
3342                                                                     domain so that the ma                                      */
3343 
3344     struct {
3345       __IOM uint32_t SCMPR6     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3346                                                      according to the match criterion, as selected in the COMPARE_G_EN
3347                                                      bit in the REG_CTIMER_STCGF register.                                     */
3348     } SCMPR6_b;
3349   } ;
3350 
3351   union {
3352     __IOM uint32_t SCMPR7;                      /*!< (@ 0x0000016C) The VALUE in this bit field is used to compare
3353                                                                     against the VALUE in the COUNTER register.
3354                                                                     If the match criterion in the configuration
3355                                                                     register is met then a corresponding interrupt
3356                                                                     status bit is set. The match criterion is
3357                                                                     defined as COUNTER equal to COMPARE. To
3358                                                                     establish a desired value in this COMPARE
3359                                                                     register, write the number of ticks in the
3360                                                                     future to this register to indicate when
3361                                                                     to interrupt. The hardware does the addition
3362                                                                     to the COUNTER value in the STIMER clock
3363                                                                     domain so that the ma                                      */
3364 
3365     struct {
3366       __IOM uint32_t SCMPR7     : 32;           /*!< [31..0] Compare this value to the value in the COUNTER register
3367                                                      according to the match criterion, as selected in the COMPARE_H_EN
3368                                                      bit in the REG_CTIMER_STCGF register.                                     */
3369     } SCMPR7_b;
3370   } ;
3371   __IM  uint32_t  RESERVED11[28];
3372 
3373   union {
3374     __IOM uint32_t SCAPT0;                      /*!< (@ 0x000001E0) The STIMER Capture Register A grabs the VALUE
3375                                                                     in the COUNTER register whenever capture
3376                                                                     condition (event) A is asserted. This register
3377                                                                     holds a time stamp for the event.                          */
3378 
3379     struct {
3380       __IOM uint32_t SCAPT0     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3381                                                      is copied into this register and the corresponding interrupt
3382                                                      status bit is set.                                                        */
3383     } SCAPT0_b;
3384   } ;
3385 
3386   union {
3387     __IOM uint32_t SCAPT1;                      /*!< (@ 0x000001E4) The STIMER Capture Register B grabs the VALUE
3388                                                                     in the COUNTER register whenever capture
3389                                                                     condition (event) B is asserted. This register
3390                                                                     holds a time stamp for the event.                          */
3391 
3392     struct {
3393       __IOM uint32_t SCAPT1     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3394                                                      is copied into this register and the corresponding interrupt
3395                                                      status bit is set.                                                        */
3396     } SCAPT1_b;
3397   } ;
3398 
3399   union {
3400     __IOM uint32_t SCAPT2;                      /*!< (@ 0x000001E8) The STIMER Capture Register C grabs the VALUE
3401                                                                     in the COUNTER register whenever capture
3402                                                                     condition (event) C is asserted. This register
3403                                                                     holds a time stamp for the event.                          */
3404 
3405     struct {
3406       __IOM uint32_t SCAPT2     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3407                                                      is copied into this register and the corresponding interrupt
3408                                                      status bit is set.                                                        */
3409     } SCAPT2_b;
3410   } ;
3411 
3412   union {
3413     __IOM uint32_t SCAPT3;                      /*!< (@ 0x000001EC) The STIMER Capture Register D grabs the VALUE
3414                                                                     in the COUNTER register whenever capture
3415                                                                     condition (event) D is asserted. This register
3416                                                                     holds a time stamp for the event.                          */
3417 
3418     struct {
3419       __IOM uint32_t SCAPT3     : 32;           /*!< [31..0] Whenever the event is detected, the value in the COUNTER
3420                                                      is copied into this register and the corresponding interrupt
3421                                                      status bit is set.                                                        */
3422     } SCAPT3_b;
3423   } ;
3424 
3425   union {
3426     __IOM uint32_t SNVR0;                       /*!< (@ 0x000001F0) The NVRAM_A Register contains a portion of the
3427                                                                     stored epoch offset associated with the
3428                                                                     time in the COUNTER register. This register
3429                                                                     is only reset by POI not by HRESETn. Its
3430                                                                     contents are intended to survive all reset
3431                                                                     level except POI and full power cycles.                    */
3432 
3433     struct {
3434       __IOM uint32_t SNVR0      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3435     } SNVR0_b;
3436   } ;
3437 
3438   union {
3439     __IOM uint32_t SNVR1;                       /*!< (@ 0x000001F4) The NVRAM_B Register contains a portion of the
3440                                                                     stored epoch offset associated with the
3441                                                                     time in the COUNTER register. This register
3442                                                                     is only reset by POI not by HRESETn. Its
3443                                                                     contents are intended to survive all reset
3444                                                                     level except POI and full power cycles.                    */
3445 
3446     struct {
3447       __IOM uint32_t SNVR1      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3448     } SNVR1_b;
3449   } ;
3450 
3451   union {
3452     __IOM uint32_t SNVR2;                       /*!< (@ 0x000001F8) The NVRAM_C Register contains a portion of the
3453                                                                     stored epoch offset associated with the
3454                                                                     time in the COUNTER register. This register
3455                                                                     is only reset by POI not by HRESETn. Its
3456                                                                     contents are intended to survive all reset
3457                                                                     level except POI and full power cycles.                    */
3458 
3459     struct {
3460       __IOM uint32_t SNVR2      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3461     } SNVR2_b;
3462   } ;
3463 
3464   union {
3465     __IOM uint32_t SNVR3;                       /*!< (@ 0x000001FC) The NVRAM_D Register contains a portion of the
3466                                                                     stored epoch offset associated with the
3467                                                                     time in the COUNTER register. This register
3468                                                                     is only reset by POI not by HRESETn. Its
3469                                                                     contents are intended to survive all reset
3470                                                                     level except POI and full power cycles.                    */
3471 
3472     struct {
3473       __IOM uint32_t SNVR3      : 32;           /*!< [31..0] Value of the 32-bit counter as it ticks over.                     */
3474     } SNVR3_b;
3475   } ;
3476 
3477   union {
3478     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
3479                                                                     to generate the corresponding interrupt.                   */
3480 
3481     struct {
3482       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3483       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3484       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3485       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3486       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3487       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3488       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3489       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3490       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3491       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3492       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3493       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3494       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3495       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3496       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3497       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3498       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3499       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3500       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3501       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3502       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3503       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3504       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3505       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3506       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3507       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3508       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3509       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3510       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3511       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3512       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3513       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3514     } INTEN_b;
3515   } ;
3516 
3517   union {
3518     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
3519                                                                     cause of a recent interrupt.                               */
3520 
3521     struct {
3522       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3523       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3524       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3525       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3526       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3527       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3528       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3529       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3530       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3531       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3532       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3533       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3534       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3535       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3536       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3537       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3538       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3539       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3540       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3541       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3542       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3543       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3544       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3545       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3546       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3547       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3548       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3549       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3550       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3551       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3552       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3553       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3554     } INTSTAT_b;
3555   } ;
3556 
3557   union {
3558     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
3559                                                                     the interrupt status associated with that
3560                                                                     bit.                                                       */
3561 
3562     struct {
3563       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3564       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3565       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3566       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3567       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3568       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3569       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3570       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3571       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3572       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3573       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3574       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3575       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3576       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3577       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3578       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3579       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3580       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3581       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3582       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3583       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3584       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3585       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3586       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3587       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3588       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3589       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3590       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3591       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3592       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3593       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3594       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3595     } INTCLR_b;
3596   } ;
3597 
3598   union {
3599     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
3600                                                                     generate an interrupt from this module.
3601                                                                     (Generally used for testing purposes).                     */
3602 
3603     struct {
3604       __IOM uint32_t CTMRA0C0INT : 1;           /*!< [0..0] Counter/Timer A0 interrupt based on COMPR0.                        */
3605       __IOM uint32_t CTMRB0C0INT : 1;           /*!< [1..1] Counter/Timer B0 interrupt based on COMPR0.                        */
3606       __IOM uint32_t CTMRA1C0INT : 1;           /*!< [2..2] Counter/Timer A1 interrupt based on COMPR0.                        */
3607       __IOM uint32_t CTMRB1C0INT : 1;           /*!< [3..3] Counter/Timer B1 interrupt based on COMPR0.                        */
3608       __IOM uint32_t CTMRA2C0INT : 1;           /*!< [4..4] Counter/Timer A2 interrupt based on COMPR0.                        */
3609       __IOM uint32_t CTMRB2C0INT : 1;           /*!< [5..5] Counter/Timer B2 interrupt based on COMPR0.                        */
3610       __IOM uint32_t CTMRA3C0INT : 1;           /*!< [6..6] Counter/Timer A3 interrupt based on COMPR0.                        */
3611       __IOM uint32_t CTMRB3C0INT : 1;           /*!< [7..7] Counter/Timer B3 interrupt based on COMPR0.                        */
3612       __IOM uint32_t CTMRA4C0INT : 1;           /*!< [8..8] Counter/Timer A4 interrupt based on COMPR0.                        */
3613       __IOM uint32_t CTMRB4C0INT : 1;           /*!< [9..9] Counter/Timer B4 interrupt based on COMPR0.                        */
3614       __IOM uint32_t CTMRA5C0INT : 1;           /*!< [10..10] Counter/Timer A5 interrupt based on COMPR0.                      */
3615       __IOM uint32_t CTMRB5C0INT : 1;           /*!< [11..11] Counter/Timer B5 interrupt based on COMPR0.                      */
3616       __IOM uint32_t CTMRA6C0INT : 1;           /*!< [12..12] Counter/Timer A6 interrupt based on COMPR0.                      */
3617       __IOM uint32_t CTMRB6C0INT : 1;           /*!< [13..13] Counter/Timer B6 interrupt based on COMPR0.                      */
3618       __IOM uint32_t CTMRA7C0INT : 1;           /*!< [14..14] Counter/Timer A7 interrupt based on COMPR0.                      */
3619       __IOM uint32_t CTMRB7C0INT : 1;           /*!< [15..15] Counter/Timer B7 interrupt based on COMPR0.                      */
3620       __IOM uint32_t CTMRA0C1INT : 1;           /*!< [16..16] Counter/Timer A0 interrupt based on COMPR1.                      */
3621       __IOM uint32_t CTMRB0C1INT : 1;           /*!< [17..17] Counter/Timer B0 interrupt based on COMPR1.                      */
3622       __IOM uint32_t CTMRA1C1INT : 1;           /*!< [18..18] Counter/Timer A1 interrupt based on COMPR1.                      */
3623       __IOM uint32_t CTMRB1C1INT : 1;           /*!< [19..19] Counter/Timer B1 interrupt based on COMPR1.                      */
3624       __IOM uint32_t CTMRA2C1INT : 1;           /*!< [20..20] Counter/Timer A2 interrupt based on COMPR1.                      */
3625       __IOM uint32_t CTMRB2C1INT : 1;           /*!< [21..21] Counter/Timer B2 interrupt based on COMPR1.                      */
3626       __IOM uint32_t CTMRA3C1INT : 1;           /*!< [22..22] Counter/Timer A3 interrupt based on COMPR1.                      */
3627       __IOM uint32_t CTMRB3C1INT : 1;           /*!< [23..23] Counter/Timer B3 interrupt based on COMPR1.                      */
3628       __IOM uint32_t CTMRA4C1INT : 1;           /*!< [24..24] Counter/Timer A4 interrupt based on COMPR1.                      */
3629       __IOM uint32_t CTMRB4C1INT : 1;           /*!< [25..25] Counter/Timer B4 interrupt based on COMPR1.                      */
3630       __IOM uint32_t CTMRA5C1INT : 1;           /*!< [26..26] Counter/Timer A5 interrupt based on COMPR1.                      */
3631       __IOM uint32_t CTMRB5C1INT : 1;           /*!< [27..27] Counter/Timer B5 interrupt based on COMPR1.                      */
3632       __IOM uint32_t CTMRA6C1INT : 1;           /*!< [28..28] Counter/Timer A6 interrupt based on COMPR1.                      */
3633       __IOM uint32_t CTMRB6C1INT : 1;           /*!< [29..29] Counter/Timer B6 interrupt based on COMPR1.                      */
3634       __IOM uint32_t CTMRA7C1INT : 1;           /*!< [30..30] Counter/Timer A7 interrupt based on COMPR1.                      */
3635       __IOM uint32_t CTMRB7C1INT : 1;           /*!< [31..31] Counter/Timer B7 interrupt based on COMPR1.                      */
3636     } INTSET_b;
3637   } ;
3638   __IM  uint32_t  RESERVED12[60];
3639 
3640   union {
3641     __IOM uint32_t STMINTEN;                    /*!< (@ 0x00000300) Set bits in this register to allow this module
3642                                                                     to generate the corresponding interrupt.                   */
3643 
3644     struct {
3645       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3646                                                      A.                                                                        */
3647       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3648                                                      B.                                                                        */
3649       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3650                                                      C.                                                                        */
3651       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3652                                                      D.                                                                        */
3653       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3654                                                      E.                                                                        */
3655       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3656                                                      F.                                                                        */
3657       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3658                                                      G.                                                                        */
3659       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3660                                                      H.                                                                        */
3661       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3662       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3663       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3664       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3665       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3666             uint32_t            : 19;
3667     } STMINTEN_b;
3668   } ;
3669 
3670   union {
3671     __IOM uint32_t STMINTSTAT;                  /*!< (@ 0x00000304) Read bits from this register to discover the
3672                                                                     cause of a recent interrupt.                               */
3673 
3674     struct {
3675       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3676                                                      A.                                                                        */
3677       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3678                                                      B.                                                                        */
3679       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3680                                                      C.                                                                        */
3681       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3682                                                      D.                                                                        */
3683       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3684                                                      E.                                                                        */
3685       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3686                                                      F.                                                                        */
3687       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3688                                                      G.                                                                        */
3689       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3690                                                      H.                                                                        */
3691       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3692       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3693       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3694       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3695       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3696             uint32_t            : 19;
3697     } STMINTSTAT_b;
3698   } ;
3699 
3700   union {
3701     __IOM uint32_t STMINTCLR;                   /*!< (@ 0x00000308) Write a 1 to a bit in this register to clear
3702                                                                     the interrupt status associated with that
3703                                                                     bit.                                                       */
3704 
3705     struct {
3706       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3707                                                      A.                                                                        */
3708       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3709                                                      B.                                                                        */
3710       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3711                                                      C.                                                                        */
3712       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3713                                                      D.                                                                        */
3714       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3715                                                      E.                                                                        */
3716       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3717                                                      F.                                                                        */
3718       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3719                                                      G.                                                                        */
3720       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3721                                                      H.                                                                        */
3722       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3723       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3724       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3725       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3726       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3727             uint32_t            : 19;
3728     } STMINTCLR_b;
3729   } ;
3730 
3731   union {
3732     __IOM uint32_t STMINTSET;                   /*!< (@ 0x0000030C) Write a 1 to a bit in this register to instantly
3733                                                                     generate an interrupt from this module.
3734                                                                     (Generally used for testing purposes).                     */
3735 
3736     struct {
3737       __IOM uint32_t COMPAREA   : 1;            /*!< [0..0] COUNTER is greater than or equal to COMPARE register
3738                                                      A.                                                                        */
3739       __IOM uint32_t COMPAREB   : 1;            /*!< [1..1] COUNTER is greater than or equal to COMPARE register
3740                                                      B.                                                                        */
3741       __IOM uint32_t COMPAREC   : 1;            /*!< [2..2] COUNTER is greater than or equal to COMPARE register
3742                                                      C.                                                                        */
3743       __IOM uint32_t COMPARED   : 1;            /*!< [3..3] COUNTER is greater than or equal to COMPARE register
3744                                                      D.                                                                        */
3745       __IOM uint32_t COMPAREE   : 1;            /*!< [4..4] COUNTER is greater than or equal to COMPARE register
3746                                                      E.                                                                        */
3747       __IOM uint32_t COMPAREF   : 1;            /*!< [5..5] COUNTER is greater than or equal to COMPARE register
3748                                                      F.                                                                        */
3749       __IOM uint32_t COMPAREG   : 1;            /*!< [6..6] COUNTER is greater than or equal to COMPARE register
3750                                                      G.                                                                        */
3751       __IOM uint32_t COMPAREH   : 1;            /*!< [7..7] COUNTER is greater than or equal to COMPARE register
3752                                                      H.                                                                        */
3753       __IOM uint32_t OVERFLOW   : 1;            /*!< [8..8] COUNTER over flowed from 0xFFFFFFFF back to 0x00000000.            */
3754       __IOM uint32_t CAPTUREA   : 1;            /*!< [9..9] CAPTURE register A has grabbed the value in the counter            */
3755       __IOM uint32_t CAPTUREB   : 1;            /*!< [10..10] CAPTURE register B has grabbed the value in the counter          */
3756       __IOM uint32_t CAPTUREC   : 1;            /*!< [11..11] CAPTURE register C has grabbed the value in the counter          */
3757       __IOM uint32_t CAPTURED   : 1;            /*!< [12..12] CAPTURE register D has grabbed the value in the counter          */
3758             uint32_t            : 19;
3759     } STMINTSET_b;
3760   } ;
3761 } CTIMER_Type;                                  /*!< Size = 784 (0x310)                                                        */
3762 
3763 
3764 
3765 /* =========================================================================================================================== */
3766 /* ================                                           GPIO                                            ================ */
3767 /* =========================================================================================================================== */
3768 
3769 
3770 /**
3771   * @brief General Purpose IO (GPIO)
3772   */
3773 
3774 typedef struct {                                /*!< (@ 0x40010000) GPIO Structure                                             */
3775 
3776   union {
3777     __IOM uint32_t PADREGA;                     /*!< (@ 0x00000000) This register controls the pad configuration
3778                                                                     controls for PAD3 through PAD0. Writes to
3779                                                                     this register must be unlocked by the PADKEY
3780                                                                     register.                                                  */
3781 
3782     struct {
3783       __IOM uint32_t PAD0PULL   : 1;            /*!< [0..0] Pad 0 pullup enable                                                */
3784       __IOM uint32_t PAD0INPEN  : 1;            /*!< [1..1] Pad 0 input enable                                                 */
3785       __IOM uint32_t PAD0STRNG  : 1;            /*!< [2..2] Pad 0 drive strength                                               */
3786       __IOM uint32_t PAD0FNCSEL : 3;            /*!< [5..3] Pad 0 function select                                              */
3787       __IOM uint32_t PAD0RSEL   : 2;            /*!< [7..6] Pad 0 pullup resistor selection.                                   */
3788       __IOM uint32_t PAD1PULL   : 1;            /*!< [8..8] Pad 1 pullup enable                                                */
3789       __IOM uint32_t PAD1INPEN  : 1;            /*!< [9..9] Pad 1 input enable                                                 */
3790       __IOM uint32_t PAD1STRNG  : 1;            /*!< [10..10] Pad 1 drive strength                                             */
3791       __IOM uint32_t PAD1FNCSEL : 3;            /*!< [13..11] Pad 1 function select                                            */
3792       __IOM uint32_t PAD1RSEL   : 2;            /*!< [15..14] Pad 1 pullup resistor selection.                                 */
3793       __IOM uint32_t PAD2PULL   : 1;            /*!< [16..16] Pad 2 pullup enable                                              */
3794       __IOM uint32_t PAD2INPEN  : 1;            /*!< [17..17] Pad 2 input enable                                               */
3795       __IOM uint32_t PAD2STRNG  : 1;            /*!< [18..18] Pad 2 drive strength                                             */
3796       __IOM uint32_t PAD2FNCSEL : 3;            /*!< [21..19] Pad 2 function select                                            */
3797             uint32_t            : 2;
3798       __IOM uint32_t PAD3PULL   : 1;            /*!< [24..24] Pad 3 pullup enable                                              */
3799       __IOM uint32_t PAD3INPEN  : 1;            /*!< [25..25] Pad 3 input enable.                                              */
3800       __IOM uint32_t PAD3STRNG  : 1;            /*!< [26..26] Pad 3 drive strength.                                            */
3801       __IOM uint32_t PAD3FNCSEL : 3;            /*!< [29..27] Pad 3 function select                                            */
3802       __IOM uint32_t PAD3PWRUP  : 1;            /*!< [30..30] Pad 3 VDD power switch enable                                    */
3803             uint32_t            : 1;
3804     } PADREGA_b;
3805   } ;
3806 
3807   union {
3808     __IOM uint32_t PADREGB;                     /*!< (@ 0x00000004) This register controls the pad configuration
3809                                                                     controls for PAD7 through PAD4. Writes to
3810                                                                     this register must be unlocked by the PADKEY
3811                                                                     register.                                                  */
3812 
3813     struct {
3814       __IOM uint32_t PAD4PULL   : 1;            /*!< [0..0] Pad 4 pullup enable                                                */
3815       __IOM uint32_t PAD4INPEN  : 1;            /*!< [1..1] Pad 4 input enable                                                 */
3816       __IOM uint32_t PAD4STRNG  : 1;            /*!< [2..2] Pad 4 drive strength                                               */
3817       __IOM uint32_t PAD4FNCSEL : 3;            /*!< [5..3] Pad 4 function select                                              */
3818             uint32_t            : 2;
3819       __IOM uint32_t PAD5PULL   : 1;            /*!< [8..8] Pad 5 pullup enable                                                */
3820       __IOM uint32_t PAD5INPEN  : 1;            /*!< [9..9] Pad 5 input enable                                                 */
3821       __IOM uint32_t PAD5STRNG  : 1;            /*!< [10..10] Pad 5 drive strength                                             */
3822       __IOM uint32_t PAD5FNCSEL : 3;            /*!< [13..11] Pad 5 function select                                            */
3823       __IOM uint32_t PAD5RSEL   : 2;            /*!< [15..14] Pad 5 pullup resistor selection.                                 */
3824       __IOM uint32_t PAD6PULL   : 1;            /*!< [16..16] Pad 6 pullup enable                                              */
3825       __IOM uint32_t PAD6INPEN  : 1;            /*!< [17..17] Pad 6 input enable                                               */
3826       __IOM uint32_t PAD6STRNG  : 1;            /*!< [18..18] Pad 6 drive strength                                             */
3827       __IOM uint32_t PAD6FNCSEL : 3;            /*!< [21..19] Pad 6 function select                                            */
3828       __IOM uint32_t PAD6RSEL   : 2;            /*!< [23..22] Pad 6 pullup resistor selection.                                 */
3829       __IOM uint32_t PAD7PULL   : 1;            /*!< [24..24] Pad 7 pullup enable                                              */
3830       __IOM uint32_t PAD7INPEN  : 1;            /*!< [25..25] Pad 7 input enable                                               */
3831       __IOM uint32_t PAD7STRNG  : 1;            /*!< [26..26] Pad 7 drive strength                                             */
3832       __IOM uint32_t PAD7FNCSEL : 3;            /*!< [29..27] Pad 7 function select                                            */
3833             uint32_t            : 2;
3834     } PADREGB_b;
3835   } ;
3836 
3837   union {
3838     __IOM uint32_t PADREGC;                     /*!< (@ 0x00000008) This register controls the pad configuration
3839                                                                     controls for PAD11 through PAD8. Writes
3840                                                                     to this register must be unlocked by the
3841                                                                     PADKEY register.                                           */
3842 
3843     struct {
3844       __IOM uint32_t PAD8PULL   : 1;            /*!< [0..0] Pad 8 pullup enable                                                */
3845       __IOM uint32_t PAD8INPEN  : 1;            /*!< [1..1] Pad 8 input enable                                                 */
3846       __IOM uint32_t PAD8STRNG  : 1;            /*!< [2..2] Pad 8 drive strength                                               */
3847       __IOM uint32_t PAD8FNCSEL : 3;            /*!< [5..3] Pad 8 function select                                              */
3848       __IOM uint32_t PAD8RSEL   : 2;            /*!< [7..6] Pad 8 pullup resistor selection.                                   */
3849       __IOM uint32_t PAD9PULL   : 1;            /*!< [8..8] Pad 9 pullup enable                                                */
3850       __IOM uint32_t PAD9INPEN  : 1;            /*!< [9..9] Pad 9 input enable                                                 */
3851       __IOM uint32_t PAD9STRNG  : 1;            /*!< [10..10] Pad 9 drive strength                                             */
3852       __IOM uint32_t PAD9FNCSEL : 3;            /*!< [13..11] Pad 9 function select                                            */
3853       __IOM uint32_t PAD9RSEL   : 2;            /*!< [15..14] Pad 9 pullup resistor selection                                  */
3854       __IOM uint32_t PAD10PULL  : 1;            /*!< [16..16] Pad 10 pullup enable                                             */
3855       __IOM uint32_t PAD10INPEN : 1;            /*!< [17..17] Pad 10 input enable                                              */
3856       __IOM uint32_t PAD10STRNG : 1;            /*!< [18..18] Pad 10 drive strength                                            */
3857       __IOM uint32_t PAD10FNCSEL : 3;           /*!< [21..19] Pad 10 function select                                           */
3858             uint32_t            : 2;
3859       __IOM uint32_t PAD11PULL  : 1;            /*!< [24..24] Pad 11 pullup enable                                             */
3860       __IOM uint32_t PAD11INPEN : 1;            /*!< [25..25] Pad 11 input enable                                              */
3861       __IOM uint32_t PAD11STRNG : 1;            /*!< [26..26] Pad 11 drive strength                                            */
3862       __IOM uint32_t PAD11FNCSEL : 3;           /*!< [29..27] Pad 11 function select                                           */
3863             uint32_t            : 2;
3864     } PADREGC_b;
3865   } ;
3866 
3867   union {
3868     __IOM uint32_t PADREGD;                     /*!< (@ 0x0000000C) This register controls the pad configuration
3869                                                                     controls for PAD15 through PAD12. Writes
3870                                                                     to this register must be unlocked by the
3871                                                                     PADKEY register.                                           */
3872 
3873     struct {
3874       __IOM uint32_t PAD12PULL  : 1;            /*!< [0..0] Pad 12 pullup enable                                               */
3875       __IOM uint32_t PAD12INPEN : 1;            /*!< [1..1] Pad 12 input enable                                                */
3876       __IOM uint32_t PAD12STRNG : 1;            /*!< [2..2] Pad 12 drive strength                                              */
3877       __IOM uint32_t PAD12FNCSEL : 3;           /*!< [5..3] Pad 12 function select                                             */
3878             uint32_t            : 2;
3879       __IOM uint32_t PAD13PULL  : 1;            /*!< [8..8] Pad 13 pullup enable                                               */
3880       __IOM uint32_t PAD13INPEN : 1;            /*!< [9..9] Pad 13 input enable                                                */
3881       __IOM uint32_t PAD13STRNG : 1;            /*!< [10..10] Pad 13 drive strength                                            */
3882       __IOM uint32_t PAD13FNCSEL : 3;           /*!< [13..11] Pad 13 function select                                           */
3883             uint32_t            : 2;
3884       __IOM uint32_t PAD14PULL  : 1;            /*!< [16..16] Pad 14 pullup enable                                             */
3885       __IOM uint32_t PAD14INPEN : 1;            /*!< [17..17] Pad 14 input enable                                              */
3886       __IOM uint32_t PAD14STRNG : 1;            /*!< [18..18] Pad 14 drive strength                                            */
3887       __IOM uint32_t PAD14FNCSEL : 3;           /*!< [21..19] Pad 14 function select                                           */
3888             uint32_t            : 2;
3889       __IOM uint32_t PAD15PULL  : 1;            /*!< [24..24] Pad 15 pullup enable                                             */
3890       __IOM uint32_t PAD15INPEN : 1;            /*!< [25..25] Pad 15 input enable                                              */
3891       __IOM uint32_t PAD15STRNG : 1;            /*!< [26..26] Pad 15 drive strength                                            */
3892       __IOM uint32_t PAD15FNCSEL : 3;           /*!< [29..27] Pad 15 function select                                           */
3893             uint32_t            : 2;
3894     } PADREGD_b;
3895   } ;
3896 
3897   union {
3898     __IOM uint32_t PADREGE;                     /*!< (@ 0x00000010) This register controls the pad configuration
3899                                                                     controls for PAD19 through PAD16. Writes
3900                                                                     to this register must be unlocked by the
3901                                                                     PADKEY register.                                           */
3902 
3903     struct {
3904       __IOM uint32_t PAD16PULL  : 1;            /*!< [0..0] Pad 16 pullup enable                                               */
3905       __IOM uint32_t PAD16INPEN : 1;            /*!< [1..1] Pad 16 input enable                                                */
3906       __IOM uint32_t PAD16STRNG : 1;            /*!< [2..2] Pad 16 drive strength                                              */
3907       __IOM uint32_t PAD16FNCSEL : 3;           /*!< [5..3] Pad 16 function select                                             */
3908             uint32_t            : 2;
3909       __IOM uint32_t PAD17PULL  : 1;            /*!< [8..8] Pad 17 pullup enable                                               */
3910       __IOM uint32_t PAD17INPEN : 1;            /*!< [9..9] Pad 17 input enable                                                */
3911       __IOM uint32_t PAD17STRNG : 1;            /*!< [10..10] Pad 17 drive strength                                            */
3912       __IOM uint32_t PAD17FNCSEL : 3;           /*!< [13..11] Pad 17 function select                                           */
3913             uint32_t            : 2;
3914       __IOM uint32_t PAD18PULL  : 1;            /*!< [16..16] Pad 18 pullup enable                                             */
3915       __IOM uint32_t PAD18INPEN : 1;            /*!< [17..17] Pad 18 input enable                                              */
3916       __IOM uint32_t PAD18STRNG : 1;            /*!< [18..18] Pad 18 drive strength                                            */
3917       __IOM uint32_t PAD18FNCSEL : 3;           /*!< [21..19] Pad 18 function select                                           */
3918             uint32_t            : 2;
3919       __IOM uint32_t PAD19PULL  : 1;            /*!< [24..24] Pad 19 pullup enable                                             */
3920       __IOM uint32_t PAD19INPEN : 1;            /*!< [25..25] Pad 19 input enable                                              */
3921       __IOM uint32_t PAD19STRNG : 1;            /*!< [26..26] Pad 19 drive strength                                            */
3922       __IOM uint32_t PAD19FNCSEL : 3;           /*!< [29..27] Pad 19 function select                                           */
3923             uint32_t            : 2;
3924     } PADREGE_b;
3925   } ;
3926 
3927   union {
3928     __IOM uint32_t PADREGF;                     /*!< (@ 0x00000014) This register controls the pad configuration
3929                                                                     controls for PAD23 through PAD20. Writes
3930                                                                     to this register must be unlocked by the
3931                                                                     PADKEY register.                                           */
3932 
3933     struct {
3934       __IOM uint32_t PAD20PULL  : 1;            /*!< [0..0] Pad 20 pulldown enable                                             */
3935       __IOM uint32_t PAD20INPEN : 1;            /*!< [1..1] Pad 20 input enable                                                */
3936       __IOM uint32_t PAD20STRNG : 1;            /*!< [2..2] Pad 20 drive strength                                              */
3937       __IOM uint32_t PAD20FNCSEL : 3;           /*!< [5..3] Pad 20 function select                                             */
3938             uint32_t            : 2;
3939       __IOM uint32_t PAD21PULL  : 1;            /*!< [8..8] Pad 21 pullup enable                                               */
3940       __IOM uint32_t PAD21INPEN : 1;            /*!< [9..9] Pad 21 input enable                                                */
3941       __IOM uint32_t PAD21STRNG : 1;            /*!< [10..10] Pad 21 drive strength                                            */
3942       __IOM uint32_t PAD21FNCSEL : 3;           /*!< [13..11] Pad 21 function select                                           */
3943             uint32_t            : 2;
3944       __IOM uint32_t PAD22PULL  : 1;            /*!< [16..16] Pad 22 pullup enable                                             */
3945       __IOM uint32_t PAD22INPEN : 1;            /*!< [17..17] Pad 22 input enable                                              */
3946       __IOM uint32_t PAD22STRNG : 1;            /*!< [18..18] Pad 22 drive strength                                            */
3947       __IOM uint32_t PAD22FNCSEL : 3;           /*!< [21..19] Pad 22 function select                                           */
3948             uint32_t            : 2;
3949       __IOM uint32_t PAD23PULL  : 1;            /*!< [24..24] Pad 23 pullup enable                                             */
3950       __IOM uint32_t PAD23INPEN : 1;            /*!< [25..25] Pad 23 input enable                                              */
3951       __IOM uint32_t PAD23STRNG : 1;            /*!< [26..26] Pad 23 drive strength                                            */
3952       __IOM uint32_t PAD23FNCSEL : 3;           /*!< [29..27] Pad 23 function select                                           */
3953             uint32_t            : 2;
3954     } PADREGF_b;
3955   } ;
3956 
3957   union {
3958     __IOM uint32_t PADREGG;                     /*!< (@ 0x00000018) This register controls the pad configuration
3959                                                                     controls for PAD27 through PAD24. Writes
3960                                                                     to this register must be unlocked by the
3961                                                                     PADKEY register.                                           */
3962 
3963     struct {
3964       __IOM uint32_t PAD24PULL  : 1;            /*!< [0..0] Pad 24 pullup enable                                               */
3965       __IOM uint32_t PAD24INPEN : 1;            /*!< [1..1] Pad 24 input enable                                                */
3966       __IOM uint32_t PAD24STRNG : 1;            /*!< [2..2] Pad 24 drive strength                                              */
3967       __IOM uint32_t PAD24FNCSEL : 3;           /*!< [5..3] Pad 24 function select                                             */
3968             uint32_t            : 2;
3969       __IOM uint32_t PAD25PULL  : 1;            /*!< [8..8] Pad 25 pullup enable                                               */
3970       __IOM uint32_t PAD25INPEN : 1;            /*!< [9..9] Pad 25 input enable                                                */
3971       __IOM uint32_t PAD25STRNG : 1;            /*!< [10..10] Pad 25 drive strength                                            */
3972       __IOM uint32_t PAD25FNCSEL : 3;           /*!< [13..11] Pad 25 function select                                           */
3973       __IOM uint32_t PAD25RSEL  : 2;            /*!< [15..14] Pad 25 pullup resistor selection.                                */
3974       __IOM uint32_t PAD26PULL  : 1;            /*!< [16..16] Pad 26 pullup enable                                             */
3975       __IOM uint32_t PAD26INPEN : 1;            /*!< [17..17] Pad 26 input enable                                              */
3976       __IOM uint32_t PAD26STRNG : 1;            /*!< [18..18] Pad 26 drive strength                                            */
3977       __IOM uint32_t PAD26FNCSEL : 3;           /*!< [21..19] Pad 26 function select                                           */
3978             uint32_t            : 2;
3979       __IOM uint32_t PAD27PULL  : 1;            /*!< [24..24] Pad 27 pullup enable                                             */
3980       __IOM uint32_t PAD27INPEN : 1;            /*!< [25..25] Pad 27 input enable                                              */
3981       __IOM uint32_t PAD27STRNG : 1;            /*!< [26..26] Pad 27 drive strength                                            */
3982       __IOM uint32_t PAD27FNCSEL : 3;           /*!< [29..27] Pad 27 function select                                           */
3983       __IOM uint32_t PAD27RSEL  : 2;            /*!< [31..30] Pad 27 pullup resistor selection.                                */
3984     } PADREGG_b;
3985   } ;
3986 
3987   union {
3988     __IOM uint32_t PADREGH;                     /*!< (@ 0x0000001C) This register controls the pad configuration
3989                                                                     controls for PAD31 through PAD28. Writes
3990                                                                     to this register must be unlocked by the
3991                                                                     PADKEY register.                                           */
3992 
3993     struct {
3994       __IOM uint32_t PAD28PULL  : 1;            /*!< [0..0] Pad 28 pullup enable                                               */
3995       __IOM uint32_t PAD28INPEN : 1;            /*!< [1..1] Pad 28 input enable                                                */
3996       __IOM uint32_t PAD28STRNG : 1;            /*!< [2..2] Pad 28 drive strength                                              */
3997       __IOM uint32_t PAD28FNCSEL : 3;           /*!< [5..3] Pad 28 function select                                             */
3998             uint32_t            : 2;
3999       __IOM uint32_t PAD29PULL  : 1;            /*!< [8..8] Pad 29 pullup enable                                               */
4000       __IOM uint32_t PAD29INPEN : 1;            /*!< [9..9] Pad 29 input enable                                                */
4001       __IOM uint32_t PAD29STRNG : 1;            /*!< [10..10] Pad 29 drive strength                                            */
4002       __IOM uint32_t PAD29FNCSEL : 3;           /*!< [13..11] Pad 29 function select                                           */
4003             uint32_t            : 2;
4004       __IOM uint32_t PAD30PULL  : 1;            /*!< [16..16] Pad 30 pullup enable                                             */
4005       __IOM uint32_t PAD30INPEN : 1;            /*!< [17..17] Pad 30 input enable                                              */
4006       __IOM uint32_t PAD30STRNG : 1;            /*!< [18..18] Pad 30 drive strength                                            */
4007       __IOM uint32_t PAD30FNCSEL : 3;           /*!< [21..19] Pad 30 function select                                           */
4008             uint32_t            : 2;
4009       __IOM uint32_t PAD31PULL  : 1;            /*!< [24..24] Pad 31 pullup enable                                             */
4010       __IOM uint32_t PAD31INPEN : 1;            /*!< [25..25] Pad 31 input enable                                              */
4011       __IOM uint32_t PAD31STRNG : 1;            /*!< [26..26] Pad 31 drive strength                                            */
4012       __IOM uint32_t PAD31FNCSEL : 3;           /*!< [29..27] Pad 31 function select                                           */
4013             uint32_t            : 2;
4014     } PADREGH_b;
4015   } ;
4016 
4017   union {
4018     __IOM uint32_t PADREGI;                     /*!< (@ 0x00000020) This register controls the pad configuration
4019                                                                     controls for PAD35 through PAD32. Writes
4020                                                                     to this register must be unlocked by the
4021                                                                     PADKEY register.                                           */
4022 
4023     struct {
4024       __IOM uint32_t PAD32PULL  : 1;            /*!< [0..0] Pad 32 pullup enable                                               */
4025       __IOM uint32_t PAD32INPEN : 1;            /*!< [1..1] Pad 32 input enable                                                */
4026       __IOM uint32_t PAD32STRNG : 1;            /*!< [2..2] Pad 32 drive strength                                              */
4027       __IOM uint32_t PAD32FNCSEL : 3;           /*!< [5..3] Pad 32 function select                                             */
4028             uint32_t            : 2;
4029       __IOM uint32_t PAD33PULL  : 1;            /*!< [8..8] Pad 33 pullup enable                                               */
4030       __IOM uint32_t PAD33INPEN : 1;            /*!< [9..9] Pad 33 input enable                                                */
4031       __IOM uint32_t PAD33STRNG : 1;            /*!< [10..10] Pad 33 drive strength                                            */
4032       __IOM uint32_t PAD33FNCSEL : 3;           /*!< [13..11] Pad 33 function select                                           */
4033             uint32_t            : 2;
4034       __IOM uint32_t PAD34PULL  : 1;            /*!< [16..16] Pad 34 pullup enable                                             */
4035       __IOM uint32_t PAD34INPEN : 1;            /*!< [17..17] Pad 34 input enable                                              */
4036       __IOM uint32_t PAD34STRNG : 1;            /*!< [18..18] Pad 34 drive strength                                            */
4037       __IOM uint32_t PAD34FNCSEL : 3;           /*!< [21..19] Pad 34 function select                                           */
4038             uint32_t            : 2;
4039       __IOM uint32_t PAD35PULL  : 1;            /*!< [24..24] Pad 35 pullup enable                                             */
4040       __IOM uint32_t PAD35INPEN : 1;            /*!< [25..25] Pad 35 input enable                                              */
4041       __IOM uint32_t PAD35STRNG : 1;            /*!< [26..26] Pad 35 drive strength                                            */
4042       __IOM uint32_t PAD35FNCSEL : 3;           /*!< [29..27] Pad 35 function select                                           */
4043             uint32_t            : 2;
4044     } PADREGI_b;
4045   } ;
4046 
4047   union {
4048     __IOM uint32_t PADREGJ;                     /*!< (@ 0x00000024) This register controls the pad configuration
4049                                                                     controls for PAD39 through PAD36. Writes
4050                                                                     to this register must be unlocked by the
4051                                                                     PADKEY register.                                           */
4052 
4053     struct {
4054       __IOM uint32_t PAD36PULL  : 1;            /*!< [0..0] Pad 36 pullup enable                                               */
4055       __IOM uint32_t PAD36INPEN : 1;            /*!< [1..1] Pad 36 input enable                                                */
4056       __IOM uint32_t PAD36STRNG : 1;            /*!< [2..2] Pad 36 drive strength                                              */
4057       __IOM uint32_t PAD36FNCSEL : 3;           /*!< [5..3] Pad 36 function select                                             */
4058       __IOM uint32_t PAD36PWRUP : 1;            /*!< [6..6] Pad 36 VDD power switch enable                                     */
4059             uint32_t            : 1;
4060       __IOM uint32_t PAD37PULL  : 1;            /*!< [8..8] Pad 37 pullup enable                                               */
4061       __IOM uint32_t PAD37INPEN : 1;            /*!< [9..9] Pad 37 input enable                                                */
4062       __IOM uint32_t PAD37STRNG : 1;            /*!< [10..10] Pad 37 drive strength                                            */
4063       __IOM uint32_t PAD37FNCSEL : 3;           /*!< [13..11] Pad 37 function select                                           */
4064             uint32_t            : 1;
4065       __IOM uint32_t PAD37PWRDN : 1;            /*!< [15..15] Pad 37 VSS power switch enable                                   */
4066       __IOM uint32_t PAD38PULL  : 1;            /*!< [16..16] Pad 38 pullup enable                                             */
4067       __IOM uint32_t PAD38INPEN : 1;            /*!< [17..17] Pad 38 input enable                                              */
4068       __IOM uint32_t PAD38STRNG : 1;            /*!< [18..18] Pad 38 drive strength                                            */
4069       __IOM uint32_t PAD38FNCSEL : 3;           /*!< [21..19] Pad 38 function select                                           */
4070             uint32_t            : 2;
4071       __IOM uint32_t PAD39PULL  : 1;            /*!< [24..24] Pad 39 pullup enable                                             */
4072       __IOM uint32_t PAD39INPEN : 1;            /*!< [25..25] Pad 39 input enable                                              */
4073       __IOM uint32_t PAD39STRNG : 1;            /*!< [26..26] Pad 39 drive strength                                            */
4074       __IOM uint32_t PAD39FNCSEL : 3;           /*!< [29..27] Pad 39 function select                                           */
4075       __IOM uint32_t PAD39RSEL  : 2;            /*!< [31..30] Pad 39 pullup resistor selection.                                */
4076     } PADREGJ_b;
4077   } ;
4078 
4079   union {
4080     __IOM uint32_t PADREGK;                     /*!< (@ 0x00000028) This register controls the pad configuration
4081                                                                     controls for PAD43 through PAD40. Writes
4082                                                                     to this register must be unlocked by the
4083                                                                     PADKEY register.                                           */
4084 
4085     struct {
4086       __IOM uint32_t PAD40PULL  : 1;            /*!< [0..0] Pad 40 pullup enable                                               */
4087       __IOM uint32_t PAD40INPEN : 1;            /*!< [1..1] Pad 40 input enable                                                */
4088       __IOM uint32_t PAD40STRNG : 1;            /*!< [2..2] Pad 40 drive strength                                              */
4089       __IOM uint32_t PAD40FNCSEL : 3;           /*!< [5..3] Pad 40 function select                                             */
4090       __IOM uint32_t PAD40RSEL  : 2;            /*!< [7..6] Pad 40 pullup resistor selection.                                  */
4091       __IOM uint32_t PAD41PULL  : 1;            /*!< [8..8] Pad 41 pullup enable                                               */
4092       __IOM uint32_t PAD41INPEN : 1;            /*!< [9..9] Pad 41 input enable                                                */
4093       __IOM uint32_t PAD41STRNG : 1;            /*!< [10..10] Pad 41 drive strength                                            */
4094       __IOM uint32_t PAD41FNCSEL : 3;           /*!< [13..11] Pad 41 function select                                           */
4095             uint32_t            : 1;
4096       __IOM uint32_t PAD41PWRDN : 1;            /*!< [15..15] Pad 41 power switch enable                                       */
4097       __IOM uint32_t PAD42PULL  : 1;            /*!< [16..16] Pad 42 pullup enable                                             */
4098       __IOM uint32_t PAD42INPEN : 1;            /*!< [17..17] Pad 42 input enable                                              */
4099       __IOM uint32_t PAD42STRNG : 1;            /*!< [18..18] Pad 42 drive strength                                            */
4100       __IOM uint32_t PAD42FNCSEL : 3;           /*!< [21..19] Pad 42 function select                                           */
4101       __IOM uint32_t PAD42RSEL  : 2;            /*!< [23..22] Pad 42 pullup resistor selection.                                */
4102       __IOM uint32_t PAD43PULL  : 1;            /*!< [24..24] Pad 43 pullup enable                                             */
4103       __IOM uint32_t PAD43INPEN : 1;            /*!< [25..25] Pad 43 input enable                                              */
4104       __IOM uint32_t PAD43STRNG : 1;            /*!< [26..26] Pad 43 drive strength                                            */
4105       __IOM uint32_t PAD43FNCSEL : 3;           /*!< [29..27] Pad 43 function select                                           */
4106       __IOM uint32_t PAD43RSEL  : 2;            /*!< [31..30] Pad 43 pullup resistor selection.                                */
4107     } PADREGK_b;
4108   } ;
4109 
4110   union {
4111     __IOM uint32_t PADREGL;                     /*!< (@ 0x0000002C) This register controls the pad configuration
4112                                                                     controls for PAD47 through PAD44. Writes
4113                                                                     to this register must be unlocked by the
4114                                                                     PADKEY register.                                           */
4115 
4116     struct {
4117       __IOM uint32_t PAD44PULL  : 1;            /*!< [0..0] Pad 44 pullup enable                                               */
4118       __IOM uint32_t PAD44INPEN : 1;            /*!< [1..1] Pad 44 input enable                                                */
4119       __IOM uint32_t PAD44STRNG : 1;            /*!< [2..2] Pad 44 drive strength                                              */
4120       __IOM uint32_t PAD44FNCSEL : 3;           /*!< [5..3] Pad 44 function select                                             */
4121             uint32_t            : 2;
4122       __IOM uint32_t PAD45PULL  : 1;            /*!< [8..8] Pad 45 pullup enable                                               */
4123       __IOM uint32_t PAD45INPEN : 1;            /*!< [9..9] Pad 45 input enable                                                */
4124       __IOM uint32_t PAD45STRNG : 1;            /*!< [10..10] Pad 45 drive strength                                            */
4125       __IOM uint32_t PAD45FNCSEL : 3;           /*!< [13..11] Pad 45 function select                                           */
4126             uint32_t            : 2;
4127       __IOM uint32_t PAD46PULL  : 1;            /*!< [16..16] Pad 46 pullup enable                                             */
4128       __IOM uint32_t PAD46INPEN : 1;            /*!< [17..17] Pad 46 input enable                                              */
4129       __IOM uint32_t PAD46STRNG : 1;            /*!< [18..18] Pad 46 drive strength                                            */
4130       __IOM uint32_t PAD46FNCSEL : 3;           /*!< [21..19] Pad 46 function select                                           */
4131             uint32_t            : 2;
4132       __IOM uint32_t PAD47PULL  : 1;            /*!< [24..24] Pad 47 pullup enable                                             */
4133       __IOM uint32_t PAD47INPEN : 1;            /*!< [25..25] Pad 47 input enable                                              */
4134       __IOM uint32_t PAD47STRNG : 1;            /*!< [26..26] Pad 47 drive strength                                            */
4135       __IOM uint32_t PAD47FNCSEL : 3;           /*!< [29..27] Pad 47 function select                                           */
4136             uint32_t            : 2;
4137     } PADREGL_b;
4138   } ;
4139 
4140   union {
4141     __IOM uint32_t PADREGM;                     /*!< (@ 0x00000030) This register controls the pad configuration
4142                                                                     controls for PAD49 through PAD48. Writes
4143                                                                     to this register must be unlocked by the
4144                                                                     PADKEY register.                                           */
4145 
4146     struct {
4147       __IOM uint32_t PAD48PULL  : 1;            /*!< [0..0] Pad 48 pullup enable                                               */
4148       __IOM uint32_t PAD48INPEN : 1;            /*!< [1..1] Pad 48 input enable                                                */
4149       __IOM uint32_t PAD48STRNG : 1;            /*!< [2..2] Pad 48 drive strength                                              */
4150       __IOM uint32_t PAD48FNCSEL : 3;           /*!< [5..3] Pad 48 function select                                             */
4151       __IOM uint32_t PAD48RSEL  : 2;            /*!< [7..6] Pad 48 pullup resistor selection.                                  */
4152       __IOM uint32_t PAD49PULL  : 1;            /*!< [8..8] Pad 49 pullup enable                                               */
4153       __IOM uint32_t PAD49INPEN : 1;            /*!< [9..9] Pad 49 input enable                                                */
4154       __IOM uint32_t PAD49STRNG : 1;            /*!< [10..10] Pad 49 drive strength                                            */
4155       __IOM uint32_t PAD49FNCSEL : 3;           /*!< [13..11] Pad 49 function select                                           */
4156       __IOM uint32_t PAD49RSEL  : 2;            /*!< [15..14] Pad 49 pullup resistor selection.                                */
4157             uint32_t            : 16;
4158     } PADREGM_b;
4159   } ;
4160   __IM  uint32_t  RESERVED[3];
4161 
4162   union {
4163     __IOM uint32_t CFGA;                        /*!< (@ 0x00000040) GPIO configuration controls for GPIO[7:0]. Writes
4164                                                                     to this register must be unlocked by the
4165                                                                     PADKEY register.                                           */
4166 
4167     struct {
4168       __IOM uint32_t GPIO0INCFG : 1;            /*!< [0..0] GPIO0 input enable.                                                */
4169       __IOM uint32_t GPIO0OUTCFG : 2;           /*!< [2..1] GPIO0 output configuration.                                        */
4170       __IOM uint32_t GPIO0INTD  : 1;            /*!< [3..3] GPIO0 interrupt direction.                                         */
4171       __IOM uint32_t GPIO1INCFG : 1;            /*!< [4..4] GPIO1 input enable.                                                */
4172       __IOM uint32_t GPIO1OUTCFG : 2;           /*!< [6..5] GPIO1 output configuration.                                        */
4173       __IOM uint32_t GPIO1INTD  : 1;            /*!< [7..7] GPIO1 interrupt direction.                                         */
4174       __IOM uint32_t GPIO2INCFG : 1;            /*!< [8..8] GPIO2 input enable.                                                */
4175       __IOM uint32_t GPIO2OUTCFG : 2;           /*!< [10..9] GPIO2 output configuration.                                       */
4176       __IOM uint32_t GPIO2INTD  : 1;            /*!< [11..11] GPIO2 interrupt direction.                                       */
4177       __IOM uint32_t GPIO3INCFG : 1;            /*!< [12..12] GPIO3 input enable.                                              */
4178       __IOM uint32_t GPIO3OUTCFG : 2;           /*!< [14..13] GPIO3 output configuration.                                      */
4179       __IOM uint32_t GPIO3INTD  : 1;            /*!< [15..15] GPIO3 interrupt direction.                                       */
4180       __IOM uint32_t GPIO4INCFG : 1;            /*!< [16..16] GPIO4 input enable.                                              */
4181       __IOM uint32_t GPIO4OUTCFG : 2;           /*!< [18..17] GPIO4 output configuration.                                      */
4182       __IOM uint32_t GPIO4INTD  : 1;            /*!< [19..19] GPIO4 interrupt direction.                                       */
4183       __IOM uint32_t GPIO5INCFG : 1;            /*!< [20..20] GPIO5 input enable.                                              */
4184       __IOM uint32_t GPIO5OUTCFG : 2;           /*!< [22..21] GPIO5 output configuration.                                      */
4185       __IOM uint32_t GPIO5INTD  : 1;            /*!< [23..23] GPIO5 interrupt direction.                                       */
4186       __IOM uint32_t GPIO6INCFG : 1;            /*!< [24..24] GPIO6 input enable.                                              */
4187       __IOM uint32_t GPIO6OUTCFG : 2;           /*!< [26..25] GPIO6 output configuration.                                      */
4188       __IOM uint32_t GPIO6INTD  : 1;            /*!< [27..27] GPIO6 interrupt direction.                                       */
4189       __IOM uint32_t GPIO7INCFG : 1;            /*!< [28..28] GPIO7 input enable.                                              */
4190       __IOM uint32_t GPIO7OUTCFG : 2;           /*!< [30..29] GPIO7 output configuration.                                      */
4191       __IOM uint32_t GPIO7INTD  : 1;            /*!< [31..31] GPIO7 interrupt direction, nCE polarity.                         */
4192     } CFGA_b;
4193   } ;
4194 
4195   union {
4196     __IOM uint32_t CFGB;                        /*!< (@ 0x00000044) GPIO configuration controls for GPIO[15:8]. Writes
4197                                                                     to this register must be unlocked by the
4198                                                                     PADKEY register.                                           */
4199 
4200     struct {
4201       __IOM uint32_t GPIO8INCFG : 1;            /*!< [0..0] GPIO8 input enable.                                                */
4202       __IOM uint32_t GPIO8OUTCFG : 2;           /*!< [2..1] GPIO8 output configuration.                                        */
4203       __IOM uint32_t GPIO8INTD  : 1;            /*!< [3..3] GPIO8 interrupt direction.                                         */
4204       __IOM uint32_t GPIO9INCFG : 1;            /*!< [4..4] GPIO9 input enable.                                                */
4205       __IOM uint32_t GPIO9OUTCFG : 2;           /*!< [6..5] GPIO9 output configuration.                                        */
4206       __IOM uint32_t GPIO9INTD  : 1;            /*!< [7..7] GPIO9 interrupt direction.                                         */
4207       __IOM uint32_t GPIO10INCFG : 1;           /*!< [8..8] GPIO10 input enable.                                               */
4208       __IOM uint32_t GPIO10OUTCFG : 2;          /*!< [10..9] GPIO10 output configuration.                                      */
4209       __IOM uint32_t GPIO10INTD : 1;            /*!< [11..11] GPIO10 interrupt direction.                                      */
4210       __IOM uint32_t GPIO11INCFG : 1;           /*!< [12..12] GPIO11 input enable.                                             */
4211       __IOM uint32_t GPIO11OUTCFG : 2;          /*!< [14..13] GPIO11 output configuration.                                     */
4212       __IOM uint32_t GPIO11INTD : 1;            /*!< [15..15] GPIO11 interrupt direction.                                      */
4213       __IOM uint32_t GPIO12INCFG : 1;           /*!< [16..16] GPIO12 input enable.                                             */
4214       __IOM uint32_t GPIO12OUTCFG : 2;          /*!< [18..17] GPIO12 output configuration.                                     */
4215       __IOM uint32_t GPIO12INTD : 1;            /*!< [19..19] GPIO12 interrupt direction.                                      */
4216       __IOM uint32_t GPIO13INCFG : 1;           /*!< [20..20] GPIO13 input enable.                                             */
4217       __IOM uint32_t GPIO13OUTCFG : 2;          /*!< [22..21] GPIO13 output configuration.                                     */
4218       __IOM uint32_t GPIO13INTD : 1;            /*!< [23..23] GPIO13 interrupt direction.                                      */
4219       __IOM uint32_t GPIO14INCFG : 1;           /*!< [24..24] GPIO14 input enable.                                             */
4220       __IOM uint32_t GPIO14OUTCFG : 2;          /*!< [26..25] GPIO14 output configuration.                                     */
4221       __IOM uint32_t GPIO14INTD : 1;            /*!< [27..27] GPIO14 interrupt direction.                                      */
4222       __IOM uint32_t GPIO15INCFG : 1;           /*!< [28..28] GPIO15 input enable.                                             */
4223       __IOM uint32_t GPIO15OUTCFG : 2;          /*!< [30..29] GPIO15 output configuration.                                     */
4224       __IOM uint32_t GPIO15INTD : 1;            /*!< [31..31] GPIO15 interrupt direction.                                      */
4225     } CFGB_b;
4226   } ;
4227 
4228   union {
4229     __IOM uint32_t CFGC;                        /*!< (@ 0x00000048) GPIO configuration controls for GPIO[23:16].
4230                                                                     Writes to this register must be unlocked
4231                                                                     by the PADKEY register.                                    */
4232 
4233     struct {
4234       __IOM uint32_t GPIO16INCFG : 1;           /*!< [0..0] GPIO16 input enable.                                               */
4235       __IOM uint32_t GPIO16OUTCFG : 2;          /*!< [2..1] GPIO16 output configuration.                                       */
4236       __IOM uint32_t GPIO16INTD : 1;            /*!< [3..3] GPIO16 interrupt direction.                                        */
4237       __IOM uint32_t GPIO17INCFG : 1;           /*!< [4..4] GPIO17 input enable.                                               */
4238       __IOM uint32_t GPIO17OUTCFG : 2;          /*!< [6..5] GPIO17 output configuration.                                       */
4239       __IOM uint32_t GPIO17INTD : 1;            /*!< [7..7] GPIO17 interrupt direction.                                        */
4240       __IOM uint32_t GPIO18INCFG : 1;           /*!< [8..8] GPIO18 input enable.                                               */
4241       __IOM uint32_t GPIO18OUTCFG : 2;          /*!< [10..9] GPIO18 output configuration.                                      */
4242       __IOM uint32_t GPIO18INTD : 1;            /*!< [11..11] GPIO18 interrupt direction.                                      */
4243       __IOM uint32_t GPIO19INCFG : 1;           /*!< [12..12] GPIO19 input enable.                                             */
4244       __IOM uint32_t GPIO19OUTCFG : 2;          /*!< [14..13] GPIO19 output configuration.                                     */
4245       __IOM uint32_t GPIO19INTD : 1;            /*!< [15..15] GPIO19 interrupt direction.                                      */
4246       __IOM uint32_t GPIO20INCFG : 1;           /*!< [16..16] GPIO20 input enable.                                             */
4247       __IOM uint32_t GPIO20OUTCFG : 2;          /*!< [18..17] GPIO20 output configuration.                                     */
4248       __IOM uint32_t GPIO20INTD : 1;            /*!< [19..19] GPIO20 interrupt direction.                                      */
4249       __IOM uint32_t GPIO21INCFG : 1;           /*!< [20..20] GPIO21 input enable.                                             */
4250       __IOM uint32_t GPIO21OUTCFG : 2;          /*!< [22..21] GPIO21 output configuration.                                     */
4251       __IOM uint32_t GPIO21INTD : 1;            /*!< [23..23] GPIO21 interrupt direction.                                      */
4252       __IOM uint32_t GPIO22INCFG : 1;           /*!< [24..24] GPIO22 input enable.                                             */
4253       __IOM uint32_t GPIO22OUTCFG : 2;          /*!< [26..25] GPIO22 output configuration.                                     */
4254       __IOM uint32_t GPIO22INTD : 1;            /*!< [27..27] GPIO22 interrupt direction.                                      */
4255       __IOM uint32_t GPIO23INCFG : 1;           /*!< [28..28] GPIO23 input enable.                                             */
4256       __IOM uint32_t GPIO23OUTCFG : 2;          /*!< [30..29] GPIO23 output configuration.                                     */
4257       __IOM uint32_t GPIO23INTD : 1;            /*!< [31..31] GPIO23 interrupt direction.                                      */
4258     } CFGC_b;
4259   } ;
4260 
4261   union {
4262     __IOM uint32_t CFGD;                        /*!< (@ 0x0000004C) GPIO configuration controls for GPIO[31:24].
4263                                                                     Writes to this register must be unlocked
4264                                                                     by the PADKEY register.                                    */
4265 
4266     struct {
4267       __IOM uint32_t GPIO24INCFG : 1;           /*!< [0..0] GPIO24 input enable.                                               */
4268       __IOM uint32_t GPIO24OUTCFG : 2;          /*!< [2..1] GPIO24 output configuration.                                       */
4269       __IOM uint32_t GPIO24INTD : 1;            /*!< [3..3] GPIO24 interrupt direction.                                        */
4270       __IOM uint32_t GPIO25INCFG : 1;           /*!< [4..4] GPIO25 input enable.                                               */
4271       __IOM uint32_t GPIO25OUTCFG : 2;          /*!< [6..5] GPIO25 output configuration.                                       */
4272       __IOM uint32_t GPIO25INTD : 1;            /*!< [7..7] GPIO25 interrupt direction.                                        */
4273       __IOM uint32_t GPIO26INCFG : 1;           /*!< [8..8] GPIO26 input enable.                                               */
4274       __IOM uint32_t GPIO26OUTCFG : 2;          /*!< [10..9] GPIO26 output configuration.                                      */
4275       __IOM uint32_t GPIO26INTD : 1;            /*!< [11..11] GPIO26 interrupt direction.                                      */
4276       __IOM uint32_t GPIO27INCFG : 1;           /*!< [12..12] GPIO27 input enable.                                             */
4277       __IOM uint32_t GPIO27OUTCFG : 2;          /*!< [14..13] GPIO27 output configuration.                                     */
4278       __IOM uint32_t GPIO27INTD : 1;            /*!< [15..15] GPIO27 interrupt direction.                                      */
4279       __IOM uint32_t GPIO28INCFG : 1;           /*!< [16..16] GPIO28 input enable.                                             */
4280       __IOM uint32_t GPIO28OUTCFG : 2;          /*!< [18..17] GPIO28 output configuration.                                     */
4281       __IOM uint32_t GPIO28INTD : 1;            /*!< [19..19] GPIO28 interrupt direction.                                      */
4282       __IOM uint32_t GPIO29INCFG : 1;           /*!< [20..20] GPIO29 input enable.                                             */
4283       __IOM uint32_t GPIO29OUTCFG : 2;          /*!< [22..21] GPIO29 output configuration.                                     */
4284       __IOM uint32_t GPIO29INTD : 1;            /*!< [23..23] GPIO29 interrupt direction.                                      */
4285       __IOM uint32_t GPIO30INCFG : 1;           /*!< [24..24] GPIO30 input enable.                                             */
4286       __IOM uint32_t GPIO30OUTCFG : 2;          /*!< [26..25] GPIO30 output configuration.                                     */
4287       __IOM uint32_t GPIO30INTD : 1;            /*!< [27..27] GPIO30 interrupt direction.                                      */
4288       __IOM uint32_t GPIO31INCFG : 1;           /*!< [28..28] GPIO31 input enable.                                             */
4289       __IOM uint32_t GPIO31OUTCFG : 2;          /*!< [30..29] GPIO31 output configuration.                                     */
4290       __IOM uint32_t GPIO31INTD : 1;            /*!< [31..31] GPIO31 interrupt direction.                                      */
4291     } CFGD_b;
4292   } ;
4293 
4294   union {
4295     __IOM uint32_t CFGE;                        /*!< (@ 0x00000050) GPIO configuration controls for GPIO[39:32].
4296                                                                     Writes to this register must be unlocked
4297                                                                     by the PADKEY register.                                    */
4298 
4299     struct {
4300       __IOM uint32_t GPIO32INCFG : 1;           /*!< [0..0] GPIO32 input enable.                                               */
4301       __IOM uint32_t GPIO32OUTCFG : 2;          /*!< [2..1] GPIO32 output configuration.                                       */
4302       __IOM uint32_t GPIO32INTD : 1;            /*!< [3..3] GPIO32 interrupt direction.                                        */
4303       __IOM uint32_t GPIO33INCFG : 1;           /*!< [4..4] GPIO33 input enable.                                               */
4304       __IOM uint32_t GPIO33OUTCFG : 2;          /*!< [6..5] GPIO33 output configuration.                                       */
4305       __IOM uint32_t GPIO33INTD : 1;            /*!< [7..7] GPIO33 interrupt direction.                                        */
4306       __IOM uint32_t GPIO34INCFG : 1;           /*!< [8..8] GPIO34 input enable.                                               */
4307       __IOM uint32_t GPIO34OUTCFG : 2;          /*!< [10..9] GPIO34 output configuration.                                      */
4308       __IOM uint32_t GPIO34INTD : 1;            /*!< [11..11] GPIO34 interrupt direction.                                      */
4309       __IOM uint32_t GPIO35INCFG : 1;           /*!< [12..12] GPIO35 input enable.                                             */
4310       __IOM uint32_t GPIO35OUTCFG : 2;          /*!< [14..13] GPIO35 output configuration.                                     */
4311       __IOM uint32_t GPIO35INTD : 1;            /*!< [15..15] GPIO35 interrupt direction.                                      */
4312       __IOM uint32_t GPIO36INCFG : 1;           /*!< [16..16] GPIO36 input enable.                                             */
4313       __IOM uint32_t GPIO36OUTCFG : 2;          /*!< [18..17] GPIO36 output configuration.                                     */
4314       __IOM uint32_t GPIO36INTD : 1;            /*!< [19..19] GPIO36 interrupt direction.                                      */
4315       __IOM uint32_t GPIO37INCFG : 1;           /*!< [20..20] GPIO37 input enable.                                             */
4316       __IOM uint32_t GPIO37OUTCFG : 2;          /*!< [22..21] GPIO37 output configuration.                                     */
4317       __IOM uint32_t GPIO37INTD : 1;            /*!< [23..23] GPIO37 interrupt direction.                                      */
4318       __IOM uint32_t GPIO38INCFG : 1;           /*!< [24..24] GPIO38 input enable.                                             */
4319       __IOM uint32_t GPIO38OUTCFG : 2;          /*!< [26..25] GPIO38 output configuration.                                     */
4320       __IOM uint32_t GPIO38INTD : 1;            /*!< [27..27] GPIO38 interrupt direction.                                      */
4321       __IOM uint32_t GPIO39INCFG : 1;           /*!< [28..28] GPIO39 input enable.                                             */
4322       __IOM uint32_t GPIO39OUTCFG : 2;          /*!< [30..29] GPIO39 output configuration.                                     */
4323       __IOM uint32_t GPIO39INTD : 1;            /*!< [31..31] GPIO39 interrupt direction.                                      */
4324     } CFGE_b;
4325   } ;
4326 
4327   union {
4328     __IOM uint32_t CFGF;                        /*!< (@ 0x00000054) GPIO configuration controls for GPIO[47:40].
4329                                                                     Writes to this register must be unlocked
4330                                                                     by the PADKEY register.                                    */
4331 
4332     struct {
4333       __IOM uint32_t GPIO40INCFG : 1;           /*!< [0..0] GPIO40 input enable.                                               */
4334       __IOM uint32_t GPIO40OUTCFG : 2;          /*!< [2..1] GPIO40 output configuration.                                       */
4335       __IOM uint32_t GPIO40INTD : 1;            /*!< [3..3] GPIO40 interrupt direction.                                        */
4336       __IOM uint32_t GPIO41INCFG : 1;           /*!< [4..4] GPIO41 input enable.                                               */
4337       __IOM uint32_t GPIO41OUTCFG : 2;          /*!< [6..5] GPIO41 output configuration.                                       */
4338       __IOM uint32_t GPIO41INTD : 1;            /*!< [7..7] GPIO41 interrupt direction.                                        */
4339       __IOM uint32_t GPIO42INCFG : 1;           /*!< [8..8] GPIO42 input enable.                                               */
4340       __IOM uint32_t GPIO42OUTCFG : 2;          /*!< [10..9] GPIO42 output configuration.                                      */
4341       __IOM uint32_t GPIO42INTD : 1;            /*!< [11..11] GPIO42 interrupt direction.                                      */
4342       __IOM uint32_t GPIO43INCFG : 1;           /*!< [12..12] GPIO43 input enable.                                             */
4343       __IOM uint32_t GPIO43OUTCFG : 2;          /*!< [14..13] GPIO43 output configuration.                                     */
4344       __IOM uint32_t GPIO43INTD : 1;            /*!< [15..15] GPIO43 interrupt direction.                                      */
4345       __IOM uint32_t GPIO44INCFG : 1;           /*!< [16..16] GPIO44 input enable.                                             */
4346       __IOM uint32_t GPIO44OUTCFG : 2;          /*!< [18..17] GPIO44 output configuration.                                     */
4347       __IOM uint32_t GPIO44INTD : 1;            /*!< [19..19] GPIO44 interrupt direction.                                      */
4348       __IOM uint32_t GPIO45INCFG : 1;           /*!< [20..20] GPIO45 input enable.                                             */
4349       __IOM uint32_t GPIO45OUTCFG : 2;          /*!< [22..21] GPIO45 output configuration.                                     */
4350       __IOM uint32_t GPIO45INTD : 1;            /*!< [23..23] GPIO45 interrupt direction.                                      */
4351       __IOM uint32_t GPIO46INCFG : 1;           /*!< [24..24] GPIO46 input enable.                                             */
4352       __IOM uint32_t GPIO46OUTCFG : 2;          /*!< [26..25] GPIO46 output configuration.                                     */
4353       __IOM uint32_t GPIO46INTD : 1;            /*!< [27..27] GPIO46 interrupt direction.                                      */
4354       __IOM uint32_t GPIO47INCFG : 1;           /*!< [28..28] GPIO47 input enable.                                             */
4355       __IOM uint32_t GPIO47OUTCFG : 2;          /*!< [30..29] GPIO47 output configuration.                                     */
4356       __IOM uint32_t GPIO47INTD : 1;            /*!< [31..31] GPIO47 interrupt direction.                                      */
4357     } CFGF_b;
4358   } ;
4359 
4360   union {
4361     __IOM uint32_t CFGG;                        /*!< (@ 0x00000058) GPIO configuration controls for GPIO[49:48].
4362                                                                     Writes to this register must be unlocked
4363                                                                     by the PADKEY register.                                    */
4364 
4365     struct {
4366       __IOM uint32_t GPIO48INCFG : 1;           /*!< [0..0] GPIO48 input enable.                                               */
4367       __IOM uint32_t GPIO48OUTCFG : 2;          /*!< [2..1] GPIO48 output configuration.                                       */
4368       __IOM uint32_t GPIO48INTD : 1;            /*!< [3..3] GPIO48 interrupt direction.                                        */
4369       __IOM uint32_t GPIO49INCFG : 1;           /*!< [4..4] GPIO49 input enable.                                               */
4370       __IOM uint32_t GPIO49OUTCFG : 2;          /*!< [6..5] GPIO49 output configuration.                                       */
4371       __IOM uint32_t GPIO49INTD : 1;            /*!< [7..7] GPIO49 interrupt direction.                                        */
4372             uint32_t            : 24;
4373     } CFGG_b;
4374   } ;
4375   __IM  uint32_t  RESERVED1;
4376 
4377   union {
4378     __IOM uint32_t PADKEY;                      /*!< (@ 0x00000060) Lock state of the PINCFG and GPIO configuration
4379                                                                     registers. Write a value of 0x73 to unlock
4380                                                                     write access to the PAD and GPIO configuration
4381                                                                     registers. Write any other value to lock
4382                                                                     access to PAD and GPIO registers. This register
4383                                                                     also indicates lock status when read. When
4384                                                                     in the unlccked state (i.e. 0x73 has been
4385                                                                     written), it reads as 1. When in the locked
4386                                                                     state, it reads as 0.                                      */
4387 
4388     struct {
4389       __IOM uint32_t PADKEY     : 32;           /*!< [31..0] Key register value.                                               */
4390     } PADKEY_b;
4391   } ;
4392   __IM  uint32_t  RESERVED2[7];
4393 
4394   union {
4395     __IOM uint32_t RDA;                         /*!< (@ 0x00000080) GPIO Input Register A (31-0)                               */
4396 
4397     struct {
4398       __IOM uint32_t RDA        : 32;           /*!< [31..0] GPIO31-0 read data.                                               */
4399     } RDA_b;
4400   } ;
4401 
4402   union {
4403     __IOM uint32_t RDB;                         /*!< (@ 0x00000084) GPIO Input Register B (49-32)                              */
4404 
4405     struct {
4406       __IOM uint32_t RDB        : 18;           /*!< [17..0] GPIO49-32 read data.                                              */
4407             uint32_t            : 14;
4408     } RDB_b;
4409   } ;
4410 
4411   union {
4412     __IOM uint32_t WTA;                         /*!< (@ 0x00000088) GPIO Output Register A (31-0)                              */
4413 
4414     struct {
4415       __IOM uint32_t WTA        : 32;           /*!< [31..0] GPIO31-0 write data.                                              */
4416     } WTA_b;
4417   } ;
4418 
4419   union {
4420     __IOM uint32_t WTB;                         /*!< (@ 0x0000008C) GPIO Output Register B (49-32)                             */
4421 
4422     struct {
4423       __IOM uint32_t WTB        : 18;           /*!< [17..0] GPIO49-32 write data.                                             */
4424             uint32_t            : 14;
4425     } WTB_b;
4426   } ;
4427 
4428   union {
4429     __IOM uint32_t WTSA;                        /*!< (@ 0x00000090) GPIO Output Register A Set (31-0)                          */
4430 
4431     struct {
4432       __IOM uint32_t WTSA       : 32;           /*!< [31..0] Set the GPIO31-0 write data.                                      */
4433     } WTSA_b;
4434   } ;
4435 
4436   union {
4437     __IOM uint32_t WTSB;                        /*!< (@ 0x00000094) GPIO Output Register B Set (49-32)                         */
4438 
4439     struct {
4440       __IOM uint32_t WTSB       : 18;           /*!< [17..0] Set the GPIO49-32 write data.                                     */
4441             uint32_t            : 14;
4442     } WTSB_b;
4443   } ;
4444 
4445   union {
4446     __IOM uint32_t WTCA;                        /*!< (@ 0x00000098) GPIO Output Register A Clear (31-0)                        */
4447 
4448     struct {
4449       __IOM uint32_t WTCA       : 32;           /*!< [31..0] Clear the GPIO31-0 write data.                                    */
4450     } WTCA_b;
4451   } ;
4452 
4453   union {
4454     __IOM uint32_t WTCB;                        /*!< (@ 0x0000009C) GPIO Output Register B Clear (49-32)                       */
4455 
4456     struct {
4457       __IOM uint32_t WTCB       : 18;           /*!< [17..0] Clear the GPIO49-32 write data.                                   */
4458             uint32_t            : 14;
4459     } WTCB_b;
4460   } ;
4461 
4462   union {
4463     __IOM uint32_t ENA;                         /*!< (@ 0x000000A0) GPIO Enable Register A (31-0)                              */
4464 
4465     struct {
4466       __IOM uint32_t ENA        : 32;           /*!< [31..0] GPIO31-0 output enables                                           */
4467     } ENA_b;
4468   } ;
4469 
4470   union {
4471     __IOM uint32_t ENB;                         /*!< (@ 0x000000A4) GPIO Enable Register B (49-32)                             */
4472 
4473     struct {
4474       __IOM uint32_t ENB        : 18;           /*!< [17..0] GPIO49-32 output enables                                          */
4475             uint32_t            : 14;
4476     } ENB_b;
4477   } ;
4478 
4479   union {
4480     __IOM uint32_t ENSA;                        /*!< (@ 0x000000A8) GPIO Enable Register A Set (31-0)                          */
4481 
4482     struct {
4483       __IOM uint32_t ENSA       : 32;           /*!< [31..0] Set the GPIO31-0 output enables                                   */
4484     } ENSA_b;
4485   } ;
4486 
4487   union {
4488     __IOM uint32_t ENSB;                        /*!< (@ 0x000000AC) GPIO Enable Register B Set (49-32)                         */
4489 
4490     struct {
4491       __IOM uint32_t ENSB       : 18;           /*!< [17..0] Set the GPIO49-32 output enables                                  */
4492             uint32_t            : 14;
4493     } ENSB_b;
4494   } ;
4495   __IM  uint32_t  RESERVED3;
4496 
4497   union {
4498     __IOM uint32_t ENCA;                        /*!< (@ 0x000000B4) GPIO Enable Register A Clear (31-0)                        */
4499 
4500     struct {
4501       __IOM uint32_t ENCA       : 32;           /*!< [31..0] Clear the GPIO31-0 output enables                                 */
4502     } ENCA_b;
4503   } ;
4504 
4505   union {
4506     __IOM uint32_t ENCB;                        /*!< (@ 0x000000B8) GPIO Enable Register B Clear (49-32)                       */
4507 
4508     struct {
4509       __IOM uint32_t ENCB       : 18;           /*!< [17..0] Clear the GPIO49-32 output enables                                */
4510             uint32_t            : 14;
4511     } ENCB_b;
4512   } ;
4513 
4514   union {
4515     __IOM uint32_t STMRCAP;                     /*!< (@ 0x000000BC) STIMER Capture trigger select and enable.                  */
4516 
4517     struct {
4518       __IOM uint32_t STSEL0     : 6;            /*!< [5..0] STIMER Capture 0 Select.                                           */
4519       __IOM uint32_t STPOL0     : 1;            /*!< [6..6] STIMER Capture 0 Polarity.                                         */
4520             uint32_t            : 1;
4521       __IOM uint32_t STSEL1     : 6;            /*!< [13..8] STIMER Capture 1 Select.                                          */
4522       __IOM uint32_t STPOL1     : 1;            /*!< [14..14] STIMER Capture 1 Polarity.                                       */
4523             uint32_t            : 1;
4524       __IOM uint32_t STSEL2     : 6;            /*!< [21..16] STIMER Capture 2 Select.                                         */
4525       __IOM uint32_t STPOL2     : 1;            /*!< [22..22] STIMER Capture 2 Polarity.                                       */
4526             uint32_t            : 1;
4527       __IOM uint32_t STSEL3     : 6;            /*!< [29..24] STIMER Capture 3 Select.                                         */
4528       __IOM uint32_t STPOL3     : 1;            /*!< [30..30] STIMER Capture 3 Polarity.                                       */
4529             uint32_t            : 1;
4530     } STMRCAP_b;
4531   } ;
4532 
4533   union {
4534     __IOM uint32_t IOM0IRQ;                     /*!< (@ 0x000000C0) IOMSTR0 IRQ select for flow control.                       */
4535 
4536     struct {
4537       __IOM uint32_t IOM0IRQ    : 6;            /*!< [5..0] IOMSTR0 IRQ pad select.                                            */
4538             uint32_t            : 26;
4539     } IOM0IRQ_b;
4540   } ;
4541 
4542   union {
4543     __IOM uint32_t IOM1IRQ;                     /*!< (@ 0x000000C4) IOMSTR1 IRQ select for flow control.                       */
4544 
4545     struct {
4546       __IOM uint32_t IOM1IRQ    : 6;            /*!< [5..0] IOMSTR1 IRQ pad select.                                            */
4547             uint32_t            : 26;
4548     } IOM1IRQ_b;
4549   } ;
4550 
4551   union {
4552     __IOM uint32_t IOM2IRQ;                     /*!< (@ 0x000000C8) IOMSTR2 IRQ select for flow control.                       */
4553 
4554     struct {
4555       __IOM uint32_t IOM2IRQ    : 6;            /*!< [5..0] IOMSTR2 IRQ pad select.                                            */
4556             uint32_t            : 26;
4557     } IOM2IRQ_b;
4558   } ;
4559 
4560   union {
4561     __IOM uint32_t IOM3IRQ;                     /*!< (@ 0x000000CC) IOMSTR3 IRQ select for flow control.                       */
4562 
4563     struct {
4564       __IOM uint32_t IOM3IRQ    : 6;            /*!< [5..0] IOMSTR3 IRQ pad select.                                            */
4565             uint32_t            : 26;
4566     } IOM3IRQ_b;
4567   } ;
4568 
4569   union {
4570     __IOM uint32_t IOM4IRQ;                     /*!< (@ 0x000000D0) IOMSTR4 IRQ select for flow control.                       */
4571 
4572     struct {
4573       __IOM uint32_t IOM4IRQ    : 6;            /*!< [5..0] IOMSTR4 IRQ pad select.                                            */
4574             uint32_t            : 26;
4575     } IOM4IRQ_b;
4576   } ;
4577 
4578   union {
4579     __IOM uint32_t IOM5IRQ;                     /*!< (@ 0x000000D4) IOMSTR5 IRQ select for flow control.                       */
4580 
4581     struct {
4582       __IOM uint32_t IOM5IRQ    : 6;            /*!< [5..0] IOMSTR5 IRQ pad select.                                            */
4583             uint32_t            : 26;
4584     } IOM5IRQ_b;
4585   } ;
4586 
4587   union {
4588     __IOM uint32_t BLEIFIRQ;                    /*!< (@ 0x000000D8) BLE IF IRQ select for flow control.                        */
4589 
4590     struct {
4591       __IOM uint32_t BLEIFIRQ   : 6;            /*!< [5..0] BLEIF IRQ pad select.                                              */
4592             uint32_t            : 26;
4593     } BLEIFIRQ_b;
4594   } ;
4595 
4596   union {
4597     __IOM uint32_t GPIOOBS;                     /*!< (@ 0x000000DC) GPIO Observation mode sample register                      */
4598 
4599     struct {
4600       __IOM uint32_t OBS_DATA   : 16;           /*!< [15..0] Sample of the data output on the GPIO observation port.
4601                                                      May have async sampling issues, as the data is not synronized
4602                                                      to the read operation. Intended for debug purposes only                   */
4603             uint32_t            : 16;
4604     } GPIOOBS_b;
4605   } ;
4606 
4607   union {
4608     __IOM uint32_t ALTPADCFGA;                  /*!< (@ 0x000000E0) This register has additional configuration control
4609                                                                     for pads 3, 2, 1, 0                                        */
4610 
4611     struct {
4612       __IOM uint32_t PAD0_DS1   : 1;            /*!< [0..0] Pad 0 high order drive strength selection. Used in conjunction
4613                                                      with PAD0STRNG field to set the pad drive strength.                       */
4614             uint32_t            : 3;
4615       __IOM uint32_t PAD0_SR    : 1;            /*!< [4..4] Pad 0 slew rate selection.                                         */
4616             uint32_t            : 3;
4617       __IOM uint32_t PAD1_DS1   : 1;            /*!< [8..8] Pad 1 high order drive strength selection. Used in conjunction
4618                                                      with PAD1STRNG field to set the pad drive strength.                       */
4619             uint32_t            : 3;
4620       __IOM uint32_t PAD1_SR    : 1;            /*!< [12..12] Pad 1 slew rate selection.                                       */
4621             uint32_t            : 3;
4622       __IOM uint32_t PAD2_DS1   : 1;            /*!< [16..16] Pad 2 high order drive strength selection. Used in
4623                                                      conjunction with PAD2STRNG field to set the pad drive strength.           */
4624             uint32_t            : 3;
4625       __IOM uint32_t PAD2_SR    : 1;            /*!< [20..20] Pad 2 slew rate selection.                                       */
4626             uint32_t            : 3;
4627       __IOM uint32_t PAD3_DS1   : 1;            /*!< [24..24] Pad 3 high order drive strength selection. Used in
4628                                                      conjunction with PAD3STRNG field to set the pad drive strength.           */
4629             uint32_t            : 3;
4630       __IOM uint32_t PAD3_SR    : 1;            /*!< [28..28] Pad 3 slew rate selection.                                       */
4631             uint32_t            : 3;
4632     } ALTPADCFGA_b;
4633   } ;
4634 
4635   union {
4636     __IOM uint32_t ALTPADCFGB;                  /*!< (@ 0x000000E4) This register has additional configuration control
4637                                                                     for pads 7, 6, 5, 4                                        */
4638 
4639     struct {
4640       __IOM uint32_t PAD4_DS1   : 1;            /*!< [0..0] Pad 4 high order drive strength selection. Used in conjunction
4641                                                      with PAD4STRNG field to set the pad drive strength.                       */
4642             uint32_t            : 3;
4643       __IOM uint32_t PAD4_SR    : 1;            /*!< [4..4] Pad 4 slew rate selection.                                         */
4644             uint32_t            : 3;
4645       __IOM uint32_t PAD5_DS1   : 1;            /*!< [8..8] Pad 5 high order drive strength selection. Used in conjunction
4646                                                      with PAD5STRNG field to set the pad drive strength.                       */
4647             uint32_t            : 3;
4648       __IOM uint32_t PAD5_SR    : 1;            /*!< [12..12] Pad 5 slew rate selection.                                       */
4649             uint32_t            : 3;
4650       __IOM uint32_t PAD6_DS1   : 1;            /*!< [16..16] Pad 6 high order drive strength selection. Used in
4651                                                      conjunction with PAD6STRNG field to set the pad drive strength.           */
4652             uint32_t            : 3;
4653       __IOM uint32_t PAD6_SR    : 1;            /*!< [20..20] Pad 6 slew rate selection.                                       */
4654             uint32_t            : 3;
4655       __IOM uint32_t PAD7_DS1   : 1;            /*!< [24..24] Pad 7 high order drive strength selection. Used in
4656                                                      conjunction with PAD7STRNG field to set the pad drive strength.           */
4657             uint32_t            : 3;
4658       __IOM uint32_t PAD7_SR    : 1;            /*!< [28..28] Pad 7 slew rate selection.                                       */
4659             uint32_t            : 3;
4660     } ALTPADCFGB_b;
4661   } ;
4662 
4663   union {
4664     __IOM uint32_t ALTPADCFGC;                  /*!< (@ 0x000000E8) This register has additional configuration control
4665                                                                     for pads 11, 10, 9, 8                                      */
4666 
4667     struct {
4668       __IOM uint32_t PAD8_DS1   : 1;            /*!< [0..0] Pad 8 high order drive strength selection. Used in conjunction
4669                                                      with PAD8STRNG field to set the pad drive strength.                       */
4670             uint32_t            : 3;
4671       __IOM uint32_t PAD8_SR    : 1;            /*!< [4..4] Pad 8 slew rate selection.                                         */
4672             uint32_t            : 3;
4673       __IOM uint32_t PAD9_DS1   : 1;            /*!< [8..8] Pad 9 high order drive strength selection. Used in conjunction
4674                                                      with PAD9STRNG field to set the pad drive strength.                       */
4675             uint32_t            : 3;
4676       __IOM uint32_t PAD9_SR    : 1;            /*!< [12..12] Pad 9 slew rate selection.                                       */
4677             uint32_t            : 3;
4678       __IOM uint32_t PAD10_DS1  : 1;            /*!< [16..16] Pad 10 high order drive strength selection. Used in
4679                                                      conjunction with PAD10STRNG field to set the pad drive
4680                                                      strength.                                                                 */
4681             uint32_t            : 3;
4682       __IOM uint32_t PAD10_SR   : 1;            /*!< [20..20] Pad 10 slew rate selection.                                      */
4683             uint32_t            : 3;
4684       __IOM uint32_t PAD11_DS1  : 1;            /*!< [24..24] Pad 11 high order drive strength selection. Used in
4685                                                      conjunction with PAD11STRNG field to set the pad drive
4686                                                      strength.                                                                 */
4687             uint32_t            : 3;
4688       __IOM uint32_t PAD11_SR   : 1;            /*!< [28..28] Pad 11 slew rate selection.                                      */
4689             uint32_t            : 3;
4690     } ALTPADCFGC_b;
4691   } ;
4692 
4693   union {
4694     __IOM uint32_t ALTPADCFGD;                  /*!< (@ 0x000000EC) This register has additional configuration control
4695                                                                     for pads 15, 14, 13, 12                                    */
4696 
4697     struct {
4698       __IOM uint32_t PAD12_DS1  : 1;            /*!< [0..0] Pad 12 high order drive strength selection. Used in conjunction
4699                                                      with PAD12STRNG field to set the pad drive strength.                      */
4700             uint32_t            : 3;
4701       __IOM uint32_t PAD12_SR   : 1;            /*!< [4..4] Pad 12 slew rate selection.                                        */
4702             uint32_t            : 3;
4703       __IOM uint32_t PAD13_DS1  : 1;            /*!< [8..8] Pad 13 high order drive strength selection. Used in conjunction
4704                                                      with PAD13STRNG field to set the pad drive strength.                      */
4705             uint32_t            : 3;
4706       __IOM uint32_t PAD13_SR   : 1;            /*!< [12..12] Pad 13 slew rate selection.                                      */
4707             uint32_t            : 3;
4708       __IOM uint32_t PAD14_DS1  : 1;            /*!< [16..16] Pad 14 high order drive strength selection. Used in
4709                                                      conjunction with PAD14STRNG field to set the pad drive
4710                                                      strength.                                                                 */
4711             uint32_t            : 3;
4712       __IOM uint32_t PAD14_SR   : 1;            /*!< [20..20] Pad 14 slew rate selection.                                      */
4713             uint32_t            : 3;
4714       __IOM uint32_t PAD15_DS1  : 1;            /*!< [24..24] Pad 15 high order drive strength selection. Used in
4715                                                      conjunction with PAD15STRNG field to set the pad drive
4716                                                      strength.                                                                 */
4717             uint32_t            : 3;
4718       __IOM uint32_t PAD15_SR   : 1;            /*!< [28..28] Pad 15 slew rate selection.                                      */
4719             uint32_t            : 3;
4720     } ALTPADCFGD_b;
4721   } ;
4722 
4723   union {
4724     __IOM uint32_t ALTPADCFGE;                  /*!< (@ 0x000000F0) This register has additional configuration control
4725                                                                     for pads 19, 18, 17, 16                                    */
4726 
4727     struct {
4728       __IOM uint32_t PAD16_DS1  : 1;            /*!< [0..0] Pad 16 high order drive strength selection. Used in conjunction
4729                                                      with PAD16STRNG field to set the pad drive strength.                      */
4730             uint32_t            : 3;
4731       __IOM uint32_t PAD16_SR   : 1;            /*!< [4..4] Pad 16 slew rate selection.                                        */
4732             uint32_t            : 3;
4733       __IOM uint32_t PAD17_DS1  : 1;            /*!< [8..8] Pad 17 high order drive strength selection. Used in conjunction
4734                                                      with PAD17STRNG field to set the pad drive strength.                      */
4735             uint32_t            : 3;
4736       __IOM uint32_t PAD17_SR   : 1;            /*!< [12..12] Pad 17 slew rate selection.                                      */
4737             uint32_t            : 3;
4738       __IOM uint32_t PAD18_DS1  : 1;            /*!< [16..16] Pad 18 high order drive strength selection. Used in
4739                                                      conjunction with PAD18STRNG field to set the pad drive
4740                                                      strength.                                                                 */
4741             uint32_t            : 3;
4742       __IOM uint32_t PAD18_SR   : 1;            /*!< [20..20] Pad 18 slew rate selection.                                      */
4743             uint32_t            : 3;
4744       __IOM uint32_t PAD19_DS1  : 1;            /*!< [24..24] Pad 19 high order drive strength selection. Used in
4745                                                      conjunction with PAD19STRNG field to set the pad drive
4746                                                      strength.                                                                 */
4747             uint32_t            : 3;
4748       __IOM uint32_t PAD19_SR   : 1;            /*!< [28..28] Pad 19 slew rate selection.                                      */
4749             uint32_t            : 3;
4750     } ALTPADCFGE_b;
4751   } ;
4752 
4753   union {
4754     __IOM uint32_t ALTPADCFGF;                  /*!< (@ 0x000000F4) This register has additional configuration control
4755                                                                     for pads 23, 22, 21, 20                                    */
4756 
4757     struct {
4758       __IOM uint32_t PAD20_DS1  : 1;            /*!< [0..0] Pad 20 high order drive strength selection. Used in conjunction
4759                                                      with PAD20STRNG field to set the pad drive strength.                      */
4760             uint32_t            : 3;
4761       __IOM uint32_t PAD20_SR   : 1;            /*!< [4..4] Pad 20 slew rate selection.                                        */
4762             uint32_t            : 3;
4763       __IOM uint32_t PAD21_DS1  : 1;            /*!< [8..8] Pad 21 high order drive strength selection. Used in conjunction
4764                                                      with PAD21STRNG field to set the pad drive strength.                      */
4765             uint32_t            : 3;
4766       __IOM uint32_t PAD21_SR   : 1;            /*!< [12..12] Pad 21 slew rate selection.                                      */
4767             uint32_t            : 3;
4768       __IOM uint32_t PAD22_DS1  : 1;            /*!< [16..16] Pad 22 high order drive strength selection. Used in
4769                                                      conjunction with PAD22STRNG field to set the pad drive
4770                                                      strength.                                                                 */
4771             uint32_t            : 3;
4772       __IOM uint32_t PAD22_SR   : 1;            /*!< [20..20] Pad 22 slew rate selection.                                      */
4773             uint32_t            : 3;
4774       __IOM uint32_t PAD23_DS1  : 1;            /*!< [24..24] Pad 23 high order drive strength selection. Used in
4775                                                      conjunction with PAD23STRNG field to set the pad drive
4776                                                      strength.                                                                 */
4777             uint32_t            : 3;
4778       __IOM uint32_t PAD23_SR   : 1;            /*!< [28..28] Pad 23 slew rate selection.                                      */
4779             uint32_t            : 3;
4780     } ALTPADCFGF_b;
4781   } ;
4782 
4783   union {
4784     __IOM uint32_t ALTPADCFGG;                  /*!< (@ 0x000000F8) This register has additional configuration control
4785                                                                     for pads 27, 26, 25, 24                                    */
4786 
4787     struct {
4788       __IOM uint32_t PAD24_DS1  : 1;            /*!< [0..0] Pad 24 high order drive strength selection. Used in conjunction
4789                                                      with PAD24STRNG field to set the pad drive strength.                      */
4790             uint32_t            : 3;
4791       __IOM uint32_t PAD24_SR   : 1;            /*!< [4..4] Pad 24 slew rate selection.                                        */
4792             uint32_t            : 3;
4793       __IOM uint32_t PAD25_DS1  : 1;            /*!< [8..8] Pad 25 high order drive strength selection. Used in conjunction
4794                                                      with PAD25STRNG field to set the pad drive strength.                      */
4795             uint32_t            : 3;
4796       __IOM uint32_t PAD25_SR   : 1;            /*!< [12..12] Pad 25 slew rate selection.                                      */
4797             uint32_t            : 3;
4798       __IOM uint32_t PAD26_DS1  : 1;            /*!< [16..16] Pad 26 high order drive strength selection. Used in
4799                                                      conjunction with PAD26STRNG field to set the pad drive
4800                                                      strength.                                                                 */
4801             uint32_t            : 3;
4802       __IOM uint32_t PAD26_SR   : 1;            /*!< [20..20] Pad 26 slew rate selection.                                      */
4803             uint32_t            : 3;
4804       __IOM uint32_t PAD27_DS1  : 1;            /*!< [24..24] Pad 27 high order drive strength selection. Used in
4805                                                      conjunction with PAD27STRNG field to set the pad drive
4806                                                      strength.                                                                 */
4807             uint32_t            : 3;
4808       __IOM uint32_t PAD27_SR   : 1;            /*!< [28..28] Pad 27 slew rate selection.                                      */
4809             uint32_t            : 3;
4810     } ALTPADCFGG_b;
4811   } ;
4812 
4813   union {
4814     __IOM uint32_t ALTPADCFGH;                  /*!< (@ 0x000000FC) This register has additional configuration control
4815                                                                     for pads 31, 30, 29, 28                                    */
4816 
4817     struct {
4818       __IOM uint32_t PAD28_DS1  : 1;            /*!< [0..0] Pad 28 high order drive strength selection. Used in conjunction
4819                                                      with PAD28STRNG field to set the pad drive strength.                      */
4820             uint32_t            : 3;
4821       __IOM uint32_t PAD28_SR   : 1;            /*!< [4..4] Pad 28 slew rate selection.                                        */
4822             uint32_t            : 3;
4823       __IOM uint32_t PAD29_DS1  : 1;            /*!< [8..8] Pad 29 high order drive strength selection. Used in conjunction
4824                                                      with PAD29STRNG field to set the pad drive strength.                      */
4825             uint32_t            : 3;
4826       __IOM uint32_t PAD29_SR   : 1;            /*!< [12..12] Pad 29 slew rate selection.                                      */
4827             uint32_t            : 3;
4828       __IOM uint32_t PAD30_DS1  : 1;            /*!< [16..16] Pad 30 high order drive strength selection. Used in
4829                                                      conjunction with PAD30STRNG field to set the pad drive
4830                                                      strength.                                                                 */
4831             uint32_t            : 3;
4832       __IOM uint32_t PAD30_SR   : 1;            /*!< [20..20] Pad 30 slew rate selection.                                      */
4833             uint32_t            : 3;
4834       __IOM uint32_t PAD31_DS1  : 1;            /*!< [24..24] Pad 31 high order drive strength selection. Used in
4835                                                      conjunction with PAD31STRNG field to set the pad drive
4836                                                      strength.                                                                 */
4837             uint32_t            : 3;
4838       __IOM uint32_t PAD31_SR   : 1;            /*!< [28..28] Pad 31 slew rate selection.                                      */
4839             uint32_t            : 3;
4840     } ALTPADCFGH_b;
4841   } ;
4842 
4843   union {
4844     __IOM uint32_t ALTPADCFGI;                  /*!< (@ 0x00000100) This register has additional configuration control
4845                                                                     for pads 35, 34, 33, 32                                    */
4846 
4847     struct {
4848       __IOM uint32_t PAD32_DS1  : 1;            /*!< [0..0] Pad 32 high order drive strength selection. Used in conjunction
4849                                                      with PAD32STRNG field to set the pad drive strength.                      */
4850             uint32_t            : 3;
4851       __IOM uint32_t PAD32_SR   : 1;            /*!< [4..4] Pad 32 slew rate selection.                                        */
4852             uint32_t            : 3;
4853       __IOM uint32_t PAD33_DS1  : 1;            /*!< [8..8] Pad 33 high order drive strength selection. Used in conjunction
4854                                                      with PAD33STRNG field to set the pad drive strength.                      */
4855             uint32_t            : 3;
4856       __IOM uint32_t PAD33_SR   : 1;            /*!< [12..12] Pad 33 slew rate selection.                                      */
4857             uint32_t            : 3;
4858       __IOM uint32_t PAD34_DS1  : 1;            /*!< [16..16] Pad 34 high order drive strength selection. Used in
4859                                                      conjunction with PAD34STRNG field to set the pad drive
4860                                                      strength.                                                                 */
4861             uint32_t            : 3;
4862       __IOM uint32_t PAD34_SR   : 1;            /*!< [20..20] Pad 34 slew rate selection.                                      */
4863             uint32_t            : 3;
4864       __IOM uint32_t PAD35_DS1  : 1;            /*!< [24..24] Pad 35 high order drive strength selection. Used in
4865                                                      conjunction with PAD35STRNG field to set the pad drive
4866                                                      strength.                                                                 */
4867             uint32_t            : 3;
4868       __IOM uint32_t PAD35_SR   : 1;            /*!< [28..28] Pad 35 slew rate selection.                                      */
4869             uint32_t            : 3;
4870     } ALTPADCFGI_b;
4871   } ;
4872 
4873   union {
4874     __IOM uint32_t ALTPADCFGJ;                  /*!< (@ 0x00000104) This register has additional configuration control
4875                                                                     for pads 39, 38, 37, 36                                    */
4876 
4877     struct {
4878       __IOM uint32_t PAD36_DS1  : 1;            /*!< [0..0] Pad 36 high order drive strength selection. Used in conjunction
4879                                                      with PAD36STRNG field to set the pad drive strength.                      */
4880             uint32_t            : 3;
4881       __IOM uint32_t PAD36_SR   : 1;            /*!< [4..4] Pad 36 slew rate selection.                                        */
4882             uint32_t            : 3;
4883       __IOM uint32_t PAD37_DS1  : 1;            /*!< [8..8] Pad 37 high order drive strength selection. Used in conjunction
4884                                                      with PAD37STRNG field to set the pad drive strength.                      */
4885             uint32_t            : 3;
4886       __IOM uint32_t PAD37_SR   : 1;            /*!< [12..12] Pad 37 slew rate selection.                                      */
4887             uint32_t            : 3;
4888       __IOM uint32_t PAD38_DS1  : 1;            /*!< [16..16] Pad 38 high order drive strength selection. Used in
4889                                                      conjunction with PAD38STRNG field to set the pad drive
4890                                                      strength.                                                                 */
4891             uint32_t            : 3;
4892       __IOM uint32_t PAD38_SR   : 1;            /*!< [20..20] Pad 38 slew rate selection.                                      */
4893             uint32_t            : 3;
4894       __IOM uint32_t PAD39_DS1  : 1;            /*!< [24..24] Pad 39 high order drive strength selection. Used in
4895                                                      conjunction with PAD39STRNG field to set the pad drive
4896                                                      strength.                                                                 */
4897             uint32_t            : 3;
4898       __IOM uint32_t PAD39_SR   : 1;            /*!< [28..28] Pad 39 slew rate selection.                                      */
4899             uint32_t            : 3;
4900     } ALTPADCFGJ_b;
4901   } ;
4902 
4903   union {
4904     __IOM uint32_t ALTPADCFGK;                  /*!< (@ 0x00000108) This register has additional configuration control
4905                                                                     for pads 43, 42, 41, 40                                    */
4906 
4907     struct {
4908       __IOM uint32_t PAD40_DS1  : 1;            /*!< [0..0] Pad 40 high order drive strength selection. Used in conjunction
4909                                                      with PAD40STRNG field to set the pad drive strength.                      */
4910             uint32_t            : 3;
4911       __IOM uint32_t PAD40_SR   : 1;            /*!< [4..4] Pad 40 slew rate selection.                                        */
4912             uint32_t            : 3;
4913       __IOM uint32_t PAD41_DS1  : 1;            /*!< [8..8] Pad 41 high order drive strength selection. Used in conjunction
4914                                                      with PAD41STRNG field to set the pad drive strength.                      */
4915             uint32_t            : 3;
4916       __IOM uint32_t PAD41_SR   : 1;            /*!< [12..12] Pad 41 slew rate selection.                                      */
4917             uint32_t            : 3;
4918       __IOM uint32_t PAD42_DS1  : 1;            /*!< [16..16] Pad 42 high order drive strength selection. Used in
4919                                                      conjunction with PAD42STRNG field to set the pad drive
4920                                                      strength.                                                                 */
4921             uint32_t            : 3;
4922       __IOM uint32_t PAD42_SR   : 1;            /*!< [20..20] Pad 42 slew rate selection.                                      */
4923             uint32_t            : 3;
4924       __IOM uint32_t PAD43_DS1  : 1;            /*!< [24..24] Pad 43 high order drive strength selection. Used in
4925                                                      conjunction with PAD43STRNG field to set the pad drive
4926                                                      strength.                                                                 */
4927             uint32_t            : 3;
4928       __IOM uint32_t PAD43_SR   : 1;            /*!< [28..28] Pad 43 slew rate selection.                                      */
4929             uint32_t            : 3;
4930     } ALTPADCFGK_b;
4931   } ;
4932 
4933   union {
4934     __IOM uint32_t ALTPADCFGL;                  /*!< (@ 0x0000010C) This register has additional configuration control
4935                                                                     for pads 47, 46, 45, 44                                    */
4936 
4937     struct {
4938       __IOM uint32_t PAD44_DS1  : 1;            /*!< [0..0] Pad 44 high order drive strength selection. Used in conjunction
4939                                                      with PAD44STRNG field to set the pad drive strength.                      */
4940             uint32_t            : 3;
4941       __IOM uint32_t PAD44_SR   : 1;            /*!< [4..4] Pad 44 slew rate selection.                                        */
4942             uint32_t            : 3;
4943       __IOM uint32_t PAD45_DS1  : 1;            /*!< [8..8] Pad 45 high order drive strength selection. Used in conjunction
4944                                                      with PAD45STRNG field to set the pad drive strength.                      */
4945             uint32_t            : 3;
4946       __IOM uint32_t PAD45_SR   : 1;            /*!< [12..12] Pad 45 slew rate selection.                                      */
4947             uint32_t            : 3;
4948       __IOM uint32_t PAD46_DS1  : 1;            /*!< [16..16] Pad 46 high order drive strength selection. Used in
4949                                                      conjunction with PAD46STRNG field to set the pad drive
4950                                                      strength.                                                                 */
4951             uint32_t            : 3;
4952       __IOM uint32_t PAD46_SR   : 1;            /*!< [20..20] Pad 46 slew rate selection.                                      */
4953             uint32_t            : 3;
4954       __IOM uint32_t PAD47_DS1  : 1;            /*!< [24..24] Pad 47 high order drive strength selection. Used in
4955                                                      conjunction with PAD47STRNG field to set the pad drive
4956                                                      strength.                                                                 */
4957             uint32_t            : 3;
4958       __IOM uint32_t PAD47_SR   : 1;            /*!< [28..28] Pad 47 slew rate selection.                                      */
4959             uint32_t            : 3;
4960     } ALTPADCFGL_b;
4961   } ;
4962 
4963   union {
4964     __IOM uint32_t ALTPADCFGM;                  /*!< (@ 0x00000110) This register has additional configuration control
4965                                                                     for pads 49, 48                                            */
4966 
4967     struct {
4968       __IOM uint32_t PAD48_DS1  : 1;            /*!< [0..0] Pad 48 high order drive strength selection. Used in conjunction
4969                                                      with PAD48STRNG field to set the pad drive strength.                      */
4970             uint32_t            : 3;
4971       __IOM uint32_t PAD48_SR   : 1;            /*!< [4..4] Pad 48 slew rate selection.                                        */
4972             uint32_t            : 3;
4973       __IOM uint32_t PAD49_DS1  : 1;            /*!< [8..8] Pad 49 high order drive strength selection. Used in conjunction
4974                                                      with PAD49STRNG field to set the pad drive strength.                      */
4975             uint32_t            : 3;
4976       __IOM uint32_t PAD49_SR   : 1;            /*!< [12..12] Pad 49 slew rate selection.                                      */
4977             uint32_t            : 19;
4978     } ALTPADCFGM_b;
4979   } ;
4980 
4981   union {
4982     __IOM uint32_t SCDET;                       /*!< (@ 0x00000114) Scard card detect select.                                  */
4983 
4984     struct {
4985       __IOM uint32_t SCDET      : 6;            /*!< [5..0] SCARD card detect pad select.                                      */
4986             uint32_t            : 26;
4987     } SCDET_b;
4988   } ;
4989 
4990   union {
4991     __IOM uint32_t CTENCFG;                     /*!< (@ 0x00000118) Pad enable configuration.                                  */
4992 
4993     struct {
4994       __IOM uint32_t EN0        : 1;            /*!< [0..0] CT0 Enable                                                         */
4995       __IOM uint32_t EN1        : 1;            /*!< [1..1] CT1 Enable                                                         */
4996       __IOM uint32_t EN2        : 1;            /*!< [2..2] CT2 Enable                                                         */
4997       __IOM uint32_t EN3        : 1;            /*!< [3..3] CT3 Enable                                                         */
4998       __IOM uint32_t EN4        : 1;            /*!< [4..4] CT4 Enable                                                         */
4999       __IOM uint32_t EN5        : 1;            /*!< [5..5] CT5 Enable                                                         */
5000       __IOM uint32_t EN6        : 1;            /*!< [6..6] CT6 Enable                                                         */
5001       __IOM uint32_t EN7        : 1;            /*!< [7..7] CT7 Enable                                                         */
5002       __IOM uint32_t EN8        : 1;            /*!< [8..8] CT8 Enable                                                         */
5003       __IOM uint32_t EN9        : 1;            /*!< [9..9] CT9 Enable                                                         */
5004       __IOM uint32_t EN10       : 1;            /*!< [10..10] CT10 Enable                                                      */
5005       __IOM uint32_t EN11       : 1;            /*!< [11..11] CT11 Enable                                                      */
5006       __IOM uint32_t EN12       : 1;            /*!< [12..12] CT12 Enable                                                      */
5007       __IOM uint32_t EN13       : 1;            /*!< [13..13] CT13 Enable                                                      */
5008       __IOM uint32_t EN14       : 1;            /*!< [14..14] CT14 Enable                                                      */
5009       __IOM uint32_t EN15       : 1;            /*!< [15..15] CT15 Enable                                                      */
5010       __IOM uint32_t EN16       : 1;            /*!< [16..16] CT16 Enable                                                      */
5011       __IOM uint32_t EN17       : 1;            /*!< [17..17] CT17 Enable                                                      */
5012       __IOM uint32_t EN18       : 1;            /*!< [18..18] CT18 Enable                                                      */
5013       __IOM uint32_t EN19       : 1;            /*!< [19..19] CT19 Enable                                                      */
5014       __IOM uint32_t EN20       : 1;            /*!< [20..20] CT20 Enable                                                      */
5015       __IOM uint32_t EN21       : 1;            /*!< [21..21] CT21 Enable                                                      */
5016       __IOM uint32_t EN22       : 1;            /*!< [22..22] CT22 Enable                                                      */
5017       __IOM uint32_t EN23       : 1;            /*!< [23..23] CT23 Enable                                                      */
5018       __IOM uint32_t EN24       : 1;            /*!< [24..24] CT24 Enable                                                      */
5019       __IOM uint32_t EN25       : 1;            /*!< [25..25] CT25 Enable                                                      */
5020       __IOM uint32_t EN26       : 1;            /*!< [26..26] CT26 Enable                                                      */
5021       __IOM uint32_t EN27       : 1;            /*!< [27..27] CT27 Enable                                                      */
5022       __IOM uint32_t EN28       : 1;            /*!< [28..28] CT28 Enable                                                      */
5023       __IOM uint32_t EN29       : 1;            /*!< [29..29] CT29 Enable                                                      */
5024       __IOM uint32_t EN30       : 1;            /*!< [30..30] CT30 Enable                                                      */
5025       __IOM uint32_t EN31       : 1;            /*!< [31..31] CT31 Enable                                                      */
5026     } CTENCFG_b;
5027   } ;
5028   __IM  uint32_t  RESERVED4[57];
5029 
5030   union {
5031     __IOM uint32_t INT0EN;                      /*!< (@ 0x00000200) Set bits in this register to allow this module
5032                                                                     to generate the corresponding interrupt.                   */
5033 
5034     struct {
5035       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5036       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5037       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5038       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5039       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5040       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5041       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5042       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5043       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5044       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5045       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5046       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5047       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5048       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5049       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5050       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5051       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5052       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5053       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5054       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5055       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5056       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5057       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5058       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5059       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5060       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5061       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5062       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5063       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5064       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5065       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5066       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5067     } INT0EN_b;
5068   } ;
5069 
5070   union {
5071     __IOM uint32_t INT0STAT;                    /*!< (@ 0x00000204) Read bits from this register to discover the
5072                                                                     cause of a recent interrupt.                               */
5073 
5074     struct {
5075       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5076       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5077       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5078       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5079       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5080       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5081       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5082       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5083       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5084       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5085       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5086       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5087       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5088       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5089       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5090       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5091       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5092       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5093       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5094       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5095       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5096       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5097       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5098       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5099       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5100       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5101       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5102       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5103       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5104       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5105       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5106       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5107     } INT0STAT_b;
5108   } ;
5109 
5110   union {
5111     __IOM uint32_t INT0CLR;                     /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
5112                                                                     the interrupt status associated with that
5113                                                                     bit.                                                       */
5114 
5115     struct {
5116       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5117       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5118       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5119       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5120       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5121       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5122       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5123       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5124       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5125       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5126       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5127       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5128       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5129       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5130       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5131       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5132       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5133       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5134       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5135       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5136       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5137       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5138       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5139       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5140       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5141       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5142       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5143       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5144       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5145       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5146       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5147       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5148     } INT0CLR_b;
5149   } ;
5150 
5151   union {
5152     __IOM uint32_t INT0SET;                     /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
5153                                                                     generate an interrupt from this module.
5154                                                                     (Generally used for testing purposes).                     */
5155 
5156     struct {
5157       __IOM uint32_t GPIO0      : 1;            /*!< [0..0] GPIO0 interrupt.                                                   */
5158       __IOM uint32_t GPIO1      : 1;            /*!< [1..1] GPIO1 interrupt.                                                   */
5159       __IOM uint32_t GPIO2      : 1;            /*!< [2..2] GPIO2 interrupt.                                                   */
5160       __IOM uint32_t GPIO3      : 1;            /*!< [3..3] GPIO3 interrupt.                                                   */
5161       __IOM uint32_t GPIO4      : 1;            /*!< [4..4] GPIO4 interrupt.                                                   */
5162       __IOM uint32_t GPIO5      : 1;            /*!< [5..5] GPIO5 interrupt.                                                   */
5163       __IOM uint32_t GPIO6      : 1;            /*!< [6..6] GPIO6 interrupt.                                                   */
5164       __IOM uint32_t GPIO7      : 1;            /*!< [7..7] GPIO7 interrupt.                                                   */
5165       __IOM uint32_t GPIO8      : 1;            /*!< [8..8] GPIO8 interrupt.                                                   */
5166       __IOM uint32_t GPIO9      : 1;            /*!< [9..9] GPIO9 interrupt.                                                   */
5167       __IOM uint32_t GPIO10     : 1;            /*!< [10..10] GPIO10 interrupt.                                                */
5168       __IOM uint32_t GPIO11     : 1;            /*!< [11..11] GPIO11 interrupt.                                                */
5169       __IOM uint32_t GPIO12     : 1;            /*!< [12..12] GPIO12 interrupt.                                                */
5170       __IOM uint32_t GPIO13     : 1;            /*!< [13..13] GPIO13 interrupt.                                                */
5171       __IOM uint32_t GPIO14     : 1;            /*!< [14..14] GPIO14 interrupt.                                                */
5172       __IOM uint32_t GPIO15     : 1;            /*!< [15..15] GPIO15 interrupt.                                                */
5173       __IOM uint32_t GPIO16     : 1;            /*!< [16..16] GPIO16 interrupt.                                                */
5174       __IOM uint32_t GPIO17     : 1;            /*!< [17..17] GPIO17 interrupt.                                                */
5175       __IOM uint32_t GPIO18     : 1;            /*!< [18..18] GPIO18interrupt.                                                 */
5176       __IOM uint32_t GPIO19     : 1;            /*!< [19..19] GPIO19 interrupt.                                                */
5177       __IOM uint32_t GPIO20     : 1;            /*!< [20..20] GPIO20 interrupt.                                                */
5178       __IOM uint32_t GPIO21     : 1;            /*!< [21..21] GPIO21 interrupt.                                                */
5179       __IOM uint32_t GPIO22     : 1;            /*!< [22..22] GPIO22 interrupt.                                                */
5180       __IOM uint32_t GPIO23     : 1;            /*!< [23..23] GPIO23 interrupt.                                                */
5181       __IOM uint32_t GPIO24     : 1;            /*!< [24..24] GPIO24 interrupt.                                                */
5182       __IOM uint32_t GPIO25     : 1;            /*!< [25..25] GPIO25 interrupt.                                                */
5183       __IOM uint32_t GPIO26     : 1;            /*!< [26..26] GPIO26 interrupt.                                                */
5184       __IOM uint32_t GPIO27     : 1;            /*!< [27..27] GPIO27 interrupt.                                                */
5185       __IOM uint32_t GPIO28     : 1;            /*!< [28..28] GPIO28 interrupt.                                                */
5186       __IOM uint32_t GPIO29     : 1;            /*!< [29..29] GPIO29 interrupt.                                                */
5187       __IOM uint32_t GPIO30     : 1;            /*!< [30..30] GPIO30 interrupt.                                                */
5188       __IOM uint32_t GPIO31     : 1;            /*!< [31..31] GPIO31 interrupt.                                                */
5189     } INT0SET_b;
5190   } ;
5191 
5192   union {
5193     __IOM uint32_t INT1EN;                      /*!< (@ 0x00000210) Set bits in this register to allow this module
5194                                                                     to generate the corresponding interrupt.                   */
5195 
5196     struct {
5197       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5198       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5199       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5200       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5201       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5202       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5203       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5204       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5205       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5206       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5207       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5208       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5209       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5210       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5211       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5212       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5213       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5214       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5215             uint32_t            : 14;
5216     } INT1EN_b;
5217   } ;
5218 
5219   union {
5220     __IOM uint32_t INT1STAT;                    /*!< (@ 0x00000214) Read bits from this register to discover the
5221                                                                     cause of a recent interrupt.                               */
5222 
5223     struct {
5224       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5225       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5226       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5227       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5228       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5229       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5230       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5231       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5232       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5233       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5234       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5235       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5236       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5237       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5238       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5239       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5240       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5241       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5242             uint32_t            : 14;
5243     } INT1STAT_b;
5244   } ;
5245 
5246   union {
5247     __IOM uint32_t INT1CLR;                     /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
5248                                                                     the interrupt status associated with that
5249                                                                     bit.                                                       */
5250 
5251     struct {
5252       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5253       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5254       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5255       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5256       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5257       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5258       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5259       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5260       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5261       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5262       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5263       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5264       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5265       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5266       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5267       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5268       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5269       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5270             uint32_t            : 14;
5271     } INT1CLR_b;
5272   } ;
5273 
5274   union {
5275     __IOM uint32_t INT1SET;                     /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
5276                                                                     generate an interrupt from this module.
5277                                                                     (Generally used for testing purposes).                     */
5278 
5279     struct {
5280       __IOM uint32_t GPIO32     : 1;            /*!< [0..0] GPIO32 interrupt.                                                  */
5281       __IOM uint32_t GPIO33     : 1;            /*!< [1..1] GPIO33 interrupt.                                                  */
5282       __IOM uint32_t GPIO34     : 1;            /*!< [2..2] GPIO34 interrupt.                                                  */
5283       __IOM uint32_t GPIO35     : 1;            /*!< [3..3] GPIO35 interrupt.                                                  */
5284       __IOM uint32_t GPIO36     : 1;            /*!< [4..4] GPIO36 interrupt.                                                  */
5285       __IOM uint32_t GPIO37     : 1;            /*!< [5..5] GPIO37 interrupt.                                                  */
5286       __IOM uint32_t GPIO38     : 1;            /*!< [6..6] GPIO38 interrupt.                                                  */
5287       __IOM uint32_t GPIO39     : 1;            /*!< [7..7] GPIO39 interrupt.                                                  */
5288       __IOM uint32_t GPIO40     : 1;            /*!< [8..8] GPIO40 interrupt.                                                  */
5289       __IOM uint32_t GPIO41     : 1;            /*!< [9..9] GPIO41 interrupt.                                                  */
5290       __IOM uint32_t GPIO42     : 1;            /*!< [10..10] GPIO42 interrupt.                                                */
5291       __IOM uint32_t GPIO43     : 1;            /*!< [11..11] GPIO43 interrupt.                                                */
5292       __IOM uint32_t GPIO44     : 1;            /*!< [12..12] GPIO44 interrupt.                                                */
5293       __IOM uint32_t GPIO45     : 1;            /*!< [13..13] GPIO45 interrupt.                                                */
5294       __IOM uint32_t GPIO46     : 1;            /*!< [14..14] GPIO46 interrupt.                                                */
5295       __IOM uint32_t GPIO47     : 1;            /*!< [15..15] GPIO47 interrupt.                                                */
5296       __IOM uint32_t GPIO48     : 1;            /*!< [16..16] GPIO48 interrupt.                                                */
5297       __IOM uint32_t GPIO49     : 1;            /*!< [17..17] GPIO49 interrupt.                                                */
5298             uint32_t            : 14;
5299     } INT1SET_b;
5300   } ;
5301 } GPIO_Type;                                    /*!< Size = 544 (0x220)                                                        */
5302 
5303 
5304 
5305 /* =========================================================================================================================== */
5306 /* ================                                           IOM0                                            ================ */
5307 /* =========================================================================================================================== */
5308 
5309 
5310 /**
5311   * @brief IO Peripheral Master (IOM0)
5312   */
5313 
5314 typedef struct {                                /*!< (@ 0x50004000) IOM0 Structure                                             */
5315 
5316   union {
5317     __IOM uint32_t FIFO;                        /*!< (@ 0x00000000) Provides direct random access to both output
5318                                                                     and input FIFOs. The state of the FIFO is
5319                                                                     not disturbed by reading these locations
5320                                                                     (i.e., no POP will be done). FIFO0 is accessible
5321                                                                     from addresses 0x0 - 0x1C, and is used for
5322                                                                     data output from the IOM to external devices.
5323                                                                     These FIFO locations can be read and written
5324                                                                     directly.FIFO1 locations 0x20 - 0x3C provide
5325                                                                     read only access to the input FIFO. These
5326                                                                     FIFO locations cannot be directly written
5327                                                                     by the MCU and are updated only by the internal
5328                                                                     hardwa                                                     */
5329 
5330     struct {
5331       __IOM uint32_t FIFO       : 32;           /*!< [31..0] FIFO direct access. Only locations 0 - 3F will return
5332                                                      valid information.                                                        */
5333     } FIFO_b;
5334   } ;
5335   __IM  uint32_t  RESERVED[63];
5336 
5337   union {
5338     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Provides the current valid byte count of data
5339                                                                     within the FIFO as seen from the internal
5340                                                                     state machines. FIFO0 is dedicated to outgoing
5341                                                                     transactions and FIFO1 is dedicated to incoming
5342                                                                     transactions. All counts are specified in
5343                                                                     units of bytes.                                            */
5344 
5345     struct {
5346       __IOM uint32_t FIFO0SIZ   : 8;            /*!< [7..0] The number of valid data bytes currently in the FIFO
5347                                                      0 (written by MCU, read by interface)                                     */
5348       __IOM uint32_t FIFO0REM   : 8;            /*!< [15..8] The number of remaining data bytes slots currently in
5349                                                      FIFO 0 (written by MCU, read by interface)                                */
5350       __IOM uint32_t FIFO1SIZ   : 8;            /*!< [23..16] The number of valid data bytes currently in FIFO 1
5351                                                      (written by interface, read by MCU)                                       */
5352       __IOM uint32_t FIFO1REM   : 8;            /*!< [31..24] The number of remaining data bytes slots currently
5353                                                      in FIFO 1 (written by interface, read by MCU)                             */
5354     } FIFOPTR_b;
5355   } ;
5356 
5357   union {
5358     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000104) Sets the threshold values for incoming and outgoing
5359                                                                     transactions. The threshold values are used
5360                                                                     to assert the interrupt if enabled, and
5361                                                                     also used during DMA to set the transfer
5362                                                                     size as a result of DMATHR trigger.The WTHR
5363                                                                     is used to indicate when there are more
5364                                                                     than WTHR bytes of open FIFO locations available
5365                                                                     in the outgoing FIFO (FIFO0). The intended
5366                                                                     use to invoke an interrupt or DMA transfer
5367                                                                     that will refill the FIFO with a byte count
5368                                                                     up to this value.The RTHR is used to indicate
5369                                                                     when t                                                     */
5370 
5371     struct {
5372       __IOM uint32_t FIFORTHR   : 6;            /*!< [5..0] FIFO read threshold in bytes. A value of 0 will disable
5373                                                      the read FIFO level from activating the threshold interrupt.
5374                                                      If this field is non-zero, it will trigger a threshold
5375                                                      interrupt when the read FIFO contains FIFORTHR valid bytes
5376                                                      of data, as indicated by the FIFO1SIZ field. This is intended
5377                                                      to signal when a data transfer of FIFORTHR bytes can be
5378                                                      done from the IOM module to the host via the read FIFO
5379                                                      to support large IOM read operations.                                     */
5380             uint32_t            : 2;
5381       __IOM uint32_t FIFOWTHR   : 6;            /*!< [13..8] FIFO write threshold in bytes. A value of 0 will disable
5382                                                      the write FIFO level from activating the threshold interrupt.
5383                                                      If this field is non-zero, it will trigger a threshold
5384                                                      interrupt when the write FIFO contains FIFOWTHR free bytes,
5385                                                      as indicated by the FIFO0REM field. This is intended to
5386                                                      signal when a transfer of FIFOWTHR bytes can be done from
5387                                                      the host to the IOM write FIFO to support large IOM write
5388                                                      operations.                                                               */
5389             uint32_t            : 18;
5390     } FIFOTHR_b;
5391   } ;
5392 
5393   union {
5394     __IOM uint32_t FIFOPOP;                     /*!< (@ 0x00000108) Will advance the internal read pointer of the
5395                                                                     incoming FIFO (FIFO1) when read, if POPWR
5396                                                                     is not active. If POPWR is active, a write
5397                                                                     to this register is needed to advance the
5398                                                                     internal FIFO pointer.                                     */
5399 
5400     struct {
5401       __IOM uint32_t FIFODOUT   : 32;           /*!< [31..0] This register will return the read data indicated by
5402                                                      the current read pointer on reads. If the POPWR control
5403                                                      bit in the FIFOCTRL register is reset (0), the FIFO read
5404                                                      pointer will be advanced by one word as a result of the
5405                                                      read.If the POPWR bit is set (1), the FIFO read pointer
5406                                                      will only be advanced after a write operation to this register.
5407                                                      The write data is ignored for this register.If less than
5408                                                      a even word multiple is available, and the command is completed,
5409                                                      the module will return the word containing                                */
5410     } FIFOPOP_b;
5411   } ;
5412 
5413   union {
5414     __IOM uint32_t FIFOPUSH;                    /*!< (@ 0x0000010C) Will write new data into the outgoing FIFO and
5415                                                                     advance the internal write pointer.                        */
5416 
5417     struct {
5418       __IOM uint32_t FIFODIN    : 32;           /*!< [31..0] This register is used to write the FIFORAM in FIFO mode
5419                                                      and will cause a push event to occur to the next open slot
5420                                                      within the FIFORAM. Writing to this register will cause
5421                                                      the write point to increment by 1 word(4 bytes).                          */
5422     } FIFOPUSH_b;
5423   } ;
5424 
5425   union {
5426     __IOM uint32_t FIFOCTRL;                    /*!< (@ 0x00000110) Provides controls for the operation of the internal
5427                                                                     FIFOs. Contains fields used to control the
5428                                                                     operation of the POP register, and also
5429                                                                     controls to reset the internal pointers
5430                                                                     of the FIFOs.                                              */
5431 
5432     struct {
5433       __IOM uint32_t POPWR      : 1;            /*!< [0..0] Selects the mode in which 'pop' events are done for the
5434                                                      FIFO read operations. A value of '1' will prevent a pop
5435                                                      event on a read operation, and will require a write to
5436                                                      the FIFOPOP register to create a pop event.A value of '0'
5437                                                      in this register will allow a pop event to occur on the
5438                                                      read of the FIFOPOP register, and may cause inadvertent
5439                                                      FIFO pops when used in a debugging mode.                                  */
5440       __IOM uint32_t FIFORSTN   : 1;            /*!< [1..1] Active low manual reset of the FIFO. Write to 0 to reset
5441                                                      FIFO, and then write to 1 to remove the reset.                            */
5442             uint32_t            : 30;
5443     } FIFOCTRL_b;
5444   } ;
5445 
5446   union {
5447     __IOM uint32_t FIFOLOC;                     /*!< (@ 0x00000114) Provides a read only value of the current read
5448                                                                     and write pointers. This register is read
5449                                                                     only and can be used along with the FIFO
5450                                                                     direct access method to determine the next
5451                                                                     data to be used for input and output functions.            */
5452 
5453     struct {
5454       __IOM uint32_t FIFOWPTR   : 4;            /*!< [3..0] Current FIFO write pointer. Value is the index into the
5455                                                      outgoing FIFO (FIFO0), which is used during write operations
5456                                                      to external devices.                                                      */
5457             uint32_t            : 4;
5458       __IOM uint32_t FIFORPTR   : 4;            /*!< [11..8] Current FIFO read pointer. Used to index into the incoming
5459                                                      FIFO (FIFO1), which is used to store read data returned
5460                                                      from external devices during a read operation.                            */
5461             uint32_t            : 20;
5462     } FIFOLOC_b;
5463   } ;
5464   __IM  uint32_t  RESERVED1[58];
5465 
5466   union {
5467     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
5468                                                                     to generate the corresponding interrupt.                   */
5469 
5470     struct {
5471       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
5472                                                      operation has completed. For repeated commands, this will
5473                                                      only be asserted when the final repeated command is completed.            */
5474       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
5475                                                      when the number of free bytes in the write FIFO equals
5476                                                      or exceeds the WTHR field.For read operations, asserted
5477                                                      when the number of valid bytes in the read FIFO equals
5478                                                      of exceeds the value set in the RTHR field.                               */
5479       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
5480                                                      tries to pop from an empty FIFO.                                          */
5481       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
5482                                                      tries to write to a full FIFO. The current operation does
5483                                                      not stop.                                                                 */
5484       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
5485                                                      been received on the I2C bus.                                             */
5486       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
5487                                                      a overflow or underflow event                                             */
5488       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
5489                                                      written when an active command is in progress.                            */
5490       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
5491                                                      on the bus has signaled a START command.                                  */
5492       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
5493                                                      on the bus has signaled a STOP command.                                   */
5494       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
5495                                                      is enabled and has been lost to another master on the bus.                */
5496       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
5497                                                      and the DMA submodule is returned into the idle state                     */
5498       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
5499                                                      DMA command. The DMA error could occur when the memory
5500                                                      access specified in the DMA operation is not available
5501                                                      or incorrectly specified.                                                 */
5502       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
5503                                                      in the PAUSEEN register. The interrupt is posted when the
5504                                                      event is enabled within the PAUSEEN register, the mask
5505                                                      is active in the CQIRQMASK field and the event occurs.                    */
5506       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
5507                                                      the register address bit 0 set to 1. The low address bits
5508                                                      in the CQ address fields are unused and bit 0 can be used
5509                                                      to trigger an interrupt to indicate when this register
5510                                                      write is performed by the CQ operation.                                   */
5511       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
5512             uint32_t            : 17;
5513     } INTEN_b;
5514   } ;
5515 
5516   union {
5517     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
5518                                                                     cause of a recent interrupt.                               */
5519 
5520     struct {
5521       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
5522                                                      operation has completed. For repeated commands, this will
5523                                                      only be asserted when the final repeated command is completed.            */
5524       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
5525                                                      when the number of free bytes in the write FIFO equals
5526                                                      or exceeds the WTHR field.For read operations, asserted
5527                                                      when the number of valid bytes in the read FIFO equals
5528                                                      of exceeds the value set in the RTHR field.                               */
5529       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
5530                                                      tries to pop from an empty FIFO.                                          */
5531       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
5532                                                      tries to write to a full FIFO. The current operation does
5533                                                      not stop.                                                                 */
5534       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
5535                                                      been received on the I2C bus.                                             */
5536       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
5537                                                      a overflow or underflow event                                             */
5538       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
5539                                                      written when an active command is in progress.                            */
5540       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
5541                                                      on the bus has signaled a START command.                                  */
5542       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
5543                                                      on the bus has signaled a STOP command.                                   */
5544       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
5545                                                      is enabled and has been lost to another master on the bus.                */
5546       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
5547                                                      and the DMA submodule is returned into the idle state                     */
5548       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
5549                                                      DMA command. The DMA error could occur when the memory
5550                                                      access specified in the DMA operation is not available
5551                                                      or incorrectly specified.                                                 */
5552       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
5553                                                      in the PAUSEEN register. The interrupt is posted when the
5554                                                      event is enabled within the PAUSEEN register, the mask
5555                                                      is active in the CQIRQMASK field and the event occurs.                    */
5556       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
5557                                                      the register address bit 0 set to 1. The low address bits
5558                                                      in the CQ address fields are unused and bit 0 can be used
5559                                                      to trigger an interrupt to indicate when this register
5560                                                      write is performed by the CQ operation.                                   */
5561       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
5562             uint32_t            : 17;
5563     } INTSTAT_b;
5564   } ;
5565 
5566   union {
5567     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
5568                                                                     the interrupt status associated with that
5569                                                                     bit.                                                       */
5570 
5571     struct {
5572       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
5573                                                      operation has completed. For repeated commands, this will
5574                                                      only be asserted when the final repeated command is completed.            */
5575       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
5576                                                      when the number of free bytes in the write FIFO equals
5577                                                      or exceeds the WTHR field.For read operations, asserted
5578                                                      when the number of valid bytes in the read FIFO equals
5579                                                      of exceeds the value set in the RTHR field.                               */
5580       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
5581                                                      tries to pop from an empty FIFO.                                          */
5582       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
5583                                                      tries to write to a full FIFO. The current operation does
5584                                                      not stop.                                                                 */
5585       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
5586                                                      been received on the I2C bus.                                             */
5587       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
5588                                                      a overflow or underflow event                                             */
5589       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
5590                                                      written when an active command is in progress.                            */
5591       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
5592                                                      on the bus has signaled a START command.                                  */
5593       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
5594                                                      on the bus has signaled a STOP command.                                   */
5595       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
5596                                                      is enabled and has been lost to another master on the bus.                */
5597       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
5598                                                      and the DMA submodule is returned into the idle state                     */
5599       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
5600                                                      DMA command. The DMA error could occur when the memory
5601                                                      access specified in the DMA operation is not available
5602                                                      or incorrectly specified.                                                 */
5603       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
5604                                                      in the PAUSEEN register. The interrupt is posted when the
5605                                                      event is enabled within the PAUSEEN register, the mask
5606                                                      is active in the CQIRQMASK field and the event occurs.                    */
5607       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
5608                                                      the register address bit 0 set to 1. The low address bits
5609                                                      in the CQ address fields are unused and bit 0 can be used
5610                                                      to trigger an interrupt to indicate when this register
5611                                                      write is performed by the CQ operation.                                   */
5612       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
5613             uint32_t            : 17;
5614     } INTCLR_b;
5615   } ;
5616 
5617   union {
5618     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
5619                                                                     generate an interrupt from this module.
5620                                                                     (Generally used for testing purposes).                     */
5621 
5622     struct {
5623       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Command Complete interrupt. Asserted when the current
5624                                                      operation has completed. For repeated commands, this will
5625                                                      only be asserted when the final repeated command is completed.            */
5626       __IOM uint32_t THR        : 1;            /*!< [1..1] FIFO Threshold interrupt. For write operations, asserted
5627                                                      when the number of free bytes in the write FIFO equals
5628                                                      or exceeds the WTHR field.For read operations, asserted
5629                                                      when the number of valid bytes in the read FIFO equals
5630                                                      of exceeds the value set in the RTHR field.                               */
5631       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] Read FIFO Underflow interrupt. This occurs when software
5632                                                      tries to pop from an empty FIFO.                                          */
5633       __IOM uint32_t FOVFL      : 1;            /*!< [3..3] Write FIFO Overflow interrupt. This occurs when software
5634                                                      tries to write to a full FIFO. The current operation does
5635                                                      not stop.                                                                 */
5636       __IOM uint32_t NAK        : 1;            /*!< [4..4] I2C NAK interrupt. Asserted when an unexpected NAK has
5637                                                      been received on the I2C bus.                                             */
5638       __IOM uint32_t IACC       : 1;            /*!< [5..5] illegal FIFO access interrupt. Asserted when there is
5639                                                      a overflow or underflow event                                             */
5640       __IOM uint32_t ICMD       : 1;            /*!< [6..6] illegal command interrupt. Asserted when a command is
5641                                                      written when an active command is in progress.                            */
5642       __IOM uint32_t START      : 1;            /*!< [7..7] START command interrupt. Asserted when another master
5643                                                      on the bus has signaled a START command.                                  */
5644       __IOM uint32_t STOP       : 1;            /*!< [8..8] STOP command interrupt. Asserted when another master
5645                                                      on the bus has signaled a STOP command.                                   */
5646       __IOM uint32_t ARB        : 1;            /*!< [9..9] Arbitration loss interrupt. Asserted when arbitration
5647                                                      is enabled and has been lost to another master on the bus.                */
5648       __IOM uint32_t DCMP       : 1;            /*!< [10..10] DMA Complete. Processing of the DMA operation has completed
5649                                                      and the DMA submodule is returned into the idle state                     */
5650       __IOM uint32_t DERR       : 1;            /*!< [11..11] DMA Error encountered during the processing of the
5651                                                      DMA command. The DMA error could occur when the memory
5652                                                      access specified in the DMA operation is not available
5653                                                      or incorrectly specified.                                                 */
5654       __IOM uint32_t CQPAUSED   : 1;            /*!< [12..12] Command queue is paused due to an active event enabled
5655                                                      in the PAUSEEN register. The interrupt is posted when the
5656                                                      event is enabled within the PAUSEEN register, the mask
5657                                                      is active in the CQIRQMASK field and the event occurs.                    */
5658       __IOM uint32_t CQUPD      : 1;            /*!< [13..13] CQ write operation performed a register write with
5659                                                      the register address bit 0 set to 1. The low address bits
5660                                                      in the CQ address fields are unused and bit 0 can be used
5661                                                      to trigger an interrupt to indicate when this register
5662                                                      write is performed by the CQ operation.                                   */
5663       __IOM uint32_t CQERR      : 1;            /*!< [14..14] Error during command queue operations                            */
5664             uint32_t            : 17;
5665     } INTSET_b;
5666   } ;
5667 
5668   union {
5669     __IOM uint32_t CLKCFG;                      /*!< (@ 0x00000210) Provides clock related controls used internal
5670                                                                     to the BLEIF module, and enablement of 32KHz
5671                                                                     clock to the BLE Core module. The internal
5672                                                                     clock sourced is selected via the FSEL and
5673                                                                     can be further divided by 3 using the DIV3
5674                                                                     control.This register is also used to enable
5675                                                                     the clock, which must be done prior to performing
5676                                                                     any IO transactions.                                       */
5677 
5678     struct {
5679       __IOM uint32_t IOCLKEN    : 1;            /*!< [0..0] Enable for the interface clock. Must be enabled prior
5680                                                      to executing any IO operations.                                           */
5681             uint32_t            : 7;
5682       __IOM uint32_t FSEL       : 3;            /*!< [10..8] Select the input clock frequency.                                 */
5683       __IOM uint32_t DIV3       : 1;            /*!< [11..11] Enable divide by 3 of the source IOCLK. Division by
5684                                                      3 is done before the DIVEN programmable divider, and if
5685                                                      enabledwill provide the divided by 3 clock as the source
5686                                                      to the programmable divider.                                              */
5687       __IOM uint32_t DIVEN      : 1;            /*!< [12..12] Enable clock division by TOTPER and LOWPER                       */
5688             uint32_t            : 3;
5689       __IOM uint32_t LOWPER     : 8;            /*!< [23..16] Clock low clock count minus 1. This provides the number
5690                                                      of clocks the divided clock will be low when the DIVEN
5691                                                      = 1.Only applicable when DIVEN = 1.                                       */
5692       __IOM uint32_t TOTPER     : 8;            /*!< [31..24] Clock total clock count minus 1. This provides the
5693                                                      total period of the divided clock -1 when the DIVEN is
5694                                                      active. Thesource clock is selected by FSEL. Only applicable
5695                                                      when DIVEN = 1.                                                           */
5696     } CLKCFG_b;
5697   } ;
5698 
5699   union {
5700     __IOM uint32_t SUBMODCTRL;                  /*!< (@ 0x00000214) Provides enable for each submodule. Only a single
5701                                                                     submodule can be enabled at one time.                      */
5702 
5703     struct {
5704       __IOM uint32_t SMOD0EN    : 1;            /*!< [0..0] Submodule 0 enable (1) or disable (0)                              */
5705       __IOM uint32_t SMOD0TYPE  : 3;            /*!< [3..1] Submodule 0 module type. This is the SPI Master interface.         */
5706       __IOM uint32_t SMOD1EN    : 1;            /*!< [4..4] Submodule 1 enable (1) or disable (0)                              */
5707       __IOM uint32_t SMOD1TYPE  : 3;            /*!< [7..5] Submodule 0 module type. This is the I2C Master interface          */
5708             uint32_t            : 24;
5709     } SUBMODCTRL_b;
5710   } ;
5711 
5712   union {
5713     __IOM uint32_t CMD;                         /*!< (@ 0x00000218) Writes to this register will start an IO transaction,
5714                                                                     as well as set various parameters for the
5715                                                                     command itself. Reads will return the command
5716                                                                     value written to the CMD register.To read
5717                                                                     the number of bytes that have yet to be
5718                                                                     transferred, refer to the CTSIZE field within
5719                                                                     the CMDSTAT register.                                      */
5720 
5721     struct {
5722       __IOM uint32_t CMD        : 5;            /*!< [4..0] Command for submodule.                                             */
5723       __IOM uint32_t OFFSETCNT  : 2;            /*!< [6..5] Number of offset bytes to use for the command - 0, 1,
5724                                                      2, 3 are valid selections. The second (byte 1) and third
5725                                                      byte (byte 2) are read from the OFFSETHI register, and
5726                                                      the low order byte is pulled from this register in the
5727                                                      OFFSETLO field.Offset bytes are transmitted highest byte
5728                                                      first. EG if OFFSETCNT == 3, OFFSETHI[15:8] will be transmitted
5729                                                      first, then OFFSETHI[7:0] then OFFSETLO.If OFFSETCNT ==
5730                                                      2, OFFSETHI[7:0] will be transmitted, then OFFSETLO.If
5731                                                      OFFSETCNT == 1, only OFFSETLO will be transmitted.                        */
5732       __IOM uint32_t CONT       : 1;            /*!< [7..7] Continue to hold the bus after the current transaction
5733                                                      if set to a 1 with a new command issued.                                  */
5734       __IOM uint32_t TSIZE      : 12;           /*!< [19..8] Defines the transaction size in bytes. The offset transfer
5735                                                      is not included in this size.                                             */
5736       __IOM uint32_t CMDSEL     : 2;            /*!< [21..20] Command Specific selection information. Not used in
5737                                                      Master I2C. Used as CEn select for Master SPI transactions                */
5738             uint32_t            : 2;
5739       __IOM uint32_t OFFSETLO   : 8;            /*!< [31..24] This register holds the low order byte of offset to
5740                                                      be used in the transaction. The number of offset bytes
5741                                                      to use is set with bits 1:0 of the command.                               */
5742     } CMD_b;
5743   } ;
5744 
5745   union {
5746     __IOM uint32_t DCX;                         /*!< (@ 0x0000021C) Enables use of CE signals to transmit DCX level
5747                                                                     for SPI transactions. Only used in Apollo3
5748                                                                     Revision B. For Revision A, this register
5749                                                                     MUST NOT be programmed!                                    */
5750 
5751     struct {
5752       __IOM uint32_t CE0OUT     : 1;            /*!< [0..0] Revision A: MUST NOT be programmed! Revision B: Enable
5753                                                      DCX output for CE0 output.                                                */
5754       __IOM uint32_t CE1OUT     : 1;            /*!< [1..1] Revision A: MUST NOT be programmed! Revision B: Enable
5755                                                      DCX output for CE1 output.                                                */
5756       __IOM uint32_t CE2OUT     : 1;            /*!< [2..2] Revision A: MUST NOT be programmed! Revision B: Enable
5757                                                      DCX output for CE2 output.                                                */
5758       __IOM uint32_t CE3OUT     : 1;            /*!< [3..3] Revision A: MUST NOT be programmed! Revision B: Enable
5759                                                      DCX output for CE3 output.                                                */
5760       __IOM uint32_t DCXEN      : 1;            /*!< [4..4] Revision A: MUST NOT be programmed! Revision B: Bit 4:
5761                                                      DCX Signaling Enable via other CE signals. The selected
5762                                                      DCX signal (unused CE pin) will be driven low during write
5763                                                      of offset byte, and high during transmission of data bytes.               */
5764             uint32_t            : 27;
5765     } DCX_b;
5766   } ;
5767 
5768   union {
5769     __IOM uint32_t OFFSETHI;                    /*!< (@ 0x00000220) High order 2 bytes of 3 byte offset for IO transaction     */
5770 
5771     struct {
5772       __IOM uint32_t OFFSETHI   : 16;           /*!< [15..0] Holds the high order 2 bytes of the 3 byte addressing/offset
5773                                                      field to use with IO commands. The number of offset bytes
5774                                                      to use is specified in the command register                               */
5775             uint32_t            : 16;
5776     } OFFSETHI_b;
5777   } ;
5778 
5779   union {
5780     __IOM uint32_t CMDSTAT;                     /*!< (@ 0x00000224) Provides status on the execution of the command
5781                                                                     currently in progress. The fields in this
5782                                                                     register will reflect the real time status
5783                                                                     of the internal state machines and data
5784                                                                     transfers within the IOM.These are read
5785                                                                     only fields and writes to the registers
5786                                                                     are ignored.                                               */
5787 
5788     struct {
5789       __IOM uint32_t CCMD       : 5;            /*!< [4..0] current command that is being executed                             */
5790       __IOM uint32_t CMDSTAT    : 3;            /*!< [7..5] The current status of the command execution.                       */
5791       __IOM uint32_t CTSIZE     : 12;           /*!< [19..8] The current number of bytes still to be transferred
5792                                                      with this command. This field will count down to zero.                    */
5793             uint32_t            : 12;
5794     } CMDSTAT_b;
5795   } ;
5796   __IM  uint32_t  RESERVED2[6];
5797 
5798   union {
5799     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) Provides control on which event will trigger
5800                                                                     the DMA transfer after the DMA operation
5801                                                                     is setup and enabled. The trigger event
5802                                                                     will cause a number of bytes (depending
5803                                                                     on trigger event) to betransferred via the
5804                                                                     DMA operation, and can be used to adjust
5805                                                                     the latency of data to/from the IOM module
5806                                                                     to/from the DMA target. DMA transfers are
5807                                                                     broken into smaller transfers internally
5808                                                                     of up to16 bytes each, and multiple trigger
5809                                                                     events can be used to complete the entire
5810                                                                     programmed DMA transfer.                                   */
5811 
5812     struct {
5813       __IOM uint32_t DCMDCMPEN  : 1;            /*!< [0..0] Trigger DMA upon command complete. Enables the trigger
5814                                                      of the DMA when a command is completed. When this event
5815                                                      is triggered, the number of words transferred will be the
5816                                                      lesser of the remaining TOTCOUNT bytes, or                                */
5817       __IOM uint32_t DTHREN     : 1;            /*!< [1..1] Trigger DMA upon THR level reached. For M2P DMA operations
5818                                                      (IOM writes), the trigger will assert when the write FIFO
5819                                                      has (WTHR/4) number of words free in the write FIFO, and
5820                                                      will transfer (WTHR/4) number of wordsor, if the number
5821                                                      of words left to transfer is less than the WTHR value,
5822                                                      will transfer the remaining byte count.For P2M DMA operations,
5823                                                      the trigger will assert when the read FIFO has (RTHR/4)
5824                                                      words available in the read FIFO, and will transfer (RTHR/4)
5825                                                      words to SRAM. This trigger will NOT asser                                */
5826             uint32_t            : 30;
5827     } DMATRIGEN_b;
5828   } ;
5829 
5830   union {
5831     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) Provides the status of trigger events that have
5832                                                                     occurred for the transaction. Some of the
5833                                                                     bits are read only and some can be reset
5834                                                                     via a write of 0.                                          */
5835 
5836     struct {
5837       __IOM uint32_t DCMDCMP    : 1;            /*!< [0..0] Triggered DMA from Command complete event. Bit is read
5838                                                      only and can be cleared by disabling the DCMDCMP trigger
5839                                                      enable or by disabling DMA.                                               */
5840       __IOM uint32_t DTHR       : 1;            /*!< [1..1] Triggered DMA from THR event. Bit is read only and can
5841                                                      be cleared by disabling the DTHR trigger enable or by disabling
5842                                                      DMA.                                                                      */
5843       __IOM uint32_t DTOTCMP    : 1;            /*!< [2..2] DMA triggered when DCMDCMP = 0, and the amount of data
5844                                                      in the FIFO was enough to complete the DMA operation (greater
5845                                                      than or equal to current TOTCOUNT) when the command completed.
5846                                                      This trigger is default active when the DCMDCMP trigger
5847                                                      isdisabled and there is enough data in the FIFO to complete
5848                                                      the DMA operation.                                                        */
5849             uint32_t            : 29;
5850     } DMATRIGSTAT_b;
5851   } ;
5852   __IM  uint32_t  RESERVED3[14];
5853 
5854   union {
5855     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) Configuration control of the DMA process, including
5856                                                                     the direction of DMA, and enablement of
5857                                                                     DMA                                                        */
5858 
5859     struct {
5860       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable. Setting this bit to EN will start the DMA
5861                                                      operation. This should be the last DMA related register
5862                                                      set prior to issuing the command                                          */
5863       __IOM uint32_t DMADIR     : 1;            /*!< [1..1] Direction                                                          */
5864             uint32_t            : 6;
5865       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
5866       __IOM uint32_t DPWROFF    : 1;            /*!< [9..9] Power off module after DMA is complete. If this bit is
5867                                                      active, the module will request to power off the supply
5868                                                      it is attached to. If there are other units still requiring
5869                                                      power from the same domain, power down will not be performed.             */
5870             uint32_t            : 22;
5871     } DMACFG_b;
5872   } ;
5873   __IM  uint32_t  RESERVED4;
5874 
5875   union {
5876     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) Contains the number of bytes to be transferred
5877                                                                     for this DMA transaction. This register
5878                                                                     is decremented as the data is transferred,
5879                                                                     and will be 0 at the completion of the DMA
5880                                                                     operation.                                                 */
5881 
5882     struct {
5883       __IOM uint32_t TOTCOUNT   : 12;           /*!< [11..0] Triggered DMA from Command complete event occurred.
5884                                                      Bit is read only and can be cleared by disabling the DTHR
5885                                                      trigger enable or by disabling DMA.                                       */
5886             uint32_t            : 20;
5887     } DMATOTCOUNT_b;
5888   } ;
5889 
5890   union {
5891     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) The source or destination address internal the
5892                                                                     SRAM for the DMA data. For write operations,
5893                                                                     this can only be SRAM data (ADDR bit 28
5894                                                                     = 1); For read operations, this can be either
5895                                                                     SRAM or FLASH (ADDR bit 28 = 0)                            */
5896 
5897     struct {
5898       __IOM uint32_t TARGADDR   : 20;           /*!< [19..0] Bits [19:0] of the target byte address for source of
5899                                                      DMA (either read or write). The address can be any byte
5900                                                      alignment, and does not have to be word aligned. In cases
5901                                                      of non-word aligned addresses, the DMA logic will take
5902                                                      care for ensuring only the target bytes are read/written.                 */
5903             uint32_t            : 8;
5904       __IOM uint32_t TARGADDR28 : 1;            /*!< [28..28] Bit 28 of the target byte address for source of DMA
5905                                                      (either read or write). In cases of non-word aligned addresses,
5906                                                      the DMA logic will take care for ensuring only the target
5907                                                      bytes are read/written.Setting to '1' will select the SRAM.
5908                                                      Setting to '0' will select the flash                                      */
5909             uint32_t            : 3;
5910     } DMATARGADDR_b;
5911   } ;
5912 
5913   union {
5914     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) Status of the DMA operation currently in progress.         */
5915 
5916     struct {
5917       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
5918                                                      a DMA transfer is active. The DMA transfer may be waiting
5919                                                      on data, transferring data, or waiting for priority.All
5920                                                      of these will be indicated with a 1. A 0 will indicate
5921                                                      that the DMA is fully complete and no further transactions
5922                                                      will be done. This bit is read only.                                      */
5923       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
5924                                                      operation. This bit can be cleared by writing to 0, and
5925                                                      will also be cleared when a new DMA is started.                           */
5926       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals an error was
5927                                                      encountered during the DMA operation. The bit can be cleared
5928                                                      by writing to 0. Once set, this bit will remain set until
5929                                                      cleared by software.                                                      */
5930             uint32_t            : 29;
5931     } DMASTAT_b;
5932   } ;
5933 
5934   union {
5935     __IOM uint32_t CQCFG;                       /*!< (@ 0x00000294) Controls parameters and options for execution
5936                                                                     of the command queue operation. To enable
5937                                                                     command queue, create this in memory, set
5938                                                                     the address, and enable it with a write
5939                                                                     to CQEN                                                    */
5940 
5941     struct {
5942       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
5943                                                      of the command queue and fetches of address/data pairs
5944                                                      will proceed from the word address within the CQADDR register.
5945                                                      Can be disabled using a CQ executed write to this bit as
5946                                                      well.                                                                     */
5947       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
5948             uint32_t            : 30;
5949     } CQCFG_b;
5950   } ;
5951 
5952   union {
5953     __IOM uint32_t CQADDR;                      /*!< (@ 0x00000298) The SRAM address which will be fetched next execution
5954                                                                     of the CQ operation. This register is updated
5955                                                                     as the CQ operation progresses, and is the
5956                                                                     live version of the register. The register
5957                                                                     can also be written by the Command Queue
5958                                                                     operation itself, allowing the relocation
5959                                                                     of successive CQ fetches. In this case,
5960                                                                     the new CQ address will be used for the
5961                                                                     next CQ address/data fetch.                                */
5962 
5963     struct {
5964             uint32_t            : 2;
5965       __IOM uint32_t CQADDR     : 18;           /*!< [19..2] Bits 19:2 of target byte address for source of CQ. The
5966                                                      buffer must be aligned on a word boundary                                 */
5967             uint32_t            : 8;
5968       __IOM uint32_t CQADDR28   : 1;            /*!< [28..28] Bit 28 of target byte address for source of CQ. Used
5969                                                      to denote Flash (0) or SRAM (1) access                                    */
5970             uint32_t            : 3;
5971     } CQADDR_b;
5972   } ;
5973 
5974   union {
5975     __IOM uint32_t CQSTAT;                      /*!< (@ 0x0000029C) Provides the status of the command queue operation.
5976                                                                     If the command queue is disabled, these
5977                                                                     bits will be cleared. The bits are read
5978                                                                     only                                                       */
5979 
5980     struct {
5981       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
5982                                                      indicate that a CQ transfer is active and this will remain
5983                                                      active even when paused waiting for external event.                       */
5984       __IOM uint32_t CQPAUSED   : 1;            /*!< [1..1] Command queue operation is currently paused.                       */
5985       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
5986                                                      signals that an error was encountered during the CQ operation.            */
5987             uint32_t            : 29;
5988     } CQSTAT_b;
5989   } ;
5990 
5991   union {
5992     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002A0) Command Queue Flag                                         */
5993 
5994     struct {
5995       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
5996                                                      controllable and bits [15:8] are hardware status.                         */
5997       __IOM uint32_t CQIRQMASK  : 16;           /*!< [31..16] Mask the bits used to generate the command queue interrupt.
5998                                                      A '1' in the bit position will enable the pause event to
5999                                                      trigger the interrupt, if the CQWT_int interrupt is enabled.
6000                                                      Bits definitions are the same as CQPAUSE                                  */
6001     } CQFLAGS_b;
6002   } ;
6003 
6004   union {
6005     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002A4) Set/Clear the command queue software pause flags
6006                                                                     on a per-bit basis. Contains 3 fields, allowing
6007                                                                     for setting, clearing or toggling the value
6008                                                                     in the software flags. Priority when the
6009                                                                     same bitis enabled in each field is toggle,
6010                                                                     then set, then clear.                                      */
6011 
6012     struct {
6013       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Will set to 1 the value of any
6014                                                      SWFLAG with a '1' in the corresponding bit position of
6015                                                      this field                                                                */
6016       __IOM uint32_t CQFTGL     : 8;            /*!< [15..8] Toggle the indicated bit. Will toggle the value of any
6017                                                      SWFLAG with a '1' in the corresponding bit position of
6018                                                      this field                                                                */
6019       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits. Will clear to 0 any SWFLAG
6020                                                      with a '1' in the corresponding bit position of this field                */
6021             uint32_t            : 8;
6022     } CQSETCLEAR_b;
6023   } ;
6024 
6025   union {
6026     __IOM uint32_t CQPAUSEEN;                   /*!< (@ 0x000002A8) Enables a flag to pause an active command queue
6027                                                                     operation. If a bit is '1' and the corresponding
6028                                                                     bit in the CQFLAG register is '1', CQ processing
6029                                                                     will halt until either value is changed
6030                                                                     to '0'.                                                    */
6031 
6032     struct {
6033       __IOM uint32_t CQPEN      : 16;           /*!< [15..0] Enables the specified event to pause command processing
6034                                                      when active                                                               */
6035             uint32_t            : 16;
6036     } CQPAUSEEN_b;
6037   } ;
6038 
6039   union {
6040     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002AC) Current index value, targeted to be written by
6041                                                                     register write operations within the command
6042                                                                     queue. This is compared to the CQENDIDX
6043                                                                     and will stop the CQ operation if bit 15
6044                                                                     of the CQPAUSEEN is '1' andthis current
6045                                                                     index equals the CQENDIDX register value.
6046                                                                     This will only pause when the values are
6047                                                                     equal.                                                     */
6048 
6049     struct {
6050       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQENDIX
6051                                                      register field. If the values match, the IDXEQ pause event
6052                                                      will be activated, which will cause the pausing of command
6053                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
6054             uint32_t            : 24;
6055     } CQCURIDX_b;
6056   } ;
6057 
6058   union {
6059     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002B0) End index value, targeted to be written by software
6060                                                                     to indicate the last valid register pair
6061                                                                     contained within the command queue for a
6062                                                                     register write operations within the command
6063                                                                     queue.This is compared to the CQCURIDX and
6064                                                                     will stop the CQ operation if bit 15 of
6065                                                                     the CQPAUSEEN is '1' andthis current index
6066                                                                     equals the CQCURIDX register value. This
6067                                                                     will only pause when the values are equal.                 */
6068 
6069     struct {
6070       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Holds 8 bits of data that will be compared with the CQCURIX
6071                                                      register field. If the values match, the IDXEQ pause event
6072                                                      will be activated, which will cause the pausing of command
6073                                                      queue operation if the IDXEQ bit is enabled in CQPAUSEEN.                 */
6074             uint32_t            : 24;
6075     } CQENDIDX_b;
6076   } ;
6077 
6078   union {
6079     __IOM uint32_t STATUS;                      /*!< (@ 0x000002B4) IOM Module Status                                          */
6080 
6081     struct {
6082       __IOM uint32_t ERR        : 1;            /*!< [0..0] Bit has been deprecated. Please refer to the other error
6083                                                      indicators. This will always return 0.                                    */
6084       __IOM uint32_t CMDACT     : 1;            /*!< [1..1] Indicates if the active I/O Command is currently processing
6085                                                      a transaction, or command is complete, but the FIFO pointers
6086                                                      are still synchronizing internally. This bit will go high
6087                                                      atthe start of the transaction, and will go low when the
6088                                                      command is complete, and the data and pointers within the
6089                                                      FIFO have been synchronized.                                              */
6090       __IOM uint32_t IDLEST     : 1;            /*!< [2..2] indicates if the active I/O state machine is IDLE. Note
6091                                                      - The state machine could be in idle state due to hold-offs
6092                                                      from data availability, or as the command gets propagated
6093                                                      into the logic from the registers.                                        */
6094             uint32_t            : 29;
6095     } STATUS_b;
6096   } ;
6097   __IM  uint32_t  RESERVED5[18];
6098 
6099   union {
6100     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000300) Controls the configuration of the SPI master
6101                                                                     module, including POL/PHA, LSB, flow control,
6102                                                                     and delays for MISO and MOSI                               */
6103 
6104     struct {
6105       __IOM uint32_t SPOL       : 1;            /*!< [0..0] selects SPI polarity.                                              */
6106       __IOM uint32_t SPHA       : 1;            /*!< [1..1] selects SPI phase.                                                 */
6107       __IOM uint32_t FULLDUP    : 1;            /*!< [2..2] Enables full duplex mode for Master SPI write operations.
6108                                                      Data will be captured simultaneously into the read FIFO                   */
6109             uint32_t            : 13;
6110       __IOM uint32_t WTFC       : 1;            /*!< [16..16] enables write mode flow control.                                 */
6111       __IOM uint32_t RDFC       : 1;            /*!< [17..17] enables read mode flow control.                                  */
6112       __IOM uint32_t MOSIINV    : 1;            /*!< [18..18] inverts MOSI when flow control is enabled.                       */
6113             uint32_t            : 1;
6114       __IOM uint32_t WTFCIRQ    : 1;            /*!< [20..20] selects the write mode flow control signal.                      */
6115       __IOM uint32_t WTFCPOL    : 1;            /*!< [21..21] selects the write flow control signal polarity. The
6116                                                      transfers are halted when the selected flow control signal
6117                                                      is OPPOSITE polarity of bit. (For example: WTFCPOL = 0
6118                                                      will allow a IRQ=1 to pause transfers).                                   */
6119       __IOM uint32_t RDFCPOL    : 1;            /*!< [22..22] selects the read flow control signal polarity.                   */
6120       __IOM uint32_t SPILSB     : 1;            /*!< [23..23] Selects data transfer as MSB first (0) or LSB first
6121                                                      (1) for the data portion of the SPI transaction. The offset
6122                                                      bytes are always transmitted MSB first.                                   */
6123       __IOM uint32_t DINDLY     : 3;            /*!< [26..24] Delay tap to use for the input signal (MISO). This
6124                                                      gives more hold time on the input data.                                   */
6125       __IOM uint32_t DOUTDLY    : 3;            /*!< [29..27] Delay tap to use for the output signal (MOSI). This
6126                                                      give more hold time on the output data                                    */
6127       __IOM uint32_t MSPIRST    : 1;            /*!< [30..30] Not used. To reset the module, toggle the SMOD_EN for
6128                                                      the module                                                                */
6129             uint32_t            : 1;
6130     } MSPICFG_b;
6131   } ;
6132   __IM  uint32_t  RESERVED6[63];
6133 
6134   union {
6135     __IOM uint32_t MI2CCFG;                     /*!< (@ 0x00000400) Controls the configuration of the I2C bus master.          */
6136 
6137     struct {
6138       __IOM uint32_t ADDRSZ     : 1;            /*!< [0..0] Sets the I2C master device address size to either 7 bits
6139                                                      (0) or 10 bits (1).                                                       */
6140       __IOM uint32_t I2CLSB     : 1;            /*!< [1..1] Direction of data transmit and receive, MSB(0) or LSB(1)
6141                                                      first. Default per I2C specification is MSB first. This
6142                                                      applies to both read and write data, and read data will
6143                                                      be bit                                                                    */
6144       __IOM uint32_t ARBEN      : 1;            /*!< [2..2] Enables multi-master arbitration for the I2C master.
6145                                                      If the bus is known to have only a single master, this
6146                                                      function can be disabled to save clock cycles on I2C transactions         */
6147             uint32_t            : 1;
6148       __IOM uint32_t SDADLY     : 2;            /*!< [5..4] Delay to enable on the SDA output. Values are 0x0-0x3.             */
6149       __IOM uint32_t MI2CRST    : 1;            /*!< [6..6] Not used. To reset the module, toggle the SMOD_EN for
6150                                                      the module                                                                */
6151             uint32_t            : 1;
6152       __IOM uint32_t SCLENDLY   : 4;            /*!< [11..8] Number of IOCLK cycles to delay the rising edge of the
6153                                                      SCL output en (clock will go low on this edge). Used to
6154                                                      allow clock shaping.                                                      */
6155       __IOM uint32_t SDAENDLY   : 4;            /*!< [15..12] Number of IOCLK cycles to delay the SDA output en (all
6156                                                      transitions affected). Used to delay data relative to clock               */
6157       __IOM uint32_t SMPCNT     : 8;            /*!< [23..16] Number of Base clock cycles to wait before sampling
6158                                                      the SCL clock to determine if a clock stretch event has
6159                                                      occurred                                                                  */
6160       __IOM uint32_t STRDIS     : 1;            /*!< [24..24] Disable detection of clock stretch events smaller than
6161                                                      1 cycle                                                                   */
6162             uint32_t            : 7;
6163     } MI2CCFG_b;
6164   } ;
6165 
6166   union {
6167     __IOM uint32_t DEVCFG;                      /*!< (@ 0x00000404) Contains the I2C device address.                           */
6168 
6169     struct {
6170       __IOM uint32_t DEVADDR    : 10;           /*!< [9..0] I2C address of the device that the Master will use to
6171                                                      target for read/write operations. This can be either a
6172                                                      7-bit or 10-bit address.                                                  */
6173             uint32_t            : 22;
6174     } DEVCFG_b;
6175   } ;
6176   __IM  uint32_t  RESERVED7[2];
6177 
6178   union {
6179     __IOM uint32_t IOMDBG;                      /*!< (@ 0x00000410) Debug control                                              */
6180 
6181     struct {
6182       __IOM uint32_t DBGEN      : 1;            /*!< [0..0] Debug Enable. Setting bit will enable the update of data
6183                                                      within this register, otherwise it is clock gated for power
6184                                                      savings                                                                   */
6185       __IOM uint32_t IOCLKON    : 1;            /*!< [1..1] IOCLK debug clock control. Enable IO_CLK to be active
6186                                                      when this bit is '1'. Otherwise, the clock is controlled
6187                                                      with gating from the logic as needed.                                     */
6188       __IOM uint32_t APBCLKON   : 1;            /*!< [2..2] APBCLK debug clock control. Enable APB_CLK to be active
6189                                                      when this bit is '1'. Otherwise, the clock is controlled
6190                                                      with gating from the logic as needed.                                     */
6191       __IOM uint32_t DBGDATA    : 29;           /*!< [31..3] Debug control for various options. DBGDATA[1:0] is used
6192                                                      to select between different debug data available in the
6193                                                      DBG0 and DBG1 registers.                                                  */
6194     } IOMDBG_b;
6195   } ;
6196 } IOM0_Type;                                    /*!< Size = 1044 (0x414)                                                       */
6197 
6198 
6199 
6200 /* =========================================================================================================================== */
6201 /* ================                                          IOSLAVE                                          ================ */
6202 /* =========================================================================================================================== */
6203 
6204 
6205 /**
6206   * @brief I2C/SPI Slave (IOSLAVE)
6207   */
6208 
6209 typedef struct {                                /*!< (@ 0x50000000) IOSLAVE Structure                                          */
6210   __IM  uint32_t  RESERVED[64];
6211 
6212   union {
6213     __IOM uint32_t FIFOPTR;                     /*!< (@ 0x00000100) Current FIFO Pointer                                       */
6214 
6215     struct {
6216       __IOM uint32_t FIFOPTR    : 8;            /*!< [7..0] Current FIFO pointer.                                              */
6217       __IOM uint32_t FIFOSIZ    : 8;            /*!< [15..8] The number of bytes currently in the hardware FIFO.               */
6218             uint32_t            : 16;
6219     } FIFOPTR_b;
6220   } ;
6221 
6222   union {
6223     __IOM uint32_t FIFOCFG;                     /*!< (@ 0x00000104) FIFO Configuration                                         */
6224 
6225     struct {
6226       __IOM uint32_t FIFOBASE   : 5;            /*!< [4..0] These bits hold the base address of the I/O FIFO in 8
6227                                                      byte segments. The IO Slave FIFO is situated in LRAM at
6228                                                      (FIFOBASE*8) to (FIFOMAX*8-1).                                            */
6229             uint32_t            : 3;
6230       __IOM uint32_t FIFOMAX    : 6;            /*!< [13..8] These bits hold the maximum FIFO address in 8 byte segments.
6231                                                      It is also the beginning of the RAM area of the LRAM. Note
6232                                                      that no RAM area is configured if FIFOMAX is set to 0x1F.                 */
6233             uint32_t            : 10;
6234       __IOM uint32_t ROBASE     : 6;            /*!< [29..24] Defines the read-only area. The IO Slave read-only
6235                                                      area is situated in LRAM at (ROBASE*8) to (FIFOBASE*8-1)                  */
6236             uint32_t            : 2;
6237     } FIFOCFG_b;
6238   } ;
6239 
6240   union {
6241     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000108) FIFO Threshold Configuration                               */
6242 
6243     struct {
6244       __IOM uint32_t FIFOTHR    : 8;            /*!< [7..0] FIFO size interrupt threshold.                                     */
6245             uint32_t            : 24;
6246     } FIFOTHR_b;
6247   } ;
6248 
6249   union {
6250     __IOM uint32_t FUPD;                        /*!< (@ 0x0000010C) FIFO Update Status                                         */
6251 
6252     struct {
6253       __IOM uint32_t FIFOUPD    : 1;            /*!< [0..0] This bit indicates that a FIFO update is underway.                 */
6254       __IOM uint32_t IOREAD     : 1;            /*!< [1..1] This bit field indicates an IO read is active.                     */
6255             uint32_t            : 30;
6256     } FUPD_b;
6257   } ;
6258 
6259   union {
6260     __IOM uint32_t FIFOCTR;                     /*!< (@ 0x00000110) Overall FIFO Counter                                       */
6261 
6262     struct {
6263       __IOM uint32_t FIFOCTR    : 10;           /*!< [9..0] Virtual FIFO byte count                                            */
6264             uint32_t            : 22;
6265     } FIFOCTR_b;
6266   } ;
6267 
6268   union {
6269     __IOM uint32_t FIFOINC;                     /*!< (@ 0x00000114) Overall FIFO Counter Increment                             */
6270 
6271     struct {
6272       __IOM uint32_t FIFOINC    : 10;           /*!< [9..0] Increment the Overall FIFO Counter by this value on a
6273                                                      write                                                                     */
6274             uint32_t            : 22;
6275     } FIFOINC_b;
6276   } ;
6277 
6278   union {
6279     __IOM uint32_t CFG;                         /*!< (@ 0x00000118) I/O Slave Configuration                                    */
6280 
6281     struct {
6282       __IOM uint32_t IFCSEL     : 1;            /*!< [0..0] This bit selects the I/O interface.                                */
6283       __IOM uint32_t SPOL       : 1;            /*!< [1..1] This bit selects SPI polarity.                                     */
6284       __IOM uint32_t LSB        : 1;            /*!< [2..2] This bit selects the transfer bit ordering.                        */
6285             uint32_t            : 1;
6286       __IOM uint32_t STARTRD    : 1;            /*!< [4..4] This bit holds the cycle to initiate an I/O RAM read.              */
6287             uint32_t            : 3;
6288       __IOM uint32_t I2CADDR    : 12;           /*!< [19..8] 7-bit or 10-bit I2C device address.                               */
6289             uint32_t            : 11;
6290       __IOM uint32_t IFCEN      : 1;            /*!< [31..31] IOSLAVE interface enable.                                        */
6291     } CFG_b;
6292   } ;
6293 
6294   union {
6295     __IOM uint32_t PRENC;                       /*!< (@ 0x0000011C) I/O Slave Interrupt Priority Encode                        */
6296 
6297     struct {
6298       __IOM uint32_t PRENC      : 5;            /*!< [4..0] These bits hold the priority encode of the REGACC interrupts.      */
6299             uint32_t            : 27;
6300     } PRENC_b;
6301   } ;
6302 
6303   union {
6304     __IOM uint32_t IOINTCTL;                    /*!< (@ 0x00000120) I/O Interrupt Control                                      */
6305 
6306     struct {
6307       __IOM uint32_t IOINTEN    : 8;            /*!< [7..0] These read-only bits indicate whether the IOINT interrupts
6308                                                      are enabled.                                                              */
6309       __IOM uint32_t IOINT      : 8;            /*!< [15..8] These bits read the IOINT interrupts.                             */
6310       __IOM uint32_t IOINTCLR   : 1;            /*!< [16..16] This bit clears all of the IOINT interrupts when written
6311                                                      with a 1.                                                                 */
6312             uint32_t            : 7;
6313       __IOM uint32_t IOINTSET   : 8;            /*!< [31..24] These bits set the IOINT interrupts when written with
6314                                                      a 1.                                                                      */
6315     } IOINTCTL_b;
6316   } ;
6317 
6318   union {
6319     __IOM uint32_t GENADD;                      /*!< (@ 0x00000124) General Address Data                                       */
6320 
6321     struct {
6322       __IOM uint32_t GADATA     : 8;            /*!< [7..0] The data supplied on the last General Address reference.           */
6323             uint32_t            : 24;
6324     } GENADD_b;
6325   } ;
6326   __IM  uint32_t  RESERVED1[54];
6327 
6328   union {
6329     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
6330                                                                     to generate the corresponding interrupt.                   */
6331 
6332     struct {
6333       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
6334       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
6335       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
6336       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
6337       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
6338       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
6339       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
6340       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
6341       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
6342       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
6343             uint32_t            : 22;
6344     } INTEN_b;
6345   } ;
6346 
6347   union {
6348     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
6349                                                                     cause of a recent interrupt.                               */
6350 
6351     struct {
6352       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
6353       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
6354       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
6355       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
6356       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
6357       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
6358       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
6359       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
6360       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
6361       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
6362             uint32_t            : 22;
6363     } INTSTAT_b;
6364   } ;
6365 
6366   union {
6367     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
6368                                                                     the interrupt status associated with that
6369                                                                     bit.                                                       */
6370 
6371     struct {
6372       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
6373       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
6374       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
6375       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
6376       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
6377       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
6378       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
6379       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
6380       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
6381       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
6382             uint32_t            : 22;
6383     } INTCLR_b;
6384   } ;
6385 
6386   union {
6387     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
6388                                                                     generate an interrupt from this module.
6389                                                                     (Generally used for testing purposes).                     */
6390 
6391     struct {
6392       __IOM uint32_t FSIZE      : 1;            /*!< [0..0] FIFO Size interrupt.                                               */
6393       __IOM uint32_t FOVFL      : 1;            /*!< [1..1] FIFO Overflow interrupt.                                           */
6394       __IOM uint32_t FUNDFL     : 1;            /*!< [2..2] FIFO Underflow interrupt.                                          */
6395       __IOM uint32_t FRDERR     : 1;            /*!< [3..3] FIFO Read Error interrupt.                                         */
6396       __IOM uint32_t GENAD      : 1;            /*!< [4..4] I2C General Address interrupt.                                     */
6397       __IOM uint32_t IOINTW     : 1;            /*!< [5..5] IO Write interrupt.                                                */
6398       __IOM uint32_t XCMPRF     : 1;            /*!< [6..6] Transfer complete interrupt, read from FIFO space.                 */
6399       __IOM uint32_t XCMPRR     : 1;            /*!< [7..7] Transfer complete interrupt, read from register space.             */
6400       __IOM uint32_t XCMPWF     : 1;            /*!< [8..8] Transfer complete interrupt, write to FIFO space.                  */
6401       __IOM uint32_t XCMPWR     : 1;            /*!< [9..9] Transfer complete interrupt, write to register space.              */
6402             uint32_t            : 22;
6403     } INTSET_b;
6404   } ;
6405 
6406   union {
6407     __IOM uint32_t REGACCINTEN;                 /*!< (@ 0x00000210) Set bits in this register to allow this module
6408                                                                     to generate the corresponding interrupt.                   */
6409 
6410     struct {
6411       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
6412     } REGACCINTEN_b;
6413   } ;
6414 
6415   union {
6416     __IOM uint32_t REGACCINTSTAT;               /*!< (@ 0x00000214) Read bits from this register to discover the
6417                                                                     cause of a recent interrupt.                               */
6418 
6419     struct {
6420       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
6421     } REGACCINTSTAT_b;
6422   } ;
6423 
6424   union {
6425     __IOM uint32_t REGACCINTCLR;                /*!< (@ 0x00000218) Write a 1 to a bit in this register to clear
6426                                                                     the interrupt status associated with that
6427                                                                     bit.                                                       */
6428 
6429     struct {
6430       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
6431     } REGACCINTCLR_b;
6432   } ;
6433 
6434   union {
6435     __IOM uint32_t REGACCINTSET;                /*!< (@ 0x0000021C) Write a 1 to a bit in this register to instantly
6436                                                                     generate an interrupt from this module.
6437                                                                     (Generally used for testing purposes).                     */
6438 
6439     struct {
6440       __IOM uint32_t REGACC     : 32;           /*!< [31..0] Register access interrupts.                                       */
6441     } REGACCINTSET_b;
6442   } ;
6443 } IOSLAVE_Type;                                 /*!< Size = 544 (0x220)                                                        */
6444 
6445 
6446 
6447 /* =========================================================================================================================== */
6448 /* ================                                          MCUCTRL                                          ================ */
6449 /* =========================================================================================================================== */
6450 
6451 
6452 /**
6453   * @brief MCU Miscellaneous Control Logic (MCUCTRL)
6454   */
6455 
6456 typedef struct {                                /*!< (@ 0x40020000) MCUCTRL Structure                                          */
6457 
6458   union {
6459     __IOM uint32_t CHIPPN;                      /*!< (@ 0x00000000) Chip Information Register                                  */
6460 
6461     struct {
6462       __IOM uint32_t PARTNUM    : 32;           /*!< [31..0] BCD part number.                                                  */
6463     } CHIPPN_b;
6464   } ;
6465 
6466   union {
6467     __IOM uint32_t CHIPID0;                     /*!< (@ 0x00000004) Unique Chip ID 0                                           */
6468 
6469     struct {
6470       __IOM uint32_t CHIPID0    : 32;           /*!< [31..0] Unique chip ID 0.                                                 */
6471     } CHIPID0_b;
6472   } ;
6473 
6474   union {
6475     __IOM uint32_t CHIPID1;                     /*!< (@ 0x00000008) Unique Chip ID 1                                           */
6476 
6477     struct {
6478       __IOM uint32_t CHIPID1    : 32;           /*!< [31..0] Unique chip ID 1.                                                 */
6479     } CHIPID1_b;
6480   } ;
6481 
6482   union {
6483     __IOM uint32_t CHIPREV;                     /*!< (@ 0x0000000C) Chip Revision                                              */
6484 
6485     struct {
6486       __IOM uint32_t REVMIN     : 4;            /*!< [3..0] Minor Revision ID.                                                 */
6487       __IOM uint32_t REVMAJ     : 4;            /*!< [7..4] Major Revision ID.                                                 */
6488       __IOM uint32_t SIPART     : 12;           /*!< [19..8] Silicon Part ID                                                   */
6489             uint32_t            : 12;
6490     } CHIPREV_b;
6491   } ;
6492 
6493   union {
6494     __IOM uint32_t VENDORID;                    /*!< (@ 0x00000010) Unique Vendor ID                                           */
6495 
6496     struct {
6497       __IOM uint32_t VENDORID   : 32;           /*!< [31..0] Unique Vendor ID                                                  */
6498     } VENDORID_b;
6499   } ;
6500 
6501   union {
6502     __IOM uint32_t SKU;                         /*!< (@ 0x00000014) Unique Chip SKU                                            */
6503 
6504     struct {
6505       __IOM uint32_t ALLOWBURST : 1;            /*!< [0..0] Allow Burst feature                                                */
6506       __IOM uint32_t ALLOWBLE   : 1;            /*!< [1..1] Allow BLE feature                                                  */
6507       __IOM uint32_t SECBOOT    : 1;            /*!< [2..2] Secure boot feature allowed                                        */
6508             uint32_t            : 29;
6509     } SKU_b;
6510   } ;
6511 
6512   union {
6513     __IOM uint32_t FEATUREENABLE;               /*!< (@ 0x00000018) Feature Enable on Burst and BLE                            */
6514 
6515     struct {
6516       __IOM uint32_t BLEREQ     : 1;            /*!< [0..0] Controls the BLE functionality                                     */
6517       __IOM uint32_t BLEACK     : 1;            /*!< [1..1] ACK for BLEREQ                                                     */
6518       __IOM uint32_t BLEAVAIL   : 1;            /*!< [2..2] AVAILABILITY of the BLE functionality                              */
6519             uint32_t            : 1;
6520       __IOM uint32_t BURSTREQ   : 1;            /*!< [4..4] Controls the Burst functionality                                   */
6521       __IOM uint32_t BURSTACK   : 1;            /*!< [5..5] ACK for BURSTREQ                                                   */
6522       __IOM uint32_t BURSTAVAIL : 1;            /*!< [6..6] Availability of Burst functionality                                */
6523             uint32_t            : 25;
6524     } FEATUREENABLE_b;
6525   } ;
6526   __IM  uint32_t  RESERVED;
6527 
6528   union {
6529     __IOM uint32_t DEBUGGER;                    /*!< (@ 0x00000020) Debugger Control                                           */
6530 
6531     struct {
6532       __IOM uint32_t LOCKOUT    : 1;            /*!< [0..0] Lockout of debugger (SWD).                                         */
6533             uint32_t            : 31;
6534     } DEBUGGER_b;
6535   } ;
6536   __IM  uint32_t  RESERVED1[55];
6537 
6538   union {
6539     __IOM uint32_t BODCTRL;                     /*!< (@ 0x00000100) BOD control Register                                       */
6540 
6541     struct {
6542       __IOM uint32_t BODLPWD    : 1;            /*!< [0..0] BODL Power Down.                                                   */
6543       __IOM uint32_t BODHPWD    : 1;            /*!< [1..1] BODH Power Down.                                                   */
6544       __IOM uint32_t BODCPWD    : 1;            /*!< [2..2] BODC Power Down.                                                   */
6545       __IOM uint32_t BODFPWD    : 1;            /*!< [3..3] BODF Power Down.                                                   */
6546       __IOM uint32_t BODLVREFSEL : 1;           /*!< [4..4] BODL External Reference Select. Note: the SWE mux select
6547                                                      in PWRSEQ2SWE must be set for this to take effect.                        */
6548       __IOM uint32_t BODHVREFSEL : 1;           /*!< [5..5] BODH External Reference Select. Note: the SWE mux select
6549                                                      in PWRSEQ2SWE must be set for this to take effect.                        */
6550             uint32_t            : 26;
6551     } BODCTRL_b;
6552   } ;
6553 
6554   union {
6555     __IOM uint32_t ADCPWRDLY;                   /*!< (@ 0x00000104) ADC Power Up Delay Control                                 */
6556 
6557     struct {
6558       __IOM uint32_t ADCPWR0    : 8;            /*!< [7..0] ADC Reference Buffer Power Enable delay in 64 ADC CLK
6559                                                      increments for ADC_CLKSEL = 0x1, 32 ADC CLOCK increments
6560                                                      for ADC_CLKSEL = 0x2.                                                     */
6561       __IOM uint32_t ADCPWR1    : 8;            /*!< [15..8] ADC Reference Keeper enable delay in 16 ADC CLK increments
6562                                                      for ADC_CLKSEL = 0x1, 8 ADC CLOCK increments for ADC_CLKSEL
6563                                                      = 0x2.                                                                    */
6564             uint32_t            : 16;
6565     } ADCPWRDLY_b;
6566   } ;
6567   __IM  uint32_t  RESERVED2;
6568 
6569   union {
6570     __IOM uint32_t ADCCAL;                      /*!< (@ 0x0000010C) ADC Calibration Control                                    */
6571 
6572     struct {
6573       __IOM uint32_t CALONPWRUP : 1;            /*!< [0..0] Run ADC Calibration on initial power up sequence                   */
6574       __IOM uint32_t ADCCALIBRATED : 1;         /*!< [1..1] Status for ADC Calibration                                         */
6575             uint32_t            : 30;
6576     } ADCCAL_b;
6577   } ;
6578 
6579   union {
6580     __IOM uint32_t ADCBATTLOAD;                 /*!< (@ 0x00000110) ADC Battery Load Enable                                    */
6581 
6582     struct {
6583       __IOM uint32_t BATTLOAD   : 1;            /*!< [0..0] Enable the ADC battery load resistor                               */
6584             uint32_t            : 31;
6585     } ADCBATTLOAD_b;
6586   } ;
6587   __IM  uint32_t  RESERVED3;
6588 
6589   union {
6590     __IOM uint32_t ADCTRIM;                     /*!< (@ 0x00000118) ADC Trims                                                  */
6591 
6592     struct {
6593       __IOM uint32_t ADCREFKEEPIBTRIM : 2;      /*!< [1..0] ADC Reference Ibias trim                                           */
6594             uint32_t            : 4;
6595       __IOM uint32_t ADCREFBUFTRIM : 5;         /*!< [10..6] ADC Reference buffer trim                                         */
6596       __IOM uint32_t ADCRFBUFIBTRIM : 2;        /*!< [12..11] ADC reference buffer input bias trim                             */
6597             uint32_t            : 19;
6598     } ADCTRIM_b;
6599   } ;
6600 
6601   union {
6602     __IOM uint32_t ADCREFCOMP;                  /*!< (@ 0x0000011C) ADC Reference Keeper and Comparator Control                */
6603 
6604     struct {
6605       __IOM uint32_t ADC_REFCOMP_OUT : 1;       /*!< [0..0] Output of the ADC reference comparator                             */
6606             uint32_t            : 7;
6607       __IOM uint32_t ADCREFKEEPTRIM : 5;        /*!< [12..8] ADC Reference Keeper Trim                                         */
6608             uint32_t            : 3;
6609       __IOM uint32_t ADCRFCMPEN : 1;            /*!< [16..16] ADC Reference comparator power down                              */
6610             uint32_t            : 15;
6611     } ADCREFCOMP_b;
6612   } ;
6613 
6614   union {
6615     __IOM uint32_t XTALCTRL;                    /*!< (@ 0x00000120) XTAL Oscillator Control                                    */
6616 
6617     struct {
6618       __IOM uint32_t XTALSWE    : 1;            /*!< [0..0] XTAL Software Override Enable.                                     */
6619       __IOM uint32_t FDBKDSBLXTAL : 1;          /*!< [1..1] XTAL Oscillator Disable Feedback.                                  */
6620       __IOM uint32_t BYPCMPRXTAL : 1;           /*!< [2..2] XTAL Oscillator Bypass Comparator.                                 */
6621       __IOM uint32_t PDNBCOREXTAL : 1;          /*!< [3..3] XTAL Oscillator Power Down Core.                                   */
6622       __IOM uint32_t PDNBCMPRXTAL : 1;          /*!< [4..4] XTAL Oscillator Power Down Comparator.                             */
6623       __IOM uint32_t PWDBODXTAL : 1;            /*!< [5..5] XTAL Power down on brown out.                                      */
6624       __IOM uint32_t XTALIBUFTRIM : 2;          /*!< [7..6] XTAL IBUFF trim                                                    */
6625       __IOM uint32_t XTALICOMPTRIM : 2;         /*!< [9..8] XTAL ICOMP trim                                                    */
6626             uint32_t            : 22;
6627     } XTALCTRL_b;
6628   } ;
6629 
6630   union {
6631     __IOM uint32_t XTALGENCTRL;                 /*!< (@ 0x00000124) XTAL Oscillator General Control                            */
6632 
6633     struct {
6634       __IOM uint32_t ACWARMUP   : 2;            /*!< [1..0] Auto-calibration delay control                                     */
6635       __IOM uint32_t XTALBIASTRIM : 6;          /*!< [7..2] XTAL BIAS trim                                                     */
6636       __IOM uint32_t XTALKSBIASTRIM : 6;        /*!< [13..8] XTAL IBIAS Kick start trim. This trim value is used
6637                                                      during the startup process to enable a faster lock.                       */
6638             uint32_t            : 18;
6639     } XTALGENCTRL_b;
6640   } ;
6641   __IM  uint32_t  RESERVED4[28];
6642 
6643   union {
6644     __IOM uint32_t MISCCTRL;                    /*!< (@ 0x00000198) Miscellaneous control register.                            */
6645 
6646     struct {
6647       __IOM uint32_t RESERVED_RW_0 : 5;         /*!< [4..0] Reserved bits, always leave unchanged. The MISCCTRL register
6648                                                      must be modified via atomic RMW, leaving this bit field
6649                                                      completely unmodified. Failure to do so will result in
6650                                                      unpredictable behavior.                                                   */
6651       __IOM uint32_t BLE_RESETN : 1;            /*!< [5..5] BLE reset signal.                                                  */
6652             uint32_t            : 26;
6653     } MISCCTRL_b;
6654   } ;
6655   __IM  uint32_t  RESERVED5;
6656 
6657   union {
6658     __IOM uint32_t BOOTLOADER;                  /*!< (@ 0x000001A0) Bootloader and secure boot functions                       */
6659 
6660     struct {
6661       __IOM uint32_t BOOTLOADERLOW : 1;         /*!< [0..0] Determines whether the bootloader code is visible at
6662                                                      address 0x00000000 or not. Resets to 1, write 1 to clear.                 */
6663       __IOM uint32_t SBLOCK     : 1;            /*!< [1..1] Secure boot lock. Always resets to 1, write 1 to clear.
6664                                                      Enables system visibility to bootloader until set.                        */
6665       __IOM uint32_t PROTLOCK   : 1;            /*!< [2..2] Flash protection lock. Always resets to 1, write 1 to
6666                                                      clear. Enables writes to flash protection register set.                   */
6667             uint32_t            : 23;
6668       __IOM uint32_t SECBOOTFEATURE : 2;        /*!< [27..26] Indicates whether the secure boot feature is enabled.            */
6669       __IOM uint32_t SECBOOT    : 2;            /*!< [29..28] Indicates whether the secure boot on cold reset is
6670                                                      enabled                                                                   */
6671       __IOM uint32_t SECBOOTONRST : 2;          /*!< [31..30] Indicates whether the secure boot on warm reset is
6672                                                      enabled                                                                   */
6673     } BOOTLOADER_b;
6674   } ;
6675 
6676   union {
6677     __IOM uint32_t SHADOWVALID;                 /*!< (@ 0x000001A4) Register to indicate whether the shadow registers
6678                                                                     have been successfully loaded from the Flash
6679                                                                     Information Space.                                         */
6680 
6681     struct {
6682       __IOM uint32_t VALID      : 1;            /*!< [0..0] Indicates whether the shadow registers contain valid
6683                                                      data from the Flash Information Space.                                    */
6684       __IOM uint32_t BLDSLEEP   : 1;            /*!< [1..1] Indicates whether the bootloader should sleep or deep
6685                                                      sleep if no image loaded.                                                 */
6686       __IOM uint32_t INFO0_VALID : 1;           /*!< [2..2] Indicates whether INFO0 contains valid data                        */
6687             uint32_t            : 29;
6688     } SHADOWVALID_b;
6689   } ;
6690   __IM  uint32_t  RESERVED6[2];
6691 
6692   union {
6693     __IOM uint32_t SCRATCH0;                    /*!< (@ 0x000001B0) Scratch register that is not reset by any reset            */
6694 
6695     struct {
6696       __IOM uint32_t SCRATCH0   : 32;           /*!< [31..0] Scratch register 0.                                               */
6697     } SCRATCH0_b;
6698   } ;
6699 
6700   union {
6701     __IOM uint32_t SCRATCH1;                    /*!< (@ 0x000001B4) Scratch register that is not reset by any reset            */
6702 
6703     struct {
6704       __IOM uint32_t SCRATCH1   : 32;           /*!< [31..0] Scratch register 1.                                               */
6705     } SCRATCH1_b;
6706   } ;
6707   __IM  uint32_t  RESERVED7[2];
6708 
6709   union {
6710     __IOM uint32_t ICODEFAULTADDR;              /*!< (@ 0x000001C0) ICODE bus address which was present when a bus
6711                                                                     fault occurred.                                            */
6712 
6713     struct {
6714       __IOM uint32_t ICODEFAULTADDR : 32;       /*!< [31..0] The ICODE bus address observed when a Bus Fault occurred.
6715                                                      Once an address is captured in this field, it is held until
6716                                                      the corresponding Fault Observed bit is cleared in the
6717                                                      FAULTSTATUS register.                                                     */
6718     } ICODEFAULTADDR_b;
6719   } ;
6720 
6721   union {
6722     __IOM uint32_t DCODEFAULTADDR;              /*!< (@ 0x000001C4) DCODE bus address which was present when a bus
6723                                                                     fault occurred.                                            */
6724 
6725     struct {
6726       __IOM uint32_t DCODEFAULTADDR : 32;       /*!< [31..0] The DCODE bus address observed when a Bus Fault occurred.
6727                                                      Once an address is captured in this field, it is held until
6728                                                      the corresponding Fault Observed bit is cleared in the
6729                                                      FAULTSTATUS register.                                                     */
6730     } DCODEFAULTADDR_b;
6731   } ;
6732 
6733   union {
6734     __IOM uint32_t SYSFAULTADDR;                /*!< (@ 0x000001C8) System bus address which was present when a bus
6735                                                                     fault occurred.                                            */
6736 
6737     struct {
6738       __IOM uint32_t SYSFAULTADDR : 32;         /*!< [31..0] SYS bus address observed when a Bus Fault occurred.
6739                                                      Once an address is captured in this field, it is held until
6740                                                      the corresponding Fault Observed bit is cleared in the
6741                                                      FAULTSTATUS register.                                                     */
6742     } SYSFAULTADDR_b;
6743   } ;
6744 
6745   union {
6746     __IOM uint32_t FAULTSTATUS;                 /*!< (@ 0x000001CC) Reflects the status of the bus decoders' fault
6747                                                                     detection. Any write to this register will
6748                                                                     clear all of the status bits within the
6749                                                                     register.                                                  */
6750 
6751     struct {
6752       __IOM uint32_t ICODEFAULT : 1;            /*!< [0..0] The ICODE Bus Decoder Fault Detected bit. When set, a
6753                                                      fault has been detected, and the ICODEFAULTADDR register
6754                                                      will contain the bus address which generated the fault.                   */
6755       __IOM uint32_t DCODEFAULT : 1;            /*!< [1..1] DCODE Bus Decoder Fault Detected bit. When set, a fault
6756                                                      has been detected, and the DCODEFAULTADDR register will
6757                                                      contain the bus address which generated the fault.                        */
6758       __IOM uint32_t SYSFAULT   : 1;            /*!< [2..2] SYS Bus Decoder Fault Detected bit. When set, a fault
6759                                                      has been detected, and the SYSFAULTADDR register will contain
6760                                                      the bus address which generated the fault.                                */
6761             uint32_t            : 29;
6762     } FAULTSTATUS_b;
6763   } ;
6764 
6765   union {
6766     __IOM uint32_t FAULTCAPTUREEN;              /*!< (@ 0x000001D0) Enable the fault capture registers                         */
6767 
6768     struct {
6769       __IOM uint32_t FAULTCAPTUREEN : 1;        /*!< [0..0] Fault Capture Enable field. When set, the Fault Capture
6770                                                      monitors are enabled and addresses which generate a hard
6771                                                      fault are captured into the FAULTADDR registers.                          */
6772             uint32_t            : 31;
6773     } FAULTCAPTUREEN_b;
6774   } ;
6775   __IM  uint32_t  RESERVED8[11];
6776 
6777   union {
6778     __IOM uint32_t DBGR1;                       /*!< (@ 0x00000200) Read-only debug register 1                                 */
6779 
6780     struct {
6781       __IOM uint32_t ONETO8     : 32;           /*!< [31..0] Read-only register for communication validation                   */
6782     } DBGR1_b;
6783   } ;
6784 
6785   union {
6786     __IOM uint32_t DBGR2;                       /*!< (@ 0x00000204) Read-only debug register 2                                 */
6787 
6788     struct {
6789       __IOM uint32_t COOLCODE   : 32;           /*!< [31..0] Read-only register for communication validation                   */
6790     } DBGR2_b;
6791   } ;
6792   __IM  uint32_t  RESERVED9[6];
6793 
6794   union {
6795     __IOM uint32_t PMUENABLE;                   /*!< (@ 0x00000220) Control bit to enable/disable the PMU                      */
6796 
6797     struct {
6798       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] PMU Enable Control bit. When set, the MCU's PMU will
6799                                                      place the MCU into the lowest power consuming Deep Sleep
6800                                                      mode upon execution of a WFI instruction (dependent on
6801                                                      the setting of the SLEEPDEEP bit in the ARM SCR register).
6802                                                      When cleared, regardless of the requested sleep mode, the
6803                                                      PMU will not enter the lowest power Deep Sleep mode, instead
6804                                                      entering the Sleep mode.                                                  */
6805             uint32_t            : 31;
6806     } PMUENABLE_b;
6807   } ;
6808   __IM  uint32_t  RESERVED10[11];
6809 
6810   union {
6811     __IOM uint32_t TPIUCTRL;                    /*!< (@ 0x00000250) TPIU Control Register. Determines the clock enable
6812                                                                     and frequency for the M4's TPIU interface.                 */
6813 
6814     struct {
6815       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] TPIU Enable field. When set, the ARM M4 TPIU is enabled
6816                                                      and data can be streamed out of the MCU's SWO port using
6817                                                      the ARM ITM and TPIU modules.                                             */
6818             uint32_t            : 7;
6819       __IOM uint32_t CLKSEL     : 3;            /*!< [10..8] This field selects the frequency of the ARM M4 TPIU
6820                                                      port.                                                                     */
6821             uint32_t            : 21;
6822     } TPIUCTRL_b;
6823   } ;
6824   __IM  uint32_t  RESERVED11[4];
6825 
6826   union {
6827     __IOM uint32_t OTAPOINTER;                  /*!< (@ 0x00000264) OTA (Over the Air) Update Pointer/Status. Reset
6828                                                                     only by POA                                                */
6829 
6830     struct {
6831       __IOM uint32_t OTAVALID   : 1;            /*!< [0..0] Indicates that an OTA update is valid                              */
6832       __IOM uint32_t OTASBLUPDATE : 1;          /*!< [1..1] Indicates that the sbl_init has been updated                       */
6833       __IOM uint32_t OTAPOINTER : 30;           /*!< [31..2] Flash page pointer with updated OTA image                         */
6834     } OTAPOINTER_b;
6835   } ;
6836   __IM  uint32_t  RESERVED12[6];
6837 
6838   union {
6839     __IOM uint32_t APBDMACTRL;                  /*!< (@ 0x00000280) DMA Control Register. Determines misc settings
6840                                                                     for DMA operation                                          */
6841 
6842     struct {
6843       __IOM uint32_t DMA_ENABLE : 1;            /*!< [0..0] Enable the DMA controller. When disabled, DMA requests
6844                                                      will be ignored by the controller                                         */
6845       __IOM uint32_t DECODEABORT : 1;           /*!< [1..1] APB Decode Abort. When set, the APB bridge will issue
6846                                                      a data abort (bus fault) on transactions to peripherals
6847                                                      that are powered down. When set to 0, writes are quietly
6848                                                      discarded and reads return 0.                                             */
6849             uint32_t            : 6;
6850       __IOM uint32_t HYSTERESIS : 8;            /*!< [15..8] This field determines how long the DMA will remain active
6851                                                      during deep sleep before shutting down and returning the
6852                                                      system to full deep sleep. Values are based on a 94KHz
6853                                                      clock and are roughly 10 us increments for a range of ~10
6854                                                      us to 2.55 ms                                                             */
6855             uint32_t            : 16;
6856     } APBDMACTRL_b;
6857   } ;
6858 
6859   union {
6860     __IOM uint32_t SRAMMODE;                    /*!< (@ 0x00000284) SRAM Controller mode bits                                  */
6861 
6862     struct {
6863       __IOM uint32_t IPREFETCH  : 1;            /*!< [0..0] When set, instruction accesses to the SRAM banks will
6864                                                      be pre-fetched (normally 2 cycle read access). Generally,
6865                                                      this mode bit should be set for improved performance when
6866                                                      executing instructions from SRAM.                                         */
6867       __IOM uint32_t IPREFETCH_CACHE : 1;       /*!< [1..1] Secondary pre-fetch feature that will cache pre-fetched
6868                                                      data across bus wait states (requires IPREFETCH to be set).               */
6869             uint32_t            : 2;
6870       __IOM uint32_t DPREFETCH  : 1;            /*!< [4..4] When set, data bus accesses to the SRAM banks will be
6871                                                      pre-fetched (normally 2 cycle read access). Use of this
6872                                                      mode bit is only recommended if the work flow has a large
6873                                                      number of sequential accesses.                                            */
6874       __IOM uint32_t DPREFETCH_CACHE : 1;       /*!< [5..5] Secondary pre-fetch feature that will cache pre-fetched
6875                                                      data across bus wait states (requires DPREFETCH to be set).               */
6876             uint32_t            : 26;
6877     } SRAMMODE_b;
6878   } ;
6879   __IM  uint32_t  RESERVED13[48];
6880 
6881   union {
6882     __IOM uint32_t KEXTCLKSEL;                  /*!< (@ 0x00000348) Locks the state of the EXTCLKSEL register from
6883                                                                     writes. This is done to prevent errant writes
6884                                                                     to the register, as this could cause the
6885                                                                     chip to halt. Write a value of 0x53 to unlock
6886                                                                     write access to the EXTCLKSEL register.
6887                                                                     Once unlocked, the register will read back
6888                                                                     a 1 to indicate this is unlocked. Writing
6889                                                                     the register with any other value other
6890                                                                     than 0x53 will enable the lock.                            */
6891 
6892     struct {
6893       __IOM uint32_t KEXTCLKSEL : 32;           /*!< [31..0] Key register value.                                               */
6894     } KEXTCLKSEL_b;
6895   } ;
6896   __IM  uint32_t  RESERVED14;
6897 
6898   union {
6899     __IOM uint32_t SIMOBUCK1;                   /*!< (@ 0x00000350) SIMO Buck Control Reg 1                                    */
6900 
6901     struct {
6902       __IOM uint32_t COREACTIVETRIM : 10;       /*!< [9..0] simobuck_core_active_trim (VDDF)                                   */
6903       __IOM uint32_t SIMOBUCKCORELPTRIM : 6;    /*!< [15..10] simobuck_core_lp_trim                                            */
6904       __IOM uint32_t MEMACTIVETRIM : 6;         /*!< [21..16] simobuck_mem_active_trim (VDDC)                                  */
6905       __IOM uint32_t SIMOBUCKMEMLPTRIM : 6;     /*!< [27..22] simobuck_mem_lp_trim                                             */
6906       __IOM uint32_t CORETEMPCOTRIM : 4;        /*!< [31..28] simobuck_core_tempco_trim                                        */
6907     } SIMOBUCK1_b;
6908   } ;
6909 
6910   union {
6911     __IOM uint32_t SIMOBUCK2;                   /*!< (@ 0x00000354) SIMO Buck Control Reg 2                                    */
6912 
6913     struct {
6914       __IOM uint32_t SIMOBUCKTONGENTRIM : 5;    /*!< [4..0] simobuck_tongen_trim                                               */
6915       __IOM uint32_t RESERVED_RW_5 : 11;        /*!< [15..5] Reserved bits, always leave unchanged. The SIMOBUCK2
6916                                                      register must be modified via atomic RMW, leaving this
6917                                                      bit field completely unmodified. Failure to do so will
6918                                                      result in unpredictable behavior.                                         */
6919       __IOM uint32_t SIMOBUCKCORELPHIGHTONTRIM : 4;/*!< [19..16] simobuck_core_lp_high_ton_trim                                */
6920       __IOM uint32_t SIMOBUCKCORELPLOWTONTRIM : 4;/*!< [23..20] simobuck_core_lp_low_ton_trim                                  */
6921       __IOM uint32_t RESERVED_RW_24 : 4;        /*!< [27..24] Reserved bits, always leave unchanged. The SIMOBUCK2
6922                                                      register must be modified via atomic RMW, leaving this
6923                                                      bit field completely unmodified. Failure to do so will
6924                                                      result in unpredictable behavior.                                         */
6925       __IOM uint32_t SIMOBUCKCORELEAKAGETRIM : 2;/*!< [29..28] simobuck_core_leakage_trim                                      */
6926       __IOM uint32_t RESERVED_RW_30 : 2;        /*!< [31..30] Reserved bits, always leave unchanged. The SIMOBUCK2
6927                                                      register must be modified via atomic RMW, leaving this
6928                                                      bit field completely unmodified. Failure to do so will
6929                                                      result in unpredictable behavior.                                         */
6930     } SIMOBUCK2_b;
6931   } ;
6932 
6933   union {
6934     __IOM uint32_t SIMOBUCK3;                   /*!< (@ 0x00000358) SIMO Buck Control Reg 3                                    */
6935 
6936     struct {
6937       __IOM uint32_t SIMOBUCKCORELPHIGHTOFFTRIM : 4;/*!< [3..0] simobuck_core_lp_high_toff_trim                                */
6938       __IOM uint32_t SIMOBUCKCORELPLOWTOFFTRIM : 4;/*!< [7..4] simobuck_core_lp_low_toff_trim                                  */
6939       __IOM uint32_t SIMOBUCKMEMLPHIGHTOFFTRIM : 4;/*!< [11..8] simobuck_mem_lp_high_toff_trim                                 */
6940       __IOM uint32_t SIMOBUCKMEMLPLOWTOFFTRIM : 4;/*!< [15..12] simobuck_mem_lp_low_toff_trim                                  */
6941       __IOM uint32_t RESERVED_RW_16 : 11;       /*!< [26..16] Reserved bits, always leave unchanged. The SIMOBUCK3
6942                                                      register must be modified via atomic RMW, leaving this
6943                                                      bit field completely unmodified. Failure to do so will
6944                                                      result in unpredictable behavior.                                         */
6945       __IOM uint32_t SIMOBUCKMEMLPHIGHTONTRIM : 4;/*!< [30..27] simobuck_mem_lp_high_ton_trim                                  */
6946       __IOM uint32_t RESERVED_RW_31 : 1;        /*!< [31..31] Reserved bits, always leave unchanged. The SIMOBUCK2
6947                                                      register must be modified via atomic RMW, leaving this
6948                                                      bit field completely unmodified. Failure to do so will
6949                                                      result in unpredictable behavior.                                         */
6950     } SIMOBUCK3_b;
6951   } ;
6952 
6953   union {
6954     __IOM uint32_t SIMOBUCK4;                   /*!< (@ 0x0000035C) SIMO Buck Control Reg 4                                    */
6955 
6956     struct {
6957       __IOM uint32_t SIMOBUCKMEMLPLOWTONTRIM : 4;/*!< [3..0] simobuck_mem_lp_low_ton_trim                                      */
6958             uint32_t            : 17;
6959       __IOM uint32_t SIMOBUCKCLKDIVSEL : 2;     /*!< [22..21] simobuck_clkdiv_sel                                              */
6960       __IOM uint32_t SIMOBUCKCOMP2LPEN : 1;     /*!< [23..23] simobuck_comp2_lp_en                                             */
6961       __IOM uint32_t SIMOBUCKCOMP2TIMEOUTEN : 1;/*!< [24..24] simobuck_comp2_timeout_en                                        */
6962             uint32_t            : 7;
6963     } SIMOBUCK4_b;
6964   } ;
6965   __IM  uint32_t  RESERVED15[2];
6966 
6967   union {
6968     __IOM uint32_t BLEBUCK2;                    /*!< (@ 0x00000368) BLEBUCK2 Control Reg                                       */
6969 
6970     struct {
6971       __IOM uint32_t BLEBUCKTONLOWTRIM : 6;     /*!< [5..0] blebuck_ton_low_trim                                               */
6972       __IOM uint32_t BLEBUCKTONHITRIM : 6;      /*!< [11..6] blebuck_ton_hi_trim                                               */
6973       __IOM uint32_t BLEBUCKTOND2ATRIM : 6;     /*!< [17..12] blebuck_ton_trim                                                 */
6974             uint32_t            : 14;
6975     } BLEBUCK2_b;
6976   } ;
6977   __IM  uint32_t  RESERVED16[13];
6978 
6979   union {
6980     __IOM uint32_t FLASHWPROT0;                 /*!< (@ 0x000003A0) These bits write-protect flash in 16KB chunks.             */
6981 
6982     struct {
6983       __IOM uint32_t FW0BITS    : 32;           /*!< [31..0] Write protect flash 0x00000000 - 0x0007FFFF. Each bit
6984                                                      provides write protection for 16KB chunks of flash data
6985                                                      space. Bits are cleared by writing a 1 to the bit. When
6986                                                      read, 0 indicates the region is protected. Bits are sticky
6987                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
6988     } FLASHWPROT0_b;
6989   } ;
6990 
6991   union {
6992     __IOM uint32_t FLASHWPROT1;                 /*!< (@ 0x000003A4) These bits write-protect flash in 16KB chunks.             */
6993 
6994     struct {
6995       __IOM uint32_t FW1BITS    : 32;           /*!< [31..0] Write protect flash 0x00080000 - 0x000FFFFF. Each bit
6996                                                      provides write protection for 16KB chunks of flash data
6997                                                      space. Bits are cleared by writing a 1 to the bit. When
6998                                                      read, 0 indicates the region is protected. Bits are sticky
6999                                                      (can be set when PROTLOCK is 1, but only cleared by reset)                */
7000     } FLASHWPROT1_b;
7001   } ;
7002   __IM  uint32_t  RESERVED17[2];
7003 
7004   union {
7005     __IOM uint32_t FLASHRPROT0;                 /*!< (@ 0x000003B0) These bits read-protect flash in 16KB chunks.              */
7006 
7007     struct {
7008       __IOM uint32_t FR0BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00000000 - 0x0007FFFF. Each
7009                                                      bit provides read protection for 16KB chunks of flash.
7010                                                      Bits are cleared by writing a 1 to the bit. When read,
7011                                                      0 indicates the region is protected. Bits are sticky (can
7012                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
7013     } FLASHRPROT0_b;
7014   } ;
7015 
7016   union {
7017     __IOM uint32_t FLASHRPROT1;                 /*!< (@ 0x000003B4) These bits read-protect flash in 16KB chunks.              */
7018 
7019     struct {
7020       __IOM uint32_t FR1BITS    : 32;           /*!< [31..0] Copy (read) protect flash 0x00080000 - 0x000FFFFF. Each
7021                                                      bit provides read protection for 16KB chunks of flash.
7022                                                      Bits are cleared by writing a 1 to the bit. When read,
7023                                                      0 indicates the region is protected. Bits are sticky (can
7024                                                      be set when PROTLOCK is 1, but only cleared by reset)                     */
7025     } FLASHRPROT1_b;
7026   } ;
7027   __IM  uint32_t  RESERVED18[2];
7028 
7029   union {
7030     __IOM uint32_t DMASRAMWRITEPROTECT0;        /*!< (@ 0x000003C0) These bits write-protect system SRAM from DMA
7031                                                                     operations in 8KB chunks.                                  */
7032 
7033     struct {
7034       __IOM uint32_t DMA_WPROT0 : 32;           /*!< [31..0] Write protect SRAM from DMA. Each bit provides write
7035                                                      protection for an 8KB region of memory. When set to 1,
7036                                                      the region will be protected from DMA writes, when set
7037                                                      to 0, DMA may write the region.                                           */
7038     } DMASRAMWRITEPROTECT0_b;
7039   } ;
7040 
7041   union {
7042     __IOM uint32_t DMASRAMWRITEPROTECT1;        /*!< (@ 0x000003C4) These bits write-protect system SRAM from DMA
7043                                                                     operations in 8KB chunks.                                  */
7044 
7045     struct {
7046       __IOM uint32_t DMA_WPROT1 : 16;           /*!< [15..0] Write protect SRAM from DMA. Each bit provides write
7047                                                      protection for an 8KB region of memory. When set to 1,
7048                                                      the region will be protected from DMA writes, when set
7049                                                      to 0, DMA may write the region.                                           */
7050             uint32_t            : 16;
7051     } DMASRAMWRITEPROTECT1_b;
7052   } ;
7053   __IM  uint32_t  RESERVED19[2];
7054 
7055   union {
7056     __IOM uint32_t DMASRAMREADPROTECT0;         /*!< (@ 0x000003D0) These bits read-protect system SRAM from DMA
7057                                                                     operations in 8KB chunks.                                  */
7058 
7059     struct {
7060       __IOM uint32_t DMA_RPROT0 : 32;           /*!< [31..0] Read protect SRAM from DMA. Each bit provides write
7061                                                      protection for an 8KB region of memory. When set to 1,
7062                                                      the region will be protected from DMA reads, when set to
7063                                                      0, DMA may read the region.                                               */
7064     } DMASRAMREADPROTECT0_b;
7065   } ;
7066 
7067   union {
7068     __IOM uint32_t DMASRAMREADPROTECT1;         /*!< (@ 0x000003D4) These bits read-protect system SRAM from DMA
7069                                                                     operations in 8KB chunks.                                  */
7070 
7071     struct {
7072       __IOM uint32_t DMA_RPROT1 : 16;           /*!< [15..0] Read protect SRAM from DMA. Each bit provides write
7073                                                      protection for an 8KB region of memory. When set to 1,
7074                                                      the region will be protected from DMA reads, when set to
7075                                                      0, DMA may read the region.                                               */
7076             uint32_t            : 16;
7077     } DMASRAMREADPROTECT1_b;
7078   } ;
7079 } MCUCTRL_Type;                                 /*!< Size = 984 (0x3d8)                                                        */
7080 
7081 
7082 
7083 /* =========================================================================================================================== */
7084 /* ================                                           MSPI                                            ================ */
7085 /* =========================================================================================================================== */
7086 
7087 
7088 /**
7089   * @brief Multi-bit SPI Master (MSPI)
7090   */
7091 
7092 typedef struct {                                /*!< (@ 0x50014000) MSPI Structure                                             */
7093 
7094   union {
7095     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) This register is used to enable individual PIO
7096                                                                     based transactions to a device on the bus.
7097                                                                     The CFG register must be programmed properly
7098                                                                     for the transfer, and the ADDR and INSTR
7099                                                                     registers should be programmed if the SENDI
7100                                                                     and SENDA fields are enabled.                              */
7101 
7102     struct {
7103       __IOM uint32_t START      : 1;            /*!< [0..0] Write to 1 to initiate a PIO transaction on the bus (typically
7104                                                      the entire register should be written at once with this
7105                                                      bit set).                                                                 */
7106       __IOM uint32_t STATUS     : 1;            /*!< [1..1] Command status: 1 indicates command has completed. Cleared
7107                                                      by writing 1 to this bit or starting a new transfer.                      */
7108       __IOM uint32_t BUSY       : 1;            /*!< [2..2] Command status: 1 indicates controller is busy (command
7109                                                      in progress)                                                              */
7110       __IOM uint32_t QUADCMD    : 1;            /*!< [3..3] Flag indicating that the operation is a command that
7111                                                      should be replicated to both devices in paired QUAD mode.
7112                                                      This is typically only used when reading/writing configuration
7113                                                      registers in paired flash devices (do not set for memory
7114                                                      transfers).                                                               */
7115             uint32_t            : 2;
7116       __IOM uint32_t BIGENDIAN  : 1;            /*!< [6..6] 1 indicates data in FIFO is in big endian format (MSB
7117                                                      first); 0 indicates little endian data (default, LSB first).              */
7118       __IOM uint32_t ENTURN     : 1;            /*!< [7..7] Indicates whether TX->RX turnaround cycles should be
7119                                                      enabled for this operation (see TURNAROUND field in CFG
7120                                                      register).                                                                */
7121       __IOM uint32_t SENDA      : 1;            /*!< [8..8] Indicates whether an address phase should be sent (see
7122                                                      ADDR register and ASIZE field in CFG register)                            */
7123       __IOM uint32_t SENDI      : 1;            /*!< [9..9] Indicates whether an instruction phase should be sent
7124                                                      (see INSTR field and ISIZE field in CFG register)                         */
7125       __IOM uint32_t TXRX       : 1;            /*!< [10..10] 1 Indicates a TX operation, 0 indicates an RX operation
7126                                                      of XFERBYTES                                                              */
7127       __IOM uint32_t PIOSCRAMBLE : 1;           /*!< [11..11] Enables data scrambling for PIO operations. This should
7128                                                      only be used for data operations and never for commands
7129                                                      to a device.                                                              */
7130             uint32_t            : 4;
7131       __IOM uint32_t XFERBYTES  : 16;           /*!< [31..16] Number of bytes to transmit or receive (based on TXRX
7132                                                      bit)                                                                      */
7133     } CTRL_b;
7134   } ;
7135 
7136   union {
7137     __IOM uint32_t CFG;                         /*!< (@ 0x00000004) Command formatting for PIO based transactions
7138                                                                     (initiated by writes to CTRL register)                     */
7139 
7140     struct {
7141       __IOM uint32_t DEVCFG     : 4;            /*!< [3..0] Flash configuration for XIP and AUTO DMA operations.
7142                                                      Controls value for SER (Slave Enable) for XIP operations
7143                                                      and address generation for DMA/XIP modes. Also used to
7144                                                      configure SPIFRF (frame format).                                          */
7145       __IOM uint32_t ASIZE      : 2;            /*!< [5..4] Address Size. Address bytes to send from ADDR register             */
7146       __IOM uint32_t ISIZE      : 1;            /*!< [6..6] Instruction Sizeenum name = I8 value = 0x0 desc = Instruction
7147                                                      is 1 byteenum name = I16 value = 0x1 desc = Instruction
7148                                                      is 2 bytes                                                                */
7149       __IOM uint32_t SEPIO      : 1;            /*!< [7..7] Separate IO configuration. This bit should be set when
7150                                                      the target device has separate MOSI and MISO pins. Respective
7151                                                      IN/OUT bits below should be set to map pins.                              */
7152       __IOM uint32_t TURNAROUND : 6;            /*!< [13..8] Number of turnaround cycles (for TX->RX transitions).
7153                                                      Qualified by ENTURN or XIPENTURN bit field.                               */
7154             uint32_t            : 2;
7155       __IOM uint32_t CPHA       : 1;            /*!< [16..16] Serial clock phase.                                              */
7156       __IOM uint32_t CPOL       : 1;            /*!< [17..17] Serial clock polarity.                                           */
7157             uint32_t            : 14;
7158     } CFG_b;
7159   } ;
7160 
7161   union {
7162     __IOM uint32_t ADDR;                        /*!< (@ 0x00000008) Optional Address field to send for PIO transfers           */
7163 
7164     struct {
7165       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Optional Address field to send (after optional instruction
7166                                                      field) - qualified by ASIZE in CMD register. NOTE: This
7167                                                      register is aliased to DMADEVADDR.                                        */
7168     } ADDR_b;
7169   } ;
7170 
7171   union {
7172     __IOM uint32_t INSTR;                       /*!< (@ 0x0000000C) Optional Instruction field to send for PIO transfers       */
7173 
7174     struct {
7175       __IOM uint32_t INSTR      : 16;           /*!< [15..0] Optional Instruction field to send (1st byte) - qualified
7176                                                      by ISEND/ISIZE                                                            */
7177             uint32_t            : 16;
7178     } INSTR_b;
7179   } ;
7180 
7181   union {
7182     __IOM uint32_t TXFIFO;                      /*!< (@ 0x00000010) TX Data FIFO                                               */
7183 
7184     struct {
7185       __IOM uint32_t TXFIFO     : 32;           /*!< [31..0] Data to be transmitted. Data should normally be aligned
7186                                                      to the LSB (pad the upper bits with zeros) unless BIGENDIAN
7187                                                      is set.                                                                   */
7188     } TXFIFO_b;
7189   } ;
7190 
7191   union {
7192     __IOM uint32_t RXFIFO;                      /*!< (@ 0x00000014) RX Data FIFO                                               */
7193 
7194     struct {
7195       __IOM uint32_t RXFIFO     : 32;           /*!< [31..0] Receive data. Data is aligned to the LSB (padded zeros
7196                                                      on upper bits) unless BIGENDIAN is set.                                   */
7197     } RXFIFO_b;
7198   } ;
7199 
7200   union {
7201     __IOM uint32_t TXENTRIES;                   /*!< (@ 0x00000018) Number of words in TX FIFO                                 */
7202 
7203     struct {
7204       __IOM uint32_t TXENTRIES  : 5;            /*!< [4..0] Number of 32-bit words/entries in TX FIFO                          */
7205             uint32_t            : 27;
7206     } TXENTRIES_b;
7207   } ;
7208 
7209   union {
7210     __IOM uint32_t RXENTRIES;                   /*!< (@ 0x0000001C) Number of words in RX FIFO                                 */
7211 
7212     struct {
7213       __IOM uint32_t RXENTRIES  : 5;            /*!< [4..0] Number of 32-bit words/entries in RX FIFO                          */
7214             uint32_t            : 27;
7215     } RXENTRIES_b;
7216   } ;
7217 
7218   union {
7219     __IOM uint32_t THRESHOLD;                   /*!< (@ 0x00000020) Threshold levels that trigger RXFull and TXEmpty
7220                                                                     interrupts                                                 */
7221 
7222     struct {
7223       __IOM uint32_t TXTHRESH   : 5;            /*!< [4..0] Number of entries in TX FIFO that cause TXF interrupt              */
7224             uint32_t            : 3;
7225       __IOM uint32_t RXTHRESH   : 5;            /*!< [12..8] Number of entries in TX FIFO that cause RXE interrupt             */
7226             uint32_t            : 19;
7227     } THRESHOLD_b;
7228   } ;
7229   __IM  uint32_t  RESERVED[55];
7230 
7231   union {
7232     __IOM uint32_t MSPICFG;                     /*!< (@ 0x00000100) Timing configuration bits for the MSPI module.
7233                                                                     PRSTN, IPRSTN, and FIFORESET can be used
7234                                                                     to reset portions of the MSPI interface
7235                                                                     in order to clear error conditions. The
7236                                                                     remaining bits control clock frequency and
7237                                                                     TX/RX capture timings.                                     */
7238 
7239     struct {
7240       __IOM uint32_t APBCLK     : 1;            /*!< [0..0] Enable continuous APB clock. For power-efficient operation,
7241                                                      APBCLK should be set to 0.                                                */
7242       __IOM uint32_t RXCAP      : 1;            /*!< [1..1] Controls RX data capture phase. A setting of 0 (NORMAL)
7243                                                      captures read data at the normal capture point relative
7244                                                      to the internal clock launch point. However, to accommodate
7245                                                      chip/pad/board delays, a setting of RXCAP of 1 is expected
7246                                                      to be used to align the capture point with the return data
7247                                                      window. This bit is used in conjunction with RXNEG to provide
7248                                                      4 unique capture points, all about 10 ns apart.                           */
7249       __IOM uint32_t RXNEG      : 1;            /*!< [2..2] Adjusts the RX capture phase to the negedge of the 48MHz
7250                                                      internal clock (~10 ns early). For normal operation, it
7251                                                      is expected that RXNEG will be set to 0.                                  */
7252       __IOM uint32_t TXNEG      : 1;            /*!< [3..3] Launches TX data a half clock cycle (~10 ns) early. This
7253                                                      should normally be programmed to zero (NORMAL).                           */
7254       __IOM uint32_t IOMSEL     : 3;            /*!< [6..4] Selects which IOM is selected for CQ handshake status.             */
7255             uint32_t            : 1;
7256       __IOM uint32_t CLKDIV     : 6;            /*!< [13..8] Clock Divider. Allows dividing 48 MHz base clock by
7257                                                      integer multiples. Enumerations are provided for common
7258                                                      frequency, but any integer divide from 48 MHz is allowed.
7259                                                      Odd divide ratios will result in a 33/66 percent duty cycle
7260                                                      with a long low clock pulse (to allow longer round-trip
7261                                                      for read data).                                                           */
7262             uint32_t            : 15;
7263       __IOM uint32_t FIFORESET  : 1;            /*!< [29..29] Reset MSPI FIFO (active high). 1=reset FIFO, 0=normal
7264                                                      operation. May be used to manually flush the FIFO in error
7265                                                      handling.                                                                 */
7266       __IOM uint32_t IPRSTN     : 1;            /*!< [30..30] IP block reset. Write to 0 to put the transfer module
7267                                                      in reset or 1 for normal operation. This may be required
7268                                                      after error conditions to clear the transfer on the bus.                  */
7269       __IOM uint32_t PRSTN      : 1;            /*!< [31..31] Peripheral reset. Master reset to the entire MSPI module
7270                                                      (DMA, XIP, and transfer state machines). 1=normal operation,
7271                                                      0=in reset.                                                               */
7272     } MSPICFG_b;
7273   } ;
7274 
7275   union {
7276     __IOM uint32_t PADCFG;                      /*!< (@ 0x00000104) Configuration bits for the MSPI pads. Allows
7277                                                                     pads associated with the upper quad to be
7278                                                                     mapped to corresponding bits on the lower
7279                                                                     quad. Use of Quad0 pins is recommended for
7280                                                                     optimal timing.                                            */
7281 
7282     struct {
7283       __IOM uint32_t OUT3       : 1;            /*!< [0..0] Output pad 3 configuration. 0=data[3] 1=CLK                        */
7284       __IOM uint32_t OUT4       : 1;            /*!< [1..1] Output pad 4 configuration. 0=data[4] 1=data[0]                    */
7285       __IOM uint32_t OUT5       : 1;            /*!< [2..2] Output pad 5 configuration. 0=data[5] 1=data[1]                    */
7286       __IOM uint32_t OUT6       : 1;            /*!< [3..3] Output pad 6 configuration. 0=data[6] 1=data[2]                    */
7287       __IOM uint32_t OUT7       : 1;            /*!< [4..4] Output pad 7 configuration. 0=data[7] 1=data[3]                    */
7288             uint32_t            : 11;
7289       __IOM uint32_t IN0        : 2;            /*!< [17..16] Data Input pad 0 pin muxing: 0=pad[0] 1=pad[4] 2=pad[1]
7290                                                      3=pad[5]                                                                  */
7291       __IOM uint32_t IN1        : 1;            /*!< [18..18] Data Input pad 1 pin muxing: 0=pad[1] 1=pad[5]                   */
7292       __IOM uint32_t IN2        : 1;            /*!< [19..19] Data Input pad 2 pin muxing: 0=pad[2] 1=pad[6]                   */
7293       __IOM uint32_t IN3        : 1;            /*!< [20..20] Data Input pad 3 pin muxing: 0=pad[3] 1=pad[7]                   */
7294       __IOM uint32_t REVCS      : 1;            /*!< [21..21] Reverse CS connections. Allows CS1 to be associated
7295                                                      with lower data lanes and CS0 to be associated with upper
7296                                                      data lines                                                                */
7297             uint32_t            : 10;
7298     } PADCFG_b;
7299   } ;
7300 
7301   union {
7302     __IOM uint32_t PADOUTEN;                    /*!< (@ 0x00000108) Enable bits for the MSPI output pads. Each active
7303                                                                     MSPI line should be set to 1 in the OUTEN
7304                                                                     field below.                                               */
7305 
7306     struct {
7307       __IOM uint32_t OUTEN      : 9;            /*!< [8..0] Output pad enable configuration. Indicates which pads
7308                                                      should be driven. Bits [3:0] are Quad0 data, [7:4] are
7309                                                      Quad1 data, and [8] is clock.                                             */
7310             uint32_t            : 23;
7311     } PADOUTEN_b;
7312   } ;
7313 
7314   union {
7315     __IOM uint32_t FLASH;                       /*!< (@ 0x0000010C) When any SPI flash is configured, this register
7316                                                                     must be properly programmed before XIP or
7317                                                                     AUTO DMA operations commence.                              */
7318 
7319     struct {
7320       __IOM uint32_t XIPEN      : 1;            /*!< [0..0] Enable the XIP (eXecute In Place) function which effectively
7321                                                      enables the address decoding of the MSPI device in the
7322                                                      flash/cache address space at address 0x04000000-0x07FFFFFF.               */
7323             uint32_t            : 1;
7324       __IOM uint32_t XIPACK     : 2;            /*!< [3..2] Controls transmission of Micron XIP acknowledge cycles
7325                                                      (Micron Flash devices only)                                               */
7326       __IOM uint32_t XIPBIGENDIAN : 1;          /*!< [4..4] Indicates whether XIP/AUTO DMA data transfers are in
7327                                                      big or little endian format                                               */
7328       __IOM uint32_t XIPENTURN  : 1;            /*!< [5..5] Indicates whether XIP/AUTO DMA operations should enable
7329                                                      TX->RX turnaround cycles                                                  */
7330       __IOM uint32_t XIPSENDA   : 1;            /*!< [6..6] Indicates whether XIP/AUTO DMA operations should send
7331                                                      an an address phase (see DMADEVADDR register and ASIZE
7332                                                      field in CFG)                                                             */
7333       __IOM uint32_t XIPSENDI   : 1;            /*!< [7..7] Indicates whether XIP/AUTO DMA operations should send
7334                                                      an instruction (see READINSTR field and ISIZE field in
7335                                                      CFG)                                                                      */
7336       __IOM uint32_t XIPMIXED   : 3;            /*!< [10..8] Provides override controls for data operations where
7337                                                      instruction, address, and data may transfer in different
7338                                                      rates.                                                                    */
7339             uint32_t            : 5;
7340       __IOM uint32_t WRITEINSTR : 8;            /*!< [23..16] Write command sent for DMA operations                            */
7341       __IOM uint32_t READINSTR  : 8;            /*!< [31..24] Read command sent to flash for DMA/XIP operations                */
7342     } FLASH_b;
7343   } ;
7344   __IM  uint32_t  RESERVED1[4];
7345 
7346   union {
7347     __IOM uint32_t SCRAMBLING;                  /*!< (@ 0x00000120) Enables data scrambling for the specified range
7348                                                                     external flash addresses. Scrambling does
7349                                                                     not impact flash access performance.                       */
7350 
7351     struct {
7352       __IOM uint32_t SCRSTART   : 10;           /*!< [9..0] Scrambling region start address [25:16] (64K block granularity).
7353                                                      The START block is the FIRST block included in the scrambled
7354                                                      address range.                                                            */
7355             uint32_t            : 6;
7356       __IOM uint32_t SCREND     : 10;           /*!< [25..16] Scrambling region end address [25:16] (64K block granularity).
7357                                                      The END block is the LAST block included in the scrambled
7358                                                      address range.                                                            */
7359             uint32_t            : 5;
7360       __IOM uint32_t SCRENABLE  : 1;            /*!< [31..31] Enables Data Scrambling Region. When 1 reads and writes
7361                                                      to the range will be scrambled. When 0, data will be read/written
7362                                                      unmodified. Address range is specified in 64K granularity
7363                                                      and the START/END ranges are included within the range.                   */
7364     } SCRAMBLING_b;
7365   } ;
7366   __IM  uint32_t  RESERVED2[55];
7367 
7368   union {
7369     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
7370                                                                     to generate the corresponding interrupt.                   */
7371 
7372     struct {
7373       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
7374                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
7375       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
7376       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
7377                                                      a full FIFO).                                                             */
7378       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
7379                                                      an empty FIFO)                                                            */
7380       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
7381                                                      MSPI bus pins will stall)                                                 */
7382       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
7383       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
7384       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
7385       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
7386       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
7387                                                      performs an operation where address bit[0] is set. Useful
7388                                                      for triggering CURIDX interrupts.                                         */
7389       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
7390       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
7391       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
7392                                                      be aligned to word (4-byte) start address.                                */
7393             uint32_t            : 19;
7394     } INTEN_b;
7395   } ;
7396 
7397   union {
7398     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
7399                                                                     cause of a recent interrupt.                               */
7400 
7401     struct {
7402       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
7403                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
7404       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
7405       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
7406                                                      a full FIFO).                                                             */
7407       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
7408                                                      an empty FIFO)                                                            */
7409       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
7410                                                      MSPI bus pins will stall)                                                 */
7411       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
7412       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
7413       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
7414       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
7415       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
7416                                                      performs an operation where address bit[0] is set. Useful
7417                                                      for triggering CURIDX interrupts.                                         */
7418       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
7419       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
7420       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
7421                                                      be aligned to word (4-byte) start address.                                */
7422             uint32_t            : 19;
7423     } INTSTAT_b;
7424   } ;
7425 
7426   union {
7427     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
7428                                                                     the interrupt status associated with that
7429                                                                     bit.                                                       */
7430 
7431     struct {
7432       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
7433                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
7434       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
7435       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
7436                                                      a full FIFO).                                                             */
7437       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
7438                                                      an empty FIFO)                                                            */
7439       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
7440                                                      MSPI bus pins will stall)                                                 */
7441       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
7442       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
7443       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
7444       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
7445       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
7446                                                      performs an operation where address bit[0] is set. Useful
7447                                                      for triggering CURIDX interrupts.                                         */
7448       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
7449       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
7450       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
7451                                                      be aligned to word (4-byte) start address.                                */
7452             uint32_t            : 19;
7453     } INTCLR_b;
7454   } ;
7455 
7456   union {
7457     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
7458                                                                     generate an interrupt from this module.
7459                                                                     (Generally used for testing purposes).                     */
7460 
7461     struct {
7462       __IOM uint32_t CMDCMP     : 1;            /*!< [0..0] Transfer complete. Note that DMA and CQ operations are
7463                                                      layered, so CMDCMP, DCMP, and CQ* can all be signaled simultaneously.     */
7464       __IOM uint32_t TXE        : 1;            /*!< [1..1] Transmit FIFO empty.                                               */
7465       __IOM uint32_t TXO        : 1;            /*!< [2..2] Transmit FIFO Overflow (only occurs when SW writes to
7466                                                      a full FIFO).                                                             */
7467       __IOM uint32_t RXU        : 1;            /*!< [3..3] Receive FIFO underflow (only occurs when SW reads from
7468                                                      an empty FIFO)                                                            */
7469       __IOM uint32_t RXO        : 1;            /*!< [4..4] Receive FIFO overflow (cannot happen in MSPI design --
7470                                                      MSPI bus pins will stall)                                                 */
7471       __IOM uint32_t RXF        : 1;            /*!< [5..5] Receive FIFO full                                                  */
7472       __IOM uint32_t DCMP       : 1;            /*!< [6..6] DMA Complete Interrupt                                             */
7473       __IOM uint32_t DERR       : 1;            /*!< [7..7] DMA Error Interrupt                                                */
7474       __IOM uint32_t CQCMP      : 1;            /*!< [8..8] Command Queue Complete Interrupt                                   */
7475       __IOM uint32_t CQUPD      : 1;            /*!< [9..9] Command Queue Update Interrupt. Issued whenever the CQ
7476                                                      performs an operation where address bit[0] is set. Useful
7477                                                      for triggering CURIDX interrupts.                                         */
7478       __IOM uint32_t CQPAUSED   : 1;            /*!< [10..10] Command Queue is Paused.                                         */
7479       __IOM uint32_t CQERR      : 1;            /*!< [11..11] Command Queue Error Interrupt                                    */
7480       __IOM uint32_t SCRERR     : 1;            /*!< [12..12] Scrambling Alignment Error. Scrambling operations must
7481                                                      be aligned to word (4-byte) start address.                                */
7482             uint32_t            : 19;
7483     } INTSET_b;
7484   } ;
7485   __IM  uint32_t  RESERVED3[16];
7486 
7487   union {
7488     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000250) DMA Configuration                                          */
7489 
7490     struct {
7491       __IOM uint32_t DMAEN      : 2;            /*!< [1..0] DMA Enable. Setting this bit to EN will start the DMA
7492                                                      operation                                                                 */
7493       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
7494       __IOM uint32_t DMAPRI     : 2;            /*!< [4..3] Sets the Priority of the DMA request                               */
7495             uint32_t            : 13;
7496       __IOM uint32_t DMAPWROFF  : 1;            /*!< [18..18] Power off MSPI domain upon completion of DMA operation.          */
7497             uint32_t            : 13;
7498     } DMACFG_b;
7499   } ;
7500 
7501   union {
7502     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000254) DMA Status                                                 */
7503 
7504     struct {
7505       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress indicator. 1 will indicate that
7506                                                      a DMA transfer is active. The DMA transfer may be waiting
7507                                                      on data, transferring data, or waiting for priority. All
7508                                                      of these will be indicated with a 1. A 0 will indicate
7509                                                      that the DMA is fully complete and no further transactions
7510                                                      will be done.                                                             */
7511       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete. This signals the end of the DMA
7512                                                      operation.                                                                */
7513       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error. This active high bit signals that an error
7514                                                      was encountered during the DMA operation.                                 */
7515       __IOM uint32_t SCRERR     : 1;            /*!< [3..3] Scrambling Access Alignment Error. This active high bit
7516                                                      signals that a scrambling operation was specified for a
7517                                                      non-word aligned DEVADDR.                                                 */
7518             uint32_t            : 28;
7519     } DMASTAT_b;
7520   } ;
7521 
7522   union {
7523     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x00000258) DMA Target Address                                         */
7524 
7525     struct {
7526       __IOM uint32_t TARGADDR   : 32;           /*!< [31..0] Target byte address for source of DMA (either read or
7527                                                      write). In cases of non-word aligned addresses, the DMA
7528                                                      logic will take care for ensuring only the target bytes
7529                                                      are read/written.                                                         */
7530     } DMATARGADDR_b;
7531   } ;
7532 
7533   union {
7534     __IOM uint32_t DMADEVADDR;                  /*!< (@ 0x0000025C) DMA Device Address                                         */
7535 
7536     struct {
7537       __IOM uint32_t DEVADDR    : 32;           /*!< [31..0] SPI Device address for automated DMA transactions (both
7538                                                      read and write).                                                          */
7539     } DMADEVADDR_b;
7540   } ;
7541 
7542   union {
7543     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000260) DMA Total Transfer Count                                   */
7544 
7545     struct {
7546       __IOM uint32_t TOTCOUNT   : 16;           /*!< [15..0] Total Transfer Count in bytes.                                    */
7547             uint32_t            : 16;
7548     } DMATOTCOUNT_b;
7549   } ;
7550 
7551   union {
7552     __IOM uint32_t DMABCOUNT;                   /*!< (@ 0x00000264) DMA BYTE Transfer Count                                    */
7553 
7554     struct {
7555       __IOM uint32_t BCOUNT     : 8;            /*!< [7..0] Burst transfer size in bytes. This is the number of bytes
7556                                                      transferred when a FIFO trigger event occurs. Recommended
7557                                                      values are 16 or 32.                                                      */
7558             uint32_t            : 24;
7559     } DMABCOUNT_b;
7560   } ;
7561   __IM  uint32_t  RESERVED4[4];
7562 
7563   union {
7564     __IOM uint32_t DMATHRESH;                   /*!< (@ 0x00000278) Indicates FIFO level at which a DMA should be
7565                                                                     triggered. For most configurations, a setting
7566                                                                     of 8 is recommended for both read and write
7567                                                                     operations.                                                */
7568 
7569     struct {
7570       __IOM uint32_t DMATHRESH  : 4;            /*!< [3..0] DMA transfer FIFO level trigger. For read operations,
7571                                                      DMA is triggered when the FIFO level is greater than this
7572                                                      value. For write operations, DMA is triggered when the
7573                                                      FIFO level is less than this level. Each DMA operation
7574                                                      will consist of BCOUNT bytes.                                             */
7575             uint32_t            : 28;
7576     } DMATHRESH_b;
7577   } ;
7578   __IM  uint32_t  RESERVED5[9];
7579 
7580   union {
7581     __IOM uint32_t CQCFG;                       /*!< (@ 0x000002A0) This register controls Command Queuing (CQ) operations
7582                                                                     in a manner similar to the DMACFG register.                */
7583 
7584     struct {
7585       __IOM uint32_t CQEN       : 1;            /*!< [0..0] Command queue enable. When set, will enable the processing
7586                                                      of the command queue                                                      */
7587       __IOM uint32_t CQPRI      : 1;            /*!< [1..1] Sets the Priority of the command queue DMA request                 */
7588       __IOM uint32_t CQPWROFF   : 1;            /*!< [2..2] Power off MSPI domain upon completion of DMA operation.            */
7589       __IOM uint32_t CQAUTOCLEARMASK : 1;       /*!< [3..3] Enable clear of CQMASK after each pause operation. This
7590                                                      may be useful when using software flags to pause CQ.                      */
7591             uint32_t            : 28;
7592     } CQCFG_b;
7593   } ;
7594   __IM  uint32_t  RESERVED6;
7595 
7596   union {
7597     __IOM uint32_t CQADDR;                      /*!< (@ 0x000002A8) Location of the command queue in SRAM or flash
7598                                                                     memory. This register will increment as
7599                                                                     CQ operations commence. Software should
7600                                                                     only write CQADDR when CQEN is disabled,
7601                                                                     however the command queue script itself
7602                                                                     may update CQADDR in order to perform queue
7603                                                                     management functions (like resetting the
7604                                                                     pointers)                                                  */
7605 
7606     struct {
7607       __IOM uint32_t CQADDR     : 29;           /*!< [28..0] Address of command queue buffer in SRAM or flash. The
7608                                                      buffer address must be aligned to a word boundary.                        */
7609             uint32_t            : 3;
7610     } CQADDR_b;
7611   } ;
7612 
7613   union {
7614     __IOM uint32_t CQSTAT;                      /*!< (@ 0x000002AC) Command Queue Status                                       */
7615 
7616     struct {
7617       __IOM uint32_t CQTIP      : 1;            /*!< [0..0] Command queue Transfer In Progress indicator. 1 will
7618                                                      indicate that a CQ transfer is active and this will remain
7619                                                      active even when paused waiting for external event.                       */
7620       __IOM uint32_t CQCPL      : 1;            /*!< [1..1] Command queue operation Complete. This signals the end
7621                                                      of the command queue operation.                                           */
7622       __IOM uint32_t CQERR      : 1;            /*!< [2..2] Command queue processing Error. This active high bit
7623                                                      signals that an error was encountered during the CQ operation.            */
7624       __IOM uint32_t CQPAUSED   : 1;            /*!< [3..3] Command queue is currently paused status.                          */
7625             uint32_t            : 28;
7626     } CQSTAT_b;
7627   } ;
7628 
7629   union {
7630     __IOM uint32_t CQFLAGS;                     /*!< (@ 0x000002B0) Command Queue Flags                                        */
7631 
7632     struct {
7633       __IOM uint32_t CQFLAGS    : 16;           /*!< [15..0] Current flag status (read-only). Bits [7:0] are software
7634                                                      controllable and bits [15:8] are hardware status.                         */
7635             uint32_t            : 16;
7636     } CQFLAGS_b;
7637   } ;
7638 
7639   union {
7640     __IOM uint32_t CQSETCLEAR;                  /*!< (@ 0x000002B4) Command Queue Flag Set/Clear                               */
7641 
7642     struct {
7643       __IOM uint32_t CQFSET     : 8;            /*!< [7..0] Set CQFlag status bits. Set has priority over clear if
7644                                                      both are high.                                                            */
7645       __IOM uint32_t CQFTOGGLE  : 8;            /*!< [15..8] Toggle CQFlag status bits                                         */
7646       __IOM uint32_t CQFCLR     : 8;            /*!< [23..16] Clear CQFlag status bits.                                        */
7647             uint32_t            : 8;
7648     } CQSETCLEAR_b;
7649   } ;
7650 
7651   union {
7652     __IOM uint32_t CQPAUSE;                     /*!< (@ 0x000002B8) Command Queue Pause Mask                                   */
7653 
7654     struct {
7655       __IOM uint32_t CQMASK     : 16;           /*!< [15..0] CQ will pause processing when ALL specified events are
7656                                                      satisfied -- i.e. when (CQMASK and CQPAUSE)==CQMASK.                      */
7657             uint32_t            : 16;
7658     } CQPAUSE_b;
7659   } ;
7660   __IM  uint32_t  RESERVED7;
7661 
7662   union {
7663     __IOM uint32_t CQCURIDX;                    /*!< (@ 0x000002C0) This register can be used in conjunction with
7664                                                                     the CQENDIDX register to manage the command
7665                                                                     queue. Typically software will initialize
7666                                                                     the CQCURIDX and CQENDIDX to the same value,
7667                                                                     which will cause the CQ to be paused when
7668                                                                     enabled. Software may then add entries to
7669                                                                     the command queue (in SRAM) and update CQENDIDX.
7670                                                                     The command queue operations will then increment
7671                                                                     CQCURIDX as it processes operations. Once
7672                                                                     CQCURIDX==CQENDIDX, the command queue hardware
7673                                                                     will automatically pause since no additional
7674                                                                     ope                                                        */
7675 
7676     struct {
7677       __IOM uint32_t CQCURIDX   : 8;            /*!< [7..0] Can be used to indicate the current position of the command
7678                                                      queue by having CQ operations write this field. A CQ hardware
7679                                                      status flag indicates when CURIDX and ENDIDX are not equal,
7680                                                      allowing SW to pause the CQ processing until the end index
7681                                                      is updated.                                                               */
7682             uint32_t            : 24;
7683     } CQCURIDX_b;
7684   } ;
7685 
7686   union {
7687     __IOM uint32_t CQENDIDX;                    /*!< (@ 0x000002C4) Command Queue End Index                                    */
7688 
7689     struct {
7690       __IOM uint32_t CQENDIDX   : 8;            /*!< [7..0] Can be used to indicate the end position of the command
7691                                                      queue. A CQ hardware status bit indices when CURIDX !=
7692                                                      ENDIDX so that the CQ can be paused when it reaches the
7693                                                      end pointer.                                                              */
7694             uint32_t            : 24;
7695     } CQENDIDX_b;
7696   } ;
7697 } MSPI_Type;                                    /*!< Size = 712 (0x2c8)                                                        */
7698 
7699 
7700 
7701 /* =========================================================================================================================== */
7702 /* ================                                            PDM                                            ================ */
7703 /* =========================================================================================================================== */
7704 
7705 
7706 /**
7707   * @brief PDM Audio (PDM)
7708   */
7709 
7710 typedef struct {                                /*!< (@ 0x50011000) PDM Structure                                              */
7711 
7712   union {
7713     __IOM uint32_t PCFG;                        /*!< (@ 0x00000000) PDM Configuration                                          */
7714 
7715     struct {
7716       __IOM uint32_t PDMCOREEN  : 1;            /*!< [0..0] Data Streaming Control.                                            */
7717       __IOM uint32_t SOFTMUTE   : 1;            /*!< [1..1] Soft mute control.                                                 */
7718       __IOM uint32_t CYCLES     : 3;            /*!< [4..2] Number of clocks during gain-setting changes.                      */
7719       __IOM uint32_t HPCUTOFF   : 4;            /*!< [8..5] High pass filter coefficients.                                     */
7720       __IOM uint32_t ADCHPD     : 1;            /*!< [9..9] High pass filter control.                                          */
7721       __IOM uint32_t SINCRATE   : 7;            /*!< [16..10] SINC decimation rate.                                            */
7722       __IOM uint32_t MCLKDIV    : 2;            /*!< [18..17] PDM_CLK frequency divisor.                                       */
7723             uint32_t            : 2;
7724       __IOM uint32_t PGALEFT    : 5;            /*!< [25..21] Left channel PGA gain.                                           */
7725       __IOM uint32_t PGARIGHT   : 5;            /*!< [30..26] Right channel PGA gain.                                          */
7726       __IOM uint32_t LRSWAP     : 1;            /*!< [31..31] Left/right channel swap.                                         */
7727     } PCFG_b;
7728   } ;
7729 
7730   union {
7731     __IOM uint32_t VCFG;                        /*!< (@ 0x00000004) Voice Configuration                                        */
7732 
7733     struct {
7734             uint32_t            : 3;
7735       __IOM uint32_t CHSET      : 2;            /*!< [4..3] Set PCM channels.                                                  */
7736             uint32_t            : 3;
7737       __IOM uint32_t PCMPACK    : 1;            /*!< [8..8] PCM data packing enable.                                           */
7738             uint32_t            : 7;
7739       __IOM uint32_t SELAP      : 1;            /*!< [16..16] Select PDM input clock source.                                   */
7740       __IOM uint32_t DMICKDEL   : 1;            /*!< [17..17] PDM clock sampling delay.                                        */
7741             uint32_t            : 1;
7742       __IOM uint32_t BCLKINV    : 1;            /*!< [19..19] I2S BCLK input inversion.                                        */
7743       __IOM uint32_t I2SEN      : 1;            /*!< [20..20] I2S interface enable.                                            */
7744             uint32_t            : 5;
7745       __IOM uint32_t PDMCLKEN   : 1;            /*!< [26..26] Enable the serial clock.                                         */
7746       __IOM uint32_t PDMCLKSEL  : 3;            /*!< [29..27] Select the PDM input clock.                                      */
7747       __IOM uint32_t RSTB       : 1;            /*!< [30..30] Reset the IP core.                                               */
7748       __IOM uint32_t IOCLKEN    : 1;            /*!< [31..31] Enable the IO clock.                                             */
7749     } VCFG_b;
7750   } ;
7751 
7752   union {
7753     __IOM uint32_t VOICESTAT;                   /*!< (@ 0x00000008) Voice Status                                               */
7754 
7755     struct {
7756       __IOM uint32_t FIFOCNT    : 6;            /*!< [5..0] Valid 32-bit entries currently in the FIFO.                        */
7757             uint32_t            : 26;
7758     } VOICESTAT_b;
7759   } ;
7760 
7761   union {
7762     __IOM uint32_t FIFOREAD;                    /*!< (@ 0x0000000C) FIFO Read                                                  */
7763 
7764     struct {
7765       __IOM uint32_t FIFOREAD   : 32;           /*!< [31..0] FIFO read data.                                                   */
7766     } FIFOREAD_b;
7767   } ;
7768 
7769   union {
7770     __IOM uint32_t FIFOFLUSH;                   /*!< (@ 0x00000010) FIFO Flush                                                 */
7771 
7772     struct {
7773       __IOM uint32_t FIFOFLUSH  : 1;            /*!< [0..0] FIFO FLUSH.                                                        */
7774             uint32_t            : 31;
7775     } FIFOFLUSH_b;
7776   } ;
7777 
7778   union {
7779     __IOM uint32_t FIFOTHR;                     /*!< (@ 0x00000014) FIFO Threshold                                             */
7780 
7781     struct {
7782       __IOM uint32_t FIFOTHR    : 5;            /*!< [4..0] FIFO Threshold value. When the FIFO count is equal to,
7783                                                      or larger than this value (in words), a THR interrupt is
7784                                                      generated (if enabled)                                                    */
7785             uint32_t            : 27;
7786     } FIFOTHR_b;
7787   } ;
7788   __IM  uint32_t  RESERVED[122];
7789 
7790   union {
7791     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
7792                                                                     to generate the corresponding interrupt.                   */
7793 
7794     struct {
7795       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
7796       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
7797       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
7798       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
7799       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
7800             uint32_t            : 27;
7801     } INTEN_b;
7802   } ;
7803 
7804   union {
7805     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
7806                                                                     cause of a recent interrupt.                               */
7807 
7808     struct {
7809       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
7810       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
7811       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
7812       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
7813       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
7814             uint32_t            : 27;
7815     } INTSTAT_b;
7816   } ;
7817 
7818   union {
7819     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
7820                                                                     the interrupt status associated with that
7821                                                                     bit.                                                       */
7822 
7823     struct {
7824       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
7825       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
7826       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
7827       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
7828       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
7829             uint32_t            : 27;
7830     } INTCLR_b;
7831   } ;
7832 
7833   union {
7834     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
7835                                                                     generate an interrupt from this module.
7836                                                                     (Generally used for testing purposes).                     */
7837 
7838     struct {
7839       __IOM uint32_t THR        : 1;            /*!< [0..0] This is the FIFO threshold interrupt.                              */
7840       __IOM uint32_t OVF        : 1;            /*!< [1..1] This is the FIFO overflow interrupt.                               */
7841       __IOM uint32_t UNDFL      : 1;            /*!< [2..2] This is the FIFO underflow interrupt.                              */
7842       __IOM uint32_t DCMP       : 1;            /*!< [3..3] DMA completed a transfer                                           */
7843       __IOM uint32_t DERR       : 1;            /*!< [4..4] DMA Error received                                                 */
7844             uint32_t            : 27;
7845     } INTSET_b;
7846   } ;
7847   __IM  uint32_t  RESERVED1[12];
7848 
7849   union {
7850     __IOM uint32_t DMATRIGEN;                   /*!< (@ 0x00000240) DMA Trigger Enable                                         */
7851 
7852     struct {
7853       __IOM uint32_t DTHR       : 1;            /*!< [0..0] Trigger DMA upon when FIFO is filled to level indicated
7854                                                      by the FIFO THRESHOLD,at granularity of 16 bytes only                     */
7855       __IOM uint32_t DTHR90     : 1;            /*!< [1..1] Trigger DMA at FIFO 90 percent full. This signal is also
7856                                                      used internally for AUTOHIP function                                      */
7857             uint32_t            : 30;
7858     } DMATRIGEN_b;
7859   } ;
7860 
7861   union {
7862     __IOM uint32_t DMATRIGSTAT;                 /*!< (@ 0x00000244) DMA Trigger Status                                         */
7863 
7864     struct {
7865       __IOM uint32_t DTHRSTAT   : 1;            /*!< [0..0] Triggered DMA from FIFO reaching threshold                         */
7866       __IOM uint32_t DTHR90STAT : 1;            /*!< [1..1] Triggered DMA from FIFO reaching 90 percent full                   */
7867             uint32_t            : 30;
7868     } DMATRIGSTAT_b;
7869   } ;
7870   __IM  uint32_t  RESERVED2[14];
7871 
7872   union {
7873     __IOM uint32_t DMACFG;                      /*!< (@ 0x00000280) DMA Configuration                                          */
7874 
7875     struct {
7876       __IOM uint32_t DMAEN      : 1;            /*!< [0..0] DMA Enable                                                         */
7877             uint32_t            : 1;
7878       __IOM uint32_t DMADIR     : 1;            /*!< [2..2] Direction                                                          */
7879             uint32_t            : 5;
7880       __IOM uint32_t DMAPRI     : 1;            /*!< [8..8] Sets the Priority of the DMA request                               */
7881       __IOM uint32_t DAUTOHIP   : 1;            /*!< [9..9] Raise priority to high on FIFO full, and DMAPRI set to
7882                                                      low                                                                       */
7883       __IOM uint32_t DPWROFF    : 1;            /*!< [10..10] Power Off the ADC System upon DMACPL.                            */
7884             uint32_t            : 21;
7885     } DMACFG_b;
7886   } ;
7887   __IM  uint32_t  RESERVED3;
7888 
7889   union {
7890     __IOM uint32_t DMATOTCOUNT;                 /*!< (@ 0x00000288) DMA Total Transfer Count                                   */
7891 
7892     struct {
7893       __IOM uint32_t TOTCOUNT   : 20;           /*!< [19..0] Total Transfer Count. The transfer count must be a multiple
7894                                                      of the THR setting to avoid DMA overruns.                                 */
7895             uint32_t            : 12;
7896     } DMATOTCOUNT_b;
7897   } ;
7898 
7899   union {
7900     __IOM uint32_t DMATARGADDR;                 /*!< (@ 0x0000028C) DMA Target Address                                         */
7901 
7902     struct {
7903       __IOM uint32_t LTARGADDR  : 20;           /*!< [19..0] DMA Target Address. This register is not updated with
7904                                                      the current address of the DMA, but will remain static
7905                                                      with the original address during the DMA transfer.                        */
7906       __IOM uint32_t UTARGADDR  : 12;           /*!< [31..20] SRAM Target                                                      */
7907     } DMATARGADDR_b;
7908   } ;
7909 
7910   union {
7911     __IOM uint32_t DMASTAT;                     /*!< (@ 0x00000290) DMA Status                                                 */
7912 
7913     struct {
7914       __IOM uint32_t DMATIP     : 1;            /*!< [0..0] DMA Transfer In Progress                                           */
7915       __IOM uint32_t DMACPL     : 1;            /*!< [1..1] DMA Transfer Complete                                              */
7916       __IOM uint32_t DMAERR     : 1;            /*!< [2..2] DMA Error                                                          */
7917             uint32_t            : 29;
7918     } DMASTAT_b;
7919   } ;
7920 } PDM_Type;                                     /*!< Size = 660 (0x294)                                                        */
7921 
7922 
7923 
7924 /* =========================================================================================================================== */
7925 /* ================                                          PWRCTRL                                          ================ */
7926 /* =========================================================================================================================== */
7927 
7928 
7929 /**
7930   * @brief PWR Controller Register Bank (PWRCTRL)
7931   */
7932 
7933 typedef struct {                                /*!< (@ 0x40021000) PWRCTRL Structure                                          */
7934 
7935   union {
7936     __IOM uint32_t SUPPLYSRC;                   /*!< (@ 0x00000000) This register controls the enable for BLE BUCK.            */
7937 
7938     struct {
7939       __IOM uint32_t BLEBUCKEN  : 1;            /*!< [0..0] Enables and Selects the BLE Buck as the supply for the
7940                                                      BLE power domain or for Burst LDO. It takes the initial
7941                                                      value from Customer INFO space. Buck will be powered up
7942                                                      only if there is an active request for BLEH domain or Burst
7943                                                      mode and appropriate feature is allowed.                                  */
7944             uint32_t            : 31;
7945     } SUPPLYSRC_b;
7946   } ;
7947 
7948   union {
7949     __IOM uint32_t SUPPLYSTATUS;                /*!< (@ 0x00000004) Provides an indicator for the BLE BUCK and SIMO
7950                                                                     BUCK status. Once the SIMO BUCK is powered
7951                                                                     up MEM and CORE LDOs are disabled.                         */
7952 
7953     struct {
7954       __IOM uint32_t SIMOBUCKON : 1;            /*!< [0..0] Indicates whether the Core/Mem low-voltage domains are
7955                                                      supplied from the LDO or the Buck.                                        */
7956       __IOM uint32_t BLEBUCKON  : 1;            /*!< [1..1] Indicates whether the BLE (if supported) domain and burst
7957                                                      (if supported) domain is supplied from the LDO or the Buck.
7958                                                      Buck will be powered up only if there is an active request
7959                                                      for BLEH domain or Burst mode and appropriate feature is
7960                                                      allowed.                                                                  */
7961             uint32_t            : 30;
7962     } SUPPLYSTATUS_b;
7963   } ;
7964 
7965   union {
7966     __IOM uint32_t DEVPWREN;                    /*!< (@ 0x00000008) This enables various peripherals power domains.            */
7967 
7968     struct {
7969       __IOM uint32_t PWRIOS     : 1;            /*!< [0..0] Power up IO Slave                                                  */
7970       __IOM uint32_t PWRIOM0    : 1;            /*!< [1..1] Power up IO Master 0                                               */
7971       __IOM uint32_t PWRIOM1    : 1;            /*!< [2..2] Power up IO Master 1                                               */
7972       __IOM uint32_t PWRIOM2    : 1;            /*!< [3..3] Power up IO Master 2                                               */
7973       __IOM uint32_t PWRIOM3    : 1;            /*!< [4..4] Power up IO Master 3                                               */
7974       __IOM uint32_t PWRIOM4    : 1;            /*!< [5..5] Power up IO Master 4                                               */
7975       __IOM uint32_t PWRIOM5    : 1;            /*!< [6..6] Power up IO Master 5                                               */
7976       __IOM uint32_t PWRUART0   : 1;            /*!< [7..7] Power up UART Controller 0                                         */
7977       __IOM uint32_t PWRUART1   : 1;            /*!< [8..8] Power up UART Controller 1                                         */
7978       __IOM uint32_t PWRADC     : 1;            /*!< [9..9] Power up ADC Digital Controller                                    */
7979       __IOM uint32_t PWRSCARD   : 1;            /*!< [10..10] Power up SCARD Controller                                        */
7980       __IOM uint32_t PWRMSPI    : 1;            /*!< [11..11] Power up MSPI Controller                                         */
7981       __IOM uint32_t PWRPDM     : 1;            /*!< [12..12] Power up PDM block                                               */
7982       __IOM uint32_t PWRBLEL    : 1;            /*!< [13..13] Power up BLE controller                                          */
7983             uint32_t            : 18;
7984     } DEVPWREN_b;
7985   } ;
7986 
7987   union {
7988     __IOM uint32_t MEMPWDINSLEEP;               /*!< (@ 0x0000000C) This controls the power down of the SRAM banks
7989                                                                     in deep sleep mode. If this is set, then
7990                                                                     the power for that SRAM bank will be gated
7991                                                                     when the core goes into deep sleep. Upon
7992                                                                     wake, the data within the SRAMs will be
7993                                                                     erased. If this is not set, retention voltage
7994                                                                     will be applied to the SRAM bank when the
7995                                                                     core goes into deep sleep. Upon wake, the
7996                                                                     data within the SRAMs are retained. Do not
7997                                                                     set this if the SRAM bank is used as the
7998                                                                     target for DMA transfer while CPU in deep
7999                                                                     sleep.                                                     */
8000 
8001     struct {
8002       __IOM uint32_t DTCMPWDSLP : 3;            /*!< [2..0] power down DTCM in deep sleep                                      */
8003       __IOM uint32_t SRAMPWDSLP : 10;           /*!< [12..3] Selects which SRAM banks are powered down in deep sleep
8004                                                      mode, causing the contents of the bank to be lost.                        */
8005       __IOM uint32_t FLASH0PWDSLP : 1;          /*!< [13..13] Power-down FLASH0 in deep sleep                                  */
8006       __IOM uint32_t FLASH1PWDSLP : 1;          /*!< [14..14] Power-down FLASH1 in deep sleep                                  */
8007             uint32_t            : 16;
8008       __IOM uint32_t CACHEPWDSLP : 1;           /*!< [31..31] power down cache in deep sleep                                   */
8009     } MEMPWDINSLEEP_b;
8010   } ;
8011 
8012   union {
8013     __IOM uint32_t MEMPWREN;                    /*!< (@ 0x00000010) This register enables the individual banks for
8014                                                                     the memories. When set, power will be enabled
8015                                                                     to the banks. This register works in conjunction
8016                                                                     with the MEMPWDINSLEEP register. When this
8017                                                                     register is set, then the MEMPWRINSLEEP
8018                                                                     register will determine whether power is
8019                                                                     enabled to the SRAMs in deep sleep. If this
8020                                                                     register is not set, then power will always
8021                                                                     be disabled to the memory bank.                            */
8022 
8023     struct {
8024       __IOM uint32_t DTCM       : 3;            /*!< [2..0] Power up DTCM                                                      */
8025       __IOM uint32_t SRAM       : 10;           /*!< [12..3] Power up SRAM groups                                              */
8026       __IOM uint32_t FLASH0     : 1;            /*!< [13..13] Power up FLASH0                                                  */
8027       __IOM uint32_t FLASH1     : 1;            /*!< [14..14] Power up FLASH1                                                  */
8028             uint32_t            : 15;
8029       __IOM uint32_t CACHEB0    : 1;            /*!< [30..30] Power up Cache Bank 0. This works in conjunction with
8030                                                      Cache enable from flash_cache module. To power up cache
8031                                                      bank 0, cache has to be enabled and this bit has to be
8032                                                      set.                                                                      */
8033       __IOM uint32_t CACHEB2    : 1;            /*!< [31..31] Power up Cache Bank 2. This works in conjunction with
8034                                                      Cache enable from flash_cache module. To power up cache
8035                                                      bank 2, cache has to be enabled and this bit has to be
8036                                                      set.                                                                      */
8037     } MEMPWREN_b;
8038   } ;
8039 
8040   union {
8041     __IOM uint32_t MEMPWRSTATUS;                /*!< (@ 0x00000014) It provides the power status for all the memory
8042                                                                     banks including- caches, FLASH (0 and 1)
8043                                                                     and all the SRAM groups. The status here
8044                                                                     should reflect the enable provided by the
8045                                                                     MEMPWREN register. There may be a lag time
8046                                                                     between setting the bits in MEMPWREN register
8047                                                                     and MEMPWRSTATUS register, due to the need
8048                                                                     to cycle the power gate and isolation sequences
8049                                                                     to the memory banks.                                       */
8050 
8051     struct {
8052       __IOM uint32_t DTCM00     : 1;            /*!< [0..0] This bit is 1 if power is supplied to DTCM GROUP0_0                */
8053       __IOM uint32_t DTCM01     : 1;            /*!< [1..1] This bit is 1 if power is supplied to DTCM GROUP0_1                */
8054       __IOM uint32_t DTCM1      : 1;            /*!< [2..2] This bit is 1 if power is supplied to DTCM GROUP1                  */
8055       __IOM uint32_t SRAM0      : 1;            /*!< [3..3] This bit is 1 if power is supplied to SRAM GROUP0                  */
8056       __IOM uint32_t SRAM1      : 1;            /*!< [4..4] This bit is 1 if power is supplied to SRAM GROUP1                  */
8057       __IOM uint32_t SRAM2      : 1;            /*!< [5..5] This bit is 1 if power is supplied to SRAM GROUP2                  */
8058       __IOM uint32_t SRAM3      : 1;            /*!< [6..6] This bit is 1 if power is supplied to SRAM GROUP3                  */
8059       __IOM uint32_t SRAM4      : 1;            /*!< [7..7] This bit is 1 if power is supplied to SRAM GROUP4                  */
8060       __IOM uint32_t SRAM5      : 1;            /*!< [8..8] This bit is 1 if power is supplied to SRAM GROUP5                  */
8061       __IOM uint32_t SRAM6      : 1;            /*!< [9..9] This bit is 1 if power is supplied to SRAM GROUP6                  */
8062       __IOM uint32_t SRAM7      : 1;            /*!< [10..10] This bit is 1 if power is supplied to SRAM GROUP7                */
8063       __IOM uint32_t SRAM8      : 1;            /*!< [11..11] This bit is 1 if power is supplied to SRAM GROUP8                */
8064       __IOM uint32_t SRAM9      : 1;            /*!< [12..12] This bit is 1 if power is supplied to SRAM GROUP9                */
8065       __IOM uint32_t FLASH0     : 1;            /*!< [13..13] This bit is 1 if power is supplied to FLASH 0                    */
8066       __IOM uint32_t FLASH1     : 1;            /*!< [14..14] This bit is 1 if power is supplied to FLASH 1                    */
8067       __IOM uint32_t CACHEB0    : 1;            /*!< [15..15] This bit is 1 if power is supplied to Cache Bank 0               */
8068       __IOM uint32_t CACHEB2    : 1;            /*!< [16..16] This bit is 1 if power is supplied to Cache Bank 2               */
8069             uint32_t            : 15;
8070     } MEMPWRSTATUS_b;
8071   } ;
8072 
8073   union {
8074     __IOM uint32_t DEVPWRSTATUS;                /*!< (@ 0x00000018) This provides the power status for the peripheral
8075                                                                     devices- BLEL, PDM, PDM, MSPI, SCARD, ADC,
8076                                                                     UART0 and 1, IOM5 to 0, IOSLAVE and MCUL
8077                                                                     (DMA and Fabrics) and MCUH (ARM core). The
8078                                                                     status here should reflect the enable provided
8079                                                                     by the DEVPWREN register. There may be a
8080                                                                     lag time between setting the bits in DEVPWREN
8081                                                                     register and DEVPWRSTATUS register, due
8082                                                                     to the need to cycle the power gate, isolation
8083                                                                     and reset sequences to the device power
8084                                                                     domains.                                                   */
8085 
8086     struct {
8087       __IOM uint32_t MCUL       : 1;            /*!< [0..0] This bit is 1 if power is supplied to MCUL                         */
8088       __IOM uint32_t MCUH       : 1;            /*!< [1..1] This bit is 1 if power is supplied to MCUH                         */
8089       __IOM uint32_t HCPA       : 1;            /*!< [2..2] This bit is 1 if power is supplied to HCPA domain (IO
8090                                                      SLAVE, UART0, UART1, SCARD)                                               */
8091       __IOM uint32_t HCPB       : 1;            /*!< [3..3] This bit is 1 if power is supplied to HCPB domain (IO
8092                                                      MASTER 0, 1, 2)                                                           */
8093       __IOM uint32_t HCPC       : 1;            /*!< [4..4] This bit is 1 if power is supplied to HCPC domain (IO
8094                                                      MASTER4, 5, 6)                                                            */
8095       __IOM uint32_t PWRADC     : 1;            /*!< [5..5] This bit is 1 if power is supplied to ADC                          */
8096       __IOM uint32_t PWRMSPI    : 1;            /*!< [6..6] This bit is 1 if power is supplied to MSPI                         */
8097       __IOM uint32_t PWRPDM     : 1;            /*!< [7..7] This bit is 1 if power is supplied to PDM                          */
8098       __IOM uint32_t BLEL       : 1;            /*!< [8..8] This bit is 1 if power is supplied to BLEL                         */
8099       __IOM uint32_t BLEH       : 1;            /*!< [9..9] This bit is 1 if power is supplied to BLEH                         */
8100             uint32_t            : 22;
8101     } DEVPWRSTATUS_b;
8102   } ;
8103 
8104   union {
8105     __IOM uint32_t SRAMCTRL;                    /*!< (@ 0x0000001C) This register provides additional fine-tune power
8106                                                                     management controls for the SRAMs and the
8107                                                                     SRAM controller. This includes enabling
8108                                                                     light sleep for the SRAM and TCM banks,
8109                                                                     and clock gating for reduced dynamic power.                */
8110 
8111     struct {
8112             uint32_t            : 1;
8113       __IOM uint32_t SRAMCLKGATE : 1;           /*!< [1..1] This bit is 1 if clock gating is allowed for individual
8114                                                      system SRAMs                                                              */
8115       __IOM uint32_t SRAMMASTERCLKGATE : 1;     /*!< [2..2] This bit is 1 when the master clock gate is enabled (top-level
8116                                                      clock gate for entire SRAM block)                                         */
8117             uint32_t            : 5;
8118       __IOM uint32_t SRAMLIGHTSLEEP : 12;       /*!< [19..8] Light Sleep enable for each TCM/SRAM bank. When 1, corresponding
8119                                                      bank will be put into light sleep. For optimal power, banks
8120                                                      should be put into light sleep while the system is active
8121                                                      but the bank has minimal or no accesses.                                  */
8122             uint32_t            : 12;
8123     } SRAMCTRL_b;
8124   } ;
8125 
8126   union {
8127     __IOM uint32_t ADCSTATUS;                   /*!< (@ 0x00000020) This provides the power status for various blocks
8128                                                                     within the ADC. These status comes directly
8129                                                                     from the ADC module and is captured through
8130                                                                     this interface.                                            */
8131 
8132     struct {
8133       __IOM uint32_t ADCPWD     : 1;            /*!< [0..0] This bit indicates that the ADC is powered down                    */
8134       __IOM uint32_t BGTPWD     : 1;            /*!< [1..1] This bit indicates that the ADC Band Gap is powered down           */
8135       __IOM uint32_t VPTATPWD   : 1;            /*!< [2..2] This bit indicates that the ADC temperature sensor input
8136                                                      buffer is powered down                                                    */
8137       __IOM uint32_t VBATPWD    : 1;            /*!< [3..3] This bit indicates that the ADC VBAT resistor divider
8138                                                      is powered down                                                           */
8139       __IOM uint32_t REFKEEPPWD : 1;            /*!< [4..4] This bit indicates that the ADC REFKEEP is powered down            */
8140       __IOM uint32_t REFBUFPWD  : 1;            /*!< [5..5] This bit indicates that the ADC REFBUF is powered down             */
8141             uint32_t            : 26;
8142     } ADCSTATUS_b;
8143   } ;
8144 
8145   union {
8146     __IOM uint32_t MISC;                        /*!< (@ 0x00000024) This register includes additional debug control
8147                                                                     bits. This is an internal Ambiq-only register.
8148                                                                     Customers should not attempt to change this
8149                                                                     or else functionality cannot be guaranteed.                */
8150 
8151     struct {
8152             uint32_t            : 3;
8153       __IOM uint32_t FORCEMEMVRLPTIMERS : 1;    /*!< [3..3] Control Bit to force Mem VR to LP mode in deep sleep
8154                                                      even when hfrc based ctimer or stimer is running.                         */
8155             uint32_t            : 2;
8156       __IOM uint32_t MEMVRLPBLE : 1;            /*!< [6..6] Control Bit to let Mem VR go to lp mode in deep sleep
8157                                                      even when BLEL or BLEH is powered on given none of the
8158                                                      other domains require it.                                                 */
8159             uint32_t            : 25;
8160     } MISC_b;
8161   } ;
8162 
8163   union {
8164     __IOM uint32_t DEVPWREVENTEN;               /*!< (@ 0x00000028) This register controls which feature trigger
8165                                                                     will result in an event to the CPU. It includes
8166                                                                     all the power on status for the core domains,
8167                                                                     as well as the Burst event. If any bits
8168                                                                     are set, then if the domain is turned on,
8169                                                                     it will result in an event to the ARM core.                */
8170 
8171     struct {
8172       __IOM uint32_t MCULEVEN   : 1;            /*!< [0..0] Control MCUL power-on status event                                 */
8173       __IOM uint32_t MCUHEVEN   : 1;            /*!< [1..1] Control MCUH power-on status event                                 */
8174       __IOM uint32_t HCPAEVEN   : 1;            /*!< [2..2] Control HCPA power-on status event                                 */
8175       __IOM uint32_t HCPBEVEN   : 1;            /*!< [3..3] Control HCPB power-on status event                                 */
8176       __IOM uint32_t HCPCEVEN   : 1;            /*!< [4..4] Control HCPC power-on status event                                 */
8177       __IOM uint32_t ADCEVEN    : 1;            /*!< [5..5] Control ADC power-on status event                                  */
8178       __IOM uint32_t MSPIEVEN   : 1;            /*!< [6..6] Control MSPI power-on status event                                 */
8179       __IOM uint32_t PDMEVEN    : 1;            /*!< [7..7] Control PDM power-on status event                                  */
8180       __IOM uint32_t BLELEVEN   : 1;            /*!< [8..8] Control BLE power-on status event                                  */
8181             uint32_t            : 20;
8182       __IOM uint32_t BLEFEATUREEVEN : 1;        /*!< [29..29] Control BLEFEATURE status event                                  */
8183       __IOM uint32_t BURSTFEATUREEVEN : 1;      /*!< [30..30] Control BURSTFEATURE status event                                */
8184       __IOM uint32_t BURSTEVEN  : 1;            /*!< [31..31] Control BURST status event                                       */
8185     } DEVPWREVENTEN_b;
8186   } ;
8187 
8188   union {
8189     __IOM uint32_t MEMPWREVENTEN;               /*!< (@ 0x0000002C) This register controls which power enable for
8190                                                                     the memories will result in an event to
8191                                                                     the CPU. It includes all the power on status
8192                                                                     for the memory domains. If any bits are
8193                                                                     set, then if the domain is turned on, it
8194                                                                     will result in an event to the ARM core.                   */
8195 
8196     struct {
8197       __IOM uint32_t DTCMEN     : 3;            /*!< [2..0] Enable DTCM power-on status event                                  */
8198       __IOM uint32_t SRAMEN     : 10;           /*!< [12..3] Control SRAM power-on status event                                */
8199       __IOM uint32_t FLASH0EN   : 1;            /*!< [13..13] Control FLASH power-on status event                              */
8200       __IOM uint32_t FLASH1EN   : 1;            /*!< [14..14] Control FLASH power-on status event                              */
8201             uint32_t            : 15;
8202       __IOM uint32_t CACHEB0EN  : 1;            /*!< [30..30] Control CACHE BANK 0 power-on status event                       */
8203       __IOM uint32_t CACHEB2EN  : 1;            /*!< [31..31] Control CACHEB2 power-on status event                            */
8204     } MEMPWREVENTEN_b;
8205   } ;
8206 } PWRCTRL_Type;                                 /*!< Size = 48 (0x30)                                                          */
8207 
8208 
8209 
8210 /* =========================================================================================================================== */
8211 /* ================                                          RSTGEN                                           ================ */
8212 /* =========================================================================================================================== */
8213 
8214 
8215 /**
8216   * @brief MCU Reset Generator (RSTGEN)
8217   */
8218 
8219 typedef struct {                                /*!< (@ 0x40000000) RSTGEN Structure                                           */
8220 
8221   union {
8222     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) Reset configuration register. This controls the
8223                                                                     reset enables for brownout condition, and
8224                                                                     for the expiration of the watch dog timer.                 */
8225 
8226     struct {
8227       __IOM uint32_t BODHREN    : 1;            /*!< [0..0] Brown out high (2.1 V) reset enable.                               */
8228       __IOM uint32_t WDREN      : 1;            /*!< [1..1] Watchdog Timer Reset Enable. NOTE: The WDT module must
8229                                                      also be configured for WDT reset. This includes enabling
8230                                                      the RESEN bit in WDTCFG register in Watch dog timer block.                */
8231             uint32_t            : 30;
8232     } CFG_b;
8233   } ;
8234 
8235   union {
8236     __IOM uint32_t SWPOI;                       /*!< (@ 0x00000004) This is the software POI reset. writing the key
8237                                                                     value to this register will trigger a POI
8238                                                                     to the system. This will cause a reset to
8239                                                                     all blocks except for registers in clock
8240                                                                     gen, RTC and the STIMER.                                   */
8241 
8242     struct {
8243       __IOM uint32_t SWPOIKEY   : 8;            /*!< [7..0] 0x1B generates a software POI reset. This is a write-only
8244                                                      register. Reading from this register will yield only all
8245                                                      0's.                                                                      */
8246             uint32_t            : 24;
8247     } SWPOI_b;
8248   } ;
8249 
8250   union {
8251     __IOM uint32_t SWPOR;                       /*!< (@ 0x00000008) This is the software POR reset. Writing the key
8252                                                                     value to this register will trigger a POR
8253                                                                     to the system. This will cause a reset to
8254                                                                     all blocks except for registers in clock
8255                                                                     gen, RTC, power management unit, the STIMER,
8256                                                                     and the power management unit.                             */
8257 
8258     struct {
8259       __IOM uint32_t SWPORKEY   : 8;            /*!< [7..0] 0xD4 generates a software POR reset.                               */
8260             uint32_t            : 24;
8261     } SWPOR_b;
8262   } ;
8263   __IM  uint32_t  RESERVED[2];
8264 
8265   union {
8266     __IOM uint32_t TPIURST;                     /*!< (@ 0x00000014) This will trigger a reset for the TPIU unit.               */
8267 
8268     struct {
8269       __IOM uint32_t TPIURST    : 1;            /*!< [0..0] Static reset for the TPIU. Write to '1' to assert reset
8270                                                      to TPIU. Write to '0' to clear the reset.                                 */
8271             uint32_t            : 31;
8272     } TPIURST_b;
8273   } ;
8274   __IM  uint32_t  RESERVED1[122];
8275 
8276   union {
8277     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
8278                                                                     to generate the corresponding interrupt.                   */
8279 
8280     struct {
8281       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
8282                                                      BODH level.                                                               */
8283             uint32_t            : 31;
8284     } INTEN_b;
8285   } ;
8286 
8287   union {
8288     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
8289                                                                     cause of a recent interrupt.                               */
8290 
8291     struct {
8292       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
8293                                                      BODH level.                                                               */
8294             uint32_t            : 31;
8295     } INTSTAT_b;
8296   } ;
8297 
8298   union {
8299     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
8300                                                                     the interrupt status associated with that
8301                                                                     bit.                                                       */
8302 
8303     struct {
8304       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
8305                                                      BODH level.                                                               */
8306             uint32_t            : 31;
8307     } INTCLR_b;
8308   } ;
8309 
8310   union {
8311     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
8312                                                                     generate an interrupt from this module.
8313                                                                     (Generally used for testing purposes).                     */
8314 
8315     struct {
8316       __IOM uint32_t BODH       : 1;            /*!< [0..0] Enables an interrupt that triggers when VCC is below
8317                                                      BODH level.                                                               */
8318             uint32_t            : 31;
8319     } INTSET_b;
8320   } ;
8321   __IM  uint32_t  RESERVED2[67107708];
8322 
8323   union {
8324     __IOM uint32_t STAT;                        /*!< (@ 0x0FFFF000) This register contains the status for brownout
8325                                                                     events and the causes for resets.
8326                                                                     NOTE 1: All bits in this register, including
8327                                                                     reserved bits, are writable. Therefore care
8328                                                                     should be taken not to write this register.
8329                                                                     NOTE 2: This register does not retain its
8330                                                                     value across a core deep sleep cycle. Therefore
8331                                                                     applications needing to use this value after
8332                                                                     deep sleep must copy and save this register
8333                                                                     to SRAM before initiating the first deep
8334                                                                     sleep cycle.                                               */
8335 
8336     struct {
8337       __IOM uint32_t EXRSTAT    : 1;            /*!< [0..0] Reset was initiated by an External Reset (SBL).                    */
8338       __IOM uint32_t PORSTAT    : 1;            /*!< [1..1] Reset was initiated by a Power-On Reset (SBL).                     */
8339       __IOM uint32_t BORSTAT    : 1;            /*!< [2..2] Reset was initiated by a Brown-Out Reset (SBL).                    */
8340       __IOM uint32_t SWRSTAT    : 1;            /*!< [3..3] Reset was a initiated by SW POR or AIRCR Reset (SBL).              */
8341       __IOM uint32_t POIRSTAT   : 1;            /*!< [4..4] Reset was a initiated by Software POI Reset (SBL).                 */
8342       __IOM uint32_t DBGRSTAT   : 1;            /*!< [5..5] Reset was a initiated by Debugger Reset (SBL).                     */
8343       __IOM uint32_t WDRSTAT    : 1;            /*!< [6..6] Reset was initiated by a Watchdog Timer Reset (SBL).               */
8344       __IOM uint32_t BOUSTAT    : 1;            /*!< [7..7] An Unregulated Supply Brownout Event occurred (SBL).               */
8345       __IOM uint32_t BOCSTAT    : 1;            /*!< [8..8] A Core Regulator Brownout Event occurred (SBL).                    */
8346       __IOM uint32_t BOFSTAT    : 1;            /*!< [9..9] A Memory Regulator Brownout Event occurred (SBL).                  */
8347       __IOM uint32_t BOBSTAT    : 1;            /*!< [10..10] A BLE/Burst Regulator Brownout Event occurred (SBL).             */
8348             uint32_t            : 19;
8349       __IOM uint32_t FBOOT      : 1;            /*!< [30..30] Set if current boot was initiated by soft reset and
8350                                                      resulted in Fast Boot (SBL).                                              */
8351       __IOM uint32_t SBOOT      : 1;            /*!< [31..31] Set when booting securely (SBL).                                 */
8352     } STAT_b;
8353   } ;
8354 } RSTGEN_Type;                                  /*!< Size = 268431364 (0xffff004)                                              */
8355 
8356 
8357 
8358 /* =========================================================================================================================== */
8359 /* ================                                            RTC                                            ================ */
8360 /* =========================================================================================================================== */
8361 
8362 
8363 /**
8364   * @brief Real Time Clock (RTC)
8365   */
8366 
8367 typedef struct {                                /*!< (@ 0x40004200) RTC Structure                                              */
8368   __IM  uint32_t  RESERVED[16];
8369 
8370   union {
8371     __IOM uint32_t CTRLOW;                      /*!< (@ 0x00000040) This counter contains the values for hour, minutes,
8372                                                                     seconds and 100ths of a second Counter.                    */
8373 
8374     struct {
8375       __IOM uint32_t CTR100     : 8;            /*!< [7..0] 100ths of a second Counter                                         */
8376       __IOM uint32_t CTRSEC     : 7;            /*!< [14..8] Seconds Counter                                                   */
8377             uint32_t            : 1;
8378       __IOM uint32_t CTRMIN     : 7;            /*!< [22..16] Minutes Counter                                                  */
8379             uint32_t            : 1;
8380       __IOM uint32_t CTRHR      : 6;            /*!< [29..24] Hours Counter                                                    */
8381             uint32_t            : 2;
8382     } CTRLOW_b;
8383   } ;
8384 
8385   union {
8386     __IOM uint32_t CTRUP;                       /*!< (@ 0x00000044) This register contains the day, month and year
8387                                                                     information. It contains which day in the
8388                                                                     week, and the century as well. The information
8389                                                                     of the century can also be derived from
8390                                                                     the year information. The 31st bit contains
8391                                                                     the error bit. See description in the register
8392                                                                     bit for condition when error is triggered.                 */
8393 
8394     struct {
8395       __IOM uint32_t CTRDATE    : 6;            /*!< [5..0] Date Counter                                                       */
8396             uint32_t            : 2;
8397       __IOM uint32_t CTRMO      : 5;            /*!< [12..8] Months Counter                                                    */
8398             uint32_t            : 3;
8399       __IOM uint32_t CTRYR      : 8;            /*!< [23..16] Years Counter                                                    */
8400       __IOM uint32_t CTRWKDY    : 3;            /*!< [26..24] Weekdays Counter                                                 */
8401       __IOM uint32_t CB         : 1;            /*!< [27..27] Century Bit. This bit will be toggled when the Years
8402                                                      register rolls over from 99 to 00 if the CEB bit is a 1.
8403                                                      CB=0 assumes the century it 19xx or 21xx, and CB=1 assumes
8404                                                      it is 20xx for leap year calculations.                                    */
8405       __IOM uint32_t CEB        : 1;            /*!< [28..28] Century Enable Bit                                               */
8406             uint32_t            : 2;
8407       __IOM uint32_t CTERR      : 1;            /*!< [31..31] Counter read error status. Error is triggered when
8408                                                      software reads the lower word of the counters, and fails
8409                                                      to read the upper counter within 1/100 second. This is
8410                                                      because when the lower counter is read, the upper counter
8411                                                      is held off from incrementing until it is read so that
8412                                                      the full time stamp can be read.                                          */
8413     } CTRUP_b;
8414   } ;
8415 
8416   union {
8417     __IOM uint32_t ALMLOW;                      /*!< (@ 0x00000048) This register is the Alarm settings for hours,
8418                                                                     minutes, second and 1/100th seconds settings.              */
8419 
8420     struct {
8421       __IOM uint32_t ALM100     : 8;            /*!< [7..0] 100ths of a second Alarm                                           */
8422       __IOM uint32_t ALMSEC     : 7;            /*!< [14..8] Seconds Alarm                                                     */
8423             uint32_t            : 1;
8424       __IOM uint32_t ALMMIN     : 7;            /*!< [22..16] Minutes Alarm                                                    */
8425             uint32_t            : 1;
8426       __IOM uint32_t ALMHR      : 6;            /*!< [29..24] Hours Alarm                                                      */
8427             uint32_t            : 2;
8428     } ALMLOW_b;
8429   } ;
8430 
8431   union {
8432     __IOM uint32_t ALMUP;                       /*!< (@ 0x0000004C) This register is the alarm settings for week,
8433                                                                     month and day.                                             */
8434 
8435     struct {
8436       __IOM uint32_t ALMDATE    : 6;            /*!< [5..0] Date Alarm                                                         */
8437             uint32_t            : 2;
8438       __IOM uint32_t ALMMO      : 5;            /*!< [12..8] Months Alarm                                                      */
8439             uint32_t            : 3;
8440       __IOM uint32_t ALMWKDY    : 3;            /*!< [18..16] Weekdays Alarm                                                   */
8441             uint32_t            : 13;
8442     } ALMUP_b;
8443   } ;
8444 
8445   union {
8446     __IOM uint32_t RTCCTL;                      /*!< (@ 0x00000050) This is the register control for the RTC module.
8447                                                                     It sets the 12 or 24 hours mode, enables
8448                                                                     counter writes and sets the alarm repeat
8449                                                                     interval.                                                  */
8450 
8451     struct {
8452       __IOM uint32_t WRTC       : 1;            /*!< [0..0] Counter write control                                              */
8453       __IOM uint32_t RPT        : 3;            /*!< [3..1] Alarm repeat interval                                              */
8454       __IOM uint32_t RSTOP      : 1;            /*!< [4..4] RTC input clock control                                            */
8455       __IOM uint32_t HR1224     : 1;            /*!< [5..5] Hours Counter mode                                                 */
8456             uint32_t            : 26;
8457     } RTCCTL_b;
8458   } ;
8459   __IM  uint32_t  RESERVED1[43];
8460 
8461   union {
8462     __IOM uint32_t INTEN;                       /*!< (@ 0x00000100) Set bits in this register to allow this module
8463                                                                     to generate the corresponding interrupt.                   */
8464 
8465     struct {
8466       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
8467             uint32_t            : 31;
8468     } INTEN_b;
8469   } ;
8470 
8471   union {
8472     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000104) Read bits from this register to discover the
8473                                                                     cause of a recent interrupt.                               */
8474 
8475     struct {
8476       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
8477             uint32_t            : 31;
8478     } INTSTAT_b;
8479   } ;
8480 
8481   union {
8482     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000108) Write a 1 to a bit in this register to clear
8483                                                                     the interrupt status associated with that
8484                                                                     bit.                                                       */
8485 
8486     struct {
8487       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
8488             uint32_t            : 31;
8489     } INTCLR_b;
8490   } ;
8491 
8492   union {
8493     __IOM uint32_t INTSET;                      /*!< (@ 0x0000010C) Write a 1 to a bit in this register to instantly
8494                                                                     generate an interrupt from this module.
8495                                                                     (Generally used for testing purposes).                     */
8496 
8497     struct {
8498       __IOM uint32_t ALM        : 1;            /*!< [0..0] RTC Alarm interrupt                                                */
8499             uint32_t            : 31;
8500     } INTSET_b;
8501   } ;
8502 } RTC_Type;                                     /*!< Size = 272 (0x110)                                                        */
8503 
8504 
8505 
8506 /* =========================================================================================================================== */
8507 /* ================                                           SCARD                                           ================ */
8508 /* =========================================================================================================================== */
8509 
8510 
8511 /**
8512   * @brief Serial ISO7816 (SCARD)
8513   */
8514 
8515 typedef struct {                                /*!< (@ 0x40080000) SCARD Structure                                            */
8516 
8517   union {
8518     __IOM uint32_t SR;                          /*!< (@ 0x00000000) ISO7816 interrupt status                                   */
8519 
8520     struct {
8521       __IOM uint32_t FNE        : 1;            /*!< [0..0] RX FIFO not empty.                                                 */
8522       __IOM uint32_t TBERBF     : 1;            /*!< [1..1] FIFO empty (transmit) or full (receive).                           */
8523       __IOM uint32_t FER        : 1;            /*!< [2..2] Framing error.                                                     */
8524       __IOM uint32_t OVR        : 1;            /*!< [3..3] RX FIFO overflow.                                                  */
8525       __IOM uint32_t PE         : 1;            /*!< [4..4] Parity Error.                                                      */
8526       __IOM uint32_t FT2REND    : 1;            /*!< [5..5] TX to RX finished.                                                 */
8527       __IOM uint32_t FHF        : 1;            /*!< [6..6] FIFO Half Full.                                                    */
8528             uint32_t            : 25;
8529     } SR_b;
8530   } ;
8531 
8532   union {
8533     __IOM uint32_t IER;                         /*!< (@ 0x00000004) ISO7816 interrupt enable                                   */
8534 
8535     struct {
8536       __IOM uint32_t FNEEN      : 1;            /*!< [0..0] RX FIFO not empty interrupt enable.                                */
8537       __IOM uint32_t TBERBFEN   : 1;            /*!< [1..1] FIFO empty (transmit) or full (receive) interrupt enable.          */
8538       __IOM uint32_t FEREN      : 1;            /*!< [2..2] Framing error interrupt enable.                                    */
8539       __IOM uint32_t OVREN      : 1;            /*!< [3..3] RX FIFOI overflow interrupt enable.                                */
8540       __IOM uint32_t PEEN       : 1;            /*!< [4..4] Parity Error interrupt enable.                                     */
8541       __IOM uint32_t FT2RENDEN  : 1;            /*!< [5..5] TX to RX finished interrupt enable.                                */
8542       __IOM uint32_t FHFEN      : 1;            /*!< [6..6] FIFO Half Full interrupt enable.                                   */
8543             uint32_t            : 25;
8544     } IER_b;
8545   } ;
8546 
8547   union {
8548     __IOM uint32_t TCR;                         /*!< (@ 0x00000008) ISO7816 transmit control                                   */
8549 
8550     struct {
8551       __IOM uint32_t CONV       : 1;            /*!< [0..0] Conversion inversion control.                                      */
8552       __IOM uint32_t SS         : 1;            /*!< [1..1] Use first byte to configure conversion.                            */
8553       __IOM uint32_t LCT        : 1;            /*!< [2..2] Fast TX to RX.                                                     */
8554       __IOM uint32_t TR         : 1;            /*!< [3..3] Transmit/receive mode.                                             */
8555       __IOM uint32_t PROT       : 1;            /*!< [4..4] PROT control.                                                      */
8556       __IOM uint32_t AUTOCONV   : 1;            /*!< [5..5] Automatic conversion.                                              */
8557       __IOM uint32_t FIP        : 1;            /*!< [6..6] Parity select.                                                     */
8558       __IOM uint32_t DMAMD      : 1;            /*!< [7..7] DMA direction.                                                     */
8559             uint32_t            : 24;
8560     } TCR_b;
8561   } ;
8562 
8563   union {
8564     __IOM uint32_t UCR;                         /*!< (@ 0x0000000C) ISO7816 user control                                       */
8565 
8566     struct {
8567       __IOM uint32_t CST        : 1;            /*!< [0..0] Clock control.                                                     */
8568       __IOM uint32_t RIU        : 1;            /*!< [1..1] ISO7816 reset. This bit is write-only.                             */
8569       __IOM uint32_t RSTIN      : 1;            /*!< [2..2] Reset polarity.                                                    */
8570       __IOM uint32_t RETXEN     : 1;            /*!< [3..3] Enable TX/RX time configuration.                                   */
8571             uint32_t            : 28;
8572     } UCR_b;
8573   } ;
8574 
8575   union {
8576     __IOM uint32_t DR;                          /*!< (@ 0x00000010) ISO7816 data                                               */
8577 
8578     struct {
8579       __IOM uint32_t DR         : 8;            /*!< [7..0] Data register.                                                     */
8580             uint32_t            : 24;
8581     } DR_b;
8582   } ;
8583 
8584   union {
8585     __IOM uint32_t BPRL;                        /*!< (@ 0x00000014) ISO7816 baud rate low                                      */
8586 
8587     struct {
8588       __IOM uint32_t BPRL       : 8;            /*!< [7..0] Baud rate low                                                      */
8589             uint32_t            : 24;
8590     } BPRL_b;
8591   } ;
8592 
8593   union {
8594     __IOM uint32_t BPRH;                        /*!< (@ 0x00000018) ISO7816 baud rate high                                     */
8595 
8596     struct {
8597       __IOM uint32_t BPRH       : 4;            /*!< [3..0] Baud rate high                                                     */
8598             uint32_t            : 28;
8599     } BPRH_b;
8600   } ;
8601 
8602   union {
8603     __IOM uint32_t UCR1;                        /*!< (@ 0x0000001C) ISO7816 user control 1                                     */
8604 
8605     struct {
8606       __IOM uint32_t PR         : 1;            /*!< [0..0] Query Card Detect.                                                 */
8607             uint32_t            : 1;
8608       __IOM uint32_t STSP       : 1;            /*!< [2..2] ETU counter control. This bit is write-only.                       */
8609       __IOM uint32_t T1PAREN    : 1;            /*!< [3..3] Parity check control.                                              */
8610       __IOM uint32_t CLKIOV     : 1;            /*!< [4..4] Output clock level.                                                */
8611       __IOM uint32_t ENLASTB    : 1;            /*!< [5..5] Enable last byte function.                                         */
8612             uint32_t            : 26;
8613     } UCR1_b;
8614   } ;
8615 
8616   union {
8617     __IOM uint32_t SR1;                         /*!< (@ 0x00000020) ISO7816 interrupt status 1                                 */
8618 
8619     struct {
8620       __IOM uint32_t ECNTOVER   : 1;            /*!< [0..0] ETU counter overflow.                                              */
8621       __IOM uint32_t PRL        : 1;            /*!< [1..1] Card insert/remove.                                                */
8622       __IOM uint32_t SYNCEND    : 1;            /*!< [2..2] Write complete synchronization.                                    */
8623       __IOM uint32_t IDLE       : 1;            /*!< [3..3] ISO7816 idle.                                                      */
8624             uint32_t            : 28;
8625     } SR1_b;
8626   } ;
8627 
8628   union {
8629     __IOM uint32_t IER1;                        /*!< (@ 0x00000024) ISO7816 interrupt enable 1                                 */
8630 
8631     struct {
8632       __IOM uint32_t ECNTOVEREN : 1;            /*!< [0..0] ETU counter overflow interrupt enable.                             */
8633       __IOM uint32_t PRLEN      : 1;            /*!< [1..1] Card insert/remove interrupt enable.                               */
8634       __IOM uint32_t SYNCENDEN  : 1;            /*!< [2..2] Write complete synchronization interrupt enable.                   */
8635             uint32_t            : 29;
8636     } IER1_b;
8637   } ;
8638 
8639   union {
8640     __IOM uint32_t ECNTL;                       /*!< (@ 0x00000028) ETU counter low                                            */
8641 
8642     struct {
8643       __IOM uint32_t ECNTL      : 8;            /*!< [7..0] ETU counter low register.                                          */
8644             uint32_t            : 24;
8645     } ECNTL_b;
8646   } ;
8647 
8648   union {
8649     __IOM uint32_t ECNTH;                       /*!< (@ 0x0000002C) ETU counter high                                           */
8650 
8651     struct {
8652       __IOM uint32_t ECNTH      : 8;            /*!< [7..0] ETU counter high register.                                         */
8653             uint32_t            : 24;
8654     } ECNTH_b;
8655   } ;
8656 
8657   union {
8658     __IOM uint32_t GTR;                         /*!< (@ 0x00000030) ISO7816 guard time configuration                           */
8659 
8660     struct {
8661       __IOM uint32_t GTR        : 8;            /*!< [7..0] Guard time configuration register.                                 */
8662             uint32_t            : 24;
8663     } GTR_b;
8664   } ;
8665 
8666   union {
8667     __IOM uint32_t RETXCNT;                     /*!< (@ 0x00000034) ISO7816 resend count                                       */
8668 
8669     struct {
8670       __IOM uint32_t RETXCNT    : 4;            /*!< [3..0] Resend count register.                                             */
8671             uint32_t            : 28;
8672     } RETXCNT_b;
8673   } ;
8674 
8675   union {
8676     __IOM uint32_t RETXCNTRMI;                  /*!< (@ 0x00000038) ISO7816 resent count inquiry                               */
8677 
8678     struct {
8679       __IOM uint32_t RETXCNTRMI : 4;            /*!< [3..0] Resent count inquiry register.                                     */
8680             uint32_t            : 28;
8681     } RETXCNTRMI_b;
8682   } ;
8683   __IM  uint32_t  RESERVED[49];
8684 
8685   union {
8686     __IOM uint32_t CLKCTRL;                     /*!< (@ 0x00000100) SCARD external clock control                               */
8687 
8688     struct {
8689       __IOM uint32_t CLKEN      : 1;            /*!< [0..0] Enable the serial source clock for SCARD.                          */
8690       __IOM uint32_t APBCLKEN   : 1;            /*!< [1..1] Enable the SCARD APB clock to run continuously.                    */
8691             uint32_t            : 30;
8692     } CLKCTRL_b;
8693   } ;
8694 } SCARD_Type;                                   /*!< Size = 260 (0x104)                                                        */
8695 
8696 
8697 
8698 /* =========================================================================================================================== */
8699 /* ================                                         SECURITY                                          ================ */
8700 /* =========================================================================================================================== */
8701 
8702 
8703 /**
8704   * @brief Security Interfaces (SECURITY)
8705   */
8706 
8707 typedef struct {                                /*!< (@ 0x40030000) SECURITY Structure                                         */
8708 
8709   union {
8710     __IOM uint32_t CTRL;                        /*!< (@ 0x00000000) Control                                                    */
8711 
8712     struct {
8713       __IOM uint32_t ENABLE     : 1;            /*!< [0..0] Function Enable. Software should set the ENABLE bit to
8714                                                      initiate a CRC operation. Hardware will clear the ENABLE
8715                                                      bit upon completion.                                                      */
8716             uint32_t            : 3;
8717       __IOM uint32_t FUNCTION   : 4;            /*!< [7..4] Function Select                                                    */
8718             uint32_t            : 23;
8719       __IOM uint32_t CRCERROR   : 1;            /*!< [31..31] CRC Error Status - Set to 1 if an error occurs during
8720                                                      a CRC operation. Cleared when CTRL register is written
8721                                                      (with any value). Usually indicates an invalid address
8722                                                      range.                                                                    */
8723     } CTRL_b;
8724   } ;
8725   __IM  uint32_t  RESERVED[3];
8726 
8727   union {
8728     __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000010) Source Address                                             */
8729 
8730     struct {
8731       __IOM uint32_t ADDR       : 32;           /*!< [31..0] Source Buffer Address. Address may be byte aligned,
8732                                                      but the length must be a multiple of 4 bits.                              */
8733     } SRCADDR_b;
8734   } ;
8735   __IM  uint32_t  RESERVED1[3];
8736 
8737   union {
8738     __IOM uint32_t LEN;                         /*!< (@ 0x00000020) Length                                                     */
8739 
8740     struct {
8741             uint32_t            : 2;
8742       __IOM uint32_t LEN        : 18;           /*!< [19..2] Buffer size (bottom two bits assumed to be zero to ensure
8743                                                      a multiple of 4 bytes)                                                    */
8744             uint32_t            : 12;
8745     } LEN_b;
8746   } ;
8747   __IM  uint32_t  RESERVED2[3];
8748 
8749   union {
8750     __IOM uint32_t RESULT;                      /*!< (@ 0x00000030) CRC Seed/Result                                            */
8751 
8752     struct {
8753       __IOM uint32_t CRC        : 32;           /*!< [31..0] CRC Seed/Result. Software must seed the CRC with 0xFFFFFFFF
8754                                                      before starting a CRC operation (unless the CRC is continued
8755                                                      from a previous operation).                                               */
8756     } RESULT_b;
8757   } ;
8758   __IM  uint32_t  RESERVED3[17];
8759 
8760   union {
8761     __IOM uint32_t LOCKCTRL;                    /*!< (@ 0x00000078) LOCK Control                                               */
8762 
8763     struct {
8764       __IOM uint32_t SELECT     : 8;            /*!< [7..0] LOCK Function Select register.                                     */
8765             uint32_t            : 24;
8766     } LOCKCTRL_b;
8767   } ;
8768 
8769   union {
8770     __IOM uint32_t LOCKSTAT;                    /*!< (@ 0x0000007C) LOCK Status                                                */
8771 
8772     struct {
8773       __IOM uint32_t STATUS     : 32;           /*!< [31..0] LOCK Status register. This register is a bit mask for
8774                                                      which resources are currently unlocked. These bits are
8775                                                      one-hot per resource.                                                     */
8776     } LOCKSTAT_b;
8777   } ;
8778 
8779   union {
8780     __IOM uint32_t KEY0;                        /*!< (@ 0x00000080) Key0                                                       */
8781 
8782     struct {
8783       __IOM uint32_t KEY0       : 32;           /*!< [31..0] Bits [31:0] of the 128-bit key should be written to
8784                                                      this register. To protect key values, the register always
8785                                                      returns 0x00000000.                                                       */
8786     } KEY0_b;
8787   } ;
8788 
8789   union {
8790     __IOM uint32_t KEY1;                        /*!< (@ 0x00000084) Key1                                                       */
8791 
8792     struct {
8793       __IOM uint32_t KEY1       : 32;           /*!< [31..0] Bits [63:32] of the 128-bit key should be written to
8794                                                      this register. To protect key values, the register always
8795                                                      returns 0x00000000.                                                       */
8796     } KEY1_b;
8797   } ;
8798 
8799   union {
8800     __IOM uint32_t KEY2;                        /*!< (@ 0x00000088) Key2                                                       */
8801 
8802     struct {
8803       __IOM uint32_t KEY2       : 32;           /*!< [31..0] Bits [95:64] of the 128-bit key should be written to
8804                                                      this register. To protect key values, the register always
8805                                                      returns 0x00000000.                                                       */
8806     } KEY2_b;
8807   } ;
8808 
8809   union {
8810     __IOM uint32_t KEY3;                        /*!< (@ 0x0000008C) Key3                                                       */
8811 
8812     struct {
8813       __IOM uint32_t KEY3       : 32;           /*!< [31..0] Bits [127:96] of the 128-bit key should be written to
8814                                                      this register. To protect key values, the register always
8815                                                      returns 0x00000000.                                                       */
8816     } KEY3_b;
8817   } ;
8818 } SECURITY_Type;                                /*!< Size = 144 (0x90)                                                         */
8819 
8820 
8821 
8822 /* =========================================================================================================================== */
8823 /* ================                                           UART0                                           ================ */
8824 /* =========================================================================================================================== */
8825 
8826 
8827 /**
8828   * @brief Serial UART (UART0)
8829   */
8830 
8831 typedef struct {                                /*!< (@ 0x4001C000) UART0 Structure                                            */
8832 
8833   union {
8834     __IOM uint32_t DR;                          /*!< (@ 0x00000000) UART Data                                                  */
8835 
8836     struct {
8837       __IOM uint32_t DATA       : 8;            /*!< [7..0] This is the UART data port.                                        */
8838       __IOM uint32_t FEDATA     : 1;            /*!< [8..8] This is the framing error indicator.                               */
8839       __IOM uint32_t PEDATA     : 1;            /*!< [9..9] This is the parity error indicator.                                */
8840       __IOM uint32_t BEDATA     : 1;            /*!< [10..10] This is the break error indicator.                               */
8841       __IOM uint32_t OEDATA     : 1;            /*!< [11..11] This is the overrun error indicator.                             */
8842             uint32_t            : 20;
8843     } DR_b;
8844   } ;
8845 
8846   union {
8847     __IOM uint32_t RSR;                         /*!< (@ 0x00000004) UART Status                                                */
8848 
8849     struct {
8850       __IOM uint32_t FESTAT     : 1;            /*!< [0..0] This is the framing error indicator.                               */
8851       __IOM uint32_t PESTAT     : 1;            /*!< [1..1] This is the parity error indicator.                                */
8852       __IOM uint32_t BESTAT     : 1;            /*!< [2..2] This is the break error indicator.                                 */
8853       __IOM uint32_t OESTAT     : 1;            /*!< [3..3] This is the overrun error indicator.                               */
8854             uint32_t            : 28;
8855     } RSR_b;
8856   } ;
8857   __IM  uint32_t  RESERVED[4];
8858 
8859   union {
8860     __IOM uint32_t FR;                          /*!< (@ 0x00000018) Flag                                                       */
8861 
8862     struct {
8863       __IOM uint32_t CTS        : 1;            /*!< [0..0] This bit holds the clear to send indicator.                        */
8864       __IOM uint32_t DSR        : 1;            /*!< [1..1] This bit holds the data set ready indicator.                       */
8865       __IOM uint32_t DCD        : 1;            /*!< [2..2] This bit holds the data carrier detect indicator.                  */
8866       __IOM uint32_t BUSY       : 1;            /*!< [3..3] This bit holds the busy indicator.                                 */
8867       __IOM uint32_t RXFE       : 1;            /*!< [4..4] This bit holds the receive FIFO empty indicator.                   */
8868       __IOM uint32_t TXFF       : 1;            /*!< [5..5] This bit holds the transmit FIFO full indicator.                   */
8869       __IOM uint32_t RXFF       : 1;            /*!< [6..6] This bit holds the receive FIFO full indicator.                    */
8870       __IOM uint32_t TXFE       : 1;            /*!< [7..7] This bit holds the transmit FIFO empty indicator.                  */
8871       __IOM uint32_t TXBUSY     : 1;            /*!< [8..8] This bit holds the transmit BUSY indicator.                        */
8872             uint32_t            : 23;
8873     } FR_b;
8874   } ;
8875   __IM  uint32_t  RESERVED1;
8876 
8877   union {
8878     __IOM uint32_t ILPR;                        /*!< (@ 0x00000020) IrDA Counter                                               */
8879 
8880     struct {
8881       __IOM uint32_t ILPDVSR    : 8;            /*!< [7..0] These bits hold the IrDA counter divisor.                          */
8882             uint32_t            : 24;
8883     } ILPR_b;
8884   } ;
8885 
8886   union {
8887     __IOM uint32_t IBRD;                        /*!< (@ 0x00000024) Integer Baud Rate Divisor                                  */
8888 
8889     struct {
8890       __IOM uint32_t DIVINT     : 16;           /*!< [15..0] These bits hold the baud integer divisor.                         */
8891             uint32_t            : 16;
8892     } IBRD_b;
8893   } ;
8894 
8895   union {
8896     __IOM uint32_t FBRD;                        /*!< (@ 0x00000028) Fractional Baud Rate Divisor                               */
8897 
8898     struct {
8899       __IOM uint32_t DIVFRAC    : 6;            /*!< [5..0] These bits hold the baud fractional divisor.                       */
8900             uint32_t            : 26;
8901     } FBRD_b;
8902   } ;
8903 
8904   union {
8905     __IOM uint32_t LCRH;                        /*!< (@ 0x0000002C) Line Control High                                          */
8906 
8907     struct {
8908       __IOM uint32_t BRK        : 1;            /*!< [0..0] This bit holds the break set.                                      */
8909       __IOM uint32_t PEN        : 1;            /*!< [1..1] This bit holds the parity enable.                                  */
8910       __IOM uint32_t EPS        : 1;            /*!< [2..2] This bit holds the even parity select.                             */
8911       __IOM uint32_t STP2       : 1;            /*!< [3..3] This bit holds the two stop bits select.                           */
8912       __IOM uint32_t FEN        : 1;            /*!< [4..4] This bit holds the FIFO enable.                                    */
8913       __IOM uint32_t WLEN       : 2;            /*!< [6..5] These bits hold the write length.                                  */
8914       __IOM uint32_t SPS        : 1;            /*!< [7..7] This bit holds the stick parity select.                            */
8915             uint32_t            : 24;
8916     } LCRH_b;
8917   } ;
8918 
8919   union {
8920     __IOM uint32_t CR;                          /*!< (@ 0x00000030) Control                                                    */
8921 
8922     struct {
8923       __IOM uint32_t UARTEN     : 1;            /*!< [0..0] This bit is the UART enable.                                       */
8924       __IOM uint32_t SIREN      : 1;            /*!< [1..1] This bit is the SIR ENDEC enable.                                  */
8925       __IOM uint32_t SIRLP      : 1;            /*!< [2..2] This bit is the SIR low power select.                              */
8926       __IOM uint32_t CLKEN      : 1;            /*!< [3..3] This bit is the UART clock enable.                                 */
8927       __IOM uint32_t CLKSEL     : 3;            /*!< [6..4] This bit field is the UART clock select.                           */
8928       __IOM uint32_t LBE        : 1;            /*!< [7..7] This bit is the loopback enable.                                   */
8929       __IOM uint32_t TXE        : 1;            /*!< [8..8] This bit is the transmit enable.                                   */
8930       __IOM uint32_t RXE        : 1;            /*!< [9..9] This bit is the receive enable.                                    */
8931       __IOM uint32_t DTR        : 1;            /*!< [10..10] This bit enables data transmit ready.                            */
8932       __IOM uint32_t RTS        : 1;            /*!< [11..11] This bit enables request to send.                                */
8933       __IOM uint32_t OUT1       : 1;            /*!< [12..12] This bit holds modem Out1.                                       */
8934       __IOM uint32_t OUT2       : 1;            /*!< [13..13] This bit holds modem Out2.                                       */
8935       __IOM uint32_t RTSEN      : 1;            /*!< [14..14] This bit enables RTS hardware flow control.                      */
8936       __IOM uint32_t CTSEN      : 1;            /*!< [15..15] This bit enables CTS hardware flow control.                      */
8937             uint32_t            : 16;
8938     } CR_b;
8939   } ;
8940 
8941   union {
8942     __IOM uint32_t IFLS;                        /*!< (@ 0x00000034) FIFO Interrupt Level Select                                */
8943 
8944     struct {
8945       __IOM uint32_t TXIFLSEL   : 3;            /*!< [2..0] These bits hold the transmit FIFO interrupt level.                 */
8946       __IOM uint32_t RXIFLSEL   : 3;            /*!< [5..3] These bits hold the receive FIFO interrupt level.                  */
8947             uint32_t            : 26;
8948     } IFLS_b;
8949   } ;
8950 
8951   union {
8952     __IOM uint32_t IER;                         /*!< (@ 0x00000038) Interrupt Enable                                           */
8953 
8954     struct {
8955       __IOM uint32_t TXCMPMIM   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt enable.                   */
8956       __IOM uint32_t CTSMIM     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt enable.                     */
8957       __IOM uint32_t DCDMIM     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt enable.                     */
8958       __IOM uint32_t DSRMIM     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt enable.                     */
8959       __IOM uint32_t RXIM       : 1;            /*!< [4..4] This bit holds the receive interrupt enable.                       */
8960       __IOM uint32_t TXIM       : 1;            /*!< [5..5] This bit holds the transmit interrupt enable.                      */
8961       __IOM uint32_t RTIM       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt enable.               */
8962       __IOM uint32_t FEIM       : 1;            /*!< [7..7] This bit holds the framing error interrupt enable.                 */
8963       __IOM uint32_t PEIM       : 1;            /*!< [8..8] This bit holds the parity error interrupt enable.                  */
8964       __IOM uint32_t BEIM       : 1;            /*!< [9..9] This bit holds the break error interrupt enable.                   */
8965       __IOM uint32_t OEIM       : 1;            /*!< [10..10] This bit holds the overflow interrupt enable.                    */
8966             uint32_t            : 21;
8967     } IER_b;
8968   } ;
8969 
8970   union {
8971     __IOM uint32_t IES;                         /*!< (@ 0x0000003C) Interrupt Status                                           */
8972 
8973     struct {
8974       __IOM uint32_t TXCMPMRIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status.                   */
8975       __IOM uint32_t CTSMRIS    : 1;            /*!< [1..1] This bit holds the modem CTS interrupt status.                     */
8976       __IOM uint32_t DCDMRIS    : 1;            /*!< [2..2] This bit holds the modem DCD interrupt status.                     */
8977       __IOM uint32_t DSRMRIS    : 1;            /*!< [3..3] This bit holds the modem DSR interrupt status.                     */
8978       __IOM uint32_t RXRIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status.                       */
8979       __IOM uint32_t TXRIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status.                      */
8980       __IOM uint32_t RTRIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status.               */
8981       __IOM uint32_t FERIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status.                 */
8982       __IOM uint32_t PERIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status.                  */
8983       __IOM uint32_t BERIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status.                   */
8984       __IOM uint32_t OERIS      : 1;            /*!< [10..10] This bit holds the overflow interrupt status.                    */
8985             uint32_t            : 21;
8986     } IES_b;
8987   } ;
8988 
8989   union {
8990     __IOM uint32_t MIS;                         /*!< (@ 0x00000040) Masked Interrupt Status                                    */
8991 
8992     struct {
8993       __IOM uint32_t TXCMPMMIS  : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt status masked.            */
8994       __IOM uint32_t CTSMMIS    : 1;            /*!< [1..1] This bit holds the modem CTS interrupt status masked.              */
8995       __IOM uint32_t DCDMMIS    : 1;            /*!< [2..2] This bit holds the modem DCD interrupt status masked.              */
8996       __IOM uint32_t DSRMMIS    : 1;            /*!< [3..3] This bit holds the modem DSR interrupt status masked.              */
8997       __IOM uint32_t RXMIS      : 1;            /*!< [4..4] This bit holds the receive interrupt status masked.                */
8998       __IOM uint32_t TXMIS      : 1;            /*!< [5..5] This bit holds the transmit interrupt status masked.               */
8999       __IOM uint32_t RTMIS      : 1;            /*!< [6..6] This bit holds the receive timeout interrupt status masked.        */
9000       __IOM uint32_t FEMIS      : 1;            /*!< [7..7] This bit holds the framing error interrupt status masked.          */
9001       __IOM uint32_t PEMIS      : 1;            /*!< [8..8] This bit holds the parity error interrupt status masked.           */
9002       __IOM uint32_t BEMIS      : 1;            /*!< [9..9] This bit holds the break error interrupt status masked.            */
9003       __IOM uint32_t OEMIS      : 1;            /*!< [10..10] This bit holds the overflow interrupt status masked.             */
9004             uint32_t            : 21;
9005     } MIS_b;
9006   } ;
9007 
9008   union {
9009     __IOM uint32_t IEC;                         /*!< (@ 0x00000044) Interrupt Clear                                            */
9010 
9011     struct {
9012       __IOM uint32_t TXCMPMIC   : 1;            /*!< [0..0] This bit holds the modem TXCMP interrupt clear.                    */
9013       __IOM uint32_t CTSMIC     : 1;            /*!< [1..1] This bit holds the modem CTS interrupt clear.                      */
9014       __IOM uint32_t DCDMIC     : 1;            /*!< [2..2] This bit holds the modem DCD interrupt clear.                      */
9015       __IOM uint32_t DSRMIC     : 1;            /*!< [3..3] This bit holds the modem DSR interrupt clear.                      */
9016       __IOM uint32_t RXIC       : 1;            /*!< [4..4] This bit holds the receive interrupt clear.                        */
9017       __IOM uint32_t TXIC       : 1;            /*!< [5..5] This bit holds the transmit interrupt clear.                       */
9018       __IOM uint32_t RTIC       : 1;            /*!< [6..6] This bit holds the receive timeout interrupt clear.                */
9019       __IOM uint32_t FEIC       : 1;            /*!< [7..7] This bit holds the framing error interrupt clear.                  */
9020       __IOM uint32_t PEIC       : 1;            /*!< [8..8] This bit holds the parity error interrupt clear.                   */
9021       __IOM uint32_t BEIC       : 1;            /*!< [9..9] This bit holds the break error interrupt clear.                    */
9022       __IOM uint32_t OEIC       : 1;            /*!< [10..10] This bit holds the overflow interrupt clear.                     */
9023             uint32_t            : 21;
9024     } IEC_b;
9025   } ;
9026 } UART0_Type;                                   /*!< Size = 72 (0x48)                                                          */
9027 
9028 
9029 
9030 /* =========================================================================================================================== */
9031 /* ================                                           VCOMP                                           ================ */
9032 /* =========================================================================================================================== */
9033 
9034 
9035 /**
9036   * @brief Voltage Comparator (VCOMP)
9037   */
9038 
9039 typedef struct {                                /*!< (@ 0x4000C000) VCOMP Structure                                            */
9040 
9041   union {
9042     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) The Voltage Comparator Configuration Register
9043                                                                     contains the software control for selecting
9044                                                                     between the 4 options for the positive input
9045                                                                     as well as the multiple options for the
9046                                                                     reference input.                                           */
9047 
9048     struct {
9049       __IOM uint32_t PSEL       : 2;            /*!< [1..0] This bit field selects the positive input to the comparator.       */
9050             uint32_t            : 6;
9051       __IOM uint32_t NSEL       : 2;            /*!< [9..8] This bit field selects the negative input to the comparator.       */
9052             uint32_t            : 6;
9053       __IOM uint32_t LVLSEL     : 4;            /*!< [19..16] When the reference input NSEL is set to NSEL_DAC, this
9054                                                      bit field selects the voltage level for the negative input
9055                                                      to the comparator.                                                        */
9056             uint32_t            : 12;
9057     } CFG_b;
9058   } ;
9059 
9060   union {
9061     __IOM uint32_t STAT;                        /*!< (@ 0x00000004) Status                                                     */
9062 
9063     struct {
9064       __IOM uint32_t CMPOUT     : 1;            /*!< [0..0] This bit is 1 if the positive input of the comparator
9065                                                      is greater than the negative input.                                       */
9066       __IOM uint32_t PWDSTAT    : 1;            /*!< [1..1] This bit indicates the power down state of the voltage
9067                                                      comparator.                                                               */
9068             uint32_t            : 30;
9069     } STAT_b;
9070   } ;
9071 
9072   union {
9073     __IOM uint32_t PWDKEY;                      /*!< (@ 0x00000008) Write a value of 0x37 to unlock, write any other
9074                                                                     value to lock. This register also indicates
9075                                                                     lock status when read. When in the unlocked
9076                                                                     state (i.e. 0x37 has been written), it reads
9077                                                                     as 1. When in the locked state, it reads
9078                                                                     as 0.                                                      */
9079 
9080     struct {
9081       __IOM uint32_t PWDKEY     : 32;           /*!< [31..0] Key register value.                                               */
9082     } PWDKEY_b;
9083   } ;
9084   __IM  uint32_t  RESERVED[125];
9085 
9086   union {
9087     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
9088                                                                     to generate the corresponding interrupt.                   */
9089 
9090     struct {
9091       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
9092       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
9093             uint32_t            : 30;
9094     } INTEN_b;
9095   } ;
9096 
9097   union {
9098     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
9099                                                                     cause of a recent interrupt.                               */
9100 
9101     struct {
9102       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
9103       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
9104             uint32_t            : 30;
9105     } INTSTAT_b;
9106   } ;
9107 
9108   union {
9109     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
9110                                                                     the interrupt status associated with that
9111                                                                     bit.                                                       */
9112 
9113     struct {
9114       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
9115       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
9116             uint32_t            : 30;
9117     } INTCLR_b;
9118   } ;
9119 
9120   union {
9121     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
9122                                                                     generate an interrupt from this module.
9123                                                                     (Generally used for testing purposes).                     */
9124 
9125     struct {
9126       __IOM uint32_t OUTLOW     : 1;            /*!< [0..0] This bit is the vcompout low interrupt.                            */
9127       __IOM uint32_t OUTHI      : 1;            /*!< [1..1] This bit is the vcompout high interrupt.                           */
9128             uint32_t            : 30;
9129     } INTSET_b;
9130   } ;
9131 } VCOMP_Type;                                   /*!< Size = 528 (0x210)                                                        */
9132 
9133 
9134 
9135 /* =========================================================================================================================== */
9136 /* ================                                            WDT                                            ================ */
9137 /* =========================================================================================================================== */
9138 
9139 
9140 /**
9141   * @brief Watchdog Timer (WDT)
9142   */
9143 
9144 typedef struct {                                /*!< (@ 0x40024000) WDT Structure                                              */
9145 
9146   union {
9147     __IOM uint32_t CFG;                         /*!< (@ 0x00000000) This is the configuration register for the watch
9148                                                                     dog timer. It controls the enable, interrupt
9149                                                                     set, clocks for the timer, the compare values
9150                                                                     for the counters to trigger a reset or interrupt.
9151                                                                     This register can only be written to if
9152                                                                     the watch dog timer is unlocked (WDTLOCK
9153                                                                     is not set).                                               */
9154 
9155     struct {
9156       __IOM uint32_t WDTEN      : 1;            /*!< [0..0] This bit field enables the WDT.                                    */
9157       __IOM uint32_t INTEN      : 1;            /*!< [1..1] This bit field enables the WDT interrupt. Note : This
9158                                                      bit must be set before the interrupt status bit will reflect
9159                                                      a watchdog timer expiration. The IER interrupt register
9160                                                      must also be enabled for a WDT interrupt to be sent to
9161                                                      the NVIC.                                                                 */
9162       __IOM uint32_t RESEN      : 1;            /*!< [2..2] This bit field enables the WDT reset. This needs to be
9163                                                      set together with the WDREN bit in REG_RSTGEN_CFG register
9164                                                      (in reset gen) to trigger the reset.                                      */
9165             uint32_t            : 5;
9166       __IOM uint32_t RESVAL     : 8;            /*!< [15..8] This bit field is the compare value for counter bits
9167                                                      7:0 to generate a watchdog reset. This will cause a software
9168                                                      reset.                                                                    */
9169       __IOM uint32_t INTVAL     : 8;            /*!< [23..16] This bit field is the compare value for counter bits
9170                                                      7:0 to generate a watchdog interrupt.                                     */
9171       __IOM uint32_t CLKSEL     : 3;            /*!< [26..24] Select the frequency for the WDT. All values not enumerated
9172                                                      below are undefined.                                                      */
9173             uint32_t            : 5;
9174     } CFG_b;
9175   } ;
9176 
9177   union {
9178     __IOM uint32_t RSTRT;                       /*!< (@ 0x00000004) This register will Restart the watchdog timer.
9179                                                                     Writing a special key value into this register
9180                                                                     will result in the watch dog timer being
9181                                                                     reset, so that the count will start again.
9182                                                                     It is expected that the software will periodically
9183                                                                     write to this register to indicate that
9184                                                                     the system is functional. The watch dog
9185                                                                     timer can continue running when the system
9186                                                                     is in deep sleep, and the interrupt will
9187                                                                     trigger the wake. After the wake, the core
9188                                                                     can reset the watch dog timer.                             */
9189 
9190     struct {
9191       __IOM uint32_t RSTRT      : 8;            /*!< [7..0] Writing 0xB2 to WDTRSTRT restarts the watchdog timer.
9192                                                      This is a write only register. Reading this register will
9193                                                      only provide all 0.                                                       */
9194             uint32_t            : 24;
9195     } RSTRT_b;
9196   } ;
9197 
9198   union {
9199     __IOM uint32_t LOCK;                        /*!< (@ 0x00000008) This register locks the watch dog timer. Once
9200                                                                     it is locked, the configuration register
9201                                                                     (WDTCFG) for watch dog timer cannot be written
9202                                                                     to.                                                        */
9203 
9204     struct {
9205       __IOM uint32_t LOCK       : 8;            /*!< [7..0] Writing 0x3A locks the watchdog timer. Once locked, the
9206                                                      WDTCFG reg cannot be written and WDTEN is set.                            */
9207             uint32_t            : 24;
9208     } LOCK_b;
9209   } ;
9210 
9211   union {
9212     __IOM uint32_t COUNT;                       /*!< (@ 0x0000000C) This register holds the current count for the
9213                                                                     watch dog timer. This is a read only register.
9214                                                                     SW cannot set the value in the counter,
9215                                                                     but can reset it.                                          */
9216 
9217     struct {
9218       __IOM uint32_t COUNT      : 8;            /*!< [7..0] Read-Only current value of the WDT counter                         */
9219             uint32_t            : 24;
9220     } COUNT_b;
9221   } ;
9222   __IM  uint32_t  RESERVED[124];
9223 
9224   union {
9225     __IOM uint32_t INTEN;                       /*!< (@ 0x00000200) Set bits in this register to allow this module
9226                                                                     to generate the corresponding interrupt.                   */
9227 
9228     struct {
9229       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
9230             uint32_t            : 31;
9231     } INTEN_b;
9232   } ;
9233 
9234   union {
9235     __IOM uint32_t INTSTAT;                     /*!< (@ 0x00000204) Read bits from this register to discover the
9236                                                                     cause of a recent interrupt.                               */
9237 
9238     struct {
9239       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
9240             uint32_t            : 31;
9241     } INTSTAT_b;
9242   } ;
9243 
9244   union {
9245     __IOM uint32_t INTCLR;                      /*!< (@ 0x00000208) Write a 1 to a bit in this register to clear
9246                                                                     the interrupt status associated with that
9247                                                                     bit.                                                       */
9248 
9249     struct {
9250       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
9251             uint32_t            : 31;
9252     } INTCLR_b;
9253   } ;
9254 
9255   union {
9256     __IOM uint32_t INTSET;                      /*!< (@ 0x0000020C) Write a 1 to a bit in this register to instantly
9257                                                                     generate an interrupt from this module.
9258                                                                     (Generally used for testing purposes).                     */
9259 
9260     struct {
9261       __IOM uint32_t WDTINT     : 1;            /*!< [0..0] Watchdog Timer Interrupt.                                          */
9262             uint32_t            : 31;
9263     } INTSET_b;
9264   } ;
9265 } WDT_Type;                                     /*!< Size = 528 (0x210)                                                        */
9266 
9267 
9268 /** @} */ /* End of group Device_Peripheral_peripherals */
9269 
9270 
9271 /* =========================================================================================================================== */
9272 /* ================                          Device Specific Peripheral Address Map                           ================ */
9273 /* =========================================================================================================================== */
9274 
9275 
9276 /** @addtogroup Device_Peripheral_peripheralAddr
9277   * @{
9278   */
9279 
9280 #define ADC_BASE                    0x50010000UL
9281 #define APBDMA_BASE                 0x40011000UL
9282 #define BLEIF_BASE                  0x5000C000UL
9283 #define CACHECTRL_BASE              0x40018000UL
9284 #define CLKGEN_BASE                 0x40004000UL
9285 #define CTIMER_BASE                 0x40008000UL
9286 #define GPIO_BASE                   0x40010000UL
9287 #define IOM0_BASE                   0x50004000UL
9288 #define IOM1_BASE                   0x50005000UL
9289 #define IOM2_BASE                   0x50006000UL
9290 #define IOM3_BASE                   0x50007000UL
9291 #define IOM4_BASE                   0x50008000UL
9292 #define IOM5_BASE                   0x50009000UL
9293 #define IOSLAVE_BASE                0x50000000UL
9294 #define MCUCTRL_BASE                0x40020000UL
9295 #define MSPI_BASE                   0x50014000UL
9296 #define PDM_BASE                    0x50011000UL
9297 #define PWRCTRL_BASE                0x40021000UL
9298 #define RSTGEN_BASE                 0x40000000UL
9299 #define RTC_BASE                    0x40004200UL
9300 #define SCARD_BASE                  0x40080000UL
9301 #define SECURITY_BASE               0x40030000UL
9302 #define UART0_BASE                  0x4001C000UL
9303 #define UART1_BASE                  0x4001D000UL
9304 #define VCOMP_BASE                  0x4000C000UL
9305 #define WDT_BASE                    0x40024000UL
9306 
9307 /** @} */ /* End of group Device_Peripheral_peripheralAddr */
9308 
9309 
9310 /* =========================================================================================================================== */
9311 /* ================                                  Peripheral declaration                                   ================ */
9312 /* =========================================================================================================================== */
9313 
9314 
9315 /** @addtogroup Device_Peripheral_declaration
9316   * @{
9317   */
9318 
9319 #define ADC                         ((ADC_Type*)               ADC_BASE)
9320 #define APBDMA                      ((APBDMA_Type*)            APBDMA_BASE)
9321 #define BLEIF                       ((BLEIF_Type*)             BLEIF_BASE)
9322 #define CACHECTRL                   ((CACHECTRL_Type*)         CACHECTRL_BASE)
9323 #define CLKGEN                      ((CLKGEN_Type*)            CLKGEN_BASE)
9324 #define CTIMER                      ((CTIMER_Type*)            CTIMER_BASE)
9325 #define GPIO                        ((GPIO_Type*)              GPIO_BASE)
9326 #define IOM0                        ((IOM0_Type*)              IOM0_BASE)
9327 #define IOM1                        ((IOM0_Type*)              IOM1_BASE)
9328 #define IOM2                        ((IOM0_Type*)              IOM2_BASE)
9329 #define IOM3                        ((IOM0_Type*)              IOM3_BASE)
9330 #define IOM4                        ((IOM0_Type*)              IOM4_BASE)
9331 #define IOM5                        ((IOM0_Type*)              IOM5_BASE)
9332 #define IOSLAVE                     ((IOSLAVE_Type*)           IOSLAVE_BASE)
9333 #define MCUCTRL                     ((MCUCTRL_Type*)           MCUCTRL_BASE)
9334 #define MSPI                        ((MSPI_Type*)              MSPI_BASE)
9335 #define PDM                         ((PDM_Type*)               PDM_BASE)
9336 #define PWRCTRL                     ((PWRCTRL_Type*)           PWRCTRL_BASE)
9337 #define RSTGEN                      ((RSTGEN_Type*)            RSTGEN_BASE)
9338 #define RTC                         ((RTC_Type*)               RTC_BASE)
9339 #define SCARD                       ((SCARD_Type*)             SCARD_BASE)
9340 #define SECURITY                    ((SECURITY_Type*)          SECURITY_BASE)
9341 #define UART0                       ((UART0_Type*)             UART0_BASE)
9342 #define UART1                       ((UART0_Type*)             UART1_BASE)
9343 #define VCOMP                       ((VCOMP_Type*)             VCOMP_BASE)
9344 #define WDT                         ((WDT_Type*)               WDT_BASE)
9345 
9346 /** @} */ /* End of group Device_Peripheral_declaration */
9347 
9348 
9349 /* =========================================  End of section using anonymous unions  ========================================= */
9350 #if defined (__CC_ARM)
9351   #pragma pop
9352 #elif defined (__ICCARM__)
9353   /* leave anonymous unions enabled */
9354 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
9355   #pragma clang diagnostic pop
9356 #elif defined (__GNUC__)
9357   /* anonymous unions are enabled by default */
9358 #elif defined (__TMS470__)
9359   /* anonymous unions are enabled by default */
9360 #elif defined (__TASKING__)
9361   #pragma warning restore
9362 #elif defined (__CSMC__)
9363   /* anonymous unions are enabled by default */
9364 #endif
9365 
9366 
9367 /* =========================================================================================================================== */
9368 /* ================                                Pos/Mask Peripheral Section                                ================ */
9369 /* =========================================================================================================================== */
9370 
9371 
9372 /** @addtogroup PosMask_peripherals
9373   * @{
9374   */
9375 
9376 
9377 
9378 /* =========================================================================================================================== */
9379 /* ================                                            ADC                                            ================ */
9380 /* =========================================================================================================================== */
9381 
9382 /* ==========================================================  CFG  ========================================================== */
9383 #define ADC_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
9384 #define ADC_CFG_CLKSEL_Msk                (0x3000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x03)                          */
9385 #define ADC_CFG_TRIGPOL_Pos               (19UL)                    /*!< TRIGPOL (Bit 19)                                      */
9386 #define ADC_CFG_TRIGPOL_Msk               (0x80000UL)               /*!< TRIGPOL (Bitfield-Mask: 0x01)                         */
9387 #define ADC_CFG_TRIGSEL_Pos               (16UL)                    /*!< TRIGSEL (Bit 16)                                      */
9388 #define ADC_CFG_TRIGSEL_Msk               (0x70000UL)               /*!< TRIGSEL (Bitfield-Mask: 0x07)                         */
9389 #define ADC_CFG_DFIFORDEN_Pos             (12UL)                    /*!< DFIFORDEN (Bit 12)                                    */
9390 #define ADC_CFG_DFIFORDEN_Msk             (0x1000UL)                /*!< DFIFORDEN (Bitfield-Mask: 0x01)                       */
9391 #define ADC_CFG_REFSEL_Pos                (8UL)                     /*!< REFSEL (Bit 8)                                        */
9392 #define ADC_CFG_REFSEL_Msk                (0x300UL)                 /*!< REFSEL (Bitfield-Mask: 0x03)                          */
9393 #define ADC_CFG_CKMODE_Pos                (4UL)                     /*!< CKMODE (Bit 4)                                        */
9394 #define ADC_CFG_CKMODE_Msk                (0x10UL)                  /*!< CKMODE (Bitfield-Mask: 0x01)                          */
9395 #define ADC_CFG_LPMODE_Pos                (3UL)                     /*!< LPMODE (Bit 3)                                        */
9396 #define ADC_CFG_LPMODE_Msk                (0x8UL)                   /*!< LPMODE (Bitfield-Mask: 0x01)                          */
9397 #define ADC_CFG_RPTEN_Pos                 (2UL)                     /*!< RPTEN (Bit 2)                                         */
9398 #define ADC_CFG_RPTEN_Msk                 (0x4UL)                   /*!< RPTEN (Bitfield-Mask: 0x01)                           */
9399 #define ADC_CFG_ADCEN_Pos                 (0UL)                     /*!< ADCEN (Bit 0)                                         */
9400 #define ADC_CFG_ADCEN_Msk                 (0x1UL)                   /*!< ADCEN (Bitfield-Mask: 0x01)                           */
9401 /* =========================================================  STAT  ========================================================== */
9402 #define ADC_STAT_PWDSTAT_Pos              (0UL)                     /*!< PWDSTAT (Bit 0)                                       */
9403 #define ADC_STAT_PWDSTAT_Msk              (0x1UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
9404 /* ==========================================================  SWT  ========================================================== */
9405 #define ADC_SWT_SWT_Pos                   (0UL)                     /*!< SWT (Bit 0)                                           */
9406 #define ADC_SWT_SWT_Msk                   (0xffUL)                  /*!< SWT (Bitfield-Mask: 0xff)                             */
9407 /* ========================================================  SL0CFG  ========================================================= */
9408 #define ADC_SL0CFG_ADSEL0_Pos             (24UL)                    /*!< ADSEL0 (Bit 24)                                       */
9409 #define ADC_SL0CFG_ADSEL0_Msk             (0x7000000UL)             /*!< ADSEL0 (Bitfield-Mask: 0x07)                          */
9410 #define ADC_SL0CFG_PRMODE0_Pos            (16UL)                    /*!< PRMODE0 (Bit 16)                                      */
9411 #define ADC_SL0CFG_PRMODE0_Msk            (0x30000UL)               /*!< PRMODE0 (Bitfield-Mask: 0x03)                         */
9412 #define ADC_SL0CFG_CHSEL0_Pos             (8UL)                     /*!< CHSEL0 (Bit 8)                                        */
9413 #define ADC_SL0CFG_CHSEL0_Msk             (0xf00UL)                 /*!< CHSEL0 (Bitfield-Mask: 0x0f)                          */
9414 #define ADC_SL0CFG_WCEN0_Pos              (1UL)                     /*!< WCEN0 (Bit 1)                                         */
9415 #define ADC_SL0CFG_WCEN0_Msk              (0x2UL)                   /*!< WCEN0 (Bitfield-Mask: 0x01)                           */
9416 #define ADC_SL0CFG_SLEN0_Pos              (0UL)                     /*!< SLEN0 (Bit 0)                                         */
9417 #define ADC_SL0CFG_SLEN0_Msk              (0x1UL)                   /*!< SLEN0 (Bitfield-Mask: 0x01)                           */
9418 /* ========================================================  SL1CFG  ========================================================= */
9419 #define ADC_SL1CFG_ADSEL1_Pos             (24UL)                    /*!< ADSEL1 (Bit 24)                                       */
9420 #define ADC_SL1CFG_ADSEL1_Msk             (0x7000000UL)             /*!< ADSEL1 (Bitfield-Mask: 0x07)                          */
9421 #define ADC_SL1CFG_PRMODE1_Pos            (16UL)                    /*!< PRMODE1 (Bit 16)                                      */
9422 #define ADC_SL1CFG_PRMODE1_Msk            (0x30000UL)               /*!< PRMODE1 (Bitfield-Mask: 0x03)                         */
9423 #define ADC_SL1CFG_CHSEL1_Pos             (8UL)                     /*!< CHSEL1 (Bit 8)                                        */
9424 #define ADC_SL1CFG_CHSEL1_Msk             (0xf00UL)                 /*!< CHSEL1 (Bitfield-Mask: 0x0f)                          */
9425 #define ADC_SL1CFG_WCEN1_Pos              (1UL)                     /*!< WCEN1 (Bit 1)                                         */
9426 #define ADC_SL1CFG_WCEN1_Msk              (0x2UL)                   /*!< WCEN1 (Bitfield-Mask: 0x01)                           */
9427 #define ADC_SL1CFG_SLEN1_Pos              (0UL)                     /*!< SLEN1 (Bit 0)                                         */
9428 #define ADC_SL1CFG_SLEN1_Msk              (0x1UL)                   /*!< SLEN1 (Bitfield-Mask: 0x01)                           */
9429 /* ========================================================  SL2CFG  ========================================================= */
9430 #define ADC_SL2CFG_ADSEL2_Pos             (24UL)                    /*!< ADSEL2 (Bit 24)                                       */
9431 #define ADC_SL2CFG_ADSEL2_Msk             (0x7000000UL)             /*!< ADSEL2 (Bitfield-Mask: 0x07)                          */
9432 #define ADC_SL2CFG_PRMODE2_Pos            (16UL)                    /*!< PRMODE2 (Bit 16)                                      */
9433 #define ADC_SL2CFG_PRMODE2_Msk            (0x30000UL)               /*!< PRMODE2 (Bitfield-Mask: 0x03)                         */
9434 #define ADC_SL2CFG_CHSEL2_Pos             (8UL)                     /*!< CHSEL2 (Bit 8)                                        */
9435 #define ADC_SL2CFG_CHSEL2_Msk             (0xf00UL)                 /*!< CHSEL2 (Bitfield-Mask: 0x0f)                          */
9436 #define ADC_SL2CFG_WCEN2_Pos              (1UL)                     /*!< WCEN2 (Bit 1)                                         */
9437 #define ADC_SL2CFG_WCEN2_Msk              (0x2UL)                   /*!< WCEN2 (Bitfield-Mask: 0x01)                           */
9438 #define ADC_SL2CFG_SLEN2_Pos              (0UL)                     /*!< SLEN2 (Bit 0)                                         */
9439 #define ADC_SL2CFG_SLEN2_Msk              (0x1UL)                   /*!< SLEN2 (Bitfield-Mask: 0x01)                           */
9440 /* ========================================================  SL3CFG  ========================================================= */
9441 #define ADC_SL3CFG_ADSEL3_Pos             (24UL)                    /*!< ADSEL3 (Bit 24)                                       */
9442 #define ADC_SL3CFG_ADSEL3_Msk             (0x7000000UL)             /*!< ADSEL3 (Bitfield-Mask: 0x07)                          */
9443 #define ADC_SL3CFG_PRMODE3_Pos            (16UL)                    /*!< PRMODE3 (Bit 16)                                      */
9444 #define ADC_SL3CFG_PRMODE3_Msk            (0x30000UL)               /*!< PRMODE3 (Bitfield-Mask: 0x03)                         */
9445 #define ADC_SL3CFG_CHSEL3_Pos             (8UL)                     /*!< CHSEL3 (Bit 8)                                        */
9446 #define ADC_SL3CFG_CHSEL3_Msk             (0xf00UL)                 /*!< CHSEL3 (Bitfield-Mask: 0x0f)                          */
9447 #define ADC_SL3CFG_WCEN3_Pos              (1UL)                     /*!< WCEN3 (Bit 1)                                         */
9448 #define ADC_SL3CFG_WCEN3_Msk              (0x2UL)                   /*!< WCEN3 (Bitfield-Mask: 0x01)                           */
9449 #define ADC_SL3CFG_SLEN3_Pos              (0UL)                     /*!< SLEN3 (Bit 0)                                         */
9450 #define ADC_SL3CFG_SLEN3_Msk              (0x1UL)                   /*!< SLEN3 (Bitfield-Mask: 0x01)                           */
9451 /* ========================================================  SL4CFG  ========================================================= */
9452 #define ADC_SL4CFG_ADSEL4_Pos             (24UL)                    /*!< ADSEL4 (Bit 24)                                       */
9453 #define ADC_SL4CFG_ADSEL4_Msk             (0x7000000UL)             /*!< ADSEL4 (Bitfield-Mask: 0x07)                          */
9454 #define ADC_SL4CFG_PRMODE4_Pos            (16UL)                    /*!< PRMODE4 (Bit 16)                                      */
9455 #define ADC_SL4CFG_PRMODE4_Msk            (0x30000UL)               /*!< PRMODE4 (Bitfield-Mask: 0x03)                         */
9456 #define ADC_SL4CFG_CHSEL4_Pos             (8UL)                     /*!< CHSEL4 (Bit 8)                                        */
9457 #define ADC_SL4CFG_CHSEL4_Msk             (0xf00UL)                 /*!< CHSEL4 (Bitfield-Mask: 0x0f)                          */
9458 #define ADC_SL4CFG_WCEN4_Pos              (1UL)                     /*!< WCEN4 (Bit 1)                                         */
9459 #define ADC_SL4CFG_WCEN4_Msk              (0x2UL)                   /*!< WCEN4 (Bitfield-Mask: 0x01)                           */
9460 #define ADC_SL4CFG_SLEN4_Pos              (0UL)                     /*!< SLEN4 (Bit 0)                                         */
9461 #define ADC_SL4CFG_SLEN4_Msk              (0x1UL)                   /*!< SLEN4 (Bitfield-Mask: 0x01)                           */
9462 /* ========================================================  SL5CFG  ========================================================= */
9463 #define ADC_SL5CFG_ADSEL5_Pos             (24UL)                    /*!< ADSEL5 (Bit 24)                                       */
9464 #define ADC_SL5CFG_ADSEL5_Msk             (0x7000000UL)             /*!< ADSEL5 (Bitfield-Mask: 0x07)                          */
9465 #define ADC_SL5CFG_PRMODE5_Pos            (16UL)                    /*!< PRMODE5 (Bit 16)                                      */
9466 #define ADC_SL5CFG_PRMODE5_Msk            (0x30000UL)               /*!< PRMODE5 (Bitfield-Mask: 0x03)                         */
9467 #define ADC_SL5CFG_CHSEL5_Pos             (8UL)                     /*!< CHSEL5 (Bit 8)                                        */
9468 #define ADC_SL5CFG_CHSEL5_Msk             (0xf00UL)                 /*!< CHSEL5 (Bitfield-Mask: 0x0f)                          */
9469 #define ADC_SL5CFG_WCEN5_Pos              (1UL)                     /*!< WCEN5 (Bit 1)                                         */
9470 #define ADC_SL5CFG_WCEN5_Msk              (0x2UL)                   /*!< WCEN5 (Bitfield-Mask: 0x01)                           */
9471 #define ADC_SL5CFG_SLEN5_Pos              (0UL)                     /*!< SLEN5 (Bit 0)                                         */
9472 #define ADC_SL5CFG_SLEN5_Msk              (0x1UL)                   /*!< SLEN5 (Bitfield-Mask: 0x01)                           */
9473 /* ========================================================  SL6CFG  ========================================================= */
9474 #define ADC_SL6CFG_ADSEL6_Pos             (24UL)                    /*!< ADSEL6 (Bit 24)                                       */
9475 #define ADC_SL6CFG_ADSEL6_Msk             (0x7000000UL)             /*!< ADSEL6 (Bitfield-Mask: 0x07)                          */
9476 #define ADC_SL6CFG_PRMODE6_Pos            (16UL)                    /*!< PRMODE6 (Bit 16)                                      */
9477 #define ADC_SL6CFG_PRMODE6_Msk            (0x30000UL)               /*!< PRMODE6 (Bitfield-Mask: 0x03)                         */
9478 #define ADC_SL6CFG_CHSEL6_Pos             (8UL)                     /*!< CHSEL6 (Bit 8)                                        */
9479 #define ADC_SL6CFG_CHSEL6_Msk             (0xf00UL)                 /*!< CHSEL6 (Bitfield-Mask: 0x0f)                          */
9480 #define ADC_SL6CFG_WCEN6_Pos              (1UL)                     /*!< WCEN6 (Bit 1)                                         */
9481 #define ADC_SL6CFG_WCEN6_Msk              (0x2UL)                   /*!< WCEN6 (Bitfield-Mask: 0x01)                           */
9482 #define ADC_SL6CFG_SLEN6_Pos              (0UL)                     /*!< SLEN6 (Bit 0)                                         */
9483 #define ADC_SL6CFG_SLEN6_Msk              (0x1UL)                   /*!< SLEN6 (Bitfield-Mask: 0x01)                           */
9484 /* ========================================================  SL7CFG  ========================================================= */
9485 #define ADC_SL7CFG_ADSEL7_Pos             (24UL)                    /*!< ADSEL7 (Bit 24)                                       */
9486 #define ADC_SL7CFG_ADSEL7_Msk             (0x7000000UL)             /*!< ADSEL7 (Bitfield-Mask: 0x07)                          */
9487 #define ADC_SL7CFG_PRMODE7_Pos            (16UL)                    /*!< PRMODE7 (Bit 16)                                      */
9488 #define ADC_SL7CFG_PRMODE7_Msk            (0x30000UL)               /*!< PRMODE7 (Bitfield-Mask: 0x03)                         */
9489 #define ADC_SL7CFG_CHSEL7_Pos             (8UL)                     /*!< CHSEL7 (Bit 8)                                        */
9490 #define ADC_SL7CFG_CHSEL7_Msk             (0xf00UL)                 /*!< CHSEL7 (Bitfield-Mask: 0x0f)                          */
9491 #define ADC_SL7CFG_WCEN7_Pos              (1UL)                     /*!< WCEN7 (Bit 1)                                         */
9492 #define ADC_SL7CFG_WCEN7_Msk              (0x2UL)                   /*!< WCEN7 (Bitfield-Mask: 0x01)                           */
9493 #define ADC_SL7CFG_SLEN7_Pos              (0UL)                     /*!< SLEN7 (Bit 0)                                         */
9494 #define ADC_SL7CFG_SLEN7_Msk              (0x1UL)                   /*!< SLEN7 (Bitfield-Mask: 0x01)                           */
9495 /* =========================================================  WULIM  ========================================================= */
9496 #define ADC_WULIM_ULIM_Pos                (0UL)                     /*!< ULIM (Bit 0)                                          */
9497 #define ADC_WULIM_ULIM_Msk                (0xfffffUL)               /*!< ULIM (Bitfield-Mask: 0xfffff)                         */
9498 /* =========================================================  WLLIM  ========================================================= */
9499 #define ADC_WLLIM_LLIM_Pos                (0UL)                     /*!< LLIM (Bit 0)                                          */
9500 #define ADC_WLLIM_LLIM_Msk                (0xfffffUL)               /*!< LLIM (Bitfield-Mask: 0xfffff)                         */
9501 /* ========================================================  SCWLIM  ========================================================= */
9502 #define ADC_SCWLIM_SCWLIMEN_Pos           (0UL)                     /*!< SCWLIMEN (Bit 0)                                      */
9503 #define ADC_SCWLIM_SCWLIMEN_Msk           (0x1UL)                   /*!< SCWLIMEN (Bitfield-Mask: 0x01)                        */
9504 /* =========================================================  FIFO  ========================================================== */
9505 #define ADC_FIFO_RSVD_Pos                 (31UL)                    /*!< RSVD (Bit 31)                                         */
9506 #define ADC_FIFO_RSVD_Msk                 (0x80000000UL)            /*!< RSVD (Bitfield-Mask: 0x01)                            */
9507 #define ADC_FIFO_SLOTNUM_Pos              (28UL)                    /*!< SLOTNUM (Bit 28)                                      */
9508 #define ADC_FIFO_SLOTNUM_Msk              (0x70000000UL)            /*!< SLOTNUM (Bitfield-Mask: 0x07)                         */
9509 #define ADC_FIFO_COUNT_Pos                (20UL)                    /*!< COUNT (Bit 20)                                        */
9510 #define ADC_FIFO_COUNT_Msk                (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
9511 #define ADC_FIFO_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
9512 #define ADC_FIFO_DATA_Msk                 (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
9513 /* ========================================================  FIFOPR  ========================================================= */
9514 #define ADC_FIFOPR_RSVDPR_Pos             (31UL)                    /*!< RSVDPR (Bit 31)                                       */
9515 #define ADC_FIFOPR_RSVDPR_Msk             (0x80000000UL)            /*!< RSVDPR (Bitfield-Mask: 0x01)                          */
9516 #define ADC_FIFOPR_SLOTNUMPR_Pos          (28UL)                    /*!< SLOTNUMPR (Bit 28)                                    */
9517 #define ADC_FIFOPR_SLOTNUMPR_Msk          (0x70000000UL)            /*!< SLOTNUMPR (Bitfield-Mask: 0x07)                       */
9518 #define ADC_FIFOPR_COUNT_Pos              (20UL)                    /*!< COUNT (Bit 20)                                        */
9519 #define ADC_FIFOPR_COUNT_Msk              (0xff00000UL)             /*!< COUNT (Bitfield-Mask: 0xff)                           */
9520 #define ADC_FIFOPR_DATA_Pos               (0UL)                     /*!< DATA (Bit 0)                                          */
9521 #define ADC_FIFOPR_DATA_Msk               (0xfffffUL)               /*!< DATA (Bitfield-Mask: 0xfffff)                         */
9522 /* =========================================================  INTEN  ========================================================= */
9523 #define ADC_INTEN_DERR_Pos                (7UL)                     /*!< DERR (Bit 7)                                          */
9524 #define ADC_INTEN_DERR_Msk                (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
9525 #define ADC_INTEN_DCMP_Pos                (6UL)                     /*!< DCMP (Bit 6)                                          */
9526 #define ADC_INTEN_DCMP_Msk                (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
9527 #define ADC_INTEN_WCINC_Pos               (5UL)                     /*!< WCINC (Bit 5)                                         */
9528 #define ADC_INTEN_WCINC_Msk               (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
9529 #define ADC_INTEN_WCEXC_Pos               (4UL)                     /*!< WCEXC (Bit 4)                                         */
9530 #define ADC_INTEN_WCEXC_Msk               (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
9531 #define ADC_INTEN_FIFOOVR2_Pos            (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
9532 #define ADC_INTEN_FIFOOVR2_Msk            (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
9533 #define ADC_INTEN_FIFOOVR1_Pos            (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
9534 #define ADC_INTEN_FIFOOVR1_Msk            (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
9535 #define ADC_INTEN_SCNCMP_Pos              (1UL)                     /*!< SCNCMP (Bit 1)                                        */
9536 #define ADC_INTEN_SCNCMP_Msk              (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
9537 #define ADC_INTEN_CNVCMP_Pos              (0UL)                     /*!< CNVCMP (Bit 0)                                        */
9538 #define ADC_INTEN_CNVCMP_Msk              (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
9539 /* ========================================================  INTSTAT  ======================================================== */
9540 #define ADC_INTSTAT_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
9541 #define ADC_INTSTAT_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
9542 #define ADC_INTSTAT_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
9543 #define ADC_INTSTAT_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
9544 #define ADC_INTSTAT_WCINC_Pos             (5UL)                     /*!< WCINC (Bit 5)                                         */
9545 #define ADC_INTSTAT_WCINC_Msk             (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
9546 #define ADC_INTSTAT_WCEXC_Pos             (4UL)                     /*!< WCEXC (Bit 4)                                         */
9547 #define ADC_INTSTAT_WCEXC_Msk             (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
9548 #define ADC_INTSTAT_FIFOOVR2_Pos          (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
9549 #define ADC_INTSTAT_FIFOOVR2_Msk          (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
9550 #define ADC_INTSTAT_FIFOOVR1_Pos          (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
9551 #define ADC_INTSTAT_FIFOOVR1_Msk          (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
9552 #define ADC_INTSTAT_SCNCMP_Pos            (1UL)                     /*!< SCNCMP (Bit 1)                                        */
9553 #define ADC_INTSTAT_SCNCMP_Msk            (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
9554 #define ADC_INTSTAT_CNVCMP_Pos            (0UL)                     /*!< CNVCMP (Bit 0)                                        */
9555 #define ADC_INTSTAT_CNVCMP_Msk            (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
9556 /* ========================================================  INTCLR  ========================================================= */
9557 #define ADC_INTCLR_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
9558 #define ADC_INTCLR_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
9559 #define ADC_INTCLR_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
9560 #define ADC_INTCLR_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
9561 #define ADC_INTCLR_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
9562 #define ADC_INTCLR_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
9563 #define ADC_INTCLR_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
9564 #define ADC_INTCLR_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
9565 #define ADC_INTCLR_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
9566 #define ADC_INTCLR_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
9567 #define ADC_INTCLR_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
9568 #define ADC_INTCLR_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
9569 #define ADC_INTCLR_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
9570 #define ADC_INTCLR_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
9571 #define ADC_INTCLR_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
9572 #define ADC_INTCLR_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
9573 /* ========================================================  INTSET  ========================================================= */
9574 #define ADC_INTSET_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
9575 #define ADC_INTSET_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
9576 #define ADC_INTSET_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
9577 #define ADC_INTSET_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
9578 #define ADC_INTSET_WCINC_Pos              (5UL)                     /*!< WCINC (Bit 5)                                         */
9579 #define ADC_INTSET_WCINC_Msk              (0x20UL)                  /*!< WCINC (Bitfield-Mask: 0x01)                           */
9580 #define ADC_INTSET_WCEXC_Pos              (4UL)                     /*!< WCEXC (Bit 4)                                         */
9581 #define ADC_INTSET_WCEXC_Msk              (0x10UL)                  /*!< WCEXC (Bitfield-Mask: 0x01)                           */
9582 #define ADC_INTSET_FIFOOVR2_Pos           (3UL)                     /*!< FIFOOVR2 (Bit 3)                                      */
9583 #define ADC_INTSET_FIFOOVR2_Msk           (0x8UL)                   /*!< FIFOOVR2 (Bitfield-Mask: 0x01)                        */
9584 #define ADC_INTSET_FIFOOVR1_Pos           (2UL)                     /*!< FIFOOVR1 (Bit 2)                                      */
9585 #define ADC_INTSET_FIFOOVR1_Msk           (0x4UL)                   /*!< FIFOOVR1 (Bitfield-Mask: 0x01)                        */
9586 #define ADC_INTSET_SCNCMP_Pos             (1UL)                     /*!< SCNCMP (Bit 1)                                        */
9587 #define ADC_INTSET_SCNCMP_Msk             (0x2UL)                   /*!< SCNCMP (Bitfield-Mask: 0x01)                          */
9588 #define ADC_INTSET_CNVCMP_Pos             (0UL)                     /*!< CNVCMP (Bit 0)                                        */
9589 #define ADC_INTSET_CNVCMP_Msk             (0x1UL)                   /*!< CNVCMP (Bitfield-Mask: 0x01)                          */
9590 /* =======================================================  DMATRIGEN  ======================================================= */
9591 #define ADC_DMATRIGEN_DFIFOFULL_Pos       (1UL)                     /*!< DFIFOFULL (Bit 1)                                     */
9592 #define ADC_DMATRIGEN_DFIFOFULL_Msk       (0x2UL)                   /*!< DFIFOFULL (Bitfield-Mask: 0x01)                       */
9593 #define ADC_DMATRIGEN_DFIFO75_Pos         (0UL)                     /*!< DFIFO75 (Bit 0)                                       */
9594 #define ADC_DMATRIGEN_DFIFO75_Msk         (0x1UL)                   /*!< DFIFO75 (Bitfield-Mask: 0x01)                         */
9595 /* ======================================================  DMATRIGSTAT  ====================================================== */
9596 #define ADC_DMATRIGSTAT_DFULLSTAT_Pos     (1UL)                     /*!< DFULLSTAT (Bit 1)                                     */
9597 #define ADC_DMATRIGSTAT_DFULLSTAT_Msk     (0x2UL)                   /*!< DFULLSTAT (Bitfield-Mask: 0x01)                       */
9598 #define ADC_DMATRIGSTAT_D75STAT_Pos       (0UL)                     /*!< D75STAT (Bit 0)                                       */
9599 #define ADC_DMATRIGSTAT_D75STAT_Msk       (0x1UL)                   /*!< D75STAT (Bitfield-Mask: 0x01)                         */
9600 /* ========================================================  DMACFG  ========================================================= */
9601 #define ADC_DMACFG_DPWROFF_Pos            (18UL)                    /*!< DPWROFF (Bit 18)                                      */
9602 #define ADC_DMACFG_DPWROFF_Msk            (0x40000UL)               /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
9603 #define ADC_DMACFG_DMAMSK_Pos             (17UL)                    /*!< DMAMSK (Bit 17)                                       */
9604 #define ADC_DMACFG_DMAMSK_Msk             (0x20000UL)               /*!< DMAMSK (Bitfield-Mask: 0x01)                          */
9605 #define ADC_DMACFG_DMAHONSTAT_Pos         (16UL)                    /*!< DMAHONSTAT (Bit 16)                                   */
9606 #define ADC_DMACFG_DMAHONSTAT_Msk         (0x10000UL)               /*!< DMAHONSTAT (Bitfield-Mask: 0x01)                      */
9607 #define ADC_DMACFG_DMADYNPRI_Pos          (9UL)                     /*!< DMADYNPRI (Bit 9)                                     */
9608 #define ADC_DMACFG_DMADYNPRI_Msk          (0x200UL)                 /*!< DMADYNPRI (Bitfield-Mask: 0x01)                       */
9609 #define ADC_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
9610 #define ADC_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
9611 #define ADC_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
9612 #define ADC_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
9613 #define ADC_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
9614 #define ADC_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
9615 /* ======================================================  DMATOTCOUNT  ====================================================== */
9616 #define ADC_DMATOTCOUNT_TOTCOUNT_Pos      (2UL)                     /*!< TOTCOUNT (Bit 2)                                      */
9617 #define ADC_DMATOTCOUNT_TOTCOUNT_Msk      (0x3fffcUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
9618 /* ======================================================  DMATARGADDR  ====================================================== */
9619 #define ADC_DMATARGADDR_UTARGADDR_Pos     (19UL)                    /*!< UTARGADDR (Bit 19)                                    */
9620 #define ADC_DMATARGADDR_UTARGADDR_Msk     (0xfff80000UL)            /*!< UTARGADDR (Bitfield-Mask: 0x1fff)                     */
9621 #define ADC_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
9622 #define ADC_DMATARGADDR_LTARGADDR_Msk     (0x7ffffUL)               /*!< LTARGADDR (Bitfield-Mask: 0x7ffff)                    */
9623 /* ========================================================  DMASTAT  ======================================================== */
9624 #define ADC_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
9625 #define ADC_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
9626 #define ADC_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
9627 #define ADC_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
9628 #define ADC_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
9629 #define ADC_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
9630 
9631 
9632 /* =========================================================================================================================== */
9633 /* ================                                          APBDMA                                           ================ */
9634 /* =========================================================================================================================== */
9635 
9636 /* ========================================================  BBVALUE  ======================================================== */
9637 #define APBDMA_BBVALUE_PIN_Pos            (16UL)                    /*!< PIN (Bit 16)                                          */
9638 #define APBDMA_BBVALUE_PIN_Msk            (0xff0000UL)              /*!< PIN (Bitfield-Mask: 0xff)                             */
9639 #define APBDMA_BBVALUE_DATAOUT_Pos        (0UL)                     /*!< DATAOUT (Bit 0)                                       */
9640 #define APBDMA_BBVALUE_DATAOUT_Msk        (0xffUL)                  /*!< DATAOUT (Bitfield-Mask: 0xff)                         */
9641 /* ======================================================  BBSETCLEAR  ======================================================= */
9642 #define APBDMA_BBSETCLEAR_CLEAR_Pos       (16UL)                    /*!< CLEAR (Bit 16)                                        */
9643 #define APBDMA_BBSETCLEAR_CLEAR_Msk       (0xff0000UL)              /*!< CLEAR (Bitfield-Mask: 0xff)                           */
9644 #define APBDMA_BBSETCLEAR_SET_Pos         (0UL)                     /*!< SET (Bit 0)                                           */
9645 #define APBDMA_BBSETCLEAR_SET_Msk         (0xffUL)                  /*!< SET (Bitfield-Mask: 0xff)                             */
9646 /* ========================================================  BBINPUT  ======================================================== */
9647 #define APBDMA_BBINPUT_DATAIN_Pos         (0UL)                     /*!< DATAIN (Bit 0)                                        */
9648 #define APBDMA_BBINPUT_DATAIN_Msk         (0xffUL)                  /*!< DATAIN (Bitfield-Mask: 0xff)                          */
9649 /* =======================================================  DEBUGDATA  ======================================================= */
9650 #define APBDMA_DEBUGDATA_DEBUGDATA_Pos    (0UL)                     /*!< DEBUGDATA (Bit 0)                                     */
9651 #define APBDMA_DEBUGDATA_DEBUGDATA_Msk    (0xffffffffUL)            /*!< DEBUGDATA (Bitfield-Mask: 0xffffffff)                 */
9652 /* =========================================================  DEBUG  ========================================================= */
9653 #define APBDMA_DEBUG_DEBUGEN_Pos          (0UL)                     /*!< DEBUGEN (Bit 0)                                       */
9654 #define APBDMA_DEBUG_DEBUGEN_Msk          (0xfUL)                   /*!< DEBUGEN (Bitfield-Mask: 0x0f)                         */
9655 
9656 
9657 /* =========================================================================================================================== */
9658 /* ================                                           BLEIF                                           ================ */
9659 /* =========================================================================================================================== */
9660 
9661 /* =========================================================  FIFO  ========================================================== */
9662 #define BLEIF_FIFO_FIFO_Pos               (0UL)                     /*!< FIFO (Bit 0)                                          */
9663 #define BLEIF_FIFO_FIFO_Msk               (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
9664 /* ========================================================  FIFOPTR  ======================================================== */
9665 #define BLEIF_FIFOPTR_FIFO1REM_Pos        (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
9666 #define BLEIF_FIFOPTR_FIFO1REM_Msk        (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
9667 #define BLEIF_FIFOPTR_FIFO1SIZ_Pos        (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
9668 #define BLEIF_FIFOPTR_FIFO1SIZ_Msk        (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
9669 #define BLEIF_FIFOPTR_FIFO0REM_Pos        (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
9670 #define BLEIF_FIFOPTR_FIFO0REM_Msk        (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
9671 #define BLEIF_FIFOPTR_FIFO0SIZ_Pos        (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
9672 #define BLEIF_FIFOPTR_FIFO0SIZ_Msk        (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
9673 /* ========================================================  FIFOTHR  ======================================================== */
9674 #define BLEIF_FIFOTHR_FIFOWTHR_Pos        (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
9675 #define BLEIF_FIFOTHR_FIFOWTHR_Msk        (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
9676 #define BLEIF_FIFOTHR_FIFORTHR_Pos        (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
9677 #define BLEIF_FIFOTHR_FIFORTHR_Msk        (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
9678 /* ========================================================  FIFOPOP  ======================================================== */
9679 #define BLEIF_FIFOPOP_FIFODOUT_Pos        (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
9680 #define BLEIF_FIFOPOP_FIFODOUT_Msk        (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
9681 /* =======================================================  FIFOPUSH  ======================================================== */
9682 #define BLEIF_FIFOPUSH_FIFODIN_Pos        (0UL)                     /*!< FIFODIN (Bit 0)                                       */
9683 #define BLEIF_FIFOPUSH_FIFODIN_Msk        (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
9684 /* =======================================================  FIFOCTRL  ======================================================== */
9685 #define BLEIF_FIFOCTRL_FIFORSTN_Pos       (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
9686 #define BLEIF_FIFOCTRL_FIFORSTN_Msk       (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
9687 #define BLEIF_FIFOCTRL_POPWR_Pos          (0UL)                     /*!< POPWR (Bit 0)                                         */
9688 #define BLEIF_FIFOCTRL_POPWR_Msk          (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
9689 /* ========================================================  FIFOLOC  ======================================================== */
9690 #define BLEIF_FIFOLOC_FIFORPTR_Pos        (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
9691 #define BLEIF_FIFOLOC_FIFORPTR_Msk        (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
9692 #define BLEIF_FIFOLOC_FIFOWPTR_Pos        (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
9693 #define BLEIF_FIFOLOC_FIFOWPTR_Msk        (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
9694 /* ========================================================  CLKCFG  ========================================================= */
9695 #define BLEIF_CLKCFG_DIV3_Pos             (12UL)                    /*!< DIV3 (Bit 12)                                         */
9696 #define BLEIF_CLKCFG_DIV3_Msk             (0x1000UL)                /*!< DIV3 (Bitfield-Mask: 0x01)                            */
9697 #define BLEIF_CLKCFG_CLK32KEN_Pos         (11UL)                    /*!< CLK32KEN (Bit 11)                                     */
9698 #define BLEIF_CLKCFG_CLK32KEN_Msk         (0x800UL)                 /*!< CLK32KEN (Bitfield-Mask: 0x01)                        */
9699 #define BLEIF_CLKCFG_FSEL_Pos             (8UL)                     /*!< FSEL (Bit 8)                                          */
9700 #define BLEIF_CLKCFG_FSEL_Msk             (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
9701 #define BLEIF_CLKCFG_IOCLKEN_Pos          (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
9702 #define BLEIF_CLKCFG_IOCLKEN_Msk          (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
9703 /* ==========================================================  CMD  ========================================================== */
9704 #define BLEIF_CMD_OFFSETLO_Pos            (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
9705 #define BLEIF_CMD_OFFSETLO_Msk            (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
9706 #define BLEIF_CMD_CMDSEL_Pos              (20UL)                    /*!< CMDSEL (Bit 20)                                       */
9707 #define BLEIF_CMD_CMDSEL_Msk              (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
9708 #define BLEIF_CMD_TSIZE_Pos               (8UL)                     /*!< TSIZE (Bit 8)                                         */
9709 #define BLEIF_CMD_TSIZE_Msk               (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
9710 #define BLEIF_CMD_CONT_Pos                (7UL)                     /*!< CONT (Bit 7)                                          */
9711 #define BLEIF_CMD_CONT_Msk                (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
9712 #define BLEIF_CMD_OFFSETCNT_Pos           (5UL)                     /*!< OFFSETCNT (Bit 5)                                     */
9713 #define BLEIF_CMD_OFFSETCNT_Msk           (0x60UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x03)                       */
9714 #define BLEIF_CMD_CMD_Pos                 (0UL)                     /*!< CMD (Bit 0)                                           */
9715 #define BLEIF_CMD_CMD_Msk                 (0x1fUL)                  /*!< CMD (Bitfield-Mask: 0x1f)                             */
9716 /* ========================================================  CMDRPT  ========================================================= */
9717 #define BLEIF_CMDRPT_CMDRPT_Pos           (0UL)                     /*!< CMDRPT (Bit 0)                                        */
9718 #define BLEIF_CMDRPT_CMDRPT_Msk           (0x1fUL)                  /*!< CMDRPT (Bitfield-Mask: 0x1f)                          */
9719 /* =======================================================  OFFSETHI  ======================================================== */
9720 #define BLEIF_OFFSETHI_OFFSETHI_Pos       (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
9721 #define BLEIF_OFFSETHI_OFFSETHI_Msk       (0xffffUL)                /*!< OFFSETHI (Bitfield-Mask: 0xffff)                      */
9722 /* ========================================================  CMDSTAT  ======================================================== */
9723 #define BLEIF_CMDSTAT_CTSIZE_Pos          (8UL)                     /*!< CTSIZE (Bit 8)                                        */
9724 #define BLEIF_CMDSTAT_CTSIZE_Msk          (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
9725 #define BLEIF_CMDSTAT_CMDSTAT_Pos         (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
9726 #define BLEIF_CMDSTAT_CMDSTAT_Msk         (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
9727 #define BLEIF_CMDSTAT_CCMD_Pos            (0UL)                     /*!< CCMD (Bit 0)                                          */
9728 #define BLEIF_CMDSTAT_CCMD_Msk            (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
9729 /* =========================================================  INTEN  ========================================================= */
9730 #define BLEIF_INTEN_B2MSHUTDN_Pos         (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
9731 #define BLEIF_INTEN_B2MSHUTDN_Msk         (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
9732 #define BLEIF_INTEN_B2MACTIVE_Pos         (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
9733 #define BLEIF_INTEN_B2MACTIVE_Msk         (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
9734 #define BLEIF_INTEN_B2MSLEEP_Pos          (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
9735 #define BLEIF_INTEN_B2MSLEEP_Msk          (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
9736 #define BLEIF_INTEN_CQERR_Pos             (13UL)                    /*!< CQERR (Bit 13)                                        */
9737 #define BLEIF_INTEN_CQERR_Msk             (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
9738 #define BLEIF_INTEN_CQUPD_Pos             (12UL)                    /*!< CQUPD (Bit 12)                                        */
9739 #define BLEIF_INTEN_CQUPD_Msk             (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
9740 #define BLEIF_INTEN_CQPAUSED_Pos          (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
9741 #define BLEIF_INTEN_CQPAUSED_Msk          (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
9742 #define BLEIF_INTEN_DERR_Pos              (10UL)                    /*!< DERR (Bit 10)                                         */
9743 #define BLEIF_INTEN_DERR_Msk              (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
9744 #define BLEIF_INTEN_DCMP_Pos              (9UL)                     /*!< DCMP (Bit 9)                                          */
9745 #define BLEIF_INTEN_DCMP_Msk              (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
9746 #define BLEIF_INTEN_BLECSSTAT_Pos         (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
9747 #define BLEIF_INTEN_BLECSSTAT_Msk         (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
9748 #define BLEIF_INTEN_BLECIRQ_Pos           (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
9749 #define BLEIF_INTEN_BLECIRQ_Msk           (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
9750 #define BLEIF_INTEN_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
9751 #define BLEIF_INTEN_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
9752 #define BLEIF_INTEN_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
9753 #define BLEIF_INTEN_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
9754 #define BLEIF_INTEN_B2MST_Pos             (4UL)                     /*!< B2MST (Bit 4)                                         */
9755 #define BLEIF_INTEN_B2MST_Msk             (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
9756 #define BLEIF_INTEN_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
9757 #define BLEIF_INTEN_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
9758 #define BLEIF_INTEN_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
9759 #define BLEIF_INTEN_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
9760 #define BLEIF_INTEN_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
9761 #define BLEIF_INTEN_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
9762 #define BLEIF_INTEN_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
9763 #define BLEIF_INTEN_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
9764 /* ========================================================  INTSTAT  ======================================================== */
9765 #define BLEIF_INTSTAT_B2MSHUTDN_Pos       (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
9766 #define BLEIF_INTSTAT_B2MSHUTDN_Msk       (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
9767 #define BLEIF_INTSTAT_B2MACTIVE_Pos       (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
9768 #define BLEIF_INTSTAT_B2MACTIVE_Msk       (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
9769 #define BLEIF_INTSTAT_B2MSLEEP_Pos        (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
9770 #define BLEIF_INTSTAT_B2MSLEEP_Msk        (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
9771 #define BLEIF_INTSTAT_CQERR_Pos           (13UL)                    /*!< CQERR (Bit 13)                                        */
9772 #define BLEIF_INTSTAT_CQERR_Msk           (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
9773 #define BLEIF_INTSTAT_CQUPD_Pos           (12UL)                    /*!< CQUPD (Bit 12)                                        */
9774 #define BLEIF_INTSTAT_CQUPD_Msk           (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
9775 #define BLEIF_INTSTAT_CQPAUSED_Pos        (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
9776 #define BLEIF_INTSTAT_CQPAUSED_Msk        (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
9777 #define BLEIF_INTSTAT_DERR_Pos            (10UL)                    /*!< DERR (Bit 10)                                         */
9778 #define BLEIF_INTSTAT_DERR_Msk            (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
9779 #define BLEIF_INTSTAT_DCMP_Pos            (9UL)                     /*!< DCMP (Bit 9)                                          */
9780 #define BLEIF_INTSTAT_DCMP_Msk            (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
9781 #define BLEIF_INTSTAT_BLECSSTAT_Pos       (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
9782 #define BLEIF_INTSTAT_BLECSSTAT_Msk       (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
9783 #define BLEIF_INTSTAT_BLECIRQ_Pos         (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
9784 #define BLEIF_INTSTAT_BLECIRQ_Msk         (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
9785 #define BLEIF_INTSTAT_ICMD_Pos            (6UL)                     /*!< ICMD (Bit 6)                                          */
9786 #define BLEIF_INTSTAT_ICMD_Msk            (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
9787 #define BLEIF_INTSTAT_IACC_Pos            (5UL)                     /*!< IACC (Bit 5)                                          */
9788 #define BLEIF_INTSTAT_IACC_Msk            (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
9789 #define BLEIF_INTSTAT_B2MST_Pos           (4UL)                     /*!< B2MST (Bit 4)                                         */
9790 #define BLEIF_INTSTAT_B2MST_Msk           (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
9791 #define BLEIF_INTSTAT_FOVFL_Pos           (3UL)                     /*!< FOVFL (Bit 3)                                         */
9792 #define BLEIF_INTSTAT_FOVFL_Msk           (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
9793 #define BLEIF_INTSTAT_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
9794 #define BLEIF_INTSTAT_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
9795 #define BLEIF_INTSTAT_THR_Pos             (1UL)                     /*!< THR (Bit 1)                                           */
9796 #define BLEIF_INTSTAT_THR_Msk             (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
9797 #define BLEIF_INTSTAT_CMDCMP_Pos          (0UL)                     /*!< CMDCMP (Bit 0)                                        */
9798 #define BLEIF_INTSTAT_CMDCMP_Msk          (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
9799 /* ========================================================  INTCLR  ========================================================= */
9800 #define BLEIF_INTCLR_B2MSHUTDN_Pos        (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
9801 #define BLEIF_INTCLR_B2MSHUTDN_Msk        (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
9802 #define BLEIF_INTCLR_B2MACTIVE_Pos        (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
9803 #define BLEIF_INTCLR_B2MACTIVE_Msk        (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
9804 #define BLEIF_INTCLR_B2MSLEEP_Pos         (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
9805 #define BLEIF_INTCLR_B2MSLEEP_Msk         (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
9806 #define BLEIF_INTCLR_CQERR_Pos            (13UL)                    /*!< CQERR (Bit 13)                                        */
9807 #define BLEIF_INTCLR_CQERR_Msk            (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
9808 #define BLEIF_INTCLR_CQUPD_Pos            (12UL)                    /*!< CQUPD (Bit 12)                                        */
9809 #define BLEIF_INTCLR_CQUPD_Msk            (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
9810 #define BLEIF_INTCLR_CQPAUSED_Pos         (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
9811 #define BLEIF_INTCLR_CQPAUSED_Msk         (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
9812 #define BLEIF_INTCLR_DERR_Pos             (10UL)                    /*!< DERR (Bit 10)                                         */
9813 #define BLEIF_INTCLR_DERR_Msk             (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
9814 #define BLEIF_INTCLR_DCMP_Pos             (9UL)                     /*!< DCMP (Bit 9)                                          */
9815 #define BLEIF_INTCLR_DCMP_Msk             (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
9816 #define BLEIF_INTCLR_BLECSSTAT_Pos        (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
9817 #define BLEIF_INTCLR_BLECSSTAT_Msk        (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
9818 #define BLEIF_INTCLR_BLECIRQ_Pos          (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
9819 #define BLEIF_INTCLR_BLECIRQ_Msk          (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
9820 #define BLEIF_INTCLR_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
9821 #define BLEIF_INTCLR_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
9822 #define BLEIF_INTCLR_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
9823 #define BLEIF_INTCLR_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
9824 #define BLEIF_INTCLR_B2MST_Pos            (4UL)                     /*!< B2MST (Bit 4)                                         */
9825 #define BLEIF_INTCLR_B2MST_Msk            (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
9826 #define BLEIF_INTCLR_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
9827 #define BLEIF_INTCLR_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
9828 #define BLEIF_INTCLR_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
9829 #define BLEIF_INTCLR_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
9830 #define BLEIF_INTCLR_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
9831 #define BLEIF_INTCLR_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
9832 #define BLEIF_INTCLR_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
9833 #define BLEIF_INTCLR_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
9834 /* ========================================================  INTSET  ========================================================= */
9835 #define BLEIF_INTSET_B2MSHUTDN_Pos        (16UL)                    /*!< B2MSHUTDN (Bit 16)                                    */
9836 #define BLEIF_INTSET_B2MSHUTDN_Msk        (0x10000UL)               /*!< B2MSHUTDN (Bitfield-Mask: 0x01)                       */
9837 #define BLEIF_INTSET_B2MACTIVE_Pos        (15UL)                    /*!< B2MACTIVE (Bit 15)                                    */
9838 #define BLEIF_INTSET_B2MACTIVE_Msk        (0x8000UL)                /*!< B2MACTIVE (Bitfield-Mask: 0x01)                       */
9839 #define BLEIF_INTSET_B2MSLEEP_Pos         (14UL)                    /*!< B2MSLEEP (Bit 14)                                     */
9840 #define BLEIF_INTSET_B2MSLEEP_Msk         (0x4000UL)                /*!< B2MSLEEP (Bitfield-Mask: 0x01)                        */
9841 #define BLEIF_INTSET_CQERR_Pos            (13UL)                    /*!< CQERR (Bit 13)                                        */
9842 #define BLEIF_INTSET_CQERR_Msk            (0x2000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
9843 #define BLEIF_INTSET_CQUPD_Pos            (12UL)                    /*!< CQUPD (Bit 12)                                        */
9844 #define BLEIF_INTSET_CQUPD_Msk            (0x1000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
9845 #define BLEIF_INTSET_CQPAUSED_Pos         (11UL)                    /*!< CQPAUSED (Bit 11)                                     */
9846 #define BLEIF_INTSET_CQPAUSED_Msk         (0x800UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
9847 #define BLEIF_INTSET_DERR_Pos             (10UL)                    /*!< DERR (Bit 10)                                         */
9848 #define BLEIF_INTSET_DERR_Msk             (0x400UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
9849 #define BLEIF_INTSET_DCMP_Pos             (9UL)                     /*!< DCMP (Bit 9)                                          */
9850 #define BLEIF_INTSET_DCMP_Msk             (0x200UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
9851 #define BLEIF_INTSET_BLECSSTAT_Pos        (8UL)                     /*!< BLECSSTAT (Bit 8)                                     */
9852 #define BLEIF_INTSET_BLECSSTAT_Msk        (0x100UL)                 /*!< BLECSSTAT (Bitfield-Mask: 0x01)                       */
9853 #define BLEIF_INTSET_BLECIRQ_Pos          (7UL)                     /*!< BLECIRQ (Bit 7)                                       */
9854 #define BLEIF_INTSET_BLECIRQ_Msk          (0x80UL)                  /*!< BLECIRQ (Bitfield-Mask: 0x01)                         */
9855 #define BLEIF_INTSET_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
9856 #define BLEIF_INTSET_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
9857 #define BLEIF_INTSET_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
9858 #define BLEIF_INTSET_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
9859 #define BLEIF_INTSET_B2MST_Pos            (4UL)                     /*!< B2MST (Bit 4)                                         */
9860 #define BLEIF_INTSET_B2MST_Msk            (0x10UL)                  /*!< B2MST (Bitfield-Mask: 0x01)                           */
9861 #define BLEIF_INTSET_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
9862 #define BLEIF_INTSET_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
9863 #define BLEIF_INTSET_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
9864 #define BLEIF_INTSET_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
9865 #define BLEIF_INTSET_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
9866 #define BLEIF_INTSET_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
9867 #define BLEIF_INTSET_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
9868 #define BLEIF_INTSET_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
9869 /* =======================================================  DMATRIGEN  ======================================================= */
9870 #define BLEIF_DMATRIGEN_DTHREN_Pos        (1UL)                     /*!< DTHREN (Bit 1)                                        */
9871 #define BLEIF_DMATRIGEN_DTHREN_Msk        (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
9872 #define BLEIF_DMATRIGEN_DCMDCMPEN_Pos     (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
9873 #define BLEIF_DMATRIGEN_DCMDCMPEN_Msk     (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
9874 /* ======================================================  DMATRIGSTAT  ====================================================== */
9875 #define BLEIF_DMATRIGSTAT_DTOTCMP_Pos     (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
9876 #define BLEIF_DMATRIGSTAT_DTOTCMP_Msk     (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
9877 #define BLEIF_DMATRIGSTAT_DTHR_Pos        (1UL)                     /*!< DTHR (Bit 1)                                          */
9878 #define BLEIF_DMATRIGSTAT_DTHR_Msk        (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
9879 #define BLEIF_DMATRIGSTAT_DCMDCMP_Pos     (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
9880 #define BLEIF_DMATRIGSTAT_DCMDCMP_Msk     (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
9881 /* ========================================================  DMACFG  ========================================================= */
9882 #define BLEIF_DMACFG_DPWROFF_Pos          (9UL)                     /*!< DPWROFF (Bit 9)                                       */
9883 #define BLEIF_DMACFG_DPWROFF_Msk          (0x200UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
9884 #define BLEIF_DMACFG_DMAPRI_Pos           (8UL)                     /*!< DMAPRI (Bit 8)                                        */
9885 #define BLEIF_DMACFG_DMAPRI_Msk           (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
9886 #define BLEIF_DMACFG_DMADIR_Pos           (1UL)                     /*!< DMADIR (Bit 1)                                        */
9887 #define BLEIF_DMACFG_DMADIR_Msk           (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
9888 #define BLEIF_DMACFG_DMAEN_Pos            (0UL)                     /*!< DMAEN (Bit 0)                                         */
9889 #define BLEIF_DMACFG_DMAEN_Msk            (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
9890 /* ======================================================  DMATOTCOUNT  ====================================================== */
9891 #define BLEIF_DMATOTCOUNT_TOTCOUNT_Pos    (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
9892 #define BLEIF_DMATOTCOUNT_TOTCOUNT_Msk    (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
9893 /* ======================================================  DMATARGADDR  ====================================================== */
9894 #define BLEIF_DMATARGADDR_TARGADDR28_Pos  (28UL)                    /*!< TARGADDR28 (Bit 28)                                   */
9895 #define BLEIF_DMATARGADDR_TARGADDR28_Msk  (0x10000000UL)            /*!< TARGADDR28 (Bitfield-Mask: 0x01)                      */
9896 #define BLEIF_DMATARGADDR_TARGADDR_Pos    (0UL)                     /*!< TARGADDR (Bit 0)                                      */
9897 #define BLEIF_DMATARGADDR_TARGADDR_Msk    (0xfffffUL)               /*!< TARGADDR (Bitfield-Mask: 0xfffff)                     */
9898 /* ========================================================  DMASTAT  ======================================================== */
9899 #define BLEIF_DMASTAT_DMAERR_Pos          (2UL)                     /*!< DMAERR (Bit 2)                                        */
9900 #define BLEIF_DMASTAT_DMAERR_Msk          (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
9901 #define BLEIF_DMASTAT_DMACPL_Pos          (1UL)                     /*!< DMACPL (Bit 1)                                        */
9902 #define BLEIF_DMASTAT_DMACPL_Msk          (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
9903 #define BLEIF_DMASTAT_DMATIP_Pos          (0UL)                     /*!< DMATIP (Bit 0)                                        */
9904 #define BLEIF_DMASTAT_DMATIP_Msk          (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
9905 /* =========================================================  CQCFG  ========================================================= */
9906 #define BLEIF_CQCFG_CQPRI_Pos             (1UL)                     /*!< CQPRI (Bit 1)                                         */
9907 #define BLEIF_CQCFG_CQPRI_Msk             (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
9908 #define BLEIF_CQCFG_CQEN_Pos              (0UL)                     /*!< CQEN (Bit 0)                                          */
9909 #define BLEIF_CQCFG_CQEN_Msk              (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
9910 /* ========================================================  CQADDR  ========================================================= */
9911 #define BLEIF_CQADDR_CQADDR28_Pos         (28UL)                    /*!< CQADDR28 (Bit 28)                                     */
9912 #define BLEIF_CQADDR_CQADDR28_Msk         (0x10000000UL)            /*!< CQADDR28 (Bitfield-Mask: 0x01)                        */
9913 #define BLEIF_CQADDR_CQADDR_Pos           (2UL)                     /*!< CQADDR (Bit 2)                                        */
9914 #define BLEIF_CQADDR_CQADDR_Msk           (0xffffcUL)               /*!< CQADDR (Bitfield-Mask: 0x3ffff)                       */
9915 /* ========================================================  CQSTAT  ========================================================= */
9916 #define BLEIF_CQSTAT_CQERR_Pos            (2UL)                     /*!< CQERR (Bit 2)                                         */
9917 #define BLEIF_CQSTAT_CQERR_Msk            (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
9918 #define BLEIF_CQSTAT_CQPAUSED_Pos         (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
9919 #define BLEIF_CQSTAT_CQPAUSED_Msk         (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
9920 #define BLEIF_CQSTAT_CQTIP_Pos            (0UL)                     /*!< CQTIP (Bit 0)                                         */
9921 #define BLEIF_CQSTAT_CQTIP_Msk            (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
9922 /* ========================================================  CQFLAGS  ======================================================== */
9923 #define BLEIF_CQFLAGS_CQIRQMASK_Pos       (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
9924 #define BLEIF_CQFLAGS_CQIRQMASK_Msk       (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
9925 #define BLEIF_CQFLAGS_CQFLAGS_Pos         (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
9926 #define BLEIF_CQFLAGS_CQFLAGS_Msk         (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
9927 /* ======================================================  CQSETCLEAR  ======================================================= */
9928 #define BLEIF_CQSETCLEAR_CQFCLR_Pos       (16UL)                    /*!< CQFCLR (Bit 16)                                       */
9929 #define BLEIF_CQSETCLEAR_CQFCLR_Msk       (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
9930 #define BLEIF_CQSETCLEAR_CQFTGL_Pos       (8UL)                     /*!< CQFTGL (Bit 8)                                        */
9931 #define BLEIF_CQSETCLEAR_CQFTGL_Msk       (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
9932 #define BLEIF_CQSETCLEAR_CQFSET_Pos       (0UL)                     /*!< CQFSET (Bit 0)                                        */
9933 #define BLEIF_CQSETCLEAR_CQFSET_Msk       (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
9934 /* =======================================================  CQPAUSEEN  ======================================================= */
9935 #define BLEIF_CQPAUSEEN_CQPEN_Pos         (0UL)                     /*!< CQPEN (Bit 0)                                         */
9936 #define BLEIF_CQPAUSEEN_CQPEN_Msk         (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
9937 /* =======================================================  CQCURIDX  ======================================================== */
9938 #define BLEIF_CQCURIDX_CQCURIDX_Pos       (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
9939 #define BLEIF_CQCURIDX_CQCURIDX_Msk       (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
9940 /* =======================================================  CQENDIDX  ======================================================== */
9941 #define BLEIF_CQENDIDX_CQENDIDX_Pos       (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
9942 #define BLEIF_CQENDIDX_CQENDIDX_Msk       (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
9943 /* ========================================================  STATUS  ========================================================= */
9944 #define BLEIF_STATUS_IDLEST_Pos           (2UL)                     /*!< IDLEST (Bit 2)                                        */
9945 #define BLEIF_STATUS_IDLEST_Msk           (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
9946 #define BLEIF_STATUS_CMDACT_Pos           (1UL)                     /*!< CMDACT (Bit 1)                                        */
9947 #define BLEIF_STATUS_CMDACT_Msk           (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
9948 #define BLEIF_STATUS_ERR_Pos              (0UL)                     /*!< ERR (Bit 0)                                           */
9949 #define BLEIF_STATUS_ERR_Msk              (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
9950 /* ========================================================  MSPICFG  ======================================================== */
9951 #define BLEIF_MSPICFG_MSPIRST_Pos         (30UL)                    /*!< MSPIRST (Bit 30)                                      */
9952 #define BLEIF_MSPICFG_MSPIRST_Msk         (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
9953 #define BLEIF_MSPICFG_DOUTDLY_Pos         (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
9954 #define BLEIF_MSPICFG_DOUTDLY_Msk         (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
9955 #define BLEIF_MSPICFG_DINDLY_Pos          (24UL)                    /*!< DINDLY (Bit 24)                                       */
9956 #define BLEIF_MSPICFG_DINDLY_Msk          (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
9957 #define BLEIF_MSPICFG_SPILSB_Pos          (23UL)                    /*!< SPILSB (Bit 23)                                       */
9958 #define BLEIF_MSPICFG_SPILSB_Msk          (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
9959 #define BLEIF_MSPICFG_RDFCPOL_Pos         (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
9960 #define BLEIF_MSPICFG_RDFCPOL_Msk         (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
9961 #define BLEIF_MSPICFG_WTFCPOL_Pos         (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
9962 #define BLEIF_MSPICFG_WTFCPOL_Msk         (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
9963 #define BLEIF_MSPICFG_RDFC_Pos            (17UL)                    /*!< RDFC (Bit 17)                                         */
9964 #define BLEIF_MSPICFG_RDFC_Msk            (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
9965 #define BLEIF_MSPICFG_WTFC_Pos            (16UL)                    /*!< WTFC (Bit 16)                                         */
9966 #define BLEIF_MSPICFG_WTFC_Msk            (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
9967 #define BLEIF_MSPICFG_FULLDUP_Pos         (2UL)                     /*!< FULLDUP (Bit 2)                                       */
9968 #define BLEIF_MSPICFG_FULLDUP_Msk         (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
9969 #define BLEIF_MSPICFG_SPHA_Pos            (1UL)                     /*!< SPHA (Bit 1)                                          */
9970 #define BLEIF_MSPICFG_SPHA_Msk            (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
9971 #define BLEIF_MSPICFG_SPOL_Pos            (0UL)                     /*!< SPOL (Bit 0)                                          */
9972 #define BLEIF_MSPICFG_SPOL_Msk            (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
9973 /* ========================================================  BLECFG  ========================================================= */
9974 #define BLEIF_BLECFG_SPIISOCTL_Pos        (14UL)                    /*!< SPIISOCTL (Bit 14)                                    */
9975 #define BLEIF_BLECFG_SPIISOCTL_Msk        (0xc000UL)                /*!< SPIISOCTL (Bitfield-Mask: 0x03)                       */
9976 #define BLEIF_BLECFG_PWRISOCTL_Pos        (12UL)                    /*!< PWRISOCTL (Bit 12)                                    */
9977 #define BLEIF_BLECFG_PWRISOCTL_Msk        (0x3000UL)                /*!< PWRISOCTL (Bitfield-Mask: 0x03)                       */
9978 #define BLEIF_BLECFG_STAYASLEEP_Pos       (11UL)                    /*!< STAYASLEEP (Bit 11)                                   */
9979 #define BLEIF_BLECFG_STAYASLEEP_Msk       (0x800UL)                 /*!< STAYASLEEP (Bitfield-Mask: 0x01)                      */
9980 #define BLEIF_BLECFG_FRCCLK_Pos           (10UL)                    /*!< FRCCLK (Bit 10)                                       */
9981 #define BLEIF_BLECFG_FRCCLK_Msk           (0x400UL)                 /*!< FRCCLK (Bitfield-Mask: 0x01)                          */
9982 #define BLEIF_BLECFG_MCUFRCSLP_Pos        (9UL)                     /*!< MCUFRCSLP (Bit 9)                                     */
9983 #define BLEIF_BLECFG_MCUFRCSLP_Msk        (0x200UL)                 /*!< MCUFRCSLP (Bitfield-Mask: 0x01)                       */
9984 #define BLEIF_BLECFG_WT4ACTOFF_Pos        (8UL)                     /*!< WT4ACTOFF (Bit 8)                                     */
9985 #define BLEIF_BLECFG_WT4ACTOFF_Msk        (0x100UL)                 /*!< WT4ACTOFF (Bitfield-Mask: 0x01)                       */
9986 #define BLEIF_BLECFG_BLEHREQCTL_Pos       (6UL)                     /*!< BLEHREQCTL (Bit 6)                                    */
9987 #define BLEIF_BLECFG_BLEHREQCTL_Msk       (0xc0UL)                  /*!< BLEHREQCTL (Bitfield-Mask: 0x03)                      */
9988 #define BLEIF_BLECFG_DCDCFLGCTL_Pos       (4UL)                     /*!< DCDCFLGCTL (Bit 4)                                    */
9989 #define BLEIF_BLECFG_DCDCFLGCTL_Msk       (0x30UL)                  /*!< DCDCFLGCTL (Bitfield-Mask: 0x03)                      */
9990 #define BLEIF_BLECFG_WAKEUPCTL_Pos        (2UL)                     /*!< WAKEUPCTL (Bit 2)                                     */
9991 #define BLEIF_BLECFG_WAKEUPCTL_Msk        (0xcUL)                   /*!< WAKEUPCTL (Bitfield-Mask: 0x03)                       */
9992 #define BLEIF_BLECFG_BLERSTN_Pos          (1UL)                     /*!< BLERSTN (Bit 1)                                       */
9993 #define BLEIF_BLECFG_BLERSTN_Msk          (0x2UL)                   /*!< BLERSTN (Bitfield-Mask: 0x01)                         */
9994 #define BLEIF_BLECFG_PWRSMEN_Pos          (0UL)                     /*!< PWRSMEN (Bit 0)                                       */
9995 #define BLEIF_BLECFG_PWRSMEN_Msk          (0x1UL)                   /*!< PWRSMEN (Bitfield-Mask: 0x01)                         */
9996 /* ========================================================  PWRCMD  ========================================================= */
9997 #define BLEIF_PWRCMD_RESTART_Pos          (1UL)                     /*!< RESTART (Bit 1)                                       */
9998 #define BLEIF_PWRCMD_RESTART_Msk          (0x2UL)                   /*!< RESTART (Bitfield-Mask: 0x01)                         */
9999 #define BLEIF_PWRCMD_WAKEREQ_Pos          (0UL)                     /*!< WAKEREQ (Bit 0)                                       */
10000 #define BLEIF_PWRCMD_WAKEREQ_Msk          (0x1UL)                   /*!< WAKEREQ (Bitfield-Mask: 0x01)                         */
10001 /* ========================================================  BSTATUS  ======================================================== */
10002 #define BLEIF_BSTATUS_BLEHREQ_Pos         (12UL)                    /*!< BLEHREQ (Bit 12)                                      */
10003 #define BLEIF_BSTATUS_BLEHREQ_Msk         (0x1000UL)                /*!< BLEHREQ (Bitfield-Mask: 0x01)                         */
10004 #define BLEIF_BSTATUS_BLEHACK_Pos         (11UL)                    /*!< BLEHACK (Bit 11)                                      */
10005 #define BLEIF_BSTATUS_BLEHACK_Msk         (0x800UL)                 /*!< BLEHACK (Bitfield-Mask: 0x01)                         */
10006 #define BLEIF_BSTATUS_PWRST_Pos           (8UL)                     /*!< PWRST (Bit 8)                                         */
10007 #define BLEIF_BSTATUS_PWRST_Msk           (0x700UL)                 /*!< PWRST (Bitfield-Mask: 0x07)                           */
10008 #define BLEIF_BSTATUS_BLEIRQ_Pos          (7UL)                     /*!< BLEIRQ (Bit 7)                                        */
10009 #define BLEIF_BSTATUS_BLEIRQ_Msk          (0x80UL)                  /*!< BLEIRQ (Bitfield-Mask: 0x01)                          */
10010 #define BLEIF_BSTATUS_WAKEUP_Pos          (6UL)                     /*!< WAKEUP (Bit 6)                                        */
10011 #define BLEIF_BSTATUS_WAKEUP_Msk          (0x40UL)                  /*!< WAKEUP (Bitfield-Mask: 0x01)                          */
10012 #define BLEIF_BSTATUS_DCDCFLAG_Pos        (5UL)                     /*!< DCDCFLAG (Bit 5)                                      */
10013 #define BLEIF_BSTATUS_DCDCFLAG_Msk        (0x20UL)                  /*!< DCDCFLAG (Bitfield-Mask: 0x01)                        */
10014 #define BLEIF_BSTATUS_DCDCREQ_Pos         (4UL)                     /*!< DCDCREQ (Bit 4)                                       */
10015 #define BLEIF_BSTATUS_DCDCREQ_Msk         (0x10UL)                  /*!< DCDCREQ (Bitfield-Mask: 0x01)                         */
10016 #define BLEIF_BSTATUS_SPISTATUS_Pos       (3UL)                     /*!< SPISTATUS (Bit 3)                                     */
10017 #define BLEIF_BSTATUS_SPISTATUS_Msk       (0x8UL)                   /*!< SPISTATUS (Bitfield-Mask: 0x01)                       */
10018 #define BLEIF_BSTATUS_B2MSTATE_Pos        (0UL)                     /*!< B2MSTATE (Bit 0)                                      */
10019 #define BLEIF_BSTATUS_B2MSTATE_Msk        (0x7UL)                   /*!< B2MSTATE (Bitfield-Mask: 0x07)                        */
10020 /* ========================================================  BLEDBG  ========================================================= */
10021 #define BLEIF_BLEDBG_DBGDATA_Pos          (3UL)                     /*!< DBGDATA (Bit 3)                                       */
10022 #define BLEIF_BLEDBG_DBGDATA_Msk          (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
10023 #define BLEIF_BLEDBG_APBCLKON_Pos         (2UL)                     /*!< APBCLKON (Bit 2)                                      */
10024 #define BLEIF_BLEDBG_APBCLKON_Msk         (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
10025 #define BLEIF_BLEDBG_IOCLKON_Pos          (1UL)                     /*!< IOCLKON (Bit 1)                                       */
10026 #define BLEIF_BLEDBG_IOCLKON_Msk          (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
10027 #define BLEIF_BLEDBG_DBGEN_Pos            (0UL)                     /*!< DBGEN (Bit 0)                                         */
10028 #define BLEIF_BLEDBG_DBGEN_Msk            (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
10029 
10030 
10031 /* =========================================================================================================================== */
10032 /* ================                                         CACHECTRL                                         ================ */
10033 /* =========================================================================================================================== */
10034 
10035 /* =======================================================  CACHECFG  ======================================================== */
10036 #define CACHECTRL_CACHECFG_ENABLE_MONITOR_Pos (24UL)                /*!< ENABLE_MONITOR (Bit 24)                               */
10037 #define CACHECTRL_CACHECFG_ENABLE_MONITOR_Msk (0x1000000UL)         /*!< ENABLE_MONITOR (Bitfield-Mask: 0x01)                  */
10038 #define CACHECTRL_CACHECFG_DATA_CLKGATE_Pos (20UL)                  /*!< DATA_CLKGATE (Bit 20)                                 */
10039 #define CACHECTRL_CACHECFG_DATA_CLKGATE_Msk (0x100000UL)            /*!< DATA_CLKGATE (Bitfield-Mask: 0x01)                    */
10040 #define CACHECTRL_CACHECFG_CACHE_LS_Pos   (11UL)                    /*!< CACHE_LS (Bit 11)                                     */
10041 #define CACHECTRL_CACHECFG_CACHE_LS_Msk   (0x800UL)                 /*!< CACHE_LS (Bitfield-Mask: 0x01)                        */
10042 #define CACHECTRL_CACHECFG_CACHE_CLKGATE_Pos (10UL)                 /*!< CACHE_CLKGATE (Bit 10)                                */
10043 #define CACHECTRL_CACHECFG_CACHE_CLKGATE_Msk (0x400UL)              /*!< CACHE_CLKGATE (Bitfield-Mask: 0x01)                   */
10044 #define CACHECTRL_CACHECFG_DCACHE_ENABLE_Pos (9UL)                  /*!< DCACHE_ENABLE (Bit 9)                                 */
10045 #define CACHECTRL_CACHECFG_DCACHE_ENABLE_Msk (0x200UL)              /*!< DCACHE_ENABLE (Bitfield-Mask: 0x01)                   */
10046 #define CACHECTRL_CACHECFG_ICACHE_ENABLE_Pos (8UL)                  /*!< ICACHE_ENABLE (Bit 8)                                 */
10047 #define CACHECTRL_CACHECFG_ICACHE_ENABLE_Msk (0x100UL)              /*!< ICACHE_ENABLE (Bitfield-Mask: 0x01)                   */
10048 #define CACHECTRL_CACHECFG_CONFIG_Pos     (4UL)                     /*!< CONFIG (Bit 4)                                        */
10049 #define CACHECTRL_CACHECFG_CONFIG_Msk     (0xf0UL)                  /*!< CONFIG (Bitfield-Mask: 0x0f)                          */
10050 #define CACHECTRL_CACHECFG_ENABLE_NC1_Pos (3UL)                     /*!< ENABLE_NC1 (Bit 3)                                    */
10051 #define CACHECTRL_CACHECFG_ENABLE_NC1_Msk (0x8UL)                   /*!< ENABLE_NC1 (Bitfield-Mask: 0x01)                      */
10052 #define CACHECTRL_CACHECFG_ENABLE_NC0_Pos (2UL)                     /*!< ENABLE_NC0 (Bit 2)                                    */
10053 #define CACHECTRL_CACHECFG_ENABLE_NC0_Msk (0x4UL)                   /*!< ENABLE_NC0 (Bitfield-Mask: 0x01)                      */
10054 #define CACHECTRL_CACHECFG_LRU_Pos        (1UL)                     /*!< LRU (Bit 1)                                           */
10055 #define CACHECTRL_CACHECFG_LRU_Msk        (0x2UL)                   /*!< LRU (Bitfield-Mask: 0x01)                             */
10056 #define CACHECTRL_CACHECFG_ENABLE_Pos     (0UL)                     /*!< ENABLE (Bit 0)                                        */
10057 #define CACHECTRL_CACHECFG_ENABLE_Msk     (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
10058 /* =======================================================  FLASHCFG  ======================================================== */
10059 #define CACHECTRL_FLASHCFG_LPMMODE_Pos    (12UL)                    /*!< LPMMODE (Bit 12)                                      */
10060 #define CACHECTRL_FLASHCFG_LPMMODE_Msk    (0x3000UL)                /*!< LPMMODE (Bitfield-Mask: 0x03)                         */
10061 #define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Pos (8UL)                    /*!< LPM_RD_WAIT (Bit 8)                                   */
10062 #define CACHECTRL_FLASHCFG_LPM_RD_WAIT_Msk (0xf00UL)                /*!< LPM_RD_WAIT (Bitfield-Mask: 0x0f)                     */
10063 #define CACHECTRL_FLASHCFG_SEDELAY_Pos    (4UL)                     /*!< SEDELAY (Bit 4)                                       */
10064 #define CACHECTRL_FLASHCFG_SEDELAY_Msk    (0x70UL)                  /*!< SEDELAY (Bitfield-Mask: 0x07)                         */
10065 #define CACHECTRL_FLASHCFG_RD_WAIT_Pos    (0UL)                     /*!< RD_WAIT (Bit 0)                                       */
10066 #define CACHECTRL_FLASHCFG_RD_WAIT_Msk    (0xfUL)                   /*!< RD_WAIT (Bitfield-Mask: 0x0f)                         */
10067 /* =========================================================  CTRL  ========================================================== */
10068 #define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Pos (10UL)                 /*!< FLASH1_SLM_ENABLE (Bit 10)                            */
10069 #define CACHECTRL_CTRL_FLASH1_SLM_ENABLE_Msk (0x400UL)              /*!< FLASH1_SLM_ENABLE (Bitfield-Mask: 0x01)               */
10070 #define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Pos (9UL)                 /*!< FLASH1_SLM_DISABLE (Bit 9)                            */
10071 #define CACHECTRL_CTRL_FLASH1_SLM_DISABLE_Msk (0x200UL)             /*!< FLASH1_SLM_DISABLE (Bitfield-Mask: 0x01)              */
10072 #define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Pos (8UL)                  /*!< FLASH1_SLM_STATUS (Bit 8)                             */
10073 #define CACHECTRL_CTRL_FLASH1_SLM_STATUS_Msk (0x100UL)              /*!< FLASH1_SLM_STATUS (Bitfield-Mask: 0x01)               */
10074 #define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Pos (6UL)                  /*!< FLASH0_SLM_ENABLE (Bit 6)                             */
10075 #define CACHECTRL_CTRL_FLASH0_SLM_ENABLE_Msk (0x40UL)               /*!< FLASH0_SLM_ENABLE (Bitfield-Mask: 0x01)               */
10076 #define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Pos (5UL)                 /*!< FLASH0_SLM_DISABLE (Bit 5)                            */
10077 #define CACHECTRL_CTRL_FLASH0_SLM_DISABLE_Msk (0x20UL)              /*!< FLASH0_SLM_DISABLE (Bitfield-Mask: 0x01)              */
10078 #define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Pos (4UL)                  /*!< FLASH0_SLM_STATUS (Bit 4)                             */
10079 #define CACHECTRL_CTRL_FLASH0_SLM_STATUS_Msk (0x10UL)               /*!< FLASH0_SLM_STATUS (Bitfield-Mask: 0x01)               */
10080 #define CACHECTRL_CTRL_CACHE_READY_Pos    (2UL)                     /*!< CACHE_READY (Bit 2)                                   */
10081 #define CACHECTRL_CTRL_CACHE_READY_Msk    (0x4UL)                   /*!< CACHE_READY (Bitfield-Mask: 0x01)                     */
10082 #define CACHECTRL_CTRL_RESET_STAT_Pos     (1UL)                     /*!< RESET_STAT (Bit 1)                                    */
10083 #define CACHECTRL_CTRL_RESET_STAT_Msk     (0x2UL)                   /*!< RESET_STAT (Bitfield-Mask: 0x01)                      */
10084 #define CACHECTRL_CTRL_INVALIDATE_Pos     (0UL)                     /*!< INVALIDATE (Bit 0)                                    */
10085 #define CACHECTRL_CTRL_INVALIDATE_Msk     (0x1UL)                   /*!< INVALIDATE (Bitfield-Mask: 0x01)                      */
10086 /* =======================================================  NCR0START  ======================================================= */
10087 #define CACHECTRL_NCR0START_ADDR_Pos      (4UL)                     /*!< ADDR (Bit 4)                                          */
10088 #define CACHECTRL_NCR0START_ADDR_Msk      (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
10089 /* ========================================================  NCR0END  ======================================================== */
10090 #define CACHECTRL_NCR0END_ADDR_Pos        (4UL)                     /*!< ADDR (Bit 4)                                          */
10091 #define CACHECTRL_NCR0END_ADDR_Msk        (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
10092 /* =======================================================  NCR1START  ======================================================= */
10093 #define CACHECTRL_NCR1START_ADDR_Pos      (4UL)                     /*!< ADDR (Bit 4)                                          */
10094 #define CACHECTRL_NCR1START_ADDR_Msk      (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
10095 /* ========================================================  NCR1END  ======================================================== */
10096 #define CACHECTRL_NCR1END_ADDR_Pos        (4UL)                     /*!< ADDR (Bit 4)                                          */
10097 #define CACHECTRL_NCR1END_ADDR_Msk        (0x7fffff0UL)             /*!< ADDR (Bitfield-Mask: 0x7fffff)                        */
10098 /* =========================================================  DMON0  ========================================================= */
10099 #define CACHECTRL_DMON0_DACCESS_COUNT_Pos (0UL)                     /*!< DACCESS_COUNT (Bit 0)                                 */
10100 #define CACHECTRL_DMON0_DACCESS_COUNT_Msk (0xffffffffUL)            /*!< DACCESS_COUNT (Bitfield-Mask: 0xffffffff)             */
10101 /* =========================================================  DMON1  ========================================================= */
10102 #define CACHECTRL_DMON1_DLOOKUP_COUNT_Pos (0UL)                     /*!< DLOOKUP_COUNT (Bit 0)                                 */
10103 #define CACHECTRL_DMON1_DLOOKUP_COUNT_Msk (0xffffffffUL)            /*!< DLOOKUP_COUNT (Bitfield-Mask: 0xffffffff)             */
10104 /* =========================================================  DMON2  ========================================================= */
10105 #define CACHECTRL_DMON2_DHIT_COUNT_Pos    (0UL)                     /*!< DHIT_COUNT (Bit 0)                                    */
10106 #define CACHECTRL_DMON2_DHIT_COUNT_Msk    (0xffffffffUL)            /*!< DHIT_COUNT (Bitfield-Mask: 0xffffffff)                */
10107 /* =========================================================  DMON3  ========================================================= */
10108 #define CACHECTRL_DMON3_DLINE_COUNT_Pos   (0UL)                     /*!< DLINE_COUNT (Bit 0)                                   */
10109 #define CACHECTRL_DMON3_DLINE_COUNT_Msk   (0xffffffffUL)            /*!< DLINE_COUNT (Bitfield-Mask: 0xffffffff)               */
10110 /* =========================================================  IMON0  ========================================================= */
10111 #define CACHECTRL_IMON0_IACCESS_COUNT_Pos (0UL)                     /*!< IACCESS_COUNT (Bit 0)                                 */
10112 #define CACHECTRL_IMON0_IACCESS_COUNT_Msk (0xffffffffUL)            /*!< IACCESS_COUNT (Bitfield-Mask: 0xffffffff)             */
10113 /* =========================================================  IMON1  ========================================================= */
10114 #define CACHECTRL_IMON1_ILOOKUP_COUNT_Pos (0UL)                     /*!< ILOOKUP_COUNT (Bit 0)                                 */
10115 #define CACHECTRL_IMON1_ILOOKUP_COUNT_Msk (0xffffffffUL)            /*!< ILOOKUP_COUNT (Bitfield-Mask: 0xffffffff)             */
10116 /* =========================================================  IMON2  ========================================================= */
10117 #define CACHECTRL_IMON2_IHIT_COUNT_Pos    (0UL)                     /*!< IHIT_COUNT (Bit 0)                                    */
10118 #define CACHECTRL_IMON2_IHIT_COUNT_Msk    (0xffffffffUL)            /*!< IHIT_COUNT (Bitfield-Mask: 0xffffffff)                */
10119 /* =========================================================  IMON3  ========================================================= */
10120 #define CACHECTRL_IMON3_ILINE_COUNT_Pos   (0UL)                     /*!< ILINE_COUNT (Bit 0)                                   */
10121 #define CACHECTRL_IMON3_ILINE_COUNT_Msk   (0xffffffffUL)            /*!< ILINE_COUNT (Bitfield-Mask: 0xffffffff)               */
10122 
10123 
10124 /* =========================================================================================================================== */
10125 /* ================                                          CLKGEN                                           ================ */
10126 /* =========================================================================================================================== */
10127 
10128 /* =========================================================  CALXT  ========================================================= */
10129 #define CLKGEN_CALXT_CALXT_Pos            (0UL)                     /*!< CALXT (Bit 0)                                         */
10130 #define CLKGEN_CALXT_CALXT_Msk            (0x7ffUL)                 /*!< CALXT (Bitfield-Mask: 0x7ff)                          */
10131 /* =========================================================  CALRC  ========================================================= */
10132 #define CLKGEN_CALRC_CALRC_Pos            (0UL)                     /*!< CALRC (Bit 0)                                         */
10133 #define CLKGEN_CALRC_CALRC_Msk            (0x3ffffUL)               /*!< CALRC (Bitfield-Mask: 0x3ffff)                        */
10134 /* ========================================================  ACALCTR  ======================================================== */
10135 #define CLKGEN_ACALCTR_ACALCTR_Pos        (0UL)                     /*!< ACALCTR (Bit 0)                                       */
10136 #define CLKGEN_ACALCTR_ACALCTR_Msk        (0xffffffUL)              /*!< ACALCTR (Bitfield-Mask: 0xffffff)                     */
10137 /* =========================================================  OCTRL  ========================================================= */
10138 #define CLKGEN_OCTRL_ACAL_Pos             (8UL)                     /*!< ACAL (Bit 8)                                          */
10139 #define CLKGEN_OCTRL_ACAL_Msk             (0x700UL)                 /*!< ACAL (Bitfield-Mask: 0x07)                            */
10140 #define CLKGEN_OCTRL_OSEL_Pos             (7UL)                     /*!< OSEL (Bit 7)                                          */
10141 #define CLKGEN_OCTRL_OSEL_Msk             (0x80UL)                  /*!< OSEL (Bitfield-Mask: 0x01)                            */
10142 #define CLKGEN_OCTRL_FOS_Pos              (6UL)                     /*!< FOS (Bit 6)                                           */
10143 #define CLKGEN_OCTRL_FOS_Msk              (0x40UL)                  /*!< FOS (Bitfield-Mask: 0x01)                             */
10144 #define CLKGEN_OCTRL_STOPRC_Pos           (1UL)                     /*!< STOPRC (Bit 1)                                        */
10145 #define CLKGEN_OCTRL_STOPRC_Msk           (0x2UL)                   /*!< STOPRC (Bitfield-Mask: 0x01)                          */
10146 #define CLKGEN_OCTRL_STOPXT_Pos           (0UL)                     /*!< STOPXT (Bit 0)                                        */
10147 #define CLKGEN_OCTRL_STOPXT_Msk           (0x1UL)                   /*!< STOPXT (Bitfield-Mask: 0x01)                          */
10148 /* ========================================================  CLKOUT  ========================================================= */
10149 #define CLKGEN_CLKOUT_CKEN_Pos            (7UL)                     /*!< CKEN (Bit 7)                                          */
10150 #define CLKGEN_CLKOUT_CKEN_Msk            (0x80UL)                  /*!< CKEN (Bitfield-Mask: 0x01)                            */
10151 #define CLKGEN_CLKOUT_CKSEL_Pos           (0UL)                     /*!< CKSEL (Bit 0)                                         */
10152 #define CLKGEN_CLKOUT_CKSEL_Msk           (0x3fUL)                  /*!< CKSEL (Bitfield-Mask: 0x3f)                           */
10153 /* ========================================================  CLKKEY  ========================================================= */
10154 #define CLKGEN_CLKKEY_CLKKEY_Pos          (0UL)                     /*!< CLKKEY (Bit 0)                                        */
10155 #define CLKGEN_CLKKEY_CLKKEY_Msk          (0xffffffffUL)            /*!< CLKKEY (Bitfield-Mask: 0xffffffff)                    */
10156 /* =========================================================  CCTRL  ========================================================= */
10157 #define CLKGEN_CCTRL_CORESEL_Pos          (0UL)                     /*!< CORESEL (Bit 0)                                       */
10158 #define CLKGEN_CCTRL_CORESEL_Msk          (0x1UL)                   /*!< CORESEL (Bitfield-Mask: 0x01)                         */
10159 /* ========================================================  STATUS  ========================================================= */
10160 #define CLKGEN_STATUS_OSCF_Pos            (1UL)                     /*!< OSCF (Bit 1)                                          */
10161 #define CLKGEN_STATUS_OSCF_Msk            (0x2UL)                   /*!< OSCF (Bitfield-Mask: 0x01)                            */
10162 #define CLKGEN_STATUS_OMODE_Pos           (0UL)                     /*!< OMODE (Bit 0)                                         */
10163 #define CLKGEN_STATUS_OMODE_Msk           (0x1UL)                   /*!< OMODE (Bitfield-Mask: 0x01)                           */
10164 /* =========================================================  HFADJ  ========================================================= */
10165 #define CLKGEN_HFADJ_HFADJGAIN_Pos        (21UL)                    /*!< HFADJGAIN (Bit 21)                                    */
10166 #define CLKGEN_HFADJ_HFADJGAIN_Msk        (0xe00000UL)              /*!< HFADJGAIN (Bitfield-Mask: 0x07)                       */
10167 #define CLKGEN_HFADJ_HFWARMUP_Pos         (20UL)                    /*!< HFWARMUP (Bit 20)                                     */
10168 #define CLKGEN_HFADJ_HFWARMUP_Msk         (0x100000UL)              /*!< HFWARMUP (Bitfield-Mask: 0x01)                        */
10169 #define CLKGEN_HFADJ_HFXTADJ_Pos          (8UL)                     /*!< HFXTADJ (Bit 8)                                       */
10170 #define CLKGEN_HFADJ_HFXTADJ_Msk          (0xfff00UL)               /*!< HFXTADJ (Bitfield-Mask: 0xfff)                        */
10171 #define CLKGEN_HFADJ_HFADJCK_Pos          (1UL)                     /*!< HFADJCK (Bit 1)                                       */
10172 #define CLKGEN_HFADJ_HFADJCK_Msk          (0xeUL)                   /*!< HFADJCK (Bitfield-Mask: 0x07)                         */
10173 #define CLKGEN_HFADJ_HFADJEN_Pos          (0UL)                     /*!< HFADJEN (Bit 0)                                       */
10174 #define CLKGEN_HFADJ_HFADJEN_Msk          (0x1UL)                   /*!< HFADJEN (Bitfield-Mask: 0x01)                         */
10175 /* ======================================================  CLOCKENSTAT  ====================================================== */
10176 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Pos (0UL)                    /*!< CLOCKENSTAT (Bit 0)                                   */
10177 #define CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Msk (0xffffffffUL)           /*!< CLOCKENSTAT (Bitfield-Mask: 0xffffffff)               */
10178 /* =====================================================  CLOCKEN2STAT  ====================================================== */
10179 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Pos (0UL)                  /*!< CLOCKEN2STAT (Bit 0)                                  */
10180 #define CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Msk (0xffffffffUL)         /*!< CLOCKEN2STAT (Bitfield-Mask: 0xffffffff)              */
10181 /* =====================================================  CLOCKEN3STAT  ====================================================== */
10182 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Pos (0UL)                  /*!< CLOCKEN3STAT (Bit 0)                                  */
10183 #define CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Msk (0xffffffffUL)         /*!< CLOCKEN3STAT (Bitfield-Mask: 0xffffffff)              */
10184 /* =======================================================  FREQCTRL  ======================================================== */
10185 #define CLKGEN_FREQCTRL_BURSTSTATUS_Pos   (2UL)                     /*!< BURSTSTATUS (Bit 2)                                   */
10186 #define CLKGEN_FREQCTRL_BURSTSTATUS_Msk   (0x4UL)                   /*!< BURSTSTATUS (Bitfield-Mask: 0x01)                     */
10187 #define CLKGEN_FREQCTRL_BURSTACK_Pos      (1UL)                     /*!< BURSTACK (Bit 1)                                      */
10188 #define CLKGEN_FREQCTRL_BURSTACK_Msk      (0x2UL)                   /*!< BURSTACK (Bitfield-Mask: 0x01)                        */
10189 #define CLKGEN_FREQCTRL_BURSTREQ_Pos      (0UL)                     /*!< BURSTREQ (Bit 0)                                      */
10190 #define CLKGEN_FREQCTRL_BURSTREQ_Msk      (0x1UL)                   /*!< BURSTREQ (Bitfield-Mask: 0x01)                        */
10191 /* =====================================================  BLEBUCKTONADJ  ===================================================== */
10192 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Pos (27UL)             /*!< ZEROLENDETECTEN (Bit 27)                              */
10193 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Msk (0x8000000UL)      /*!< ZEROLENDETECTEN (Bitfield-Mask: 0x01)                 */
10194 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Pos (23UL)           /*!< ZEROLENDETECTTRIM (Bit 23)                            */
10195 #define CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Msk (0x7800000UL)    /*!< ZEROLENDETECTTRIM (Bitfield-Mask: 0x0f)               */
10196 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Pos (22UL)                 /*!< TONADJUSTEN (Bit 22)                                  */
10197 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Msk (0x400000UL)           /*!< TONADJUSTEN (Bitfield-Mask: 0x01)                     */
10198 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Pos (20UL)             /*!< TONADJUSTPERIOD (Bit 20)                              */
10199 #define CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Msk (0x300000UL)       /*!< TONADJUSTPERIOD (Bitfield-Mask: 0x03)                 */
10200 #define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Pos (10UL)            /*!< TONHIGHTHRESHOLD (Bit 10)                             */
10201 #define CLKGEN_BLEBUCKTONADJ_TONHIGHTHRESHOLD_Msk (0xffc00UL)       /*!< TONHIGHTHRESHOLD (Bitfield-Mask: 0x3ff)               */
10202 #define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Pos (0UL)              /*!< TONLOWTHRESHOLD (Bit 0)                               */
10203 #define CLKGEN_BLEBUCKTONADJ_TONLOWTHRESHOLD_Msk (0x3ffUL)          /*!< TONLOWTHRESHOLD (Bitfield-Mask: 0x3ff)                */
10204 /* =======================================================  INTRPTEN  ======================================================== */
10205 #define CLKGEN_INTRPTEN_OF_Pos            (2UL)                     /*!< OF (Bit 2)                                            */
10206 #define CLKGEN_INTRPTEN_OF_Msk            (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
10207 #define CLKGEN_INTRPTEN_ACC_Pos           (1UL)                     /*!< ACC (Bit 1)                                           */
10208 #define CLKGEN_INTRPTEN_ACC_Msk           (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
10209 #define CLKGEN_INTRPTEN_ACF_Pos           (0UL)                     /*!< ACF (Bit 0)                                           */
10210 #define CLKGEN_INTRPTEN_ACF_Msk           (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
10211 /* ======================================================  INTRPTSTAT  ======================================================= */
10212 #define CLKGEN_INTRPTSTAT_OF_Pos          (2UL)                     /*!< OF (Bit 2)                                            */
10213 #define CLKGEN_INTRPTSTAT_OF_Msk          (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
10214 #define CLKGEN_INTRPTSTAT_ACC_Pos         (1UL)                     /*!< ACC (Bit 1)                                           */
10215 #define CLKGEN_INTRPTSTAT_ACC_Msk         (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
10216 #define CLKGEN_INTRPTSTAT_ACF_Pos         (0UL)                     /*!< ACF (Bit 0)                                           */
10217 #define CLKGEN_INTRPTSTAT_ACF_Msk         (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
10218 /* =======================================================  INTRPTCLR  ======================================================= */
10219 #define CLKGEN_INTRPTCLR_OF_Pos           (2UL)                     /*!< OF (Bit 2)                                            */
10220 #define CLKGEN_INTRPTCLR_OF_Msk           (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
10221 #define CLKGEN_INTRPTCLR_ACC_Pos          (1UL)                     /*!< ACC (Bit 1)                                           */
10222 #define CLKGEN_INTRPTCLR_ACC_Msk          (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
10223 #define CLKGEN_INTRPTCLR_ACF_Pos          (0UL)                     /*!< ACF (Bit 0)                                           */
10224 #define CLKGEN_INTRPTCLR_ACF_Msk          (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
10225 /* =======================================================  INTRPTSET  ======================================================= */
10226 #define CLKGEN_INTRPTSET_OF_Pos           (2UL)                     /*!< OF (Bit 2)                                            */
10227 #define CLKGEN_INTRPTSET_OF_Msk           (0x4UL)                   /*!< OF (Bitfield-Mask: 0x01)                              */
10228 #define CLKGEN_INTRPTSET_ACC_Pos          (1UL)                     /*!< ACC (Bit 1)                                           */
10229 #define CLKGEN_INTRPTSET_ACC_Msk          (0x2UL)                   /*!< ACC (Bitfield-Mask: 0x01)                             */
10230 #define CLKGEN_INTRPTSET_ACF_Pos          (0UL)                     /*!< ACF (Bit 0)                                           */
10231 #define CLKGEN_INTRPTSET_ACF_Msk          (0x1UL)                   /*!< ACF (Bitfield-Mask: 0x01)                             */
10232 
10233 
10234 /* =========================================================================================================================== */
10235 /* ================                                          CTIMER                                           ================ */
10236 /* =========================================================================================================================== */
10237 
10238 /* =========================================================  TMR0  ========================================================== */
10239 #define CTIMER_TMR0_CTTMRB0_Pos           (16UL)                    /*!< CTTMRB0 (Bit 16)                                      */
10240 #define CTIMER_TMR0_CTTMRB0_Msk           (0xffff0000UL)            /*!< CTTMRB0 (Bitfield-Mask: 0xffff)                       */
10241 #define CTIMER_TMR0_CTTMRA0_Pos           (0UL)                     /*!< CTTMRA0 (Bit 0)                                       */
10242 #define CTIMER_TMR0_CTTMRA0_Msk           (0xffffUL)                /*!< CTTMRA0 (Bitfield-Mask: 0xffff)                       */
10243 /* ========================================================  CMPRA0  ========================================================= */
10244 #define CTIMER_CMPRA0_CMPR1A0_Pos         (16UL)                    /*!< CMPR1A0 (Bit 16)                                      */
10245 #define CTIMER_CMPRA0_CMPR1A0_Msk         (0xffff0000UL)            /*!< CMPR1A0 (Bitfield-Mask: 0xffff)                       */
10246 #define CTIMER_CMPRA0_CMPR0A0_Pos         (0UL)                     /*!< CMPR0A0 (Bit 0)                                       */
10247 #define CTIMER_CMPRA0_CMPR0A0_Msk         (0xffffUL)                /*!< CMPR0A0 (Bitfield-Mask: 0xffff)                       */
10248 /* ========================================================  CMPRB0  ========================================================= */
10249 #define CTIMER_CMPRB0_CMPR1B0_Pos         (16UL)                    /*!< CMPR1B0 (Bit 16)                                      */
10250 #define CTIMER_CMPRB0_CMPR1B0_Msk         (0xffff0000UL)            /*!< CMPR1B0 (Bitfield-Mask: 0xffff)                       */
10251 #define CTIMER_CMPRB0_CMPR0B0_Pos         (0UL)                     /*!< CMPR0B0 (Bit 0)                                       */
10252 #define CTIMER_CMPRB0_CMPR0B0_Msk         (0xffffUL)                /*!< CMPR0B0 (Bitfield-Mask: 0xffff)                       */
10253 /* =========================================================  CTRL0  ========================================================= */
10254 #define CTIMER_CTRL0_CTLINK0_Pos          (31UL)                    /*!< CTLINK0 (Bit 31)                                      */
10255 #define CTIMER_CTRL0_CTLINK0_Msk          (0x80000000UL)            /*!< CTLINK0 (Bitfield-Mask: 0x01)                         */
10256 #define CTIMER_CTRL0_TMRB0POL_Pos         (28UL)                    /*!< TMRB0POL (Bit 28)                                     */
10257 #define CTIMER_CTRL0_TMRB0POL_Msk         (0x10000000UL)            /*!< TMRB0POL (Bitfield-Mask: 0x01)                        */
10258 #define CTIMER_CTRL0_TMRB0CLR_Pos         (27UL)                    /*!< TMRB0CLR (Bit 27)                                     */
10259 #define CTIMER_CTRL0_TMRB0CLR_Msk         (0x8000000UL)             /*!< TMRB0CLR (Bitfield-Mask: 0x01)                        */
10260 #define CTIMER_CTRL0_TMRB0IE1_Pos         (26UL)                    /*!< TMRB0IE1 (Bit 26)                                     */
10261 #define CTIMER_CTRL0_TMRB0IE1_Msk         (0x4000000UL)             /*!< TMRB0IE1 (Bitfield-Mask: 0x01)                        */
10262 #define CTIMER_CTRL0_TMRB0IE0_Pos         (25UL)                    /*!< TMRB0IE0 (Bit 25)                                     */
10263 #define CTIMER_CTRL0_TMRB0IE0_Msk         (0x2000000UL)             /*!< TMRB0IE0 (Bitfield-Mask: 0x01)                        */
10264 #define CTIMER_CTRL0_TMRB0FN_Pos          (22UL)                    /*!< TMRB0FN (Bit 22)                                      */
10265 #define CTIMER_CTRL0_TMRB0FN_Msk          (0x1c00000UL)             /*!< TMRB0FN (Bitfield-Mask: 0x07)                         */
10266 #define CTIMER_CTRL0_TMRB0CLK_Pos         (17UL)                    /*!< TMRB0CLK (Bit 17)                                     */
10267 #define CTIMER_CTRL0_TMRB0CLK_Msk         (0x3e0000UL)              /*!< TMRB0CLK (Bitfield-Mask: 0x1f)                        */
10268 #define CTIMER_CTRL0_TMRB0EN_Pos          (16UL)                    /*!< TMRB0EN (Bit 16)                                      */
10269 #define CTIMER_CTRL0_TMRB0EN_Msk          (0x10000UL)               /*!< TMRB0EN (Bitfield-Mask: 0x01)                         */
10270 #define CTIMER_CTRL0_TMRA0POL_Pos         (12UL)                    /*!< TMRA0POL (Bit 12)                                     */
10271 #define CTIMER_CTRL0_TMRA0POL_Msk         (0x1000UL)                /*!< TMRA0POL (Bitfield-Mask: 0x01)                        */
10272 #define CTIMER_CTRL0_TMRA0CLR_Pos         (11UL)                    /*!< TMRA0CLR (Bit 11)                                     */
10273 #define CTIMER_CTRL0_TMRA0CLR_Msk         (0x800UL)                 /*!< TMRA0CLR (Bitfield-Mask: 0x01)                        */
10274 #define CTIMER_CTRL0_TMRA0IE1_Pos         (10UL)                    /*!< TMRA0IE1 (Bit 10)                                     */
10275 #define CTIMER_CTRL0_TMRA0IE1_Msk         (0x400UL)                 /*!< TMRA0IE1 (Bitfield-Mask: 0x01)                        */
10276 #define CTIMER_CTRL0_TMRA0IE0_Pos         (9UL)                     /*!< TMRA0IE0 (Bit 9)                                      */
10277 #define CTIMER_CTRL0_TMRA0IE0_Msk         (0x200UL)                 /*!< TMRA0IE0 (Bitfield-Mask: 0x01)                        */
10278 #define CTIMER_CTRL0_TMRA0FN_Pos          (6UL)                     /*!< TMRA0FN (Bit 6)                                       */
10279 #define CTIMER_CTRL0_TMRA0FN_Msk          (0x1c0UL)                 /*!< TMRA0FN (Bitfield-Mask: 0x07)                         */
10280 #define CTIMER_CTRL0_TMRA0CLK_Pos         (1UL)                     /*!< TMRA0CLK (Bit 1)                                      */
10281 #define CTIMER_CTRL0_TMRA0CLK_Msk         (0x3eUL)                  /*!< TMRA0CLK (Bitfield-Mask: 0x1f)                        */
10282 #define CTIMER_CTRL0_TMRA0EN_Pos          (0UL)                     /*!< TMRA0EN (Bit 0)                                       */
10283 #define CTIMER_CTRL0_TMRA0EN_Msk          (0x1UL)                   /*!< TMRA0EN (Bitfield-Mask: 0x01)                         */
10284 /* =======================================================  CMPRAUXA0  ======================================================= */
10285 #define CTIMER_CMPRAUXA0_CMPR3A0_Pos      (16UL)                    /*!< CMPR3A0 (Bit 16)                                      */
10286 #define CTIMER_CMPRAUXA0_CMPR3A0_Msk      (0xffff0000UL)            /*!< CMPR3A0 (Bitfield-Mask: 0xffff)                       */
10287 #define CTIMER_CMPRAUXA0_CMPR2A0_Pos      (0UL)                     /*!< CMPR2A0 (Bit 0)                                       */
10288 #define CTIMER_CMPRAUXA0_CMPR2A0_Msk      (0xffffUL)                /*!< CMPR2A0 (Bitfield-Mask: 0xffff)                       */
10289 /* =======================================================  CMPRAUXB0  ======================================================= */
10290 #define CTIMER_CMPRAUXB0_CMPR3B0_Pos      (16UL)                    /*!< CMPR3B0 (Bit 16)                                      */
10291 #define CTIMER_CMPRAUXB0_CMPR3B0_Msk      (0xffff0000UL)            /*!< CMPR3B0 (Bitfield-Mask: 0xffff)                       */
10292 #define CTIMER_CMPRAUXB0_CMPR2B0_Pos      (0UL)                     /*!< CMPR2B0 (Bit 0)                                       */
10293 #define CTIMER_CMPRAUXB0_CMPR2B0_Msk      (0xffffUL)                /*!< CMPR2B0 (Bitfield-Mask: 0xffff)                       */
10294 /* =========================================================  AUX0  ========================================================== */
10295 #define CTIMER_AUX0_TMRB0EN23_Pos         (30UL)                    /*!< TMRB0EN23 (Bit 30)                                    */
10296 #define CTIMER_AUX0_TMRB0EN23_Msk         (0x40000000UL)            /*!< TMRB0EN23 (Bitfield-Mask: 0x01)                       */
10297 #define CTIMER_AUX0_TMRB0POL23_Pos        (29UL)                    /*!< TMRB0POL23 (Bit 29)                                   */
10298 #define CTIMER_AUX0_TMRB0POL23_Msk        (0x20000000UL)            /*!< TMRB0POL23 (Bitfield-Mask: 0x01)                      */
10299 #define CTIMER_AUX0_TMRB0TINV_Pos         (28UL)                    /*!< TMRB0TINV (Bit 28)                                    */
10300 #define CTIMER_AUX0_TMRB0TINV_Msk         (0x10000000UL)            /*!< TMRB0TINV (Bitfield-Mask: 0x01)                       */
10301 #define CTIMER_AUX0_TMRB0NOSYNC_Pos       (27UL)                    /*!< TMRB0NOSYNC (Bit 27)                                  */
10302 #define CTIMER_AUX0_TMRB0NOSYNC_Msk       (0x8000000UL)             /*!< TMRB0NOSYNC (Bitfield-Mask: 0x01)                     */
10303 #define CTIMER_AUX0_TMRB0TRIG_Pos         (23UL)                    /*!< TMRB0TRIG (Bit 23)                                    */
10304 #define CTIMER_AUX0_TMRB0TRIG_Msk         (0x7800000UL)             /*!< TMRB0TRIG (Bitfield-Mask: 0x0f)                       */
10305 #define CTIMER_AUX0_TMRB0LMT_Pos          (16UL)                    /*!< TMRB0LMT (Bit 16)                                     */
10306 #define CTIMER_AUX0_TMRB0LMT_Msk          (0x3f0000UL)              /*!< TMRB0LMT (Bitfield-Mask: 0x3f)                        */
10307 #define CTIMER_AUX0_TMRA0EN23_Pos         (14UL)                    /*!< TMRA0EN23 (Bit 14)                                    */
10308 #define CTIMER_AUX0_TMRA0EN23_Msk         (0x4000UL)                /*!< TMRA0EN23 (Bitfield-Mask: 0x01)                       */
10309 #define CTIMER_AUX0_TMRA0POL23_Pos        (13UL)                    /*!< TMRA0POL23 (Bit 13)                                   */
10310 #define CTIMER_AUX0_TMRA0POL23_Msk        (0x2000UL)                /*!< TMRA0POL23 (Bitfield-Mask: 0x01)                      */
10311 #define CTIMER_AUX0_TMRA0TINV_Pos         (12UL)                    /*!< TMRA0TINV (Bit 12)                                    */
10312 #define CTIMER_AUX0_TMRA0TINV_Msk         (0x1000UL)                /*!< TMRA0TINV (Bitfield-Mask: 0x01)                       */
10313 #define CTIMER_AUX0_TMRA0NOSYNC_Pos       (11UL)                    /*!< TMRA0NOSYNC (Bit 11)                                  */
10314 #define CTIMER_AUX0_TMRA0NOSYNC_Msk       (0x800UL)                 /*!< TMRA0NOSYNC (Bitfield-Mask: 0x01)                     */
10315 #define CTIMER_AUX0_TMRA0TRIG_Pos         (7UL)                     /*!< TMRA0TRIG (Bit 7)                                     */
10316 #define CTIMER_AUX0_TMRA0TRIG_Msk         (0x780UL)                 /*!< TMRA0TRIG (Bitfield-Mask: 0x0f)                       */
10317 #define CTIMER_AUX0_TMRA0LMT_Pos          (0UL)                     /*!< TMRA0LMT (Bit 0)                                      */
10318 #define CTIMER_AUX0_TMRA0LMT_Msk          (0x7fUL)                  /*!< TMRA0LMT (Bitfield-Mask: 0x7f)                        */
10319 /* =========================================================  TMR1  ========================================================== */
10320 #define CTIMER_TMR1_CTTMRB1_Pos           (16UL)                    /*!< CTTMRB1 (Bit 16)                                      */
10321 #define CTIMER_TMR1_CTTMRB1_Msk           (0xffff0000UL)            /*!< CTTMRB1 (Bitfield-Mask: 0xffff)                       */
10322 #define CTIMER_TMR1_CTTMRA1_Pos           (0UL)                     /*!< CTTMRA1 (Bit 0)                                       */
10323 #define CTIMER_TMR1_CTTMRA1_Msk           (0xffffUL)                /*!< CTTMRA1 (Bitfield-Mask: 0xffff)                       */
10324 /* ========================================================  CMPRA1  ========================================================= */
10325 #define CTIMER_CMPRA1_CMPR1A1_Pos         (16UL)                    /*!< CMPR1A1 (Bit 16)                                      */
10326 #define CTIMER_CMPRA1_CMPR1A1_Msk         (0xffff0000UL)            /*!< CMPR1A1 (Bitfield-Mask: 0xffff)                       */
10327 #define CTIMER_CMPRA1_CMPR0A1_Pos         (0UL)                     /*!< CMPR0A1 (Bit 0)                                       */
10328 #define CTIMER_CMPRA1_CMPR0A1_Msk         (0xffffUL)                /*!< CMPR0A1 (Bitfield-Mask: 0xffff)                       */
10329 /* ========================================================  CMPRB1  ========================================================= */
10330 #define CTIMER_CMPRB1_CMPR1B1_Pos         (16UL)                    /*!< CMPR1B1 (Bit 16)                                      */
10331 #define CTIMER_CMPRB1_CMPR1B1_Msk         (0xffff0000UL)            /*!< CMPR1B1 (Bitfield-Mask: 0xffff)                       */
10332 #define CTIMER_CMPRB1_CMPR0B1_Pos         (0UL)                     /*!< CMPR0B1 (Bit 0)                                       */
10333 #define CTIMER_CMPRB1_CMPR0B1_Msk         (0xffffUL)                /*!< CMPR0B1 (Bitfield-Mask: 0xffff)                       */
10334 /* =========================================================  CTRL1  ========================================================= */
10335 #define CTIMER_CTRL1_CTLINK1_Pos          (31UL)                    /*!< CTLINK1 (Bit 31)                                      */
10336 #define CTIMER_CTRL1_CTLINK1_Msk          (0x80000000UL)            /*!< CTLINK1 (Bitfield-Mask: 0x01)                         */
10337 #define CTIMER_CTRL1_TMRB1POL_Pos         (28UL)                    /*!< TMRB1POL (Bit 28)                                     */
10338 #define CTIMER_CTRL1_TMRB1POL_Msk         (0x10000000UL)            /*!< TMRB1POL (Bitfield-Mask: 0x01)                        */
10339 #define CTIMER_CTRL1_TMRB1CLR_Pos         (27UL)                    /*!< TMRB1CLR (Bit 27)                                     */
10340 #define CTIMER_CTRL1_TMRB1CLR_Msk         (0x8000000UL)             /*!< TMRB1CLR (Bitfield-Mask: 0x01)                        */
10341 #define CTIMER_CTRL1_TMRB1IE1_Pos         (26UL)                    /*!< TMRB1IE1 (Bit 26)                                     */
10342 #define CTIMER_CTRL1_TMRB1IE1_Msk         (0x4000000UL)             /*!< TMRB1IE1 (Bitfield-Mask: 0x01)                        */
10343 #define CTIMER_CTRL1_TMRB1IE0_Pos         (25UL)                    /*!< TMRB1IE0 (Bit 25)                                     */
10344 #define CTIMER_CTRL1_TMRB1IE0_Msk         (0x2000000UL)             /*!< TMRB1IE0 (Bitfield-Mask: 0x01)                        */
10345 #define CTIMER_CTRL1_TMRB1FN_Pos          (22UL)                    /*!< TMRB1FN (Bit 22)                                      */
10346 #define CTIMER_CTRL1_TMRB1FN_Msk          (0x1c00000UL)             /*!< TMRB1FN (Bitfield-Mask: 0x07)                         */
10347 #define CTIMER_CTRL1_TMRB1CLK_Pos         (17UL)                    /*!< TMRB1CLK (Bit 17)                                     */
10348 #define CTIMER_CTRL1_TMRB1CLK_Msk         (0x3e0000UL)              /*!< TMRB1CLK (Bitfield-Mask: 0x1f)                        */
10349 #define CTIMER_CTRL1_TMRB1EN_Pos          (16UL)                    /*!< TMRB1EN (Bit 16)                                      */
10350 #define CTIMER_CTRL1_TMRB1EN_Msk          (0x10000UL)               /*!< TMRB1EN (Bitfield-Mask: 0x01)                         */
10351 #define CTIMER_CTRL1_TMRA1POL_Pos         (12UL)                    /*!< TMRA1POL (Bit 12)                                     */
10352 #define CTIMER_CTRL1_TMRA1POL_Msk         (0x1000UL)                /*!< TMRA1POL (Bitfield-Mask: 0x01)                        */
10353 #define CTIMER_CTRL1_TMRA1CLR_Pos         (11UL)                    /*!< TMRA1CLR (Bit 11)                                     */
10354 #define CTIMER_CTRL1_TMRA1CLR_Msk         (0x800UL)                 /*!< TMRA1CLR (Bitfield-Mask: 0x01)                        */
10355 #define CTIMER_CTRL1_TMRA1IE1_Pos         (10UL)                    /*!< TMRA1IE1 (Bit 10)                                     */
10356 #define CTIMER_CTRL1_TMRA1IE1_Msk         (0x400UL)                 /*!< TMRA1IE1 (Bitfield-Mask: 0x01)                        */
10357 #define CTIMER_CTRL1_TMRA1IE0_Pos         (9UL)                     /*!< TMRA1IE0 (Bit 9)                                      */
10358 #define CTIMER_CTRL1_TMRA1IE0_Msk         (0x200UL)                 /*!< TMRA1IE0 (Bitfield-Mask: 0x01)                        */
10359 #define CTIMER_CTRL1_TMRA1FN_Pos          (6UL)                     /*!< TMRA1FN (Bit 6)                                       */
10360 #define CTIMER_CTRL1_TMRA1FN_Msk          (0x1c0UL)                 /*!< TMRA1FN (Bitfield-Mask: 0x07)                         */
10361 #define CTIMER_CTRL1_TMRA1CLK_Pos         (1UL)                     /*!< TMRA1CLK (Bit 1)                                      */
10362 #define CTIMER_CTRL1_TMRA1CLK_Msk         (0x3eUL)                  /*!< TMRA1CLK (Bitfield-Mask: 0x1f)                        */
10363 #define CTIMER_CTRL1_TMRA1EN_Pos          (0UL)                     /*!< TMRA1EN (Bit 0)                                       */
10364 #define CTIMER_CTRL1_TMRA1EN_Msk          (0x1UL)                   /*!< TMRA1EN (Bitfield-Mask: 0x01)                         */
10365 /* =======================================================  CMPRAUXA1  ======================================================= */
10366 #define CTIMER_CMPRAUXA1_CMPR3A1_Pos      (16UL)                    /*!< CMPR3A1 (Bit 16)                                      */
10367 #define CTIMER_CMPRAUXA1_CMPR3A1_Msk      (0xffff0000UL)            /*!< CMPR3A1 (Bitfield-Mask: 0xffff)                       */
10368 #define CTIMER_CMPRAUXA1_CMPR2A1_Pos      (0UL)                     /*!< CMPR2A1 (Bit 0)                                       */
10369 #define CTIMER_CMPRAUXA1_CMPR2A1_Msk      (0xffffUL)                /*!< CMPR2A1 (Bitfield-Mask: 0xffff)                       */
10370 /* =======================================================  CMPRAUXB1  ======================================================= */
10371 #define CTIMER_CMPRAUXB1_CMPR3B1_Pos      (16UL)                    /*!< CMPR3B1 (Bit 16)                                      */
10372 #define CTIMER_CMPRAUXB1_CMPR3B1_Msk      (0xffff0000UL)            /*!< CMPR3B1 (Bitfield-Mask: 0xffff)                       */
10373 #define CTIMER_CMPRAUXB1_CMPR2B1_Pos      (0UL)                     /*!< CMPR2B1 (Bit 0)                                       */
10374 #define CTIMER_CMPRAUXB1_CMPR2B1_Msk      (0xffffUL)                /*!< CMPR2B1 (Bitfield-Mask: 0xffff)                       */
10375 /* =========================================================  AUX1  ========================================================== */
10376 #define CTIMER_AUX1_TMRB1EN23_Pos         (30UL)                    /*!< TMRB1EN23 (Bit 30)                                    */
10377 #define CTIMER_AUX1_TMRB1EN23_Msk         (0x40000000UL)            /*!< TMRB1EN23 (Bitfield-Mask: 0x01)                       */
10378 #define CTIMER_AUX1_TMRB1POL23_Pos        (29UL)                    /*!< TMRB1POL23 (Bit 29)                                   */
10379 #define CTIMER_AUX1_TMRB1POL23_Msk        (0x20000000UL)            /*!< TMRB1POL23 (Bitfield-Mask: 0x01)                      */
10380 #define CTIMER_AUX1_TMRB1TINV_Pos         (28UL)                    /*!< TMRB1TINV (Bit 28)                                    */
10381 #define CTIMER_AUX1_TMRB1TINV_Msk         (0x10000000UL)            /*!< TMRB1TINV (Bitfield-Mask: 0x01)                       */
10382 #define CTIMER_AUX1_TMRB1NOSYNC_Pos       (27UL)                    /*!< TMRB1NOSYNC (Bit 27)                                  */
10383 #define CTIMER_AUX1_TMRB1NOSYNC_Msk       (0x8000000UL)             /*!< TMRB1NOSYNC (Bitfield-Mask: 0x01)                     */
10384 #define CTIMER_AUX1_TMRB1TRIG_Pos         (23UL)                    /*!< TMRB1TRIG (Bit 23)                                    */
10385 #define CTIMER_AUX1_TMRB1TRIG_Msk         (0x7800000UL)             /*!< TMRB1TRIG (Bitfield-Mask: 0x0f)                       */
10386 #define CTIMER_AUX1_TMRB1LMT_Pos          (16UL)                    /*!< TMRB1LMT (Bit 16)                                     */
10387 #define CTIMER_AUX1_TMRB1LMT_Msk          (0x3f0000UL)              /*!< TMRB1LMT (Bitfield-Mask: 0x3f)                        */
10388 #define CTIMER_AUX1_TMRA1EN23_Pos         (14UL)                    /*!< TMRA1EN23 (Bit 14)                                    */
10389 #define CTIMER_AUX1_TMRA1EN23_Msk         (0x4000UL)                /*!< TMRA1EN23 (Bitfield-Mask: 0x01)                       */
10390 #define CTIMER_AUX1_TMRA1POL23_Pos        (13UL)                    /*!< TMRA1POL23 (Bit 13)                                   */
10391 #define CTIMER_AUX1_TMRA1POL23_Msk        (0x2000UL)                /*!< TMRA1POL23 (Bitfield-Mask: 0x01)                      */
10392 #define CTIMER_AUX1_TMRA1TINV_Pos         (12UL)                    /*!< TMRA1TINV (Bit 12)                                    */
10393 #define CTIMER_AUX1_TMRA1TINV_Msk         (0x1000UL)                /*!< TMRA1TINV (Bitfield-Mask: 0x01)                       */
10394 #define CTIMER_AUX1_TMRA1NOSYNC_Pos       (11UL)                    /*!< TMRA1NOSYNC (Bit 11)                                  */
10395 #define CTIMER_AUX1_TMRA1NOSYNC_Msk       (0x800UL)                 /*!< TMRA1NOSYNC (Bitfield-Mask: 0x01)                     */
10396 #define CTIMER_AUX1_TMRA1TRIG_Pos         (7UL)                     /*!< TMRA1TRIG (Bit 7)                                     */
10397 #define CTIMER_AUX1_TMRA1TRIG_Msk         (0x780UL)                 /*!< TMRA1TRIG (Bitfield-Mask: 0x0f)                       */
10398 #define CTIMER_AUX1_TMRA1LMT_Pos          (0UL)                     /*!< TMRA1LMT (Bit 0)                                      */
10399 #define CTIMER_AUX1_TMRA1LMT_Msk          (0x7fUL)                  /*!< TMRA1LMT (Bitfield-Mask: 0x7f)                        */
10400 /* =========================================================  TMR2  ========================================================== */
10401 #define CTIMER_TMR2_CTTMRB2_Pos           (16UL)                    /*!< CTTMRB2 (Bit 16)                                      */
10402 #define CTIMER_TMR2_CTTMRB2_Msk           (0xffff0000UL)            /*!< CTTMRB2 (Bitfield-Mask: 0xffff)                       */
10403 #define CTIMER_TMR2_CTTMRA2_Pos           (0UL)                     /*!< CTTMRA2 (Bit 0)                                       */
10404 #define CTIMER_TMR2_CTTMRA2_Msk           (0xffffUL)                /*!< CTTMRA2 (Bitfield-Mask: 0xffff)                       */
10405 /* ========================================================  CMPRA2  ========================================================= */
10406 #define CTIMER_CMPRA2_CMPR1A2_Pos         (16UL)                    /*!< CMPR1A2 (Bit 16)                                      */
10407 #define CTIMER_CMPRA2_CMPR1A2_Msk         (0xffff0000UL)            /*!< CMPR1A2 (Bitfield-Mask: 0xffff)                       */
10408 #define CTIMER_CMPRA2_CMPR0A2_Pos         (0UL)                     /*!< CMPR0A2 (Bit 0)                                       */
10409 #define CTIMER_CMPRA2_CMPR0A2_Msk         (0xffffUL)                /*!< CMPR0A2 (Bitfield-Mask: 0xffff)                       */
10410 /* ========================================================  CMPRB2  ========================================================= */
10411 #define CTIMER_CMPRB2_CMPR1B2_Pos         (16UL)                    /*!< CMPR1B2 (Bit 16)                                      */
10412 #define CTIMER_CMPRB2_CMPR1B2_Msk         (0xffff0000UL)            /*!< CMPR1B2 (Bitfield-Mask: 0xffff)                       */
10413 #define CTIMER_CMPRB2_CMPR0B2_Pos         (0UL)                     /*!< CMPR0B2 (Bit 0)                                       */
10414 #define CTIMER_CMPRB2_CMPR0B2_Msk         (0xffffUL)                /*!< CMPR0B2 (Bitfield-Mask: 0xffff)                       */
10415 /* =========================================================  CTRL2  ========================================================= */
10416 #define CTIMER_CTRL2_CTLINK2_Pos          (31UL)                    /*!< CTLINK2 (Bit 31)                                      */
10417 #define CTIMER_CTRL2_CTLINK2_Msk          (0x80000000UL)            /*!< CTLINK2 (Bitfield-Mask: 0x01)                         */
10418 #define CTIMER_CTRL2_TMRB2POL_Pos         (28UL)                    /*!< TMRB2POL (Bit 28)                                     */
10419 #define CTIMER_CTRL2_TMRB2POL_Msk         (0x10000000UL)            /*!< TMRB2POL (Bitfield-Mask: 0x01)                        */
10420 #define CTIMER_CTRL2_TMRB2CLR_Pos         (27UL)                    /*!< TMRB2CLR (Bit 27)                                     */
10421 #define CTIMER_CTRL2_TMRB2CLR_Msk         (0x8000000UL)             /*!< TMRB2CLR (Bitfield-Mask: 0x01)                        */
10422 #define CTIMER_CTRL2_TMRB2IE1_Pos         (26UL)                    /*!< TMRB2IE1 (Bit 26)                                     */
10423 #define CTIMER_CTRL2_TMRB2IE1_Msk         (0x4000000UL)             /*!< TMRB2IE1 (Bitfield-Mask: 0x01)                        */
10424 #define CTIMER_CTRL2_TMRB2IE0_Pos         (25UL)                    /*!< TMRB2IE0 (Bit 25)                                     */
10425 #define CTIMER_CTRL2_TMRB2IE0_Msk         (0x2000000UL)             /*!< TMRB2IE0 (Bitfield-Mask: 0x01)                        */
10426 #define CTIMER_CTRL2_TMRB2FN_Pos          (22UL)                    /*!< TMRB2FN (Bit 22)                                      */
10427 #define CTIMER_CTRL2_TMRB2FN_Msk          (0x1c00000UL)             /*!< TMRB2FN (Bitfield-Mask: 0x07)                         */
10428 #define CTIMER_CTRL2_TMRB2CLK_Pos         (17UL)                    /*!< TMRB2CLK (Bit 17)                                     */
10429 #define CTIMER_CTRL2_TMRB2CLK_Msk         (0x3e0000UL)              /*!< TMRB2CLK (Bitfield-Mask: 0x1f)                        */
10430 #define CTIMER_CTRL2_TMRB2EN_Pos          (16UL)                    /*!< TMRB2EN (Bit 16)                                      */
10431 #define CTIMER_CTRL2_TMRB2EN_Msk          (0x10000UL)               /*!< TMRB2EN (Bitfield-Mask: 0x01)                         */
10432 #define CTIMER_CTRL2_TMRA2POL_Pos         (12UL)                    /*!< TMRA2POL (Bit 12)                                     */
10433 #define CTIMER_CTRL2_TMRA2POL_Msk         (0x1000UL)                /*!< TMRA2POL (Bitfield-Mask: 0x01)                        */
10434 #define CTIMER_CTRL2_TMRA2CLR_Pos         (11UL)                    /*!< TMRA2CLR (Bit 11)                                     */
10435 #define CTIMER_CTRL2_TMRA2CLR_Msk         (0x800UL)                 /*!< TMRA2CLR (Bitfield-Mask: 0x01)                        */
10436 #define CTIMER_CTRL2_TMRA2IE1_Pos         (10UL)                    /*!< TMRA2IE1 (Bit 10)                                     */
10437 #define CTIMER_CTRL2_TMRA2IE1_Msk         (0x400UL)                 /*!< TMRA2IE1 (Bitfield-Mask: 0x01)                        */
10438 #define CTIMER_CTRL2_TMRA2IE0_Pos         (9UL)                     /*!< TMRA2IE0 (Bit 9)                                      */
10439 #define CTIMER_CTRL2_TMRA2IE0_Msk         (0x200UL)                 /*!< TMRA2IE0 (Bitfield-Mask: 0x01)                        */
10440 #define CTIMER_CTRL2_TMRA2FN_Pos          (6UL)                     /*!< TMRA2FN (Bit 6)                                       */
10441 #define CTIMER_CTRL2_TMRA2FN_Msk          (0x1c0UL)                 /*!< TMRA2FN (Bitfield-Mask: 0x07)                         */
10442 #define CTIMER_CTRL2_TMRA2CLK_Pos         (1UL)                     /*!< TMRA2CLK (Bit 1)                                      */
10443 #define CTIMER_CTRL2_TMRA2CLK_Msk         (0x3eUL)                  /*!< TMRA2CLK (Bitfield-Mask: 0x1f)                        */
10444 #define CTIMER_CTRL2_TMRA2EN_Pos          (0UL)                     /*!< TMRA2EN (Bit 0)                                       */
10445 #define CTIMER_CTRL2_TMRA2EN_Msk          (0x1UL)                   /*!< TMRA2EN (Bitfield-Mask: 0x01)                         */
10446 /* =======================================================  CMPRAUXA2  ======================================================= */
10447 #define CTIMER_CMPRAUXA2_CMPR3A2_Pos      (16UL)                    /*!< CMPR3A2 (Bit 16)                                      */
10448 #define CTIMER_CMPRAUXA2_CMPR3A2_Msk      (0xffff0000UL)            /*!< CMPR3A2 (Bitfield-Mask: 0xffff)                       */
10449 #define CTIMER_CMPRAUXA2_CMPR2A2_Pos      (0UL)                     /*!< CMPR2A2 (Bit 0)                                       */
10450 #define CTIMER_CMPRAUXA2_CMPR2A2_Msk      (0xffffUL)                /*!< CMPR2A2 (Bitfield-Mask: 0xffff)                       */
10451 /* =======================================================  CMPRAUXB2  ======================================================= */
10452 #define CTIMER_CMPRAUXB2_CMPR3B2_Pos      (16UL)                    /*!< CMPR3B2 (Bit 16)                                      */
10453 #define CTIMER_CMPRAUXB2_CMPR3B2_Msk      (0xffff0000UL)            /*!< CMPR3B2 (Bitfield-Mask: 0xffff)                       */
10454 #define CTIMER_CMPRAUXB2_CMPR2B2_Pos      (0UL)                     /*!< CMPR2B2 (Bit 0)                                       */
10455 #define CTIMER_CMPRAUXB2_CMPR2B2_Msk      (0xffffUL)                /*!< CMPR2B2 (Bitfield-Mask: 0xffff)                       */
10456 /* =========================================================  AUX2  ========================================================== */
10457 #define CTIMER_AUX2_TMRB2EN23_Pos         (30UL)                    /*!< TMRB2EN23 (Bit 30)                                    */
10458 #define CTIMER_AUX2_TMRB2EN23_Msk         (0x40000000UL)            /*!< TMRB2EN23 (Bitfield-Mask: 0x01)                       */
10459 #define CTIMER_AUX2_TMRB2POL23_Pos        (29UL)                    /*!< TMRB2POL23 (Bit 29)                                   */
10460 #define CTIMER_AUX2_TMRB2POL23_Msk        (0x20000000UL)            /*!< TMRB2POL23 (Bitfield-Mask: 0x01)                      */
10461 #define CTIMER_AUX2_TMRB2TINV_Pos         (28UL)                    /*!< TMRB2TINV (Bit 28)                                    */
10462 #define CTIMER_AUX2_TMRB2TINV_Msk         (0x10000000UL)            /*!< TMRB2TINV (Bitfield-Mask: 0x01)                       */
10463 #define CTIMER_AUX2_TMRB2NOSYNC_Pos       (27UL)                    /*!< TMRB2NOSYNC (Bit 27)                                  */
10464 #define CTIMER_AUX2_TMRB2NOSYNC_Msk       (0x8000000UL)             /*!< TMRB2NOSYNC (Bitfield-Mask: 0x01)                     */
10465 #define CTIMER_AUX2_TMRB2TRIG_Pos         (23UL)                    /*!< TMRB2TRIG (Bit 23)                                    */
10466 #define CTIMER_AUX2_TMRB2TRIG_Msk         (0x7800000UL)             /*!< TMRB2TRIG (Bitfield-Mask: 0x0f)                       */
10467 #define CTIMER_AUX2_TMRB2LMT_Pos          (16UL)                    /*!< TMRB2LMT (Bit 16)                                     */
10468 #define CTIMER_AUX2_TMRB2LMT_Msk          (0x3f0000UL)              /*!< TMRB2LMT (Bitfield-Mask: 0x3f)                        */
10469 #define CTIMER_AUX2_TMRA2EN23_Pos         (14UL)                    /*!< TMRA2EN23 (Bit 14)                                    */
10470 #define CTIMER_AUX2_TMRA2EN23_Msk         (0x4000UL)                /*!< TMRA2EN23 (Bitfield-Mask: 0x01)                       */
10471 #define CTIMER_AUX2_TMRA2POL23_Pos        (13UL)                    /*!< TMRA2POL23 (Bit 13)                                   */
10472 #define CTIMER_AUX2_TMRA2POL23_Msk        (0x2000UL)                /*!< TMRA2POL23 (Bitfield-Mask: 0x01)                      */
10473 #define CTIMER_AUX2_TMRA2TINV_Pos         (12UL)                    /*!< TMRA2TINV (Bit 12)                                    */
10474 #define CTIMER_AUX2_TMRA2TINV_Msk         (0x1000UL)                /*!< TMRA2TINV (Bitfield-Mask: 0x01)                       */
10475 #define CTIMER_AUX2_TMRA2NOSYNC_Pos       (11UL)                    /*!< TMRA2NOSYNC (Bit 11)                                  */
10476 #define CTIMER_AUX2_TMRA2NOSYNC_Msk       (0x800UL)                 /*!< TMRA2NOSYNC (Bitfield-Mask: 0x01)                     */
10477 #define CTIMER_AUX2_TMRA2TRIG_Pos         (7UL)                     /*!< TMRA2TRIG (Bit 7)                                     */
10478 #define CTIMER_AUX2_TMRA2TRIG_Msk         (0x780UL)                 /*!< TMRA2TRIG (Bitfield-Mask: 0x0f)                       */
10479 #define CTIMER_AUX2_TMRA2LMT_Pos          (0UL)                     /*!< TMRA2LMT (Bit 0)                                      */
10480 #define CTIMER_AUX2_TMRA2LMT_Msk          (0x7fUL)                  /*!< TMRA2LMT (Bitfield-Mask: 0x7f)                        */
10481 /* =========================================================  TMR3  ========================================================== */
10482 #define CTIMER_TMR3_CTTMRB3_Pos           (16UL)                    /*!< CTTMRB3 (Bit 16)                                      */
10483 #define CTIMER_TMR3_CTTMRB3_Msk           (0xffff0000UL)            /*!< CTTMRB3 (Bitfield-Mask: 0xffff)                       */
10484 #define CTIMER_TMR3_CTTMRA3_Pos           (0UL)                     /*!< CTTMRA3 (Bit 0)                                       */
10485 #define CTIMER_TMR3_CTTMRA3_Msk           (0xffffUL)                /*!< CTTMRA3 (Bitfield-Mask: 0xffff)                       */
10486 /* ========================================================  CMPRA3  ========================================================= */
10487 #define CTIMER_CMPRA3_CMPR1A3_Pos         (16UL)                    /*!< CMPR1A3 (Bit 16)                                      */
10488 #define CTIMER_CMPRA3_CMPR1A3_Msk         (0xffff0000UL)            /*!< CMPR1A3 (Bitfield-Mask: 0xffff)                       */
10489 #define CTIMER_CMPRA3_CMPR0A3_Pos         (0UL)                     /*!< CMPR0A3 (Bit 0)                                       */
10490 #define CTIMER_CMPRA3_CMPR0A3_Msk         (0xffffUL)                /*!< CMPR0A3 (Bitfield-Mask: 0xffff)                       */
10491 /* ========================================================  CMPRB3  ========================================================= */
10492 #define CTIMER_CMPRB3_CMPR1B3_Pos         (16UL)                    /*!< CMPR1B3 (Bit 16)                                      */
10493 #define CTIMER_CMPRB3_CMPR1B3_Msk         (0xffff0000UL)            /*!< CMPR1B3 (Bitfield-Mask: 0xffff)                       */
10494 #define CTIMER_CMPRB3_CMPR0B3_Pos         (0UL)                     /*!< CMPR0B3 (Bit 0)                                       */
10495 #define CTIMER_CMPRB3_CMPR0B3_Msk         (0xffffUL)                /*!< CMPR0B3 (Bitfield-Mask: 0xffff)                       */
10496 /* =========================================================  CTRL3  ========================================================= */
10497 #define CTIMER_CTRL3_CTLINK3_Pos          (31UL)                    /*!< CTLINK3 (Bit 31)                                      */
10498 #define CTIMER_CTRL3_CTLINK3_Msk          (0x80000000UL)            /*!< CTLINK3 (Bitfield-Mask: 0x01)                         */
10499 #define CTIMER_CTRL3_TMRB3POL_Pos         (28UL)                    /*!< TMRB3POL (Bit 28)                                     */
10500 #define CTIMER_CTRL3_TMRB3POL_Msk         (0x10000000UL)            /*!< TMRB3POL (Bitfield-Mask: 0x01)                        */
10501 #define CTIMER_CTRL3_TMRB3CLR_Pos         (27UL)                    /*!< TMRB3CLR (Bit 27)                                     */
10502 #define CTIMER_CTRL3_TMRB3CLR_Msk         (0x8000000UL)             /*!< TMRB3CLR (Bitfield-Mask: 0x01)                        */
10503 #define CTIMER_CTRL3_TMRB3IE1_Pos         (26UL)                    /*!< TMRB3IE1 (Bit 26)                                     */
10504 #define CTIMER_CTRL3_TMRB3IE1_Msk         (0x4000000UL)             /*!< TMRB3IE1 (Bitfield-Mask: 0x01)                        */
10505 #define CTIMER_CTRL3_TMRB3IE0_Pos         (25UL)                    /*!< TMRB3IE0 (Bit 25)                                     */
10506 #define CTIMER_CTRL3_TMRB3IE0_Msk         (0x2000000UL)             /*!< TMRB3IE0 (Bitfield-Mask: 0x01)                        */
10507 #define CTIMER_CTRL3_TMRB3FN_Pos          (22UL)                    /*!< TMRB3FN (Bit 22)                                      */
10508 #define CTIMER_CTRL3_TMRB3FN_Msk          (0x1c00000UL)             /*!< TMRB3FN (Bitfield-Mask: 0x07)                         */
10509 #define CTIMER_CTRL3_TMRB3CLK_Pos         (17UL)                    /*!< TMRB3CLK (Bit 17)                                     */
10510 #define CTIMER_CTRL3_TMRB3CLK_Msk         (0x3e0000UL)              /*!< TMRB3CLK (Bitfield-Mask: 0x1f)                        */
10511 #define CTIMER_CTRL3_TMRB3EN_Pos          (16UL)                    /*!< TMRB3EN (Bit 16)                                      */
10512 #define CTIMER_CTRL3_TMRB3EN_Msk          (0x10000UL)               /*!< TMRB3EN (Bitfield-Mask: 0x01)                         */
10513 #define CTIMER_CTRL3_ADCEN_Pos            (15UL)                    /*!< ADCEN (Bit 15)                                        */
10514 #define CTIMER_CTRL3_ADCEN_Msk            (0x8000UL)                /*!< ADCEN (Bitfield-Mask: 0x01)                           */
10515 #define CTIMER_CTRL3_TMRA3POL_Pos         (12UL)                    /*!< TMRA3POL (Bit 12)                                     */
10516 #define CTIMER_CTRL3_TMRA3POL_Msk         (0x1000UL)                /*!< TMRA3POL (Bitfield-Mask: 0x01)                        */
10517 #define CTIMER_CTRL3_TMRA3CLR_Pos         (11UL)                    /*!< TMRA3CLR (Bit 11)                                     */
10518 #define CTIMER_CTRL3_TMRA3CLR_Msk         (0x800UL)                 /*!< TMRA3CLR (Bitfield-Mask: 0x01)                        */
10519 #define CTIMER_CTRL3_TMRA3IE1_Pos         (10UL)                    /*!< TMRA3IE1 (Bit 10)                                     */
10520 #define CTIMER_CTRL3_TMRA3IE1_Msk         (0x400UL)                 /*!< TMRA3IE1 (Bitfield-Mask: 0x01)                        */
10521 #define CTIMER_CTRL3_TMRA3IE0_Pos         (9UL)                     /*!< TMRA3IE0 (Bit 9)                                      */
10522 #define CTIMER_CTRL3_TMRA3IE0_Msk         (0x200UL)                 /*!< TMRA3IE0 (Bitfield-Mask: 0x01)                        */
10523 #define CTIMER_CTRL3_TMRA3FN_Pos          (6UL)                     /*!< TMRA3FN (Bit 6)                                       */
10524 #define CTIMER_CTRL3_TMRA3FN_Msk          (0x1c0UL)                 /*!< TMRA3FN (Bitfield-Mask: 0x07)                         */
10525 #define CTIMER_CTRL3_TMRA3CLK_Pos         (1UL)                     /*!< TMRA3CLK (Bit 1)                                      */
10526 #define CTIMER_CTRL3_TMRA3CLK_Msk         (0x3eUL)                  /*!< TMRA3CLK (Bitfield-Mask: 0x1f)                        */
10527 #define CTIMER_CTRL3_TMRA3EN_Pos          (0UL)                     /*!< TMRA3EN (Bit 0)                                       */
10528 #define CTIMER_CTRL3_TMRA3EN_Msk          (0x1UL)                   /*!< TMRA3EN (Bitfield-Mask: 0x01)                         */
10529 /* =======================================================  CMPRAUXA3  ======================================================= */
10530 #define CTIMER_CMPRAUXA3_CMPR3A3_Pos      (16UL)                    /*!< CMPR3A3 (Bit 16)                                      */
10531 #define CTIMER_CMPRAUXA3_CMPR3A3_Msk      (0xffff0000UL)            /*!< CMPR3A3 (Bitfield-Mask: 0xffff)                       */
10532 #define CTIMER_CMPRAUXA3_CMPR2A3_Pos      (0UL)                     /*!< CMPR2A3 (Bit 0)                                       */
10533 #define CTIMER_CMPRAUXA3_CMPR2A3_Msk      (0xffffUL)                /*!< CMPR2A3 (Bitfield-Mask: 0xffff)                       */
10534 /* =======================================================  CMPRAUXB3  ======================================================= */
10535 #define CTIMER_CMPRAUXB3_CMPR3B3_Pos      (16UL)                    /*!< CMPR3B3 (Bit 16)                                      */
10536 #define CTIMER_CMPRAUXB3_CMPR3B3_Msk      (0xffff0000UL)            /*!< CMPR3B3 (Bitfield-Mask: 0xffff)                       */
10537 #define CTIMER_CMPRAUXB3_CMPR2B3_Pos      (0UL)                     /*!< CMPR2B3 (Bit 0)                                       */
10538 #define CTIMER_CMPRAUXB3_CMPR2B3_Msk      (0xffffUL)                /*!< CMPR2B3 (Bitfield-Mask: 0xffff)                       */
10539 /* =========================================================  AUX3  ========================================================== */
10540 #define CTIMER_AUX3_TMRB3EN23_Pos         (30UL)                    /*!< TMRB3EN23 (Bit 30)                                    */
10541 #define CTIMER_AUX3_TMRB3EN23_Msk         (0x40000000UL)            /*!< TMRB3EN23 (Bitfield-Mask: 0x01)                       */
10542 #define CTIMER_AUX3_TMRB3POL23_Pos        (29UL)                    /*!< TMRB3POL23 (Bit 29)                                   */
10543 #define CTIMER_AUX3_TMRB3POL23_Msk        (0x20000000UL)            /*!< TMRB3POL23 (Bitfield-Mask: 0x01)                      */
10544 #define CTIMER_AUX3_TMRB3TINV_Pos         (28UL)                    /*!< TMRB3TINV (Bit 28)                                    */
10545 #define CTIMER_AUX3_TMRB3TINV_Msk         (0x10000000UL)            /*!< TMRB3TINV (Bitfield-Mask: 0x01)                       */
10546 #define CTIMER_AUX3_TMRB3NOSYNC_Pos       (27UL)                    /*!< TMRB3NOSYNC (Bit 27)                                  */
10547 #define CTIMER_AUX3_TMRB3NOSYNC_Msk       (0x8000000UL)             /*!< TMRB3NOSYNC (Bitfield-Mask: 0x01)                     */
10548 #define CTIMER_AUX3_TMRB3TRIG_Pos         (23UL)                    /*!< TMRB3TRIG (Bit 23)                                    */
10549 #define CTIMER_AUX3_TMRB3TRIG_Msk         (0x7800000UL)             /*!< TMRB3TRIG (Bitfield-Mask: 0x0f)                       */
10550 #define CTIMER_AUX3_TMRB3LMT_Pos          (16UL)                    /*!< TMRB3LMT (Bit 16)                                     */
10551 #define CTIMER_AUX3_TMRB3LMT_Msk          (0x3f0000UL)              /*!< TMRB3LMT (Bitfield-Mask: 0x3f)                        */
10552 #define CTIMER_AUX3_TMRA3EN23_Pos         (14UL)                    /*!< TMRA3EN23 (Bit 14)                                    */
10553 #define CTIMER_AUX3_TMRA3EN23_Msk         (0x4000UL)                /*!< TMRA3EN23 (Bitfield-Mask: 0x01)                       */
10554 #define CTIMER_AUX3_TMRA3POL23_Pos        (13UL)                    /*!< TMRA3POL23 (Bit 13)                                   */
10555 #define CTIMER_AUX3_TMRA3POL23_Msk        (0x2000UL)                /*!< TMRA3POL23 (Bitfield-Mask: 0x01)                      */
10556 #define CTIMER_AUX3_TMRA3TINV_Pos         (12UL)                    /*!< TMRA3TINV (Bit 12)                                    */
10557 #define CTIMER_AUX3_TMRA3TINV_Msk         (0x1000UL)                /*!< TMRA3TINV (Bitfield-Mask: 0x01)                       */
10558 #define CTIMER_AUX3_TMRA3NOSYNC_Pos       (11UL)                    /*!< TMRA3NOSYNC (Bit 11)                                  */
10559 #define CTIMER_AUX3_TMRA3NOSYNC_Msk       (0x800UL)                 /*!< TMRA3NOSYNC (Bitfield-Mask: 0x01)                     */
10560 #define CTIMER_AUX3_TMRA3TRIG_Pos         (7UL)                     /*!< TMRA3TRIG (Bit 7)                                     */
10561 #define CTIMER_AUX3_TMRA3TRIG_Msk         (0x780UL)                 /*!< TMRA3TRIG (Bitfield-Mask: 0x0f)                       */
10562 #define CTIMER_AUX3_TMRA3LMT_Pos          (0UL)                     /*!< TMRA3LMT (Bit 0)                                      */
10563 #define CTIMER_AUX3_TMRA3LMT_Msk          (0x7fUL)                  /*!< TMRA3LMT (Bitfield-Mask: 0x7f)                        */
10564 /* =========================================================  TMR4  ========================================================== */
10565 #define CTIMER_TMR4_CTTMRB4_Pos           (16UL)                    /*!< CTTMRB4 (Bit 16)                                      */
10566 #define CTIMER_TMR4_CTTMRB4_Msk           (0xffff0000UL)            /*!< CTTMRB4 (Bitfield-Mask: 0xffff)                       */
10567 #define CTIMER_TMR4_CTTMRA4_Pos           (0UL)                     /*!< CTTMRA4 (Bit 0)                                       */
10568 #define CTIMER_TMR4_CTTMRA4_Msk           (0xffffUL)                /*!< CTTMRA4 (Bitfield-Mask: 0xffff)                       */
10569 /* ========================================================  CMPRA4  ========================================================= */
10570 #define CTIMER_CMPRA4_CMPR1A4_Pos         (16UL)                    /*!< CMPR1A4 (Bit 16)                                      */
10571 #define CTIMER_CMPRA4_CMPR1A4_Msk         (0xffff0000UL)            /*!< CMPR1A4 (Bitfield-Mask: 0xffff)                       */
10572 #define CTIMER_CMPRA4_CMPR0A4_Pos         (0UL)                     /*!< CMPR0A4 (Bit 0)                                       */
10573 #define CTIMER_CMPRA4_CMPR0A4_Msk         (0xffffUL)                /*!< CMPR0A4 (Bitfield-Mask: 0xffff)                       */
10574 /* ========================================================  CMPRB4  ========================================================= */
10575 #define CTIMER_CMPRB4_CMPR1B4_Pos         (16UL)                    /*!< CMPR1B4 (Bit 16)                                      */
10576 #define CTIMER_CMPRB4_CMPR1B4_Msk         (0xffff0000UL)            /*!< CMPR1B4 (Bitfield-Mask: 0xffff)                       */
10577 #define CTIMER_CMPRB4_CMPR0B4_Pos         (0UL)                     /*!< CMPR0B4 (Bit 0)                                       */
10578 #define CTIMER_CMPRB4_CMPR0B4_Msk         (0xffffUL)                /*!< CMPR0B4 (Bitfield-Mask: 0xffff)                       */
10579 /* =========================================================  CTRL4  ========================================================= */
10580 #define CTIMER_CTRL4_CTLINK4_Pos          (31UL)                    /*!< CTLINK4 (Bit 31)                                      */
10581 #define CTIMER_CTRL4_CTLINK4_Msk          (0x80000000UL)            /*!< CTLINK4 (Bitfield-Mask: 0x01)                         */
10582 #define CTIMER_CTRL4_TMRB4POL_Pos         (28UL)                    /*!< TMRB4POL (Bit 28)                                     */
10583 #define CTIMER_CTRL4_TMRB4POL_Msk         (0x10000000UL)            /*!< TMRB4POL (Bitfield-Mask: 0x01)                        */
10584 #define CTIMER_CTRL4_TMRB4CLR_Pos         (27UL)                    /*!< TMRB4CLR (Bit 27)                                     */
10585 #define CTIMER_CTRL4_TMRB4CLR_Msk         (0x8000000UL)             /*!< TMRB4CLR (Bitfield-Mask: 0x01)                        */
10586 #define CTIMER_CTRL4_TMRB4IE1_Pos         (26UL)                    /*!< TMRB4IE1 (Bit 26)                                     */
10587 #define CTIMER_CTRL4_TMRB4IE1_Msk         (0x4000000UL)             /*!< TMRB4IE1 (Bitfield-Mask: 0x01)                        */
10588 #define CTIMER_CTRL4_TMRB4IE0_Pos         (25UL)                    /*!< TMRB4IE0 (Bit 25)                                     */
10589 #define CTIMER_CTRL4_TMRB4IE0_Msk         (0x2000000UL)             /*!< TMRB4IE0 (Bitfield-Mask: 0x01)                        */
10590 #define CTIMER_CTRL4_TMRB4FN_Pos          (22UL)                    /*!< TMRB4FN (Bit 22)                                      */
10591 #define CTIMER_CTRL4_TMRB4FN_Msk          (0x1c00000UL)             /*!< TMRB4FN (Bitfield-Mask: 0x07)                         */
10592 #define CTIMER_CTRL4_TMRB4CLK_Pos         (17UL)                    /*!< TMRB4CLK (Bit 17)                                     */
10593 #define CTIMER_CTRL4_TMRB4CLK_Msk         (0x3e0000UL)              /*!< TMRB4CLK (Bitfield-Mask: 0x1f)                        */
10594 #define CTIMER_CTRL4_TMRB4EN_Pos          (16UL)                    /*!< TMRB4EN (Bit 16)                                      */
10595 #define CTIMER_CTRL4_TMRB4EN_Msk          (0x10000UL)               /*!< TMRB4EN (Bitfield-Mask: 0x01)                         */
10596 #define CTIMER_CTRL4_TMRA4POL_Pos         (12UL)                    /*!< TMRA4POL (Bit 12)                                     */
10597 #define CTIMER_CTRL4_TMRA4POL_Msk         (0x1000UL)                /*!< TMRA4POL (Bitfield-Mask: 0x01)                        */
10598 #define CTIMER_CTRL4_TMRA4CLR_Pos         (11UL)                    /*!< TMRA4CLR (Bit 11)                                     */
10599 #define CTIMER_CTRL4_TMRA4CLR_Msk         (0x800UL)                 /*!< TMRA4CLR (Bitfield-Mask: 0x01)                        */
10600 #define CTIMER_CTRL4_TMRA4IE1_Pos         (10UL)                    /*!< TMRA4IE1 (Bit 10)                                     */
10601 #define CTIMER_CTRL4_TMRA4IE1_Msk         (0x400UL)                 /*!< TMRA4IE1 (Bitfield-Mask: 0x01)                        */
10602 #define CTIMER_CTRL4_TMRA4IE0_Pos         (9UL)                     /*!< TMRA4IE0 (Bit 9)                                      */
10603 #define CTIMER_CTRL4_TMRA4IE0_Msk         (0x200UL)                 /*!< TMRA4IE0 (Bitfield-Mask: 0x01)                        */
10604 #define CTIMER_CTRL4_TMRA4FN_Pos          (6UL)                     /*!< TMRA4FN (Bit 6)                                       */
10605 #define CTIMER_CTRL4_TMRA4FN_Msk          (0x1c0UL)                 /*!< TMRA4FN (Bitfield-Mask: 0x07)                         */
10606 #define CTIMER_CTRL4_TMRA4CLK_Pos         (1UL)                     /*!< TMRA4CLK (Bit 1)                                      */
10607 #define CTIMER_CTRL4_TMRA4CLK_Msk         (0x3eUL)                  /*!< TMRA4CLK (Bitfield-Mask: 0x1f)                        */
10608 #define CTIMER_CTRL4_TMRA4EN_Pos          (0UL)                     /*!< TMRA4EN (Bit 0)                                       */
10609 #define CTIMER_CTRL4_TMRA4EN_Msk          (0x1UL)                   /*!< TMRA4EN (Bitfield-Mask: 0x01)                         */
10610 /* =======================================================  CMPRAUXA4  ======================================================= */
10611 #define CTIMER_CMPRAUXA4_CMPR3A4_Pos      (16UL)                    /*!< CMPR3A4 (Bit 16)                                      */
10612 #define CTIMER_CMPRAUXA4_CMPR3A4_Msk      (0xffff0000UL)            /*!< CMPR3A4 (Bitfield-Mask: 0xffff)                       */
10613 #define CTIMER_CMPRAUXA4_CMPR2A4_Pos      (0UL)                     /*!< CMPR2A4 (Bit 0)                                       */
10614 #define CTIMER_CMPRAUXA4_CMPR2A4_Msk      (0xffffUL)                /*!< CMPR2A4 (Bitfield-Mask: 0xffff)                       */
10615 /* =======================================================  CMPRAUXB4  ======================================================= */
10616 #define CTIMER_CMPRAUXB4_CMPR3B4_Pos      (16UL)                    /*!< CMPR3B4 (Bit 16)                                      */
10617 #define CTIMER_CMPRAUXB4_CMPR3B4_Msk      (0xffff0000UL)            /*!< CMPR3B4 (Bitfield-Mask: 0xffff)                       */
10618 #define CTIMER_CMPRAUXB4_CMPR2B4_Pos      (0UL)                     /*!< CMPR2B4 (Bit 0)                                       */
10619 #define CTIMER_CMPRAUXB4_CMPR2B4_Msk      (0xffffUL)                /*!< CMPR2B4 (Bitfield-Mask: 0xffff)                       */
10620 /* =========================================================  AUX4  ========================================================== */
10621 #define CTIMER_AUX4_TMRB4EN23_Pos         (30UL)                    /*!< TMRB4EN23 (Bit 30)                                    */
10622 #define CTIMER_AUX4_TMRB4EN23_Msk         (0x40000000UL)            /*!< TMRB4EN23 (Bitfield-Mask: 0x01)                       */
10623 #define CTIMER_AUX4_TMRB4POL23_Pos        (29UL)                    /*!< TMRB4POL23 (Bit 29)                                   */
10624 #define CTIMER_AUX4_TMRB4POL23_Msk        (0x20000000UL)            /*!< TMRB4POL23 (Bitfield-Mask: 0x01)                      */
10625 #define CTIMER_AUX4_TMRB4TINV_Pos         (28UL)                    /*!< TMRB4TINV (Bit 28)                                    */
10626 #define CTIMER_AUX4_TMRB4TINV_Msk         (0x10000000UL)            /*!< TMRB4TINV (Bitfield-Mask: 0x01)                       */
10627 #define CTIMER_AUX4_TMRB4NOSYNC_Pos       (27UL)                    /*!< TMRB4NOSYNC (Bit 27)                                  */
10628 #define CTIMER_AUX4_TMRB4NOSYNC_Msk       (0x8000000UL)             /*!< TMRB4NOSYNC (Bitfield-Mask: 0x01)                     */
10629 #define CTIMER_AUX4_TMRB4TRIG_Pos         (23UL)                    /*!< TMRB4TRIG (Bit 23)                                    */
10630 #define CTIMER_AUX4_TMRB4TRIG_Msk         (0x7800000UL)             /*!< TMRB4TRIG (Bitfield-Mask: 0x0f)                       */
10631 #define CTIMER_AUX4_TMRB4LMT_Pos          (16UL)                    /*!< TMRB4LMT (Bit 16)                                     */
10632 #define CTIMER_AUX4_TMRB4LMT_Msk          (0x3f0000UL)              /*!< TMRB4LMT (Bitfield-Mask: 0x3f)                        */
10633 #define CTIMER_AUX4_TMRA4EN23_Pos         (14UL)                    /*!< TMRA4EN23 (Bit 14)                                    */
10634 #define CTIMER_AUX4_TMRA4EN23_Msk         (0x4000UL)                /*!< TMRA4EN23 (Bitfield-Mask: 0x01)                       */
10635 #define CTIMER_AUX4_TMRA4POL23_Pos        (13UL)                    /*!< TMRA4POL23 (Bit 13)                                   */
10636 #define CTIMER_AUX4_TMRA4POL23_Msk        (0x2000UL)                /*!< TMRA4POL23 (Bitfield-Mask: 0x01)                      */
10637 #define CTIMER_AUX4_TMRA4TINV_Pos         (12UL)                    /*!< TMRA4TINV (Bit 12)                                    */
10638 #define CTIMER_AUX4_TMRA4TINV_Msk         (0x1000UL)                /*!< TMRA4TINV (Bitfield-Mask: 0x01)                       */
10639 #define CTIMER_AUX4_TMRA4NOSYNC_Pos       (11UL)                    /*!< TMRA4NOSYNC (Bit 11)                                  */
10640 #define CTIMER_AUX4_TMRA4NOSYNC_Msk       (0x800UL)                 /*!< TMRA4NOSYNC (Bitfield-Mask: 0x01)                     */
10641 #define CTIMER_AUX4_TMRA4TRIG_Pos         (7UL)                     /*!< TMRA4TRIG (Bit 7)                                     */
10642 #define CTIMER_AUX4_TMRA4TRIG_Msk         (0x780UL)                 /*!< TMRA4TRIG (Bitfield-Mask: 0x0f)                       */
10643 #define CTIMER_AUX4_TMRA4LMT_Pos          (0UL)                     /*!< TMRA4LMT (Bit 0)                                      */
10644 #define CTIMER_AUX4_TMRA4LMT_Msk          (0x7fUL)                  /*!< TMRA4LMT (Bitfield-Mask: 0x7f)                        */
10645 /* =========================================================  TMR5  ========================================================== */
10646 #define CTIMER_TMR5_CTTMRB5_Pos           (16UL)                    /*!< CTTMRB5 (Bit 16)                                      */
10647 #define CTIMER_TMR5_CTTMRB5_Msk           (0xffff0000UL)            /*!< CTTMRB5 (Bitfield-Mask: 0xffff)                       */
10648 #define CTIMER_TMR5_CTTMRA5_Pos           (0UL)                     /*!< CTTMRA5 (Bit 0)                                       */
10649 #define CTIMER_TMR5_CTTMRA5_Msk           (0xffffUL)                /*!< CTTMRA5 (Bitfield-Mask: 0xffff)                       */
10650 /* ========================================================  CMPRA5  ========================================================= */
10651 #define CTIMER_CMPRA5_CMPR1A5_Pos         (16UL)                    /*!< CMPR1A5 (Bit 16)                                      */
10652 #define CTIMER_CMPRA5_CMPR1A5_Msk         (0xffff0000UL)            /*!< CMPR1A5 (Bitfield-Mask: 0xffff)                       */
10653 #define CTIMER_CMPRA5_CMPR0A5_Pos         (0UL)                     /*!< CMPR0A5 (Bit 0)                                       */
10654 #define CTIMER_CMPRA5_CMPR0A5_Msk         (0xffffUL)                /*!< CMPR0A5 (Bitfield-Mask: 0xffff)                       */
10655 /* ========================================================  CMPRB5  ========================================================= */
10656 #define CTIMER_CMPRB5_CMPR1B5_Pos         (16UL)                    /*!< CMPR1B5 (Bit 16)                                      */
10657 #define CTIMER_CMPRB5_CMPR1B5_Msk         (0xffff0000UL)            /*!< CMPR1B5 (Bitfield-Mask: 0xffff)                       */
10658 #define CTIMER_CMPRB5_CMPR0B5_Pos         (0UL)                     /*!< CMPR0B5 (Bit 0)                                       */
10659 #define CTIMER_CMPRB5_CMPR0B5_Msk         (0xffffUL)                /*!< CMPR0B5 (Bitfield-Mask: 0xffff)                       */
10660 /* =========================================================  CTRL5  ========================================================= */
10661 #define CTIMER_CTRL5_CTLINK5_Pos          (31UL)                    /*!< CTLINK5 (Bit 31)                                      */
10662 #define CTIMER_CTRL5_CTLINK5_Msk          (0x80000000UL)            /*!< CTLINK5 (Bitfield-Mask: 0x01)                         */
10663 #define CTIMER_CTRL5_TMRB5POL_Pos         (28UL)                    /*!< TMRB5POL (Bit 28)                                     */
10664 #define CTIMER_CTRL5_TMRB5POL_Msk         (0x10000000UL)            /*!< TMRB5POL (Bitfield-Mask: 0x01)                        */
10665 #define CTIMER_CTRL5_TMRB5CLR_Pos         (27UL)                    /*!< TMRB5CLR (Bit 27)                                     */
10666 #define CTIMER_CTRL5_TMRB5CLR_Msk         (0x8000000UL)             /*!< TMRB5CLR (Bitfield-Mask: 0x01)                        */
10667 #define CTIMER_CTRL5_TMRB5IE1_Pos         (26UL)                    /*!< TMRB5IE1 (Bit 26)                                     */
10668 #define CTIMER_CTRL5_TMRB5IE1_Msk         (0x4000000UL)             /*!< TMRB5IE1 (Bitfield-Mask: 0x01)                        */
10669 #define CTIMER_CTRL5_TMRB5IE0_Pos         (25UL)                    /*!< TMRB5IE0 (Bit 25)                                     */
10670 #define CTIMER_CTRL5_TMRB5IE0_Msk         (0x2000000UL)             /*!< TMRB5IE0 (Bitfield-Mask: 0x01)                        */
10671 #define CTIMER_CTRL5_TMRB5FN_Pos          (22UL)                    /*!< TMRB5FN (Bit 22)                                      */
10672 #define CTIMER_CTRL5_TMRB5FN_Msk          (0x1c00000UL)             /*!< TMRB5FN (Bitfield-Mask: 0x07)                         */
10673 #define CTIMER_CTRL5_TMRB5CLK_Pos         (17UL)                    /*!< TMRB5CLK (Bit 17)                                     */
10674 #define CTIMER_CTRL5_TMRB5CLK_Msk         (0x3e0000UL)              /*!< TMRB5CLK (Bitfield-Mask: 0x1f)                        */
10675 #define CTIMER_CTRL5_TMRB5EN_Pos          (16UL)                    /*!< TMRB5EN (Bit 16)                                      */
10676 #define CTIMER_CTRL5_TMRB5EN_Msk          (0x10000UL)               /*!< TMRB5EN (Bitfield-Mask: 0x01)                         */
10677 #define CTIMER_CTRL5_TMRA5POL_Pos         (12UL)                    /*!< TMRA5POL (Bit 12)                                     */
10678 #define CTIMER_CTRL5_TMRA5POL_Msk         (0x1000UL)                /*!< TMRA5POL (Bitfield-Mask: 0x01)                        */
10679 #define CTIMER_CTRL5_TMRA5CLR_Pos         (11UL)                    /*!< TMRA5CLR (Bit 11)                                     */
10680 #define CTIMER_CTRL5_TMRA5CLR_Msk         (0x800UL)                 /*!< TMRA5CLR (Bitfield-Mask: 0x01)                        */
10681 #define CTIMER_CTRL5_TMRA5IE1_Pos         (10UL)                    /*!< TMRA5IE1 (Bit 10)                                     */
10682 #define CTIMER_CTRL5_TMRA5IE1_Msk         (0x400UL)                 /*!< TMRA5IE1 (Bitfield-Mask: 0x01)                        */
10683 #define CTIMER_CTRL5_TMRA5IE0_Pos         (9UL)                     /*!< TMRA5IE0 (Bit 9)                                      */
10684 #define CTIMER_CTRL5_TMRA5IE0_Msk         (0x200UL)                 /*!< TMRA5IE0 (Bitfield-Mask: 0x01)                        */
10685 #define CTIMER_CTRL5_TMRA5FN_Pos          (6UL)                     /*!< TMRA5FN (Bit 6)                                       */
10686 #define CTIMER_CTRL5_TMRA5FN_Msk          (0x1c0UL)                 /*!< TMRA5FN (Bitfield-Mask: 0x07)                         */
10687 #define CTIMER_CTRL5_TMRA5CLK_Pos         (1UL)                     /*!< TMRA5CLK (Bit 1)                                      */
10688 #define CTIMER_CTRL5_TMRA5CLK_Msk         (0x3eUL)                  /*!< TMRA5CLK (Bitfield-Mask: 0x1f)                        */
10689 #define CTIMER_CTRL5_TMRA5EN_Pos          (0UL)                     /*!< TMRA5EN (Bit 0)                                       */
10690 #define CTIMER_CTRL5_TMRA5EN_Msk          (0x1UL)                   /*!< TMRA5EN (Bitfield-Mask: 0x01)                         */
10691 /* =======================================================  CMPRAUXA5  ======================================================= */
10692 #define CTIMER_CMPRAUXA5_CMPR3A5_Pos      (16UL)                    /*!< CMPR3A5 (Bit 16)                                      */
10693 #define CTIMER_CMPRAUXA5_CMPR3A5_Msk      (0xffff0000UL)            /*!< CMPR3A5 (Bitfield-Mask: 0xffff)                       */
10694 #define CTIMER_CMPRAUXA5_CMPR2A5_Pos      (0UL)                     /*!< CMPR2A5 (Bit 0)                                       */
10695 #define CTIMER_CMPRAUXA5_CMPR2A5_Msk      (0xffffUL)                /*!< CMPR2A5 (Bitfield-Mask: 0xffff)                       */
10696 /* =======================================================  CMPRAUXB5  ======================================================= */
10697 #define CTIMER_CMPRAUXB5_CMPR3B5_Pos      (16UL)                    /*!< CMPR3B5 (Bit 16)                                      */
10698 #define CTIMER_CMPRAUXB5_CMPR3B5_Msk      (0xffff0000UL)            /*!< CMPR3B5 (Bitfield-Mask: 0xffff)                       */
10699 #define CTIMER_CMPRAUXB5_CMPR2B5_Pos      (0UL)                     /*!< CMPR2B5 (Bit 0)                                       */
10700 #define CTIMER_CMPRAUXB5_CMPR2B5_Msk      (0xffffUL)                /*!< CMPR2B5 (Bitfield-Mask: 0xffff)                       */
10701 /* =========================================================  AUX5  ========================================================== */
10702 #define CTIMER_AUX5_TMRB5EN23_Pos         (30UL)                    /*!< TMRB5EN23 (Bit 30)                                    */
10703 #define CTIMER_AUX5_TMRB5EN23_Msk         (0x40000000UL)            /*!< TMRB5EN23 (Bitfield-Mask: 0x01)                       */
10704 #define CTIMER_AUX5_TMRB5POL23_Pos        (29UL)                    /*!< TMRB5POL23 (Bit 29)                                   */
10705 #define CTIMER_AUX5_TMRB5POL23_Msk        (0x20000000UL)            /*!< TMRB5POL23 (Bitfield-Mask: 0x01)                      */
10706 #define CTIMER_AUX5_TMRB5TINV_Pos         (28UL)                    /*!< TMRB5TINV (Bit 28)                                    */
10707 #define CTIMER_AUX5_TMRB5TINV_Msk         (0x10000000UL)            /*!< TMRB5TINV (Bitfield-Mask: 0x01)                       */
10708 #define CTIMER_AUX5_TMRB5NOSYNC_Pos       (27UL)                    /*!< TMRB5NOSYNC (Bit 27)                                  */
10709 #define CTIMER_AUX5_TMRB5NOSYNC_Msk       (0x8000000UL)             /*!< TMRB5NOSYNC (Bitfield-Mask: 0x01)                     */
10710 #define CTIMER_AUX5_TMRB5TRIG_Pos         (23UL)                    /*!< TMRB5TRIG (Bit 23)                                    */
10711 #define CTIMER_AUX5_TMRB5TRIG_Msk         (0x7800000UL)             /*!< TMRB5TRIG (Bitfield-Mask: 0x0f)                       */
10712 #define CTIMER_AUX5_TMRB5LMT_Pos          (16UL)                    /*!< TMRB5LMT (Bit 16)                                     */
10713 #define CTIMER_AUX5_TMRB5LMT_Msk          (0x3f0000UL)              /*!< TMRB5LMT (Bitfield-Mask: 0x3f)                        */
10714 #define CTIMER_AUX5_TMRA5EN23_Pos         (14UL)                    /*!< TMRA5EN23 (Bit 14)                                    */
10715 #define CTIMER_AUX5_TMRA5EN23_Msk         (0x4000UL)                /*!< TMRA5EN23 (Bitfield-Mask: 0x01)                       */
10716 #define CTIMER_AUX5_TMRA5POL23_Pos        (13UL)                    /*!< TMRA5POL23 (Bit 13)                                   */
10717 #define CTIMER_AUX5_TMRA5POL23_Msk        (0x2000UL)                /*!< TMRA5POL23 (Bitfield-Mask: 0x01)                      */
10718 #define CTIMER_AUX5_TMRA5TINV_Pos         (12UL)                    /*!< TMRA5TINV (Bit 12)                                    */
10719 #define CTIMER_AUX5_TMRA5TINV_Msk         (0x1000UL)                /*!< TMRA5TINV (Bitfield-Mask: 0x01)                       */
10720 #define CTIMER_AUX5_TMRA5NOSYNC_Pos       (11UL)                    /*!< TMRA5NOSYNC (Bit 11)                                  */
10721 #define CTIMER_AUX5_TMRA5NOSYNC_Msk       (0x800UL)                 /*!< TMRA5NOSYNC (Bitfield-Mask: 0x01)                     */
10722 #define CTIMER_AUX5_TMRA5TRIG_Pos         (7UL)                     /*!< TMRA5TRIG (Bit 7)                                     */
10723 #define CTIMER_AUX5_TMRA5TRIG_Msk         (0x780UL)                 /*!< TMRA5TRIG (Bitfield-Mask: 0x0f)                       */
10724 #define CTIMER_AUX5_TMRA5LMT_Pos          (0UL)                     /*!< TMRA5LMT (Bit 0)                                      */
10725 #define CTIMER_AUX5_TMRA5LMT_Msk          (0x7fUL)                  /*!< TMRA5LMT (Bitfield-Mask: 0x7f)                        */
10726 /* =========================================================  TMR6  ========================================================== */
10727 #define CTIMER_TMR6_CTTMRB6_Pos           (16UL)                    /*!< CTTMRB6 (Bit 16)                                      */
10728 #define CTIMER_TMR6_CTTMRB6_Msk           (0xffff0000UL)            /*!< CTTMRB6 (Bitfield-Mask: 0xffff)                       */
10729 #define CTIMER_TMR6_CTTMRA6_Pos           (0UL)                     /*!< CTTMRA6 (Bit 0)                                       */
10730 #define CTIMER_TMR6_CTTMRA6_Msk           (0xffffUL)                /*!< CTTMRA6 (Bitfield-Mask: 0xffff)                       */
10731 /* ========================================================  CMPRA6  ========================================================= */
10732 #define CTIMER_CMPRA6_CMPR1A6_Pos         (16UL)                    /*!< CMPR1A6 (Bit 16)                                      */
10733 #define CTIMER_CMPRA6_CMPR1A6_Msk         (0xffff0000UL)            /*!< CMPR1A6 (Bitfield-Mask: 0xffff)                       */
10734 #define CTIMER_CMPRA6_CMPR0A6_Pos         (0UL)                     /*!< CMPR0A6 (Bit 0)                                       */
10735 #define CTIMER_CMPRA6_CMPR0A6_Msk         (0xffffUL)                /*!< CMPR0A6 (Bitfield-Mask: 0xffff)                       */
10736 /* ========================================================  CMPRB6  ========================================================= */
10737 #define CTIMER_CMPRB6_CMPR1B6_Pos         (16UL)                    /*!< CMPR1B6 (Bit 16)                                      */
10738 #define CTIMER_CMPRB6_CMPR1B6_Msk         (0xffff0000UL)            /*!< CMPR1B6 (Bitfield-Mask: 0xffff)                       */
10739 #define CTIMER_CMPRB6_CMPR0B6_Pos         (0UL)                     /*!< CMPR0B6 (Bit 0)                                       */
10740 #define CTIMER_CMPRB6_CMPR0B6_Msk         (0xffffUL)                /*!< CMPR0B6 (Bitfield-Mask: 0xffff)                       */
10741 /* =========================================================  CTRL6  ========================================================= */
10742 #define CTIMER_CTRL6_CTLINK6_Pos          (31UL)                    /*!< CTLINK6 (Bit 31)                                      */
10743 #define CTIMER_CTRL6_CTLINK6_Msk          (0x80000000UL)            /*!< CTLINK6 (Bitfield-Mask: 0x01)                         */
10744 #define CTIMER_CTRL6_TMRB6POL_Pos         (28UL)                    /*!< TMRB6POL (Bit 28)                                     */
10745 #define CTIMER_CTRL6_TMRB6POL_Msk         (0x10000000UL)            /*!< TMRB6POL (Bitfield-Mask: 0x01)                        */
10746 #define CTIMER_CTRL6_TMRB6CLR_Pos         (27UL)                    /*!< TMRB6CLR (Bit 27)                                     */
10747 #define CTIMER_CTRL6_TMRB6CLR_Msk         (0x8000000UL)             /*!< TMRB6CLR (Bitfield-Mask: 0x01)                        */
10748 #define CTIMER_CTRL6_TMRB6IE1_Pos         (26UL)                    /*!< TMRB6IE1 (Bit 26)                                     */
10749 #define CTIMER_CTRL6_TMRB6IE1_Msk         (0x4000000UL)             /*!< TMRB6IE1 (Bitfield-Mask: 0x01)                        */
10750 #define CTIMER_CTRL6_TMRB6IE0_Pos         (25UL)                    /*!< TMRB6IE0 (Bit 25)                                     */
10751 #define CTIMER_CTRL6_TMRB6IE0_Msk         (0x2000000UL)             /*!< TMRB6IE0 (Bitfield-Mask: 0x01)                        */
10752 #define CTIMER_CTRL6_TMRB6FN_Pos          (22UL)                    /*!< TMRB6FN (Bit 22)                                      */
10753 #define CTIMER_CTRL6_TMRB6FN_Msk          (0x1c00000UL)             /*!< TMRB6FN (Bitfield-Mask: 0x07)                         */
10754 #define CTIMER_CTRL6_TMRB6CLK_Pos         (17UL)                    /*!< TMRB6CLK (Bit 17)                                     */
10755 #define CTIMER_CTRL6_TMRB6CLK_Msk         (0x3e0000UL)              /*!< TMRB6CLK (Bitfield-Mask: 0x1f)                        */
10756 #define CTIMER_CTRL6_TMRB6EN_Pos          (16UL)                    /*!< TMRB6EN (Bit 16)                                      */
10757 #define CTIMER_CTRL6_TMRB6EN_Msk          (0x10000UL)               /*!< TMRB6EN (Bitfield-Mask: 0x01)                         */
10758 #define CTIMER_CTRL6_TMRA6POL_Pos         (12UL)                    /*!< TMRA6POL (Bit 12)                                     */
10759 #define CTIMER_CTRL6_TMRA6POL_Msk         (0x1000UL)                /*!< TMRA6POL (Bitfield-Mask: 0x01)                        */
10760 #define CTIMER_CTRL6_TMRA6CLR_Pos         (11UL)                    /*!< TMRA6CLR (Bit 11)                                     */
10761 #define CTIMER_CTRL6_TMRA6CLR_Msk         (0x800UL)                 /*!< TMRA6CLR (Bitfield-Mask: 0x01)                        */
10762 #define CTIMER_CTRL6_TMRA6IE1_Pos         (10UL)                    /*!< TMRA6IE1 (Bit 10)                                     */
10763 #define CTIMER_CTRL6_TMRA6IE1_Msk         (0x400UL)                 /*!< TMRA6IE1 (Bitfield-Mask: 0x01)                        */
10764 #define CTIMER_CTRL6_TMRA6IE0_Pos         (9UL)                     /*!< TMRA6IE0 (Bit 9)                                      */
10765 #define CTIMER_CTRL6_TMRA6IE0_Msk         (0x200UL)                 /*!< TMRA6IE0 (Bitfield-Mask: 0x01)                        */
10766 #define CTIMER_CTRL6_TMRA6FN_Pos          (6UL)                     /*!< TMRA6FN (Bit 6)                                       */
10767 #define CTIMER_CTRL6_TMRA6FN_Msk          (0x1c0UL)                 /*!< TMRA6FN (Bitfield-Mask: 0x07)                         */
10768 #define CTIMER_CTRL6_TMRA6CLK_Pos         (1UL)                     /*!< TMRA6CLK (Bit 1)                                      */
10769 #define CTIMER_CTRL6_TMRA6CLK_Msk         (0x3eUL)                  /*!< TMRA6CLK (Bitfield-Mask: 0x1f)                        */
10770 #define CTIMER_CTRL6_TMRA6EN_Pos          (0UL)                     /*!< TMRA6EN (Bit 0)                                       */
10771 #define CTIMER_CTRL6_TMRA6EN_Msk          (0x1UL)                   /*!< TMRA6EN (Bitfield-Mask: 0x01)                         */
10772 /* =======================================================  CMPRAUXA6  ======================================================= */
10773 #define CTIMER_CMPRAUXA6_CMPR3A6_Pos      (16UL)                    /*!< CMPR3A6 (Bit 16)                                      */
10774 #define CTIMER_CMPRAUXA6_CMPR3A6_Msk      (0xffff0000UL)            /*!< CMPR3A6 (Bitfield-Mask: 0xffff)                       */
10775 #define CTIMER_CMPRAUXA6_CMPR2A6_Pos      (0UL)                     /*!< CMPR2A6 (Bit 0)                                       */
10776 #define CTIMER_CMPRAUXA6_CMPR2A6_Msk      (0xffffUL)                /*!< CMPR2A6 (Bitfield-Mask: 0xffff)                       */
10777 /* =======================================================  CMPRAUXB6  ======================================================= */
10778 #define CTIMER_CMPRAUXB6_CMPR3B6_Pos      (16UL)                    /*!< CMPR3B6 (Bit 16)                                      */
10779 #define CTIMER_CMPRAUXB6_CMPR3B6_Msk      (0xffff0000UL)            /*!< CMPR3B6 (Bitfield-Mask: 0xffff)                       */
10780 #define CTIMER_CMPRAUXB6_CMPR2B6_Pos      (0UL)                     /*!< CMPR2B6 (Bit 0)                                       */
10781 #define CTIMER_CMPRAUXB6_CMPR2B6_Msk      (0xffffUL)                /*!< CMPR2B6 (Bitfield-Mask: 0xffff)                       */
10782 /* =========================================================  AUX6  ========================================================== */
10783 #define CTIMER_AUX6_TMRB6EN23_Pos         (30UL)                    /*!< TMRB6EN23 (Bit 30)                                    */
10784 #define CTIMER_AUX6_TMRB6EN23_Msk         (0x40000000UL)            /*!< TMRB6EN23 (Bitfield-Mask: 0x01)                       */
10785 #define CTIMER_AUX6_TMRB6POL23_Pos        (29UL)                    /*!< TMRB6POL23 (Bit 29)                                   */
10786 #define CTIMER_AUX6_TMRB6POL23_Msk        (0x20000000UL)            /*!< TMRB6POL23 (Bitfield-Mask: 0x01)                      */
10787 #define CTIMER_AUX6_TMRB6TINV_Pos         (28UL)                    /*!< TMRB6TINV (Bit 28)                                    */
10788 #define CTIMER_AUX6_TMRB6TINV_Msk         (0x10000000UL)            /*!< TMRB6TINV (Bitfield-Mask: 0x01)                       */
10789 #define CTIMER_AUX6_TMRB6NOSYNC_Pos       (27UL)                    /*!< TMRB6NOSYNC (Bit 27)                                  */
10790 #define CTIMER_AUX6_TMRB6NOSYNC_Msk       (0x8000000UL)             /*!< TMRB6NOSYNC (Bitfield-Mask: 0x01)                     */
10791 #define CTIMER_AUX6_TMRB6TRIG_Pos         (23UL)                    /*!< TMRB6TRIG (Bit 23)                                    */
10792 #define CTIMER_AUX6_TMRB6TRIG_Msk         (0x7800000UL)             /*!< TMRB6TRIG (Bitfield-Mask: 0x0f)                       */
10793 #define CTIMER_AUX6_TMRB6LMT_Pos          (16UL)                    /*!< TMRB6LMT (Bit 16)                                     */
10794 #define CTIMER_AUX6_TMRB6LMT_Msk          (0x3f0000UL)              /*!< TMRB6LMT (Bitfield-Mask: 0x3f)                        */
10795 #define CTIMER_AUX6_TMRA6EN23_Pos         (14UL)                    /*!< TMRA6EN23 (Bit 14)                                    */
10796 #define CTIMER_AUX6_TMRA6EN23_Msk         (0x4000UL)                /*!< TMRA6EN23 (Bitfield-Mask: 0x01)                       */
10797 #define CTIMER_AUX6_TMRA6POL23_Pos        (13UL)                    /*!< TMRA6POL23 (Bit 13)                                   */
10798 #define CTIMER_AUX6_TMRA6POL23_Msk        (0x2000UL)                /*!< TMRA6POL23 (Bitfield-Mask: 0x01)                      */
10799 #define CTIMER_AUX6_TMRA6TINV_Pos         (12UL)                    /*!< TMRA6TINV (Bit 12)                                    */
10800 #define CTIMER_AUX6_TMRA6TINV_Msk         (0x1000UL)                /*!< TMRA6TINV (Bitfield-Mask: 0x01)                       */
10801 #define CTIMER_AUX6_TMRA6NOSYNC_Pos       (11UL)                    /*!< TMRA6NOSYNC (Bit 11)                                  */
10802 #define CTIMER_AUX6_TMRA6NOSYNC_Msk       (0x800UL)                 /*!< TMRA6NOSYNC (Bitfield-Mask: 0x01)                     */
10803 #define CTIMER_AUX6_TMRA6TRIG_Pos         (7UL)                     /*!< TMRA6TRIG (Bit 7)                                     */
10804 #define CTIMER_AUX6_TMRA6TRIG_Msk         (0x780UL)                 /*!< TMRA6TRIG (Bitfield-Mask: 0x0f)                       */
10805 #define CTIMER_AUX6_TMRA6LMT_Pos          (0UL)                     /*!< TMRA6LMT (Bit 0)                                      */
10806 #define CTIMER_AUX6_TMRA6LMT_Msk          (0x7fUL)                  /*!< TMRA6LMT (Bitfield-Mask: 0x7f)                        */
10807 /* =========================================================  TMR7  ========================================================== */
10808 #define CTIMER_TMR7_CTTMRB7_Pos           (16UL)                    /*!< CTTMRB7 (Bit 16)                                      */
10809 #define CTIMER_TMR7_CTTMRB7_Msk           (0xffff0000UL)            /*!< CTTMRB7 (Bitfield-Mask: 0xffff)                       */
10810 #define CTIMER_TMR7_CTTMRA7_Pos           (0UL)                     /*!< CTTMRA7 (Bit 0)                                       */
10811 #define CTIMER_TMR7_CTTMRA7_Msk           (0xffffUL)                /*!< CTTMRA7 (Bitfield-Mask: 0xffff)                       */
10812 /* ========================================================  CMPRA7  ========================================================= */
10813 #define CTIMER_CMPRA7_CMPR1A7_Pos         (16UL)                    /*!< CMPR1A7 (Bit 16)                                      */
10814 #define CTIMER_CMPRA7_CMPR1A7_Msk         (0xffff0000UL)            /*!< CMPR1A7 (Bitfield-Mask: 0xffff)                       */
10815 #define CTIMER_CMPRA7_CMPR0A7_Pos         (0UL)                     /*!< CMPR0A7 (Bit 0)                                       */
10816 #define CTIMER_CMPRA7_CMPR0A7_Msk         (0xffffUL)                /*!< CMPR0A7 (Bitfield-Mask: 0xffff)                       */
10817 /* ========================================================  CMPRB7  ========================================================= */
10818 #define CTIMER_CMPRB7_CMPR1B7_Pos         (16UL)                    /*!< CMPR1B7 (Bit 16)                                      */
10819 #define CTIMER_CMPRB7_CMPR1B7_Msk         (0xffff0000UL)            /*!< CMPR1B7 (Bitfield-Mask: 0xffff)                       */
10820 #define CTIMER_CMPRB7_CMPR0B7_Pos         (0UL)                     /*!< CMPR0B7 (Bit 0)                                       */
10821 #define CTIMER_CMPRB7_CMPR0B7_Msk         (0xffffUL)                /*!< CMPR0B7 (Bitfield-Mask: 0xffff)                       */
10822 /* =========================================================  CTRL7  ========================================================= */
10823 #define CTIMER_CTRL7_CTLINK7_Pos          (31UL)                    /*!< CTLINK7 (Bit 31)                                      */
10824 #define CTIMER_CTRL7_CTLINK7_Msk          (0x80000000UL)            /*!< CTLINK7 (Bitfield-Mask: 0x01)                         */
10825 #define CTIMER_CTRL7_TMRB7POL_Pos         (28UL)                    /*!< TMRB7POL (Bit 28)                                     */
10826 #define CTIMER_CTRL7_TMRB7POL_Msk         (0x10000000UL)            /*!< TMRB7POL (Bitfield-Mask: 0x01)                        */
10827 #define CTIMER_CTRL7_TMRB7CLR_Pos         (27UL)                    /*!< TMRB7CLR (Bit 27)                                     */
10828 #define CTIMER_CTRL7_TMRB7CLR_Msk         (0x8000000UL)             /*!< TMRB7CLR (Bitfield-Mask: 0x01)                        */
10829 #define CTIMER_CTRL7_TMRB7IE1_Pos         (26UL)                    /*!< TMRB7IE1 (Bit 26)                                     */
10830 #define CTIMER_CTRL7_TMRB7IE1_Msk         (0x4000000UL)             /*!< TMRB7IE1 (Bitfield-Mask: 0x01)                        */
10831 #define CTIMER_CTRL7_TMRB7IE0_Pos         (25UL)                    /*!< TMRB7IE0 (Bit 25)                                     */
10832 #define CTIMER_CTRL7_TMRB7IE0_Msk         (0x2000000UL)             /*!< TMRB7IE0 (Bitfield-Mask: 0x01)                        */
10833 #define CTIMER_CTRL7_TMRB7FN_Pos          (22UL)                    /*!< TMRB7FN (Bit 22)                                      */
10834 #define CTIMER_CTRL7_TMRB7FN_Msk          (0x1c00000UL)             /*!< TMRB7FN (Bitfield-Mask: 0x07)                         */
10835 #define CTIMER_CTRL7_TMRB7CLK_Pos         (17UL)                    /*!< TMRB7CLK (Bit 17)                                     */
10836 #define CTIMER_CTRL7_TMRB7CLK_Msk         (0x3e0000UL)              /*!< TMRB7CLK (Bitfield-Mask: 0x1f)                        */
10837 #define CTIMER_CTRL7_TMRB7EN_Pos          (16UL)                    /*!< TMRB7EN (Bit 16)                                      */
10838 #define CTIMER_CTRL7_TMRB7EN_Msk          (0x10000UL)               /*!< TMRB7EN (Bitfield-Mask: 0x01)                         */
10839 #define CTIMER_CTRL7_TMRA7POL_Pos         (12UL)                    /*!< TMRA7POL (Bit 12)                                     */
10840 #define CTIMER_CTRL7_TMRA7POL_Msk         (0x1000UL)                /*!< TMRA7POL (Bitfield-Mask: 0x01)                        */
10841 #define CTIMER_CTRL7_TMRA7CLR_Pos         (11UL)                    /*!< TMRA7CLR (Bit 11)                                     */
10842 #define CTIMER_CTRL7_TMRA7CLR_Msk         (0x800UL)                 /*!< TMRA7CLR (Bitfield-Mask: 0x01)                        */
10843 #define CTIMER_CTRL7_TMRA7IE1_Pos         (10UL)                    /*!< TMRA7IE1 (Bit 10)                                     */
10844 #define CTIMER_CTRL7_TMRA7IE1_Msk         (0x400UL)                 /*!< TMRA7IE1 (Bitfield-Mask: 0x01)                        */
10845 #define CTIMER_CTRL7_TMRA7IE0_Pos         (9UL)                     /*!< TMRA7IE0 (Bit 9)                                      */
10846 #define CTIMER_CTRL7_TMRA7IE0_Msk         (0x200UL)                 /*!< TMRA7IE0 (Bitfield-Mask: 0x01)                        */
10847 #define CTIMER_CTRL7_TMRA7FN_Pos          (6UL)                     /*!< TMRA7FN (Bit 6)                                       */
10848 #define CTIMER_CTRL7_TMRA7FN_Msk          (0x1c0UL)                 /*!< TMRA7FN (Bitfield-Mask: 0x07)                         */
10849 #define CTIMER_CTRL7_TMRA7CLK_Pos         (1UL)                     /*!< TMRA7CLK (Bit 1)                                      */
10850 #define CTIMER_CTRL7_TMRA7CLK_Msk         (0x3eUL)                  /*!< TMRA7CLK (Bitfield-Mask: 0x1f)                        */
10851 #define CTIMER_CTRL7_TMRA7EN_Pos          (0UL)                     /*!< TMRA7EN (Bit 0)                                       */
10852 #define CTIMER_CTRL7_TMRA7EN_Msk          (0x1UL)                   /*!< TMRA7EN (Bitfield-Mask: 0x01)                         */
10853 /* =======================================================  CMPRAUXA7  ======================================================= */
10854 #define CTIMER_CMPRAUXA7_CMPR3A7_Pos      (16UL)                    /*!< CMPR3A7 (Bit 16)                                      */
10855 #define CTIMER_CMPRAUXA7_CMPR3A7_Msk      (0xffff0000UL)            /*!< CMPR3A7 (Bitfield-Mask: 0xffff)                       */
10856 #define CTIMER_CMPRAUXA7_CMPR2A7_Pos      (0UL)                     /*!< CMPR2A7 (Bit 0)                                       */
10857 #define CTIMER_CMPRAUXA7_CMPR2A7_Msk      (0xffffUL)                /*!< CMPR2A7 (Bitfield-Mask: 0xffff)                       */
10858 /* =======================================================  CMPRAUXB7  ======================================================= */
10859 #define CTIMER_CMPRAUXB7_CMPR3B7_Pos      (16UL)                    /*!< CMPR3B7 (Bit 16)                                      */
10860 #define CTIMER_CMPRAUXB7_CMPR3B7_Msk      (0xffff0000UL)            /*!< CMPR3B7 (Bitfield-Mask: 0xffff)                       */
10861 #define CTIMER_CMPRAUXB7_CMPR2B7_Pos      (0UL)                     /*!< CMPR2B7 (Bit 0)                                       */
10862 #define CTIMER_CMPRAUXB7_CMPR2B7_Msk      (0xffffUL)                /*!< CMPR2B7 (Bitfield-Mask: 0xffff)                       */
10863 /* =========================================================  AUX7  ========================================================== */
10864 #define CTIMER_AUX7_TMRB7EN23_Pos         (30UL)                    /*!< TMRB7EN23 (Bit 30)                                    */
10865 #define CTIMER_AUX7_TMRB7EN23_Msk         (0x40000000UL)            /*!< TMRB7EN23 (Bitfield-Mask: 0x01)                       */
10866 #define CTIMER_AUX7_TMRB7POL23_Pos        (29UL)                    /*!< TMRB7POL23 (Bit 29)                                   */
10867 #define CTIMER_AUX7_TMRB7POL23_Msk        (0x20000000UL)            /*!< TMRB7POL23 (Bitfield-Mask: 0x01)                      */
10868 #define CTIMER_AUX7_TMRB7TINV_Pos         (28UL)                    /*!< TMRB7TINV (Bit 28)                                    */
10869 #define CTIMER_AUX7_TMRB7TINV_Msk         (0x10000000UL)            /*!< TMRB7TINV (Bitfield-Mask: 0x01)                       */
10870 #define CTIMER_AUX7_TMRB7NOSYNC_Pos       (27UL)                    /*!< TMRB7NOSYNC (Bit 27)                                  */
10871 #define CTIMER_AUX7_TMRB7NOSYNC_Msk       (0x8000000UL)             /*!< TMRB7NOSYNC (Bitfield-Mask: 0x01)                     */
10872 #define CTIMER_AUX7_TMRB7TRIG_Pos         (23UL)                    /*!< TMRB7TRIG (Bit 23)                                    */
10873 #define CTIMER_AUX7_TMRB7TRIG_Msk         (0x7800000UL)             /*!< TMRB7TRIG (Bitfield-Mask: 0x0f)                       */
10874 #define CTIMER_AUX7_TMRB7LMT_Pos          (16UL)                    /*!< TMRB7LMT (Bit 16)                                     */
10875 #define CTIMER_AUX7_TMRB7LMT_Msk          (0x3f0000UL)              /*!< TMRB7LMT (Bitfield-Mask: 0x3f)                        */
10876 #define CTIMER_AUX7_TMRA7EN23_Pos         (14UL)                    /*!< TMRA7EN23 (Bit 14)                                    */
10877 #define CTIMER_AUX7_TMRA7EN23_Msk         (0x4000UL)                /*!< TMRA7EN23 (Bitfield-Mask: 0x01)                       */
10878 #define CTIMER_AUX7_TMRA7POL23_Pos        (13UL)                    /*!< TMRA7POL23 (Bit 13)                                   */
10879 #define CTIMER_AUX7_TMRA7POL23_Msk        (0x2000UL)                /*!< TMRA7POL23 (Bitfield-Mask: 0x01)                      */
10880 #define CTIMER_AUX7_TMRA7TINV_Pos         (12UL)                    /*!< TMRA7TINV (Bit 12)                                    */
10881 #define CTIMER_AUX7_TMRA7TINV_Msk         (0x1000UL)                /*!< TMRA7TINV (Bitfield-Mask: 0x01)                       */
10882 #define CTIMER_AUX7_TMRA7NOSYNC_Pos       (11UL)                    /*!< TMRA7NOSYNC (Bit 11)                                  */
10883 #define CTIMER_AUX7_TMRA7NOSYNC_Msk       (0x800UL)                 /*!< TMRA7NOSYNC (Bitfield-Mask: 0x01)                     */
10884 #define CTIMER_AUX7_TMRA7TRIG_Pos         (7UL)                     /*!< TMRA7TRIG (Bit 7)                                     */
10885 #define CTIMER_AUX7_TMRA7TRIG_Msk         (0x780UL)                 /*!< TMRA7TRIG (Bitfield-Mask: 0x0f)                       */
10886 #define CTIMER_AUX7_TMRA7LMT_Pos          (0UL)                     /*!< TMRA7LMT (Bit 0)                                      */
10887 #define CTIMER_AUX7_TMRA7LMT_Msk          (0x7fUL)                  /*!< TMRA7LMT (Bitfield-Mask: 0x7f)                        */
10888 /* ========================================================  GLOBEN  ========================================================= */
10889 #define CTIMER_GLOBEN_ENB7_Pos            (15UL)                    /*!< ENB7 (Bit 15)                                         */
10890 #define CTIMER_GLOBEN_ENB7_Msk            (0x8000UL)                /*!< ENB7 (Bitfield-Mask: 0x01)                            */
10891 #define CTIMER_GLOBEN_ENA7_Pos            (14UL)                    /*!< ENA7 (Bit 14)                                         */
10892 #define CTIMER_GLOBEN_ENA7_Msk            (0x4000UL)                /*!< ENA7 (Bitfield-Mask: 0x01)                            */
10893 #define CTIMER_GLOBEN_ENB6_Pos            (13UL)                    /*!< ENB6 (Bit 13)                                         */
10894 #define CTIMER_GLOBEN_ENB6_Msk            (0x2000UL)                /*!< ENB6 (Bitfield-Mask: 0x01)                            */
10895 #define CTIMER_GLOBEN_ENA6_Pos            (12UL)                    /*!< ENA6 (Bit 12)                                         */
10896 #define CTIMER_GLOBEN_ENA6_Msk            (0x1000UL)                /*!< ENA6 (Bitfield-Mask: 0x01)                            */
10897 #define CTIMER_GLOBEN_ENB5_Pos            (11UL)                    /*!< ENB5 (Bit 11)                                         */
10898 #define CTIMER_GLOBEN_ENB5_Msk            (0x800UL)                 /*!< ENB5 (Bitfield-Mask: 0x01)                            */
10899 #define CTIMER_GLOBEN_ENA5_Pos            (10UL)                    /*!< ENA5 (Bit 10)                                         */
10900 #define CTIMER_GLOBEN_ENA5_Msk            (0x400UL)                 /*!< ENA5 (Bitfield-Mask: 0x01)                            */
10901 #define CTIMER_GLOBEN_ENB4_Pos            (9UL)                     /*!< ENB4 (Bit 9)                                          */
10902 #define CTIMER_GLOBEN_ENB4_Msk            (0x200UL)                 /*!< ENB4 (Bitfield-Mask: 0x01)                            */
10903 #define CTIMER_GLOBEN_ENA4_Pos            (8UL)                     /*!< ENA4 (Bit 8)                                          */
10904 #define CTIMER_GLOBEN_ENA4_Msk            (0x100UL)                 /*!< ENA4 (Bitfield-Mask: 0x01)                            */
10905 #define CTIMER_GLOBEN_ENB3_Pos            (7UL)                     /*!< ENB3 (Bit 7)                                          */
10906 #define CTIMER_GLOBEN_ENB3_Msk            (0x80UL)                  /*!< ENB3 (Bitfield-Mask: 0x01)                            */
10907 #define CTIMER_GLOBEN_ENA3_Pos            (6UL)                     /*!< ENA3 (Bit 6)                                          */
10908 #define CTIMER_GLOBEN_ENA3_Msk            (0x40UL)                  /*!< ENA3 (Bitfield-Mask: 0x01)                            */
10909 #define CTIMER_GLOBEN_ENB2_Pos            (5UL)                     /*!< ENB2 (Bit 5)                                          */
10910 #define CTIMER_GLOBEN_ENB2_Msk            (0x20UL)                  /*!< ENB2 (Bitfield-Mask: 0x01)                            */
10911 #define CTIMER_GLOBEN_ENA2_Pos            (4UL)                     /*!< ENA2 (Bit 4)                                          */
10912 #define CTIMER_GLOBEN_ENA2_Msk            (0x10UL)                  /*!< ENA2 (Bitfield-Mask: 0x01)                            */
10913 #define CTIMER_GLOBEN_ENB1_Pos            (3UL)                     /*!< ENB1 (Bit 3)                                          */
10914 #define CTIMER_GLOBEN_ENB1_Msk            (0x8UL)                   /*!< ENB1 (Bitfield-Mask: 0x01)                            */
10915 #define CTIMER_GLOBEN_ENA1_Pos            (2UL)                     /*!< ENA1 (Bit 2)                                          */
10916 #define CTIMER_GLOBEN_ENA1_Msk            (0x4UL)                   /*!< ENA1 (Bitfield-Mask: 0x01)                            */
10917 #define CTIMER_GLOBEN_ENB0_Pos            (1UL)                     /*!< ENB0 (Bit 1)                                          */
10918 #define CTIMER_GLOBEN_ENB0_Msk            (0x2UL)                   /*!< ENB0 (Bitfield-Mask: 0x01)                            */
10919 #define CTIMER_GLOBEN_ENA0_Pos            (0UL)                     /*!< ENA0 (Bit 0)                                          */
10920 #define CTIMER_GLOBEN_ENA0_Msk            (0x1UL)                   /*!< ENA0 (Bitfield-Mask: 0x01)                            */
10921 /* ========================================================  OUTCFG0  ======================================================== */
10922 #define CTIMER_OUTCFG0_CFG9_Pos           (28UL)                    /*!< CFG9 (Bit 28)                                         */
10923 #define CTIMER_OUTCFG0_CFG9_Msk           (0x70000000UL)            /*!< CFG9 (Bitfield-Mask: 0x07)                            */
10924 #define CTIMER_OUTCFG0_CFG8_Pos           (25UL)                    /*!< CFG8 (Bit 25)                                         */
10925 #define CTIMER_OUTCFG0_CFG8_Msk           (0xe000000UL)             /*!< CFG8 (Bitfield-Mask: 0x07)                            */
10926 #define CTIMER_OUTCFG0_CFG7_Pos           (22UL)                    /*!< CFG7 (Bit 22)                                         */
10927 #define CTIMER_OUTCFG0_CFG7_Msk           (0x1c00000UL)             /*!< CFG7 (Bitfield-Mask: 0x07)                            */
10928 #define CTIMER_OUTCFG0_CFG6_Pos           (19UL)                    /*!< CFG6 (Bit 19)                                         */
10929 #define CTIMER_OUTCFG0_CFG6_Msk           (0x380000UL)              /*!< CFG6 (Bitfield-Mask: 0x07)                            */
10930 #define CTIMER_OUTCFG0_CFG5_Pos           (16UL)                    /*!< CFG5 (Bit 16)                                         */
10931 #define CTIMER_OUTCFG0_CFG5_Msk           (0x70000UL)               /*!< CFG5 (Bitfield-Mask: 0x07)                            */
10932 #define CTIMER_OUTCFG0_CFG4_Pos           (12UL)                    /*!< CFG4 (Bit 12)                                         */
10933 #define CTIMER_OUTCFG0_CFG4_Msk           (0x7000UL)                /*!< CFG4 (Bitfield-Mask: 0x07)                            */
10934 #define CTIMER_OUTCFG0_CFG3_Pos           (9UL)                     /*!< CFG3 (Bit 9)                                          */
10935 #define CTIMER_OUTCFG0_CFG3_Msk           (0xe00UL)                 /*!< CFG3 (Bitfield-Mask: 0x07)                            */
10936 #define CTIMER_OUTCFG0_CFG2_Pos           (6UL)                     /*!< CFG2 (Bit 6)                                          */
10937 #define CTIMER_OUTCFG0_CFG2_Msk           (0x1c0UL)                 /*!< CFG2 (Bitfield-Mask: 0x07)                            */
10938 #define CTIMER_OUTCFG0_CFG1_Pos           (3UL)                     /*!< CFG1 (Bit 3)                                          */
10939 #define CTIMER_OUTCFG0_CFG1_Msk           (0x38UL)                  /*!< CFG1 (Bitfield-Mask: 0x07)                            */
10940 #define CTIMER_OUTCFG0_CFG0_Pos           (0UL)                     /*!< CFG0 (Bit 0)                                          */
10941 #define CTIMER_OUTCFG0_CFG0_Msk           (0x7UL)                   /*!< CFG0 (Bitfield-Mask: 0x07)                            */
10942 /* ========================================================  OUTCFG1  ======================================================== */
10943 #define CTIMER_OUTCFG1_CFG19_Pos          (28UL)                    /*!< CFG19 (Bit 28)                                        */
10944 #define CTIMER_OUTCFG1_CFG19_Msk          (0x70000000UL)            /*!< CFG19 (Bitfield-Mask: 0x07)                           */
10945 #define CTIMER_OUTCFG1_CFG18_Pos          (25UL)                    /*!< CFG18 (Bit 25)                                        */
10946 #define CTIMER_OUTCFG1_CFG18_Msk          (0xe000000UL)             /*!< CFG18 (Bitfield-Mask: 0x07)                           */
10947 #define CTIMER_OUTCFG1_CFG17_Pos          (22UL)                    /*!< CFG17 (Bit 22)                                        */
10948 #define CTIMER_OUTCFG1_CFG17_Msk          (0x1c00000UL)             /*!< CFG17 (Bitfield-Mask: 0x07)                           */
10949 #define CTIMER_OUTCFG1_CFG16_Pos          (19UL)                    /*!< CFG16 (Bit 19)                                        */
10950 #define CTIMER_OUTCFG1_CFG16_Msk          (0x380000UL)              /*!< CFG16 (Bitfield-Mask: 0x07)                           */
10951 #define CTIMER_OUTCFG1_CFG15_Pos          (16UL)                    /*!< CFG15 (Bit 16)                                        */
10952 #define CTIMER_OUTCFG1_CFG15_Msk          (0x70000UL)               /*!< CFG15 (Bitfield-Mask: 0x07)                           */
10953 #define CTIMER_OUTCFG1_CFG14_Pos          (12UL)                    /*!< CFG14 (Bit 12)                                        */
10954 #define CTIMER_OUTCFG1_CFG14_Msk          (0x7000UL)                /*!< CFG14 (Bitfield-Mask: 0x07)                           */
10955 #define CTIMER_OUTCFG1_CFG13_Pos          (9UL)                     /*!< CFG13 (Bit 9)                                         */
10956 #define CTIMER_OUTCFG1_CFG13_Msk          (0xe00UL)                 /*!< CFG13 (Bitfield-Mask: 0x07)                           */
10957 #define CTIMER_OUTCFG1_CFG12_Pos          (6UL)                     /*!< CFG12 (Bit 6)                                         */
10958 #define CTIMER_OUTCFG1_CFG12_Msk          (0x1c0UL)                 /*!< CFG12 (Bitfield-Mask: 0x07)                           */
10959 #define CTIMER_OUTCFG1_CFG11_Pos          (3UL)                     /*!< CFG11 (Bit 3)                                         */
10960 #define CTIMER_OUTCFG1_CFG11_Msk          (0x38UL)                  /*!< CFG11 (Bitfield-Mask: 0x07)                           */
10961 #define CTIMER_OUTCFG1_CFG10_Pos          (0UL)                     /*!< CFG10 (Bit 0)                                         */
10962 #define CTIMER_OUTCFG1_CFG10_Msk          (0x7UL)                   /*!< CFG10 (Bitfield-Mask: 0x07)                           */
10963 /* ========================================================  OUTCFG2  ======================================================== */
10964 #define CTIMER_OUTCFG2_CFG29_Pos          (28UL)                    /*!< CFG29 (Bit 28)                                        */
10965 #define CTIMER_OUTCFG2_CFG29_Msk          (0x70000000UL)            /*!< CFG29 (Bitfield-Mask: 0x07)                           */
10966 #define CTIMER_OUTCFG2_CFG28_Pos          (25UL)                    /*!< CFG28 (Bit 25)                                        */
10967 #define CTIMER_OUTCFG2_CFG28_Msk          (0xe000000UL)             /*!< CFG28 (Bitfield-Mask: 0x07)                           */
10968 #define CTIMER_OUTCFG2_CFG27_Pos          (22UL)                    /*!< CFG27 (Bit 22)                                        */
10969 #define CTIMER_OUTCFG2_CFG27_Msk          (0x1c00000UL)             /*!< CFG27 (Bitfield-Mask: 0x07)                           */
10970 #define CTIMER_OUTCFG2_CFG26_Pos          (19UL)                    /*!< CFG26 (Bit 19)                                        */
10971 #define CTIMER_OUTCFG2_CFG26_Msk          (0x380000UL)              /*!< CFG26 (Bitfield-Mask: 0x07)                           */
10972 #define CTIMER_OUTCFG2_CFG25_Pos          (16UL)                    /*!< CFG25 (Bit 16)                                        */
10973 #define CTIMER_OUTCFG2_CFG25_Msk          (0x70000UL)               /*!< CFG25 (Bitfield-Mask: 0x07)                           */
10974 #define CTIMER_OUTCFG2_CFG24_Pos          (12UL)                    /*!< CFG24 (Bit 12)                                        */
10975 #define CTIMER_OUTCFG2_CFG24_Msk          (0x7000UL)                /*!< CFG24 (Bitfield-Mask: 0x07)                           */
10976 #define CTIMER_OUTCFG2_CFG23_Pos          (9UL)                     /*!< CFG23 (Bit 9)                                         */
10977 #define CTIMER_OUTCFG2_CFG23_Msk          (0xe00UL)                 /*!< CFG23 (Bitfield-Mask: 0x07)                           */
10978 #define CTIMER_OUTCFG2_CFG22_Pos          (6UL)                     /*!< CFG22 (Bit 6)                                         */
10979 #define CTIMER_OUTCFG2_CFG22_Msk          (0x1c0UL)                 /*!< CFG22 (Bitfield-Mask: 0x07)                           */
10980 #define CTIMER_OUTCFG2_CFG21_Pos          (3UL)                     /*!< CFG21 (Bit 3)                                         */
10981 #define CTIMER_OUTCFG2_CFG21_Msk          (0x38UL)                  /*!< CFG21 (Bitfield-Mask: 0x07)                           */
10982 #define CTIMER_OUTCFG2_CFG20_Pos          (0UL)                     /*!< CFG20 (Bit 0)                                         */
10983 #define CTIMER_OUTCFG2_CFG20_Msk          (0x7UL)                   /*!< CFG20 (Bitfield-Mask: 0x07)                           */
10984 /* ========================================================  OUTCFG3  ======================================================== */
10985 #define CTIMER_OUTCFG3_CFG31_Pos          (3UL)                     /*!< CFG31 (Bit 3)                                         */
10986 #define CTIMER_OUTCFG3_CFG31_Msk          (0x38UL)                  /*!< CFG31 (Bitfield-Mask: 0x07)                           */
10987 #define CTIMER_OUTCFG3_CFG30_Pos          (0UL)                     /*!< CFG30 (Bit 0)                                         */
10988 #define CTIMER_OUTCFG3_CFG30_Msk          (0x7UL)                   /*!< CFG30 (Bitfield-Mask: 0x07)                           */
10989 /* =========================================================  INCFG  ========================================================= */
10990 #define CTIMER_INCFG_CFGB7_Pos            (15UL)                    /*!< CFGB7 (Bit 15)                                        */
10991 #define CTIMER_INCFG_CFGB7_Msk            (0x8000UL)                /*!< CFGB7 (Bitfield-Mask: 0x01)                           */
10992 #define CTIMER_INCFG_CFGA7_Pos            (14UL)                    /*!< CFGA7 (Bit 14)                                        */
10993 #define CTIMER_INCFG_CFGA7_Msk            (0x4000UL)                /*!< CFGA7 (Bitfield-Mask: 0x01)                           */
10994 #define CTIMER_INCFG_CFGB6_Pos            (13UL)                    /*!< CFGB6 (Bit 13)                                        */
10995 #define CTIMER_INCFG_CFGB6_Msk            (0x2000UL)                /*!< CFGB6 (Bitfield-Mask: 0x01)                           */
10996 #define CTIMER_INCFG_CFGA6_Pos            (12UL)                    /*!< CFGA6 (Bit 12)                                        */
10997 #define CTIMER_INCFG_CFGA6_Msk            (0x1000UL)                /*!< CFGA6 (Bitfield-Mask: 0x01)                           */
10998 #define CTIMER_INCFG_CFGB5_Pos            (11UL)                    /*!< CFGB5 (Bit 11)                                        */
10999 #define CTIMER_INCFG_CFGB5_Msk            (0x800UL)                 /*!< CFGB5 (Bitfield-Mask: 0x01)                           */
11000 #define CTIMER_INCFG_CFGA5_Pos            (10UL)                    /*!< CFGA5 (Bit 10)                                        */
11001 #define CTIMER_INCFG_CFGA5_Msk            (0x400UL)                 /*!< CFGA5 (Bitfield-Mask: 0x01)                           */
11002 #define CTIMER_INCFG_CFGB4_Pos            (9UL)                     /*!< CFGB4 (Bit 9)                                         */
11003 #define CTIMER_INCFG_CFGB4_Msk            (0x200UL)                 /*!< CFGB4 (Bitfield-Mask: 0x01)                           */
11004 #define CTIMER_INCFG_CFGA4_Pos            (8UL)                     /*!< CFGA4 (Bit 8)                                         */
11005 #define CTIMER_INCFG_CFGA4_Msk            (0x100UL)                 /*!< CFGA4 (Bitfield-Mask: 0x01)                           */
11006 #define CTIMER_INCFG_CFGB3_Pos            (7UL)                     /*!< CFGB3 (Bit 7)                                         */
11007 #define CTIMER_INCFG_CFGB3_Msk            (0x80UL)                  /*!< CFGB3 (Bitfield-Mask: 0x01)                           */
11008 #define CTIMER_INCFG_CFGA3_Pos            (6UL)                     /*!< CFGA3 (Bit 6)                                         */
11009 #define CTIMER_INCFG_CFGA3_Msk            (0x40UL)                  /*!< CFGA3 (Bitfield-Mask: 0x01)                           */
11010 #define CTIMER_INCFG_CFGB2_Pos            (5UL)                     /*!< CFGB2 (Bit 5)                                         */
11011 #define CTIMER_INCFG_CFGB2_Msk            (0x20UL)                  /*!< CFGB2 (Bitfield-Mask: 0x01)                           */
11012 #define CTIMER_INCFG_CFGA2_Pos            (4UL)                     /*!< CFGA2 (Bit 4)                                         */
11013 #define CTIMER_INCFG_CFGA2_Msk            (0x10UL)                  /*!< CFGA2 (Bitfield-Mask: 0x01)                           */
11014 #define CTIMER_INCFG_CFGB1_Pos            (3UL)                     /*!< CFGB1 (Bit 3)                                         */
11015 #define CTIMER_INCFG_CFGB1_Msk            (0x8UL)                   /*!< CFGB1 (Bitfield-Mask: 0x01)                           */
11016 #define CTIMER_INCFG_CFGA1_Pos            (2UL)                     /*!< CFGA1 (Bit 2)                                         */
11017 #define CTIMER_INCFG_CFGA1_Msk            (0x4UL)                   /*!< CFGA1 (Bitfield-Mask: 0x01)                           */
11018 #define CTIMER_INCFG_CFGB0_Pos            (1UL)                     /*!< CFGB0 (Bit 1)                                         */
11019 #define CTIMER_INCFG_CFGB0_Msk            (0x2UL)                   /*!< CFGB0 (Bitfield-Mask: 0x01)                           */
11020 #define CTIMER_INCFG_CFGA0_Pos            (0UL)                     /*!< CFGA0 (Bit 0)                                         */
11021 #define CTIMER_INCFG_CFGA0_Msk            (0x1UL)                   /*!< CFGA0 (Bitfield-Mask: 0x01)                           */
11022 /* =========================================================  STCFG  ========================================================= */
11023 #define CTIMER_STCFG_FREEZE_Pos           (31UL)                    /*!< FREEZE (Bit 31)                                       */
11024 #define CTIMER_STCFG_FREEZE_Msk           (0x80000000UL)            /*!< FREEZE (Bitfield-Mask: 0x01)                          */
11025 #define CTIMER_STCFG_CLEAR_Pos            (30UL)                    /*!< CLEAR (Bit 30)                                        */
11026 #define CTIMER_STCFG_CLEAR_Msk            (0x40000000UL)            /*!< CLEAR (Bitfield-Mask: 0x01)                           */
11027 #define CTIMER_STCFG_COMPARE_H_EN_Pos     (15UL)                    /*!< COMPARE_H_EN (Bit 15)                                 */
11028 #define CTIMER_STCFG_COMPARE_H_EN_Msk     (0x8000UL)                /*!< COMPARE_H_EN (Bitfield-Mask: 0x01)                    */
11029 #define CTIMER_STCFG_COMPARE_G_EN_Pos     (14UL)                    /*!< COMPARE_G_EN (Bit 14)                                 */
11030 #define CTIMER_STCFG_COMPARE_G_EN_Msk     (0x4000UL)                /*!< COMPARE_G_EN (Bitfield-Mask: 0x01)                    */
11031 #define CTIMER_STCFG_COMPARE_F_EN_Pos     (13UL)                    /*!< COMPARE_F_EN (Bit 13)                                 */
11032 #define CTIMER_STCFG_COMPARE_F_EN_Msk     (0x2000UL)                /*!< COMPARE_F_EN (Bitfield-Mask: 0x01)                    */
11033 #define CTIMER_STCFG_COMPARE_E_EN_Pos     (12UL)                    /*!< COMPARE_E_EN (Bit 12)                                 */
11034 #define CTIMER_STCFG_COMPARE_E_EN_Msk     (0x1000UL)                /*!< COMPARE_E_EN (Bitfield-Mask: 0x01)                    */
11035 #define CTIMER_STCFG_COMPARE_D_EN_Pos     (11UL)                    /*!< COMPARE_D_EN (Bit 11)                                 */
11036 #define CTIMER_STCFG_COMPARE_D_EN_Msk     (0x800UL)                 /*!< COMPARE_D_EN (Bitfield-Mask: 0x01)                    */
11037 #define CTIMER_STCFG_COMPARE_C_EN_Pos     (10UL)                    /*!< COMPARE_C_EN (Bit 10)                                 */
11038 #define CTIMER_STCFG_COMPARE_C_EN_Msk     (0x400UL)                 /*!< COMPARE_C_EN (Bitfield-Mask: 0x01)                    */
11039 #define CTIMER_STCFG_COMPARE_B_EN_Pos     (9UL)                     /*!< COMPARE_B_EN (Bit 9)                                  */
11040 #define CTIMER_STCFG_COMPARE_B_EN_Msk     (0x200UL)                 /*!< COMPARE_B_EN (Bitfield-Mask: 0x01)                    */
11041 #define CTIMER_STCFG_COMPARE_A_EN_Pos     (8UL)                     /*!< COMPARE_A_EN (Bit 8)                                  */
11042 #define CTIMER_STCFG_COMPARE_A_EN_Msk     (0x100UL)                 /*!< COMPARE_A_EN (Bitfield-Mask: 0x01)                    */
11043 #define CTIMER_STCFG_CLKSEL_Pos           (0UL)                     /*!< CLKSEL (Bit 0)                                        */
11044 #define CTIMER_STCFG_CLKSEL_Msk           (0xfUL)                   /*!< CLKSEL (Bitfield-Mask: 0x0f)                          */
11045 /* =========================================================  STTMR  ========================================================= */
11046 #define CTIMER_STTMR_STTMR_Pos            (0UL)                     /*!< STTMR (Bit 0)                                         */
11047 #define CTIMER_STTMR_STTMR_Msk            (0xffffffffUL)            /*!< STTMR (Bitfield-Mask: 0xffffffff)                     */
11048 /* ====================================================  CAPTURECONTROL  ===================================================== */
11049 #define CTIMER_CAPTURECONTROL_CAPTURE3_Pos (3UL)                    /*!< CAPTURE3 (Bit 3)                                      */
11050 #define CTIMER_CAPTURECONTROL_CAPTURE3_Msk (0x8UL)                  /*!< CAPTURE3 (Bitfield-Mask: 0x01)                        */
11051 #define CTIMER_CAPTURECONTROL_CAPTURE2_Pos (2UL)                    /*!< CAPTURE2 (Bit 2)                                      */
11052 #define CTIMER_CAPTURECONTROL_CAPTURE2_Msk (0x4UL)                  /*!< CAPTURE2 (Bitfield-Mask: 0x01)                        */
11053 #define CTIMER_CAPTURECONTROL_CAPTURE1_Pos (1UL)                    /*!< CAPTURE1 (Bit 1)                                      */
11054 #define CTIMER_CAPTURECONTROL_CAPTURE1_Msk (0x2UL)                  /*!< CAPTURE1 (Bitfield-Mask: 0x01)                        */
11055 #define CTIMER_CAPTURECONTROL_CAPTURE0_Pos (0UL)                    /*!< CAPTURE0 (Bit 0)                                      */
11056 #define CTIMER_CAPTURECONTROL_CAPTURE0_Msk (0x1UL)                  /*!< CAPTURE0 (Bitfield-Mask: 0x01)                        */
11057 /* ========================================================  SCMPR0  ========================================================= */
11058 #define CTIMER_SCMPR0_SCMPR0_Pos          (0UL)                     /*!< SCMPR0 (Bit 0)                                        */
11059 #define CTIMER_SCMPR0_SCMPR0_Msk          (0xffffffffUL)            /*!< SCMPR0 (Bitfield-Mask: 0xffffffff)                    */
11060 /* ========================================================  SCMPR1  ========================================================= */
11061 #define CTIMER_SCMPR1_SCMPR1_Pos          (0UL)                     /*!< SCMPR1 (Bit 0)                                        */
11062 #define CTIMER_SCMPR1_SCMPR1_Msk          (0xffffffffUL)            /*!< SCMPR1 (Bitfield-Mask: 0xffffffff)                    */
11063 /* ========================================================  SCMPR2  ========================================================= */
11064 #define CTIMER_SCMPR2_SCMPR2_Pos          (0UL)                     /*!< SCMPR2 (Bit 0)                                        */
11065 #define CTIMER_SCMPR2_SCMPR2_Msk          (0xffffffffUL)            /*!< SCMPR2 (Bitfield-Mask: 0xffffffff)                    */
11066 /* ========================================================  SCMPR3  ========================================================= */
11067 #define CTIMER_SCMPR3_SCMPR3_Pos          (0UL)                     /*!< SCMPR3 (Bit 0)                                        */
11068 #define CTIMER_SCMPR3_SCMPR3_Msk          (0xffffffffUL)            /*!< SCMPR3 (Bitfield-Mask: 0xffffffff)                    */
11069 /* ========================================================  SCMPR4  ========================================================= */
11070 #define CTIMER_SCMPR4_SCMPR4_Pos          (0UL)                     /*!< SCMPR4 (Bit 0)                                        */
11071 #define CTIMER_SCMPR4_SCMPR4_Msk          (0xffffffffUL)            /*!< SCMPR4 (Bitfield-Mask: 0xffffffff)                    */
11072 /* ========================================================  SCMPR5  ========================================================= */
11073 #define CTIMER_SCMPR5_SCMPR5_Pos          (0UL)                     /*!< SCMPR5 (Bit 0)                                        */
11074 #define CTIMER_SCMPR5_SCMPR5_Msk          (0xffffffffUL)            /*!< SCMPR5 (Bitfield-Mask: 0xffffffff)                    */
11075 /* ========================================================  SCMPR6  ========================================================= */
11076 #define CTIMER_SCMPR6_SCMPR6_Pos          (0UL)                     /*!< SCMPR6 (Bit 0)                                        */
11077 #define CTIMER_SCMPR6_SCMPR6_Msk          (0xffffffffUL)            /*!< SCMPR6 (Bitfield-Mask: 0xffffffff)                    */
11078 /* ========================================================  SCMPR7  ========================================================= */
11079 #define CTIMER_SCMPR7_SCMPR7_Pos          (0UL)                     /*!< SCMPR7 (Bit 0)                                        */
11080 #define CTIMER_SCMPR7_SCMPR7_Msk          (0xffffffffUL)            /*!< SCMPR7 (Bitfield-Mask: 0xffffffff)                    */
11081 /* ========================================================  SCAPT0  ========================================================= */
11082 #define CTIMER_SCAPT0_SCAPT0_Pos          (0UL)                     /*!< SCAPT0 (Bit 0)                                        */
11083 #define CTIMER_SCAPT0_SCAPT0_Msk          (0xffffffffUL)            /*!< SCAPT0 (Bitfield-Mask: 0xffffffff)                    */
11084 /* ========================================================  SCAPT1  ========================================================= */
11085 #define CTIMER_SCAPT1_SCAPT1_Pos          (0UL)                     /*!< SCAPT1 (Bit 0)                                        */
11086 #define CTIMER_SCAPT1_SCAPT1_Msk          (0xffffffffUL)            /*!< SCAPT1 (Bitfield-Mask: 0xffffffff)                    */
11087 /* ========================================================  SCAPT2  ========================================================= */
11088 #define CTIMER_SCAPT2_SCAPT2_Pos          (0UL)                     /*!< SCAPT2 (Bit 0)                                        */
11089 #define CTIMER_SCAPT2_SCAPT2_Msk          (0xffffffffUL)            /*!< SCAPT2 (Bitfield-Mask: 0xffffffff)                    */
11090 /* ========================================================  SCAPT3  ========================================================= */
11091 #define CTIMER_SCAPT3_SCAPT3_Pos          (0UL)                     /*!< SCAPT3 (Bit 0)                                        */
11092 #define CTIMER_SCAPT3_SCAPT3_Msk          (0xffffffffUL)            /*!< SCAPT3 (Bitfield-Mask: 0xffffffff)                    */
11093 /* =========================================================  SNVR0  ========================================================= */
11094 #define CTIMER_SNVR0_SNVR0_Pos            (0UL)                     /*!< SNVR0 (Bit 0)                                         */
11095 #define CTIMER_SNVR0_SNVR0_Msk            (0xffffffffUL)            /*!< SNVR0 (Bitfield-Mask: 0xffffffff)                     */
11096 /* =========================================================  SNVR1  ========================================================= */
11097 #define CTIMER_SNVR1_SNVR1_Pos            (0UL)                     /*!< SNVR1 (Bit 0)                                         */
11098 #define CTIMER_SNVR1_SNVR1_Msk            (0xffffffffUL)            /*!< SNVR1 (Bitfield-Mask: 0xffffffff)                     */
11099 /* =========================================================  SNVR2  ========================================================= */
11100 #define CTIMER_SNVR2_SNVR2_Pos            (0UL)                     /*!< SNVR2 (Bit 0)                                         */
11101 #define CTIMER_SNVR2_SNVR2_Msk            (0xffffffffUL)            /*!< SNVR2 (Bitfield-Mask: 0xffffffff)                     */
11102 /* =========================================================  SNVR3  ========================================================= */
11103 #define CTIMER_SNVR3_SNVR3_Pos            (0UL)                     /*!< SNVR3 (Bit 0)                                         */
11104 #define CTIMER_SNVR3_SNVR3_Msk            (0xffffffffUL)            /*!< SNVR3 (Bitfield-Mask: 0xffffffff)                     */
11105 /* =========================================================  INTEN  ========================================================= */
11106 #define CTIMER_INTEN_CTMRB7C1INT_Pos      (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
11107 #define CTIMER_INTEN_CTMRB7C1INT_Msk      (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
11108 #define CTIMER_INTEN_CTMRA7C1INT_Pos      (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
11109 #define CTIMER_INTEN_CTMRA7C1INT_Msk      (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
11110 #define CTIMER_INTEN_CTMRB6C1INT_Pos      (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
11111 #define CTIMER_INTEN_CTMRB6C1INT_Msk      (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
11112 #define CTIMER_INTEN_CTMRA6C1INT_Pos      (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
11113 #define CTIMER_INTEN_CTMRA6C1INT_Msk      (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
11114 #define CTIMER_INTEN_CTMRB5C1INT_Pos      (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
11115 #define CTIMER_INTEN_CTMRB5C1INT_Msk      (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
11116 #define CTIMER_INTEN_CTMRA5C1INT_Pos      (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
11117 #define CTIMER_INTEN_CTMRA5C1INT_Msk      (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
11118 #define CTIMER_INTEN_CTMRB4C1INT_Pos      (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
11119 #define CTIMER_INTEN_CTMRB4C1INT_Msk      (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
11120 #define CTIMER_INTEN_CTMRA4C1INT_Pos      (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
11121 #define CTIMER_INTEN_CTMRA4C1INT_Msk      (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
11122 #define CTIMER_INTEN_CTMRB3C1INT_Pos      (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
11123 #define CTIMER_INTEN_CTMRB3C1INT_Msk      (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
11124 #define CTIMER_INTEN_CTMRA3C1INT_Pos      (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
11125 #define CTIMER_INTEN_CTMRA3C1INT_Msk      (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
11126 #define CTIMER_INTEN_CTMRB2C1INT_Pos      (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
11127 #define CTIMER_INTEN_CTMRB2C1INT_Msk      (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
11128 #define CTIMER_INTEN_CTMRA2C1INT_Pos      (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
11129 #define CTIMER_INTEN_CTMRA2C1INT_Msk      (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
11130 #define CTIMER_INTEN_CTMRB1C1INT_Pos      (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
11131 #define CTIMER_INTEN_CTMRB1C1INT_Msk      (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
11132 #define CTIMER_INTEN_CTMRA1C1INT_Pos      (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
11133 #define CTIMER_INTEN_CTMRA1C1INT_Msk      (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
11134 #define CTIMER_INTEN_CTMRB0C1INT_Pos      (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
11135 #define CTIMER_INTEN_CTMRB0C1INT_Msk      (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
11136 #define CTIMER_INTEN_CTMRA0C1INT_Pos      (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
11137 #define CTIMER_INTEN_CTMRA0C1INT_Msk      (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
11138 #define CTIMER_INTEN_CTMRB7C0INT_Pos      (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
11139 #define CTIMER_INTEN_CTMRB7C0INT_Msk      (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
11140 #define CTIMER_INTEN_CTMRA7C0INT_Pos      (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
11141 #define CTIMER_INTEN_CTMRA7C0INT_Msk      (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
11142 #define CTIMER_INTEN_CTMRB6C0INT_Pos      (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
11143 #define CTIMER_INTEN_CTMRB6C0INT_Msk      (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
11144 #define CTIMER_INTEN_CTMRA6C0INT_Pos      (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
11145 #define CTIMER_INTEN_CTMRA6C0INT_Msk      (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
11146 #define CTIMER_INTEN_CTMRB5C0INT_Pos      (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
11147 #define CTIMER_INTEN_CTMRB5C0INT_Msk      (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
11148 #define CTIMER_INTEN_CTMRA5C0INT_Pos      (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
11149 #define CTIMER_INTEN_CTMRA5C0INT_Msk      (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
11150 #define CTIMER_INTEN_CTMRB4C0INT_Pos      (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
11151 #define CTIMER_INTEN_CTMRB4C0INT_Msk      (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
11152 #define CTIMER_INTEN_CTMRA4C0INT_Pos      (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
11153 #define CTIMER_INTEN_CTMRA4C0INT_Msk      (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
11154 #define CTIMER_INTEN_CTMRB3C0INT_Pos      (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
11155 #define CTIMER_INTEN_CTMRB3C0INT_Msk      (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
11156 #define CTIMER_INTEN_CTMRA3C0INT_Pos      (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
11157 #define CTIMER_INTEN_CTMRA3C0INT_Msk      (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
11158 #define CTIMER_INTEN_CTMRB2C0INT_Pos      (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
11159 #define CTIMER_INTEN_CTMRB2C0INT_Msk      (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
11160 #define CTIMER_INTEN_CTMRA2C0INT_Pos      (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
11161 #define CTIMER_INTEN_CTMRA2C0INT_Msk      (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
11162 #define CTIMER_INTEN_CTMRB1C0INT_Pos      (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
11163 #define CTIMER_INTEN_CTMRB1C0INT_Msk      (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
11164 #define CTIMER_INTEN_CTMRA1C0INT_Pos      (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
11165 #define CTIMER_INTEN_CTMRA1C0INT_Msk      (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
11166 #define CTIMER_INTEN_CTMRB0C0INT_Pos      (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
11167 #define CTIMER_INTEN_CTMRB0C0INT_Msk      (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
11168 #define CTIMER_INTEN_CTMRA0C0INT_Pos      (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
11169 #define CTIMER_INTEN_CTMRA0C0INT_Msk      (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
11170 /* ========================================================  INTSTAT  ======================================================== */
11171 #define CTIMER_INTSTAT_CTMRB7C1INT_Pos    (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
11172 #define CTIMER_INTSTAT_CTMRB7C1INT_Msk    (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
11173 #define CTIMER_INTSTAT_CTMRA7C1INT_Pos    (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
11174 #define CTIMER_INTSTAT_CTMRA7C1INT_Msk    (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
11175 #define CTIMER_INTSTAT_CTMRB6C1INT_Pos    (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
11176 #define CTIMER_INTSTAT_CTMRB6C1INT_Msk    (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
11177 #define CTIMER_INTSTAT_CTMRA6C1INT_Pos    (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
11178 #define CTIMER_INTSTAT_CTMRA6C1INT_Msk    (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
11179 #define CTIMER_INTSTAT_CTMRB5C1INT_Pos    (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
11180 #define CTIMER_INTSTAT_CTMRB5C1INT_Msk    (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
11181 #define CTIMER_INTSTAT_CTMRA5C1INT_Pos    (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
11182 #define CTIMER_INTSTAT_CTMRA5C1INT_Msk    (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
11183 #define CTIMER_INTSTAT_CTMRB4C1INT_Pos    (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
11184 #define CTIMER_INTSTAT_CTMRB4C1INT_Msk    (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
11185 #define CTIMER_INTSTAT_CTMRA4C1INT_Pos    (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
11186 #define CTIMER_INTSTAT_CTMRA4C1INT_Msk    (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
11187 #define CTIMER_INTSTAT_CTMRB3C1INT_Pos    (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
11188 #define CTIMER_INTSTAT_CTMRB3C1INT_Msk    (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
11189 #define CTIMER_INTSTAT_CTMRA3C1INT_Pos    (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
11190 #define CTIMER_INTSTAT_CTMRA3C1INT_Msk    (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
11191 #define CTIMER_INTSTAT_CTMRB2C1INT_Pos    (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
11192 #define CTIMER_INTSTAT_CTMRB2C1INT_Msk    (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
11193 #define CTIMER_INTSTAT_CTMRA2C1INT_Pos    (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
11194 #define CTIMER_INTSTAT_CTMRA2C1INT_Msk    (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
11195 #define CTIMER_INTSTAT_CTMRB1C1INT_Pos    (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
11196 #define CTIMER_INTSTAT_CTMRB1C1INT_Msk    (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
11197 #define CTIMER_INTSTAT_CTMRA1C1INT_Pos    (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
11198 #define CTIMER_INTSTAT_CTMRA1C1INT_Msk    (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
11199 #define CTIMER_INTSTAT_CTMRB0C1INT_Pos    (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
11200 #define CTIMER_INTSTAT_CTMRB0C1INT_Msk    (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
11201 #define CTIMER_INTSTAT_CTMRA0C1INT_Pos    (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
11202 #define CTIMER_INTSTAT_CTMRA0C1INT_Msk    (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
11203 #define CTIMER_INTSTAT_CTMRB7C0INT_Pos    (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
11204 #define CTIMER_INTSTAT_CTMRB7C0INT_Msk    (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
11205 #define CTIMER_INTSTAT_CTMRA7C0INT_Pos    (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
11206 #define CTIMER_INTSTAT_CTMRA7C0INT_Msk    (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
11207 #define CTIMER_INTSTAT_CTMRB6C0INT_Pos    (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
11208 #define CTIMER_INTSTAT_CTMRB6C0INT_Msk    (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
11209 #define CTIMER_INTSTAT_CTMRA6C0INT_Pos    (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
11210 #define CTIMER_INTSTAT_CTMRA6C0INT_Msk    (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
11211 #define CTIMER_INTSTAT_CTMRB5C0INT_Pos    (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
11212 #define CTIMER_INTSTAT_CTMRB5C0INT_Msk    (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
11213 #define CTIMER_INTSTAT_CTMRA5C0INT_Pos    (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
11214 #define CTIMER_INTSTAT_CTMRA5C0INT_Msk    (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
11215 #define CTIMER_INTSTAT_CTMRB4C0INT_Pos    (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
11216 #define CTIMER_INTSTAT_CTMRB4C0INT_Msk    (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
11217 #define CTIMER_INTSTAT_CTMRA4C0INT_Pos    (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
11218 #define CTIMER_INTSTAT_CTMRA4C0INT_Msk    (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
11219 #define CTIMER_INTSTAT_CTMRB3C0INT_Pos    (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
11220 #define CTIMER_INTSTAT_CTMRB3C0INT_Msk    (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
11221 #define CTIMER_INTSTAT_CTMRA3C0INT_Pos    (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
11222 #define CTIMER_INTSTAT_CTMRA3C0INT_Msk    (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
11223 #define CTIMER_INTSTAT_CTMRB2C0INT_Pos    (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
11224 #define CTIMER_INTSTAT_CTMRB2C0INT_Msk    (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
11225 #define CTIMER_INTSTAT_CTMRA2C0INT_Pos    (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
11226 #define CTIMER_INTSTAT_CTMRA2C0INT_Msk    (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
11227 #define CTIMER_INTSTAT_CTMRB1C0INT_Pos    (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
11228 #define CTIMER_INTSTAT_CTMRB1C0INT_Msk    (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
11229 #define CTIMER_INTSTAT_CTMRA1C0INT_Pos    (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
11230 #define CTIMER_INTSTAT_CTMRA1C0INT_Msk    (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
11231 #define CTIMER_INTSTAT_CTMRB0C0INT_Pos    (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
11232 #define CTIMER_INTSTAT_CTMRB0C0INT_Msk    (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
11233 #define CTIMER_INTSTAT_CTMRA0C0INT_Pos    (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
11234 #define CTIMER_INTSTAT_CTMRA0C0INT_Msk    (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
11235 /* ========================================================  INTCLR  ========================================================= */
11236 #define CTIMER_INTCLR_CTMRB7C1INT_Pos     (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
11237 #define CTIMER_INTCLR_CTMRB7C1INT_Msk     (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
11238 #define CTIMER_INTCLR_CTMRA7C1INT_Pos     (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
11239 #define CTIMER_INTCLR_CTMRA7C1INT_Msk     (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
11240 #define CTIMER_INTCLR_CTMRB6C1INT_Pos     (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
11241 #define CTIMER_INTCLR_CTMRB6C1INT_Msk     (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
11242 #define CTIMER_INTCLR_CTMRA6C1INT_Pos     (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
11243 #define CTIMER_INTCLR_CTMRA6C1INT_Msk     (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
11244 #define CTIMER_INTCLR_CTMRB5C1INT_Pos     (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
11245 #define CTIMER_INTCLR_CTMRB5C1INT_Msk     (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
11246 #define CTIMER_INTCLR_CTMRA5C1INT_Pos     (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
11247 #define CTIMER_INTCLR_CTMRA5C1INT_Msk     (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
11248 #define CTIMER_INTCLR_CTMRB4C1INT_Pos     (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
11249 #define CTIMER_INTCLR_CTMRB4C1INT_Msk     (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
11250 #define CTIMER_INTCLR_CTMRA4C1INT_Pos     (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
11251 #define CTIMER_INTCLR_CTMRA4C1INT_Msk     (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
11252 #define CTIMER_INTCLR_CTMRB3C1INT_Pos     (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
11253 #define CTIMER_INTCLR_CTMRB3C1INT_Msk     (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
11254 #define CTIMER_INTCLR_CTMRA3C1INT_Pos     (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
11255 #define CTIMER_INTCLR_CTMRA3C1INT_Msk     (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
11256 #define CTIMER_INTCLR_CTMRB2C1INT_Pos     (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
11257 #define CTIMER_INTCLR_CTMRB2C1INT_Msk     (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
11258 #define CTIMER_INTCLR_CTMRA2C1INT_Pos     (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
11259 #define CTIMER_INTCLR_CTMRA2C1INT_Msk     (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
11260 #define CTIMER_INTCLR_CTMRB1C1INT_Pos     (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
11261 #define CTIMER_INTCLR_CTMRB1C1INT_Msk     (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
11262 #define CTIMER_INTCLR_CTMRA1C1INT_Pos     (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
11263 #define CTIMER_INTCLR_CTMRA1C1INT_Msk     (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
11264 #define CTIMER_INTCLR_CTMRB0C1INT_Pos     (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
11265 #define CTIMER_INTCLR_CTMRB0C1INT_Msk     (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
11266 #define CTIMER_INTCLR_CTMRA0C1INT_Pos     (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
11267 #define CTIMER_INTCLR_CTMRA0C1INT_Msk     (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
11268 #define CTIMER_INTCLR_CTMRB7C0INT_Pos     (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
11269 #define CTIMER_INTCLR_CTMRB7C0INT_Msk     (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
11270 #define CTIMER_INTCLR_CTMRA7C0INT_Pos     (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
11271 #define CTIMER_INTCLR_CTMRA7C0INT_Msk     (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
11272 #define CTIMER_INTCLR_CTMRB6C0INT_Pos     (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
11273 #define CTIMER_INTCLR_CTMRB6C0INT_Msk     (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
11274 #define CTIMER_INTCLR_CTMRA6C0INT_Pos     (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
11275 #define CTIMER_INTCLR_CTMRA6C0INT_Msk     (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
11276 #define CTIMER_INTCLR_CTMRB5C0INT_Pos     (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
11277 #define CTIMER_INTCLR_CTMRB5C0INT_Msk     (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
11278 #define CTIMER_INTCLR_CTMRA5C0INT_Pos     (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
11279 #define CTIMER_INTCLR_CTMRA5C0INT_Msk     (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
11280 #define CTIMER_INTCLR_CTMRB4C0INT_Pos     (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
11281 #define CTIMER_INTCLR_CTMRB4C0INT_Msk     (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
11282 #define CTIMER_INTCLR_CTMRA4C0INT_Pos     (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
11283 #define CTIMER_INTCLR_CTMRA4C0INT_Msk     (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
11284 #define CTIMER_INTCLR_CTMRB3C0INT_Pos     (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
11285 #define CTIMER_INTCLR_CTMRB3C0INT_Msk     (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
11286 #define CTIMER_INTCLR_CTMRA3C0INT_Pos     (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
11287 #define CTIMER_INTCLR_CTMRA3C0INT_Msk     (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
11288 #define CTIMER_INTCLR_CTMRB2C0INT_Pos     (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
11289 #define CTIMER_INTCLR_CTMRB2C0INT_Msk     (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
11290 #define CTIMER_INTCLR_CTMRA2C0INT_Pos     (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
11291 #define CTIMER_INTCLR_CTMRA2C0INT_Msk     (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
11292 #define CTIMER_INTCLR_CTMRB1C0INT_Pos     (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
11293 #define CTIMER_INTCLR_CTMRB1C0INT_Msk     (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
11294 #define CTIMER_INTCLR_CTMRA1C0INT_Pos     (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
11295 #define CTIMER_INTCLR_CTMRA1C0INT_Msk     (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
11296 #define CTIMER_INTCLR_CTMRB0C0INT_Pos     (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
11297 #define CTIMER_INTCLR_CTMRB0C0INT_Msk     (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
11298 #define CTIMER_INTCLR_CTMRA0C0INT_Pos     (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
11299 #define CTIMER_INTCLR_CTMRA0C0INT_Msk     (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
11300 /* ========================================================  INTSET  ========================================================= */
11301 #define CTIMER_INTSET_CTMRB7C1INT_Pos     (31UL)                    /*!< CTMRB7C1INT (Bit 31)                                  */
11302 #define CTIMER_INTSET_CTMRB7C1INT_Msk     (0x80000000UL)            /*!< CTMRB7C1INT (Bitfield-Mask: 0x01)                     */
11303 #define CTIMER_INTSET_CTMRA7C1INT_Pos     (30UL)                    /*!< CTMRA7C1INT (Bit 30)                                  */
11304 #define CTIMER_INTSET_CTMRA7C1INT_Msk     (0x40000000UL)            /*!< CTMRA7C1INT (Bitfield-Mask: 0x01)                     */
11305 #define CTIMER_INTSET_CTMRB6C1INT_Pos     (29UL)                    /*!< CTMRB6C1INT (Bit 29)                                  */
11306 #define CTIMER_INTSET_CTMRB6C1INT_Msk     (0x20000000UL)            /*!< CTMRB6C1INT (Bitfield-Mask: 0x01)                     */
11307 #define CTIMER_INTSET_CTMRA6C1INT_Pos     (28UL)                    /*!< CTMRA6C1INT (Bit 28)                                  */
11308 #define CTIMER_INTSET_CTMRA6C1INT_Msk     (0x10000000UL)            /*!< CTMRA6C1INT (Bitfield-Mask: 0x01)                     */
11309 #define CTIMER_INTSET_CTMRB5C1INT_Pos     (27UL)                    /*!< CTMRB5C1INT (Bit 27)                                  */
11310 #define CTIMER_INTSET_CTMRB5C1INT_Msk     (0x8000000UL)             /*!< CTMRB5C1INT (Bitfield-Mask: 0x01)                     */
11311 #define CTIMER_INTSET_CTMRA5C1INT_Pos     (26UL)                    /*!< CTMRA5C1INT (Bit 26)                                  */
11312 #define CTIMER_INTSET_CTMRA5C1INT_Msk     (0x4000000UL)             /*!< CTMRA5C1INT (Bitfield-Mask: 0x01)                     */
11313 #define CTIMER_INTSET_CTMRB4C1INT_Pos     (25UL)                    /*!< CTMRB4C1INT (Bit 25)                                  */
11314 #define CTIMER_INTSET_CTMRB4C1INT_Msk     (0x2000000UL)             /*!< CTMRB4C1INT (Bitfield-Mask: 0x01)                     */
11315 #define CTIMER_INTSET_CTMRA4C1INT_Pos     (24UL)                    /*!< CTMRA4C1INT (Bit 24)                                  */
11316 #define CTIMER_INTSET_CTMRA4C1INT_Msk     (0x1000000UL)             /*!< CTMRA4C1INT (Bitfield-Mask: 0x01)                     */
11317 #define CTIMER_INTSET_CTMRB3C1INT_Pos     (23UL)                    /*!< CTMRB3C1INT (Bit 23)                                  */
11318 #define CTIMER_INTSET_CTMRB3C1INT_Msk     (0x800000UL)              /*!< CTMRB3C1INT (Bitfield-Mask: 0x01)                     */
11319 #define CTIMER_INTSET_CTMRA3C1INT_Pos     (22UL)                    /*!< CTMRA3C1INT (Bit 22)                                  */
11320 #define CTIMER_INTSET_CTMRA3C1INT_Msk     (0x400000UL)              /*!< CTMRA3C1INT (Bitfield-Mask: 0x01)                     */
11321 #define CTIMER_INTSET_CTMRB2C1INT_Pos     (21UL)                    /*!< CTMRB2C1INT (Bit 21)                                  */
11322 #define CTIMER_INTSET_CTMRB2C1INT_Msk     (0x200000UL)              /*!< CTMRB2C1INT (Bitfield-Mask: 0x01)                     */
11323 #define CTIMER_INTSET_CTMRA2C1INT_Pos     (20UL)                    /*!< CTMRA2C1INT (Bit 20)                                  */
11324 #define CTIMER_INTSET_CTMRA2C1INT_Msk     (0x100000UL)              /*!< CTMRA2C1INT (Bitfield-Mask: 0x01)                     */
11325 #define CTIMER_INTSET_CTMRB1C1INT_Pos     (19UL)                    /*!< CTMRB1C1INT (Bit 19)                                  */
11326 #define CTIMER_INTSET_CTMRB1C1INT_Msk     (0x80000UL)               /*!< CTMRB1C1INT (Bitfield-Mask: 0x01)                     */
11327 #define CTIMER_INTSET_CTMRA1C1INT_Pos     (18UL)                    /*!< CTMRA1C1INT (Bit 18)                                  */
11328 #define CTIMER_INTSET_CTMRA1C1INT_Msk     (0x40000UL)               /*!< CTMRA1C1INT (Bitfield-Mask: 0x01)                     */
11329 #define CTIMER_INTSET_CTMRB0C1INT_Pos     (17UL)                    /*!< CTMRB0C1INT (Bit 17)                                  */
11330 #define CTIMER_INTSET_CTMRB0C1INT_Msk     (0x20000UL)               /*!< CTMRB0C1INT (Bitfield-Mask: 0x01)                     */
11331 #define CTIMER_INTSET_CTMRA0C1INT_Pos     (16UL)                    /*!< CTMRA0C1INT (Bit 16)                                  */
11332 #define CTIMER_INTSET_CTMRA0C1INT_Msk     (0x10000UL)               /*!< CTMRA0C1INT (Bitfield-Mask: 0x01)                     */
11333 #define CTIMER_INTSET_CTMRB7C0INT_Pos     (15UL)                    /*!< CTMRB7C0INT (Bit 15)                                  */
11334 #define CTIMER_INTSET_CTMRB7C0INT_Msk     (0x8000UL)                /*!< CTMRB7C0INT (Bitfield-Mask: 0x01)                     */
11335 #define CTIMER_INTSET_CTMRA7C0INT_Pos     (14UL)                    /*!< CTMRA7C0INT (Bit 14)                                  */
11336 #define CTIMER_INTSET_CTMRA7C0INT_Msk     (0x4000UL)                /*!< CTMRA7C0INT (Bitfield-Mask: 0x01)                     */
11337 #define CTIMER_INTSET_CTMRB6C0INT_Pos     (13UL)                    /*!< CTMRB6C0INT (Bit 13)                                  */
11338 #define CTIMER_INTSET_CTMRB6C0INT_Msk     (0x2000UL)                /*!< CTMRB6C0INT (Bitfield-Mask: 0x01)                     */
11339 #define CTIMER_INTSET_CTMRA6C0INT_Pos     (12UL)                    /*!< CTMRA6C0INT (Bit 12)                                  */
11340 #define CTIMER_INTSET_CTMRA6C0INT_Msk     (0x1000UL)                /*!< CTMRA6C0INT (Bitfield-Mask: 0x01)                     */
11341 #define CTIMER_INTSET_CTMRB5C0INT_Pos     (11UL)                    /*!< CTMRB5C0INT (Bit 11)                                  */
11342 #define CTIMER_INTSET_CTMRB5C0INT_Msk     (0x800UL)                 /*!< CTMRB5C0INT (Bitfield-Mask: 0x01)                     */
11343 #define CTIMER_INTSET_CTMRA5C0INT_Pos     (10UL)                    /*!< CTMRA5C0INT (Bit 10)                                  */
11344 #define CTIMER_INTSET_CTMRA5C0INT_Msk     (0x400UL)                 /*!< CTMRA5C0INT (Bitfield-Mask: 0x01)                     */
11345 #define CTIMER_INTSET_CTMRB4C0INT_Pos     (9UL)                     /*!< CTMRB4C0INT (Bit 9)                                   */
11346 #define CTIMER_INTSET_CTMRB4C0INT_Msk     (0x200UL)                 /*!< CTMRB4C0INT (Bitfield-Mask: 0x01)                     */
11347 #define CTIMER_INTSET_CTMRA4C0INT_Pos     (8UL)                     /*!< CTMRA4C0INT (Bit 8)                                   */
11348 #define CTIMER_INTSET_CTMRA4C0INT_Msk     (0x100UL)                 /*!< CTMRA4C0INT (Bitfield-Mask: 0x01)                     */
11349 #define CTIMER_INTSET_CTMRB3C0INT_Pos     (7UL)                     /*!< CTMRB3C0INT (Bit 7)                                   */
11350 #define CTIMER_INTSET_CTMRB3C0INT_Msk     (0x80UL)                  /*!< CTMRB3C0INT (Bitfield-Mask: 0x01)                     */
11351 #define CTIMER_INTSET_CTMRA3C0INT_Pos     (6UL)                     /*!< CTMRA3C0INT (Bit 6)                                   */
11352 #define CTIMER_INTSET_CTMRA3C0INT_Msk     (0x40UL)                  /*!< CTMRA3C0INT (Bitfield-Mask: 0x01)                     */
11353 #define CTIMER_INTSET_CTMRB2C0INT_Pos     (5UL)                     /*!< CTMRB2C0INT (Bit 5)                                   */
11354 #define CTIMER_INTSET_CTMRB2C0INT_Msk     (0x20UL)                  /*!< CTMRB2C0INT (Bitfield-Mask: 0x01)                     */
11355 #define CTIMER_INTSET_CTMRA2C0INT_Pos     (4UL)                     /*!< CTMRA2C0INT (Bit 4)                                   */
11356 #define CTIMER_INTSET_CTMRA2C0INT_Msk     (0x10UL)                  /*!< CTMRA2C0INT (Bitfield-Mask: 0x01)                     */
11357 #define CTIMER_INTSET_CTMRB1C0INT_Pos     (3UL)                     /*!< CTMRB1C0INT (Bit 3)                                   */
11358 #define CTIMER_INTSET_CTMRB1C0INT_Msk     (0x8UL)                   /*!< CTMRB1C0INT (Bitfield-Mask: 0x01)                     */
11359 #define CTIMER_INTSET_CTMRA1C0INT_Pos     (2UL)                     /*!< CTMRA1C0INT (Bit 2)                                   */
11360 #define CTIMER_INTSET_CTMRA1C0INT_Msk     (0x4UL)                   /*!< CTMRA1C0INT (Bitfield-Mask: 0x01)                     */
11361 #define CTIMER_INTSET_CTMRB0C0INT_Pos     (1UL)                     /*!< CTMRB0C0INT (Bit 1)                                   */
11362 #define CTIMER_INTSET_CTMRB0C0INT_Msk     (0x2UL)                   /*!< CTMRB0C0INT (Bitfield-Mask: 0x01)                     */
11363 #define CTIMER_INTSET_CTMRA0C0INT_Pos     (0UL)                     /*!< CTMRA0C0INT (Bit 0)                                   */
11364 #define CTIMER_INTSET_CTMRA0C0INT_Msk     (0x1UL)                   /*!< CTMRA0C0INT (Bitfield-Mask: 0x01)                     */
11365 /* =======================================================  STMINTEN  ======================================================== */
11366 #define CTIMER_STMINTEN_CAPTURED_Pos      (12UL)                    /*!< CAPTURED (Bit 12)                                     */
11367 #define CTIMER_STMINTEN_CAPTURED_Msk      (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
11368 #define CTIMER_STMINTEN_CAPTUREC_Pos      (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
11369 #define CTIMER_STMINTEN_CAPTUREC_Msk      (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
11370 #define CTIMER_STMINTEN_CAPTUREB_Pos      (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
11371 #define CTIMER_STMINTEN_CAPTUREB_Msk      (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
11372 #define CTIMER_STMINTEN_CAPTUREA_Pos      (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
11373 #define CTIMER_STMINTEN_CAPTUREA_Msk      (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
11374 #define CTIMER_STMINTEN_OVERFLOW_Pos      (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
11375 #define CTIMER_STMINTEN_OVERFLOW_Msk      (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
11376 #define CTIMER_STMINTEN_COMPAREH_Pos      (7UL)                     /*!< COMPAREH (Bit 7)                                      */
11377 #define CTIMER_STMINTEN_COMPAREH_Msk      (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
11378 #define CTIMER_STMINTEN_COMPAREG_Pos      (6UL)                     /*!< COMPAREG (Bit 6)                                      */
11379 #define CTIMER_STMINTEN_COMPAREG_Msk      (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
11380 #define CTIMER_STMINTEN_COMPAREF_Pos      (5UL)                     /*!< COMPAREF (Bit 5)                                      */
11381 #define CTIMER_STMINTEN_COMPAREF_Msk      (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
11382 #define CTIMER_STMINTEN_COMPAREE_Pos      (4UL)                     /*!< COMPAREE (Bit 4)                                      */
11383 #define CTIMER_STMINTEN_COMPAREE_Msk      (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
11384 #define CTIMER_STMINTEN_COMPARED_Pos      (3UL)                     /*!< COMPARED (Bit 3)                                      */
11385 #define CTIMER_STMINTEN_COMPARED_Msk      (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
11386 #define CTIMER_STMINTEN_COMPAREC_Pos      (2UL)                     /*!< COMPAREC (Bit 2)                                      */
11387 #define CTIMER_STMINTEN_COMPAREC_Msk      (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
11388 #define CTIMER_STMINTEN_COMPAREB_Pos      (1UL)                     /*!< COMPAREB (Bit 1)                                      */
11389 #define CTIMER_STMINTEN_COMPAREB_Msk      (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
11390 #define CTIMER_STMINTEN_COMPAREA_Pos      (0UL)                     /*!< COMPAREA (Bit 0)                                      */
11391 #define CTIMER_STMINTEN_COMPAREA_Msk      (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
11392 /* ======================================================  STMINTSTAT  ======================================================= */
11393 #define CTIMER_STMINTSTAT_CAPTURED_Pos    (12UL)                    /*!< CAPTURED (Bit 12)                                     */
11394 #define CTIMER_STMINTSTAT_CAPTURED_Msk    (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
11395 #define CTIMER_STMINTSTAT_CAPTUREC_Pos    (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
11396 #define CTIMER_STMINTSTAT_CAPTUREC_Msk    (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
11397 #define CTIMER_STMINTSTAT_CAPTUREB_Pos    (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
11398 #define CTIMER_STMINTSTAT_CAPTUREB_Msk    (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
11399 #define CTIMER_STMINTSTAT_CAPTUREA_Pos    (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
11400 #define CTIMER_STMINTSTAT_CAPTUREA_Msk    (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
11401 #define CTIMER_STMINTSTAT_OVERFLOW_Pos    (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
11402 #define CTIMER_STMINTSTAT_OVERFLOW_Msk    (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
11403 #define CTIMER_STMINTSTAT_COMPAREH_Pos    (7UL)                     /*!< COMPAREH (Bit 7)                                      */
11404 #define CTIMER_STMINTSTAT_COMPAREH_Msk    (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
11405 #define CTIMER_STMINTSTAT_COMPAREG_Pos    (6UL)                     /*!< COMPAREG (Bit 6)                                      */
11406 #define CTIMER_STMINTSTAT_COMPAREG_Msk    (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
11407 #define CTIMER_STMINTSTAT_COMPAREF_Pos    (5UL)                     /*!< COMPAREF (Bit 5)                                      */
11408 #define CTIMER_STMINTSTAT_COMPAREF_Msk    (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
11409 #define CTIMER_STMINTSTAT_COMPAREE_Pos    (4UL)                     /*!< COMPAREE (Bit 4)                                      */
11410 #define CTIMER_STMINTSTAT_COMPAREE_Msk    (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
11411 #define CTIMER_STMINTSTAT_COMPARED_Pos    (3UL)                     /*!< COMPARED (Bit 3)                                      */
11412 #define CTIMER_STMINTSTAT_COMPARED_Msk    (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
11413 #define CTIMER_STMINTSTAT_COMPAREC_Pos    (2UL)                     /*!< COMPAREC (Bit 2)                                      */
11414 #define CTIMER_STMINTSTAT_COMPAREC_Msk    (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
11415 #define CTIMER_STMINTSTAT_COMPAREB_Pos    (1UL)                     /*!< COMPAREB (Bit 1)                                      */
11416 #define CTIMER_STMINTSTAT_COMPAREB_Msk    (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
11417 #define CTIMER_STMINTSTAT_COMPAREA_Pos    (0UL)                     /*!< COMPAREA (Bit 0)                                      */
11418 #define CTIMER_STMINTSTAT_COMPAREA_Msk    (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
11419 /* =======================================================  STMINTCLR  ======================================================= */
11420 #define CTIMER_STMINTCLR_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
11421 #define CTIMER_STMINTCLR_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
11422 #define CTIMER_STMINTCLR_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
11423 #define CTIMER_STMINTCLR_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
11424 #define CTIMER_STMINTCLR_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
11425 #define CTIMER_STMINTCLR_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
11426 #define CTIMER_STMINTCLR_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
11427 #define CTIMER_STMINTCLR_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
11428 #define CTIMER_STMINTCLR_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
11429 #define CTIMER_STMINTCLR_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
11430 #define CTIMER_STMINTCLR_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
11431 #define CTIMER_STMINTCLR_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
11432 #define CTIMER_STMINTCLR_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
11433 #define CTIMER_STMINTCLR_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
11434 #define CTIMER_STMINTCLR_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
11435 #define CTIMER_STMINTCLR_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
11436 #define CTIMER_STMINTCLR_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
11437 #define CTIMER_STMINTCLR_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
11438 #define CTIMER_STMINTCLR_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
11439 #define CTIMER_STMINTCLR_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
11440 #define CTIMER_STMINTCLR_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
11441 #define CTIMER_STMINTCLR_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
11442 #define CTIMER_STMINTCLR_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
11443 #define CTIMER_STMINTCLR_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
11444 #define CTIMER_STMINTCLR_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
11445 #define CTIMER_STMINTCLR_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
11446 /* =======================================================  STMINTSET  ======================================================= */
11447 #define CTIMER_STMINTSET_CAPTURED_Pos     (12UL)                    /*!< CAPTURED (Bit 12)                                     */
11448 #define CTIMER_STMINTSET_CAPTURED_Msk     (0x1000UL)                /*!< CAPTURED (Bitfield-Mask: 0x01)                        */
11449 #define CTIMER_STMINTSET_CAPTUREC_Pos     (11UL)                    /*!< CAPTUREC (Bit 11)                                     */
11450 #define CTIMER_STMINTSET_CAPTUREC_Msk     (0x800UL)                 /*!< CAPTUREC (Bitfield-Mask: 0x01)                        */
11451 #define CTIMER_STMINTSET_CAPTUREB_Pos     (10UL)                    /*!< CAPTUREB (Bit 10)                                     */
11452 #define CTIMER_STMINTSET_CAPTUREB_Msk     (0x400UL)                 /*!< CAPTUREB (Bitfield-Mask: 0x01)                        */
11453 #define CTIMER_STMINTSET_CAPTUREA_Pos     (9UL)                     /*!< CAPTUREA (Bit 9)                                      */
11454 #define CTIMER_STMINTSET_CAPTUREA_Msk     (0x200UL)                 /*!< CAPTUREA (Bitfield-Mask: 0x01)                        */
11455 #define CTIMER_STMINTSET_OVERFLOW_Pos     (8UL)                     /*!< OVERFLOW (Bit 8)                                      */
11456 #define CTIMER_STMINTSET_OVERFLOW_Msk     (0x100UL)                 /*!< OVERFLOW (Bitfield-Mask: 0x01)                        */
11457 #define CTIMER_STMINTSET_COMPAREH_Pos     (7UL)                     /*!< COMPAREH (Bit 7)                                      */
11458 #define CTIMER_STMINTSET_COMPAREH_Msk     (0x80UL)                  /*!< COMPAREH (Bitfield-Mask: 0x01)                        */
11459 #define CTIMER_STMINTSET_COMPAREG_Pos     (6UL)                     /*!< COMPAREG (Bit 6)                                      */
11460 #define CTIMER_STMINTSET_COMPAREG_Msk     (0x40UL)                  /*!< COMPAREG (Bitfield-Mask: 0x01)                        */
11461 #define CTIMER_STMINTSET_COMPAREF_Pos     (5UL)                     /*!< COMPAREF (Bit 5)                                      */
11462 #define CTIMER_STMINTSET_COMPAREF_Msk     (0x20UL)                  /*!< COMPAREF (Bitfield-Mask: 0x01)                        */
11463 #define CTIMER_STMINTSET_COMPAREE_Pos     (4UL)                     /*!< COMPAREE (Bit 4)                                      */
11464 #define CTIMER_STMINTSET_COMPAREE_Msk     (0x10UL)                  /*!< COMPAREE (Bitfield-Mask: 0x01)                        */
11465 #define CTIMER_STMINTSET_COMPARED_Pos     (3UL)                     /*!< COMPARED (Bit 3)                                      */
11466 #define CTIMER_STMINTSET_COMPARED_Msk     (0x8UL)                   /*!< COMPARED (Bitfield-Mask: 0x01)                        */
11467 #define CTIMER_STMINTSET_COMPAREC_Pos     (2UL)                     /*!< COMPAREC (Bit 2)                                      */
11468 #define CTIMER_STMINTSET_COMPAREC_Msk     (0x4UL)                   /*!< COMPAREC (Bitfield-Mask: 0x01)                        */
11469 #define CTIMER_STMINTSET_COMPAREB_Pos     (1UL)                     /*!< COMPAREB (Bit 1)                                      */
11470 #define CTIMER_STMINTSET_COMPAREB_Msk     (0x2UL)                   /*!< COMPAREB (Bitfield-Mask: 0x01)                        */
11471 #define CTIMER_STMINTSET_COMPAREA_Pos     (0UL)                     /*!< COMPAREA (Bit 0)                                      */
11472 #define CTIMER_STMINTSET_COMPAREA_Msk     (0x1UL)                   /*!< COMPAREA (Bitfield-Mask: 0x01)                        */
11473 
11474 
11475 /* =========================================================================================================================== */
11476 /* ================                                           GPIO                                            ================ */
11477 /* =========================================================================================================================== */
11478 
11479 /* ========================================================  PADREGA  ======================================================== */
11480 #define GPIO_PADREGA_PAD3PWRUP_Pos        (30UL)                    /*!< PAD3PWRUP (Bit 30)                                    */
11481 #define GPIO_PADREGA_PAD3PWRUP_Msk        (0x40000000UL)            /*!< PAD3PWRUP (Bitfield-Mask: 0x01)                       */
11482 #define GPIO_PADREGA_PAD3FNCSEL_Pos       (27UL)                    /*!< PAD3FNCSEL (Bit 27)                                   */
11483 #define GPIO_PADREGA_PAD3FNCSEL_Msk       (0x38000000UL)            /*!< PAD3FNCSEL (Bitfield-Mask: 0x07)                      */
11484 #define GPIO_PADREGA_PAD3STRNG_Pos        (26UL)                    /*!< PAD3STRNG (Bit 26)                                    */
11485 #define GPIO_PADREGA_PAD3STRNG_Msk        (0x4000000UL)             /*!< PAD3STRNG (Bitfield-Mask: 0x01)                       */
11486 #define GPIO_PADREGA_PAD3INPEN_Pos        (25UL)                    /*!< PAD3INPEN (Bit 25)                                    */
11487 #define GPIO_PADREGA_PAD3INPEN_Msk        (0x2000000UL)             /*!< PAD3INPEN (Bitfield-Mask: 0x01)                       */
11488 #define GPIO_PADREGA_PAD3PULL_Pos         (24UL)                    /*!< PAD3PULL (Bit 24)                                     */
11489 #define GPIO_PADREGA_PAD3PULL_Msk         (0x1000000UL)             /*!< PAD3PULL (Bitfield-Mask: 0x01)                        */
11490 #define GPIO_PADREGA_PAD2FNCSEL_Pos       (19UL)                    /*!< PAD2FNCSEL (Bit 19)                                   */
11491 #define GPIO_PADREGA_PAD2FNCSEL_Msk       (0x380000UL)              /*!< PAD2FNCSEL (Bitfield-Mask: 0x07)                      */
11492 #define GPIO_PADREGA_PAD2STRNG_Pos        (18UL)                    /*!< PAD2STRNG (Bit 18)                                    */
11493 #define GPIO_PADREGA_PAD2STRNG_Msk        (0x40000UL)               /*!< PAD2STRNG (Bitfield-Mask: 0x01)                       */
11494 #define GPIO_PADREGA_PAD2INPEN_Pos        (17UL)                    /*!< PAD2INPEN (Bit 17)                                    */
11495 #define GPIO_PADREGA_PAD2INPEN_Msk        (0x20000UL)               /*!< PAD2INPEN (Bitfield-Mask: 0x01)                       */
11496 #define GPIO_PADREGA_PAD2PULL_Pos         (16UL)                    /*!< PAD2PULL (Bit 16)                                     */
11497 #define GPIO_PADREGA_PAD2PULL_Msk         (0x10000UL)               /*!< PAD2PULL (Bitfield-Mask: 0x01)                        */
11498 #define GPIO_PADREGA_PAD1RSEL_Pos         (14UL)                    /*!< PAD1RSEL (Bit 14)                                     */
11499 #define GPIO_PADREGA_PAD1RSEL_Msk         (0xc000UL)                /*!< PAD1RSEL (Bitfield-Mask: 0x03)                        */
11500 #define GPIO_PADREGA_PAD1FNCSEL_Pos       (11UL)                    /*!< PAD1FNCSEL (Bit 11)                                   */
11501 #define GPIO_PADREGA_PAD1FNCSEL_Msk       (0x3800UL)                /*!< PAD1FNCSEL (Bitfield-Mask: 0x07)                      */
11502 #define GPIO_PADREGA_PAD1STRNG_Pos        (10UL)                    /*!< PAD1STRNG (Bit 10)                                    */
11503 #define GPIO_PADREGA_PAD1STRNG_Msk        (0x400UL)                 /*!< PAD1STRNG (Bitfield-Mask: 0x01)                       */
11504 #define GPIO_PADREGA_PAD1INPEN_Pos        (9UL)                     /*!< PAD1INPEN (Bit 9)                                     */
11505 #define GPIO_PADREGA_PAD1INPEN_Msk        (0x200UL)                 /*!< PAD1INPEN (Bitfield-Mask: 0x01)                       */
11506 #define GPIO_PADREGA_PAD1PULL_Pos         (8UL)                     /*!< PAD1PULL (Bit 8)                                      */
11507 #define GPIO_PADREGA_PAD1PULL_Msk         (0x100UL)                 /*!< PAD1PULL (Bitfield-Mask: 0x01)                        */
11508 #define GPIO_PADREGA_PAD0RSEL_Pos         (6UL)                     /*!< PAD0RSEL (Bit 6)                                      */
11509 #define GPIO_PADREGA_PAD0RSEL_Msk         (0xc0UL)                  /*!< PAD0RSEL (Bitfield-Mask: 0x03)                        */
11510 #define GPIO_PADREGA_PAD0FNCSEL_Pos       (3UL)                     /*!< PAD0FNCSEL (Bit 3)                                    */
11511 #define GPIO_PADREGA_PAD0FNCSEL_Msk       (0x38UL)                  /*!< PAD0FNCSEL (Bitfield-Mask: 0x07)                      */
11512 #define GPIO_PADREGA_PAD0STRNG_Pos        (2UL)                     /*!< PAD0STRNG (Bit 2)                                     */
11513 #define GPIO_PADREGA_PAD0STRNG_Msk        (0x4UL)                   /*!< PAD0STRNG (Bitfield-Mask: 0x01)                       */
11514 #define GPIO_PADREGA_PAD0INPEN_Pos        (1UL)                     /*!< PAD0INPEN (Bit 1)                                     */
11515 #define GPIO_PADREGA_PAD0INPEN_Msk        (0x2UL)                   /*!< PAD0INPEN (Bitfield-Mask: 0x01)                       */
11516 #define GPIO_PADREGA_PAD0PULL_Pos         (0UL)                     /*!< PAD0PULL (Bit 0)                                      */
11517 #define GPIO_PADREGA_PAD0PULL_Msk         (0x1UL)                   /*!< PAD0PULL (Bitfield-Mask: 0x01)                        */
11518 /* ========================================================  PADREGB  ======================================================== */
11519 #define GPIO_PADREGB_PAD7FNCSEL_Pos       (27UL)                    /*!< PAD7FNCSEL (Bit 27)                                   */
11520 #define GPIO_PADREGB_PAD7FNCSEL_Msk       (0x38000000UL)            /*!< PAD7FNCSEL (Bitfield-Mask: 0x07)                      */
11521 #define GPIO_PADREGB_PAD7STRNG_Pos        (26UL)                    /*!< PAD7STRNG (Bit 26)                                    */
11522 #define GPIO_PADREGB_PAD7STRNG_Msk        (0x4000000UL)             /*!< PAD7STRNG (Bitfield-Mask: 0x01)                       */
11523 #define GPIO_PADREGB_PAD7INPEN_Pos        (25UL)                    /*!< PAD7INPEN (Bit 25)                                    */
11524 #define GPIO_PADREGB_PAD7INPEN_Msk        (0x2000000UL)             /*!< PAD7INPEN (Bitfield-Mask: 0x01)                       */
11525 #define GPIO_PADREGB_PAD7PULL_Pos         (24UL)                    /*!< PAD7PULL (Bit 24)                                     */
11526 #define GPIO_PADREGB_PAD7PULL_Msk         (0x1000000UL)             /*!< PAD7PULL (Bitfield-Mask: 0x01)                        */
11527 #define GPIO_PADREGB_PAD6RSEL_Pos         (22UL)                    /*!< PAD6RSEL (Bit 22)                                     */
11528 #define GPIO_PADREGB_PAD6RSEL_Msk         (0xc00000UL)              /*!< PAD6RSEL (Bitfield-Mask: 0x03)                        */
11529 #define GPIO_PADREGB_PAD6FNCSEL_Pos       (19UL)                    /*!< PAD6FNCSEL (Bit 19)                                   */
11530 #define GPIO_PADREGB_PAD6FNCSEL_Msk       (0x380000UL)              /*!< PAD6FNCSEL (Bitfield-Mask: 0x07)                      */
11531 #define GPIO_PADREGB_PAD6STRNG_Pos        (18UL)                    /*!< PAD6STRNG (Bit 18)                                    */
11532 #define GPIO_PADREGB_PAD6STRNG_Msk        (0x40000UL)               /*!< PAD6STRNG (Bitfield-Mask: 0x01)                       */
11533 #define GPIO_PADREGB_PAD6INPEN_Pos        (17UL)                    /*!< PAD6INPEN (Bit 17)                                    */
11534 #define GPIO_PADREGB_PAD6INPEN_Msk        (0x20000UL)               /*!< PAD6INPEN (Bitfield-Mask: 0x01)                       */
11535 #define GPIO_PADREGB_PAD6PULL_Pos         (16UL)                    /*!< PAD6PULL (Bit 16)                                     */
11536 #define GPIO_PADREGB_PAD6PULL_Msk         (0x10000UL)               /*!< PAD6PULL (Bitfield-Mask: 0x01)                        */
11537 #define GPIO_PADREGB_PAD5RSEL_Pos         (14UL)                    /*!< PAD5RSEL (Bit 14)                                     */
11538 #define GPIO_PADREGB_PAD5RSEL_Msk         (0xc000UL)                /*!< PAD5RSEL (Bitfield-Mask: 0x03)                        */
11539 #define GPIO_PADREGB_PAD5FNCSEL_Pos       (11UL)                    /*!< PAD5FNCSEL (Bit 11)                                   */
11540 #define GPIO_PADREGB_PAD5FNCSEL_Msk       (0x3800UL)                /*!< PAD5FNCSEL (Bitfield-Mask: 0x07)                      */
11541 #define GPIO_PADREGB_PAD5STRNG_Pos        (10UL)                    /*!< PAD5STRNG (Bit 10)                                    */
11542 #define GPIO_PADREGB_PAD5STRNG_Msk        (0x400UL)                 /*!< PAD5STRNG (Bitfield-Mask: 0x01)                       */
11543 #define GPIO_PADREGB_PAD5INPEN_Pos        (9UL)                     /*!< PAD5INPEN (Bit 9)                                     */
11544 #define GPIO_PADREGB_PAD5INPEN_Msk        (0x200UL)                 /*!< PAD5INPEN (Bitfield-Mask: 0x01)                       */
11545 #define GPIO_PADREGB_PAD5PULL_Pos         (8UL)                     /*!< PAD5PULL (Bit 8)                                      */
11546 #define GPIO_PADREGB_PAD5PULL_Msk         (0x100UL)                 /*!< PAD5PULL (Bitfield-Mask: 0x01)                        */
11547 #define GPIO_PADREGB_PAD4FNCSEL_Pos       (3UL)                     /*!< PAD4FNCSEL (Bit 3)                                    */
11548 #define GPIO_PADREGB_PAD4FNCSEL_Msk       (0x38UL)                  /*!< PAD4FNCSEL (Bitfield-Mask: 0x07)                      */
11549 #define GPIO_PADREGB_PAD4STRNG_Pos        (2UL)                     /*!< PAD4STRNG (Bit 2)                                     */
11550 #define GPIO_PADREGB_PAD4STRNG_Msk        (0x4UL)                   /*!< PAD4STRNG (Bitfield-Mask: 0x01)                       */
11551 #define GPIO_PADREGB_PAD4INPEN_Pos        (1UL)                     /*!< PAD4INPEN (Bit 1)                                     */
11552 #define GPIO_PADREGB_PAD4INPEN_Msk        (0x2UL)                   /*!< PAD4INPEN (Bitfield-Mask: 0x01)                       */
11553 #define GPIO_PADREGB_PAD4PULL_Pos         (0UL)                     /*!< PAD4PULL (Bit 0)                                      */
11554 #define GPIO_PADREGB_PAD4PULL_Msk         (0x1UL)                   /*!< PAD4PULL (Bitfield-Mask: 0x01)                        */
11555 /* ========================================================  PADREGC  ======================================================== */
11556 #define GPIO_PADREGC_PAD11FNCSEL_Pos      (27UL)                    /*!< PAD11FNCSEL (Bit 27)                                  */
11557 #define GPIO_PADREGC_PAD11FNCSEL_Msk      (0x38000000UL)            /*!< PAD11FNCSEL (Bitfield-Mask: 0x07)                     */
11558 #define GPIO_PADREGC_PAD11STRNG_Pos       (26UL)                    /*!< PAD11STRNG (Bit 26)                                   */
11559 #define GPIO_PADREGC_PAD11STRNG_Msk       (0x4000000UL)             /*!< PAD11STRNG (Bitfield-Mask: 0x01)                      */
11560 #define GPIO_PADREGC_PAD11INPEN_Pos       (25UL)                    /*!< PAD11INPEN (Bit 25)                                   */
11561 #define GPIO_PADREGC_PAD11INPEN_Msk       (0x2000000UL)             /*!< PAD11INPEN (Bitfield-Mask: 0x01)                      */
11562 #define GPIO_PADREGC_PAD11PULL_Pos        (24UL)                    /*!< PAD11PULL (Bit 24)                                    */
11563 #define GPIO_PADREGC_PAD11PULL_Msk        (0x1000000UL)             /*!< PAD11PULL (Bitfield-Mask: 0x01)                       */
11564 #define GPIO_PADREGC_PAD10FNCSEL_Pos      (19UL)                    /*!< PAD10FNCSEL (Bit 19)                                  */
11565 #define GPIO_PADREGC_PAD10FNCSEL_Msk      (0x380000UL)              /*!< PAD10FNCSEL (Bitfield-Mask: 0x07)                     */
11566 #define GPIO_PADREGC_PAD10STRNG_Pos       (18UL)                    /*!< PAD10STRNG (Bit 18)                                   */
11567 #define GPIO_PADREGC_PAD10STRNG_Msk       (0x40000UL)               /*!< PAD10STRNG (Bitfield-Mask: 0x01)                      */
11568 #define GPIO_PADREGC_PAD10INPEN_Pos       (17UL)                    /*!< PAD10INPEN (Bit 17)                                   */
11569 #define GPIO_PADREGC_PAD10INPEN_Msk       (0x20000UL)               /*!< PAD10INPEN (Bitfield-Mask: 0x01)                      */
11570 #define GPIO_PADREGC_PAD10PULL_Pos        (16UL)                    /*!< PAD10PULL (Bit 16)                                    */
11571 #define GPIO_PADREGC_PAD10PULL_Msk        (0x10000UL)               /*!< PAD10PULL (Bitfield-Mask: 0x01)                       */
11572 #define GPIO_PADREGC_PAD9RSEL_Pos         (14UL)                    /*!< PAD9RSEL (Bit 14)                                     */
11573 #define GPIO_PADREGC_PAD9RSEL_Msk         (0xc000UL)                /*!< PAD9RSEL (Bitfield-Mask: 0x03)                        */
11574 #define GPIO_PADREGC_PAD9FNCSEL_Pos       (11UL)                    /*!< PAD9FNCSEL (Bit 11)                                   */
11575 #define GPIO_PADREGC_PAD9FNCSEL_Msk       (0x3800UL)                /*!< PAD9FNCSEL (Bitfield-Mask: 0x07)                      */
11576 #define GPIO_PADREGC_PAD9STRNG_Pos        (10UL)                    /*!< PAD9STRNG (Bit 10)                                    */
11577 #define GPIO_PADREGC_PAD9STRNG_Msk        (0x400UL)                 /*!< PAD9STRNG (Bitfield-Mask: 0x01)                       */
11578 #define GPIO_PADREGC_PAD9INPEN_Pos        (9UL)                     /*!< PAD9INPEN (Bit 9)                                     */
11579 #define GPIO_PADREGC_PAD9INPEN_Msk        (0x200UL)                 /*!< PAD9INPEN (Bitfield-Mask: 0x01)                       */
11580 #define GPIO_PADREGC_PAD9PULL_Pos         (8UL)                     /*!< PAD9PULL (Bit 8)                                      */
11581 #define GPIO_PADREGC_PAD9PULL_Msk         (0x100UL)                 /*!< PAD9PULL (Bitfield-Mask: 0x01)                        */
11582 #define GPIO_PADREGC_PAD8RSEL_Pos         (6UL)                     /*!< PAD8RSEL (Bit 6)                                      */
11583 #define GPIO_PADREGC_PAD8RSEL_Msk         (0xc0UL)                  /*!< PAD8RSEL (Bitfield-Mask: 0x03)                        */
11584 #define GPIO_PADREGC_PAD8FNCSEL_Pos       (3UL)                     /*!< PAD8FNCSEL (Bit 3)                                    */
11585 #define GPIO_PADREGC_PAD8FNCSEL_Msk       (0x38UL)                  /*!< PAD8FNCSEL (Bitfield-Mask: 0x07)                      */
11586 #define GPIO_PADREGC_PAD8STRNG_Pos        (2UL)                     /*!< PAD8STRNG (Bit 2)                                     */
11587 #define GPIO_PADREGC_PAD8STRNG_Msk        (0x4UL)                   /*!< PAD8STRNG (Bitfield-Mask: 0x01)                       */
11588 #define GPIO_PADREGC_PAD8INPEN_Pos        (1UL)                     /*!< PAD8INPEN (Bit 1)                                     */
11589 #define GPIO_PADREGC_PAD8INPEN_Msk        (0x2UL)                   /*!< PAD8INPEN (Bitfield-Mask: 0x01)                       */
11590 #define GPIO_PADREGC_PAD8PULL_Pos         (0UL)                     /*!< PAD8PULL (Bit 0)                                      */
11591 #define GPIO_PADREGC_PAD8PULL_Msk         (0x1UL)                   /*!< PAD8PULL (Bitfield-Mask: 0x01)                        */
11592 /* ========================================================  PADREGD  ======================================================== */
11593 #define GPIO_PADREGD_PAD15FNCSEL_Pos      (27UL)                    /*!< PAD15FNCSEL (Bit 27)                                  */
11594 #define GPIO_PADREGD_PAD15FNCSEL_Msk      (0x38000000UL)            /*!< PAD15FNCSEL (Bitfield-Mask: 0x07)                     */
11595 #define GPIO_PADREGD_PAD15STRNG_Pos       (26UL)                    /*!< PAD15STRNG (Bit 26)                                   */
11596 #define GPIO_PADREGD_PAD15STRNG_Msk       (0x4000000UL)             /*!< PAD15STRNG (Bitfield-Mask: 0x01)                      */
11597 #define GPIO_PADREGD_PAD15INPEN_Pos       (25UL)                    /*!< PAD15INPEN (Bit 25)                                   */
11598 #define GPIO_PADREGD_PAD15INPEN_Msk       (0x2000000UL)             /*!< PAD15INPEN (Bitfield-Mask: 0x01)                      */
11599 #define GPIO_PADREGD_PAD15PULL_Pos        (24UL)                    /*!< PAD15PULL (Bit 24)                                    */
11600 #define GPIO_PADREGD_PAD15PULL_Msk        (0x1000000UL)             /*!< PAD15PULL (Bitfield-Mask: 0x01)                       */
11601 #define GPIO_PADREGD_PAD14FNCSEL_Pos      (19UL)                    /*!< PAD14FNCSEL (Bit 19)                                  */
11602 #define GPIO_PADREGD_PAD14FNCSEL_Msk      (0x380000UL)              /*!< PAD14FNCSEL (Bitfield-Mask: 0x07)                     */
11603 #define GPIO_PADREGD_PAD14STRNG_Pos       (18UL)                    /*!< PAD14STRNG (Bit 18)                                   */
11604 #define GPIO_PADREGD_PAD14STRNG_Msk       (0x40000UL)               /*!< PAD14STRNG (Bitfield-Mask: 0x01)                      */
11605 #define GPIO_PADREGD_PAD14INPEN_Pos       (17UL)                    /*!< PAD14INPEN (Bit 17)                                   */
11606 #define GPIO_PADREGD_PAD14INPEN_Msk       (0x20000UL)               /*!< PAD14INPEN (Bitfield-Mask: 0x01)                      */
11607 #define GPIO_PADREGD_PAD14PULL_Pos        (16UL)                    /*!< PAD14PULL (Bit 16)                                    */
11608 #define GPIO_PADREGD_PAD14PULL_Msk        (0x10000UL)               /*!< PAD14PULL (Bitfield-Mask: 0x01)                       */
11609 #define GPIO_PADREGD_PAD13FNCSEL_Pos      (11UL)                    /*!< PAD13FNCSEL (Bit 11)                                  */
11610 #define GPIO_PADREGD_PAD13FNCSEL_Msk      (0x3800UL)                /*!< PAD13FNCSEL (Bitfield-Mask: 0x07)                     */
11611 #define GPIO_PADREGD_PAD13STRNG_Pos       (10UL)                    /*!< PAD13STRNG (Bit 10)                                   */
11612 #define GPIO_PADREGD_PAD13STRNG_Msk       (0x400UL)                 /*!< PAD13STRNG (Bitfield-Mask: 0x01)                      */
11613 #define GPIO_PADREGD_PAD13INPEN_Pos       (9UL)                     /*!< PAD13INPEN (Bit 9)                                    */
11614 #define GPIO_PADREGD_PAD13INPEN_Msk       (0x200UL)                 /*!< PAD13INPEN (Bitfield-Mask: 0x01)                      */
11615 #define GPIO_PADREGD_PAD13PULL_Pos        (8UL)                     /*!< PAD13PULL (Bit 8)                                     */
11616 #define GPIO_PADREGD_PAD13PULL_Msk        (0x100UL)                 /*!< PAD13PULL (Bitfield-Mask: 0x01)                       */
11617 #define GPIO_PADREGD_PAD12FNCSEL_Pos      (3UL)                     /*!< PAD12FNCSEL (Bit 3)                                   */
11618 #define GPIO_PADREGD_PAD12FNCSEL_Msk      (0x38UL)                  /*!< PAD12FNCSEL (Bitfield-Mask: 0x07)                     */
11619 #define GPIO_PADREGD_PAD12STRNG_Pos       (2UL)                     /*!< PAD12STRNG (Bit 2)                                    */
11620 #define GPIO_PADREGD_PAD12STRNG_Msk       (0x4UL)                   /*!< PAD12STRNG (Bitfield-Mask: 0x01)                      */
11621 #define GPIO_PADREGD_PAD12INPEN_Pos       (1UL)                     /*!< PAD12INPEN (Bit 1)                                    */
11622 #define GPIO_PADREGD_PAD12INPEN_Msk       (0x2UL)                   /*!< PAD12INPEN (Bitfield-Mask: 0x01)                      */
11623 #define GPIO_PADREGD_PAD12PULL_Pos        (0UL)                     /*!< PAD12PULL (Bit 0)                                     */
11624 #define GPIO_PADREGD_PAD12PULL_Msk        (0x1UL)                   /*!< PAD12PULL (Bitfield-Mask: 0x01)                       */
11625 /* ========================================================  PADREGE  ======================================================== */
11626 #define GPIO_PADREGE_PAD19FNCSEL_Pos      (27UL)                    /*!< PAD19FNCSEL (Bit 27)                                  */
11627 #define GPIO_PADREGE_PAD19FNCSEL_Msk      (0x38000000UL)            /*!< PAD19FNCSEL (Bitfield-Mask: 0x07)                     */
11628 #define GPIO_PADREGE_PAD19STRNG_Pos       (26UL)                    /*!< PAD19STRNG (Bit 26)                                   */
11629 #define GPIO_PADREGE_PAD19STRNG_Msk       (0x4000000UL)             /*!< PAD19STRNG (Bitfield-Mask: 0x01)                      */
11630 #define GPIO_PADREGE_PAD19INPEN_Pos       (25UL)                    /*!< PAD19INPEN (Bit 25)                                   */
11631 #define GPIO_PADREGE_PAD19INPEN_Msk       (0x2000000UL)             /*!< PAD19INPEN (Bitfield-Mask: 0x01)                      */
11632 #define GPIO_PADREGE_PAD19PULL_Pos        (24UL)                    /*!< PAD19PULL (Bit 24)                                    */
11633 #define GPIO_PADREGE_PAD19PULL_Msk        (0x1000000UL)             /*!< PAD19PULL (Bitfield-Mask: 0x01)                       */
11634 #define GPIO_PADREGE_PAD18FNCSEL_Pos      (19UL)                    /*!< PAD18FNCSEL (Bit 19)                                  */
11635 #define GPIO_PADREGE_PAD18FNCSEL_Msk      (0x380000UL)              /*!< PAD18FNCSEL (Bitfield-Mask: 0x07)                     */
11636 #define GPIO_PADREGE_PAD18STRNG_Pos       (18UL)                    /*!< PAD18STRNG (Bit 18)                                   */
11637 #define GPIO_PADREGE_PAD18STRNG_Msk       (0x40000UL)               /*!< PAD18STRNG (Bitfield-Mask: 0x01)                      */
11638 #define GPIO_PADREGE_PAD18INPEN_Pos       (17UL)                    /*!< PAD18INPEN (Bit 17)                                   */
11639 #define GPIO_PADREGE_PAD18INPEN_Msk       (0x20000UL)               /*!< PAD18INPEN (Bitfield-Mask: 0x01)                      */
11640 #define GPIO_PADREGE_PAD18PULL_Pos        (16UL)                    /*!< PAD18PULL (Bit 16)                                    */
11641 #define GPIO_PADREGE_PAD18PULL_Msk        (0x10000UL)               /*!< PAD18PULL (Bitfield-Mask: 0x01)                       */
11642 #define GPIO_PADREGE_PAD17FNCSEL_Pos      (11UL)                    /*!< PAD17FNCSEL (Bit 11)                                  */
11643 #define GPIO_PADREGE_PAD17FNCSEL_Msk      (0x3800UL)                /*!< PAD17FNCSEL (Bitfield-Mask: 0x07)                     */
11644 #define GPIO_PADREGE_PAD17STRNG_Pos       (10UL)                    /*!< PAD17STRNG (Bit 10)                                   */
11645 #define GPIO_PADREGE_PAD17STRNG_Msk       (0x400UL)                 /*!< PAD17STRNG (Bitfield-Mask: 0x01)                      */
11646 #define GPIO_PADREGE_PAD17INPEN_Pos       (9UL)                     /*!< PAD17INPEN (Bit 9)                                    */
11647 #define GPIO_PADREGE_PAD17INPEN_Msk       (0x200UL)                 /*!< PAD17INPEN (Bitfield-Mask: 0x01)                      */
11648 #define GPIO_PADREGE_PAD17PULL_Pos        (8UL)                     /*!< PAD17PULL (Bit 8)                                     */
11649 #define GPIO_PADREGE_PAD17PULL_Msk        (0x100UL)                 /*!< PAD17PULL (Bitfield-Mask: 0x01)                       */
11650 #define GPIO_PADREGE_PAD16FNCSEL_Pos      (3UL)                     /*!< PAD16FNCSEL (Bit 3)                                   */
11651 #define GPIO_PADREGE_PAD16FNCSEL_Msk      (0x38UL)                  /*!< PAD16FNCSEL (Bitfield-Mask: 0x07)                     */
11652 #define GPIO_PADREGE_PAD16STRNG_Pos       (2UL)                     /*!< PAD16STRNG (Bit 2)                                    */
11653 #define GPIO_PADREGE_PAD16STRNG_Msk       (0x4UL)                   /*!< PAD16STRNG (Bitfield-Mask: 0x01)                      */
11654 #define GPIO_PADREGE_PAD16INPEN_Pos       (1UL)                     /*!< PAD16INPEN (Bit 1)                                    */
11655 #define GPIO_PADREGE_PAD16INPEN_Msk       (0x2UL)                   /*!< PAD16INPEN (Bitfield-Mask: 0x01)                      */
11656 #define GPIO_PADREGE_PAD16PULL_Pos        (0UL)                     /*!< PAD16PULL (Bit 0)                                     */
11657 #define GPIO_PADREGE_PAD16PULL_Msk        (0x1UL)                   /*!< PAD16PULL (Bitfield-Mask: 0x01)                       */
11658 /* ========================================================  PADREGF  ======================================================== */
11659 #define GPIO_PADREGF_PAD23FNCSEL_Pos      (27UL)                    /*!< PAD23FNCSEL (Bit 27)                                  */
11660 #define GPIO_PADREGF_PAD23FNCSEL_Msk      (0x38000000UL)            /*!< PAD23FNCSEL (Bitfield-Mask: 0x07)                     */
11661 #define GPIO_PADREGF_PAD23STRNG_Pos       (26UL)                    /*!< PAD23STRNG (Bit 26)                                   */
11662 #define GPIO_PADREGF_PAD23STRNG_Msk       (0x4000000UL)             /*!< PAD23STRNG (Bitfield-Mask: 0x01)                      */
11663 #define GPIO_PADREGF_PAD23INPEN_Pos       (25UL)                    /*!< PAD23INPEN (Bit 25)                                   */
11664 #define GPIO_PADREGF_PAD23INPEN_Msk       (0x2000000UL)             /*!< PAD23INPEN (Bitfield-Mask: 0x01)                      */
11665 #define GPIO_PADREGF_PAD23PULL_Pos        (24UL)                    /*!< PAD23PULL (Bit 24)                                    */
11666 #define GPIO_PADREGF_PAD23PULL_Msk        (0x1000000UL)             /*!< PAD23PULL (Bitfield-Mask: 0x01)                       */
11667 #define GPIO_PADREGF_PAD22FNCSEL_Pos      (19UL)                    /*!< PAD22FNCSEL (Bit 19)                                  */
11668 #define GPIO_PADREGF_PAD22FNCSEL_Msk      (0x380000UL)              /*!< PAD22FNCSEL (Bitfield-Mask: 0x07)                     */
11669 #define GPIO_PADREGF_PAD22STRNG_Pos       (18UL)                    /*!< PAD22STRNG (Bit 18)                                   */
11670 #define GPIO_PADREGF_PAD22STRNG_Msk       (0x40000UL)               /*!< PAD22STRNG (Bitfield-Mask: 0x01)                      */
11671 #define GPIO_PADREGF_PAD22INPEN_Pos       (17UL)                    /*!< PAD22INPEN (Bit 17)                                   */
11672 #define GPIO_PADREGF_PAD22INPEN_Msk       (0x20000UL)               /*!< PAD22INPEN (Bitfield-Mask: 0x01)                      */
11673 #define GPIO_PADREGF_PAD22PULL_Pos        (16UL)                    /*!< PAD22PULL (Bit 16)                                    */
11674 #define GPIO_PADREGF_PAD22PULL_Msk        (0x10000UL)               /*!< PAD22PULL (Bitfield-Mask: 0x01)                       */
11675 #define GPIO_PADREGF_PAD21FNCSEL_Pos      (11UL)                    /*!< PAD21FNCSEL (Bit 11)                                  */
11676 #define GPIO_PADREGF_PAD21FNCSEL_Msk      (0x3800UL)                /*!< PAD21FNCSEL (Bitfield-Mask: 0x07)                     */
11677 #define GPIO_PADREGF_PAD21STRNG_Pos       (10UL)                    /*!< PAD21STRNG (Bit 10)                                   */
11678 #define GPIO_PADREGF_PAD21STRNG_Msk       (0x400UL)                 /*!< PAD21STRNG (Bitfield-Mask: 0x01)                      */
11679 #define GPIO_PADREGF_PAD21INPEN_Pos       (9UL)                     /*!< PAD21INPEN (Bit 9)                                    */
11680 #define GPIO_PADREGF_PAD21INPEN_Msk       (0x200UL)                 /*!< PAD21INPEN (Bitfield-Mask: 0x01)                      */
11681 #define GPIO_PADREGF_PAD21PULL_Pos        (8UL)                     /*!< PAD21PULL (Bit 8)                                     */
11682 #define GPIO_PADREGF_PAD21PULL_Msk        (0x100UL)                 /*!< PAD21PULL (Bitfield-Mask: 0x01)                       */
11683 #define GPIO_PADREGF_PAD20FNCSEL_Pos      (3UL)                     /*!< PAD20FNCSEL (Bit 3)                                   */
11684 #define GPIO_PADREGF_PAD20FNCSEL_Msk      (0x38UL)                  /*!< PAD20FNCSEL (Bitfield-Mask: 0x07)                     */
11685 #define GPIO_PADREGF_PAD20STRNG_Pos       (2UL)                     /*!< PAD20STRNG (Bit 2)                                    */
11686 #define GPIO_PADREGF_PAD20STRNG_Msk       (0x4UL)                   /*!< PAD20STRNG (Bitfield-Mask: 0x01)                      */
11687 #define GPIO_PADREGF_PAD20INPEN_Pos       (1UL)                     /*!< PAD20INPEN (Bit 1)                                    */
11688 #define GPIO_PADREGF_PAD20INPEN_Msk       (0x2UL)                   /*!< PAD20INPEN (Bitfield-Mask: 0x01)                      */
11689 #define GPIO_PADREGF_PAD20PULL_Pos        (0UL)                     /*!< PAD20PULL (Bit 0)                                     */
11690 #define GPIO_PADREGF_PAD20PULL_Msk        (0x1UL)                   /*!< PAD20PULL (Bitfield-Mask: 0x01)                       */
11691 /* ========================================================  PADREGG  ======================================================== */
11692 #define GPIO_PADREGG_PAD27RSEL_Pos        (30UL)                    /*!< PAD27RSEL (Bit 30)                                    */
11693 #define GPIO_PADREGG_PAD27RSEL_Msk        (0xc0000000UL)            /*!< PAD27RSEL (Bitfield-Mask: 0x03)                       */
11694 #define GPIO_PADREGG_PAD27FNCSEL_Pos      (27UL)                    /*!< PAD27FNCSEL (Bit 27)                                  */
11695 #define GPIO_PADREGG_PAD27FNCSEL_Msk      (0x38000000UL)            /*!< PAD27FNCSEL (Bitfield-Mask: 0x07)                     */
11696 #define GPIO_PADREGG_PAD27STRNG_Pos       (26UL)                    /*!< PAD27STRNG (Bit 26)                                   */
11697 #define GPIO_PADREGG_PAD27STRNG_Msk       (0x4000000UL)             /*!< PAD27STRNG (Bitfield-Mask: 0x01)                      */
11698 #define GPIO_PADREGG_PAD27INPEN_Pos       (25UL)                    /*!< PAD27INPEN (Bit 25)                                   */
11699 #define GPIO_PADREGG_PAD27INPEN_Msk       (0x2000000UL)             /*!< PAD27INPEN (Bitfield-Mask: 0x01)                      */
11700 #define GPIO_PADREGG_PAD27PULL_Pos        (24UL)                    /*!< PAD27PULL (Bit 24)                                    */
11701 #define GPIO_PADREGG_PAD27PULL_Msk        (0x1000000UL)             /*!< PAD27PULL (Bitfield-Mask: 0x01)                       */
11702 #define GPIO_PADREGG_PAD26FNCSEL_Pos      (19UL)                    /*!< PAD26FNCSEL (Bit 19)                                  */
11703 #define GPIO_PADREGG_PAD26FNCSEL_Msk      (0x380000UL)              /*!< PAD26FNCSEL (Bitfield-Mask: 0x07)                     */
11704 #define GPIO_PADREGG_PAD26STRNG_Pos       (18UL)                    /*!< PAD26STRNG (Bit 18)                                   */
11705 #define GPIO_PADREGG_PAD26STRNG_Msk       (0x40000UL)               /*!< PAD26STRNG (Bitfield-Mask: 0x01)                      */
11706 #define GPIO_PADREGG_PAD26INPEN_Pos       (17UL)                    /*!< PAD26INPEN (Bit 17)                                   */
11707 #define GPIO_PADREGG_PAD26INPEN_Msk       (0x20000UL)               /*!< PAD26INPEN (Bitfield-Mask: 0x01)                      */
11708 #define GPIO_PADREGG_PAD26PULL_Pos        (16UL)                    /*!< PAD26PULL (Bit 16)                                    */
11709 #define GPIO_PADREGG_PAD26PULL_Msk        (0x10000UL)               /*!< PAD26PULL (Bitfield-Mask: 0x01)                       */
11710 #define GPIO_PADREGG_PAD25RSEL_Pos        (14UL)                    /*!< PAD25RSEL (Bit 14)                                    */
11711 #define GPIO_PADREGG_PAD25RSEL_Msk        (0xc000UL)                /*!< PAD25RSEL (Bitfield-Mask: 0x03)                       */
11712 #define GPIO_PADREGG_PAD25FNCSEL_Pos      (11UL)                    /*!< PAD25FNCSEL (Bit 11)                                  */
11713 #define GPIO_PADREGG_PAD25FNCSEL_Msk      (0x3800UL)                /*!< PAD25FNCSEL (Bitfield-Mask: 0x07)                     */
11714 #define GPIO_PADREGG_PAD25STRNG_Pos       (10UL)                    /*!< PAD25STRNG (Bit 10)                                   */
11715 #define GPIO_PADREGG_PAD25STRNG_Msk       (0x400UL)                 /*!< PAD25STRNG (Bitfield-Mask: 0x01)                      */
11716 #define GPIO_PADREGG_PAD25INPEN_Pos       (9UL)                     /*!< PAD25INPEN (Bit 9)                                    */
11717 #define GPIO_PADREGG_PAD25INPEN_Msk       (0x200UL)                 /*!< PAD25INPEN (Bitfield-Mask: 0x01)                      */
11718 #define GPIO_PADREGG_PAD25PULL_Pos        (8UL)                     /*!< PAD25PULL (Bit 8)                                     */
11719 #define GPIO_PADREGG_PAD25PULL_Msk        (0x100UL)                 /*!< PAD25PULL (Bitfield-Mask: 0x01)                       */
11720 #define GPIO_PADREGG_PAD24FNCSEL_Pos      (3UL)                     /*!< PAD24FNCSEL (Bit 3)                                   */
11721 #define GPIO_PADREGG_PAD24FNCSEL_Msk      (0x38UL)                  /*!< PAD24FNCSEL (Bitfield-Mask: 0x07)                     */
11722 #define GPIO_PADREGG_PAD24STRNG_Pos       (2UL)                     /*!< PAD24STRNG (Bit 2)                                    */
11723 #define GPIO_PADREGG_PAD24STRNG_Msk       (0x4UL)                   /*!< PAD24STRNG (Bitfield-Mask: 0x01)                      */
11724 #define GPIO_PADREGG_PAD24INPEN_Pos       (1UL)                     /*!< PAD24INPEN (Bit 1)                                    */
11725 #define GPIO_PADREGG_PAD24INPEN_Msk       (0x2UL)                   /*!< PAD24INPEN (Bitfield-Mask: 0x01)                      */
11726 #define GPIO_PADREGG_PAD24PULL_Pos        (0UL)                     /*!< PAD24PULL (Bit 0)                                     */
11727 #define GPIO_PADREGG_PAD24PULL_Msk        (0x1UL)                   /*!< PAD24PULL (Bitfield-Mask: 0x01)                       */
11728 /* ========================================================  PADREGH  ======================================================== */
11729 #define GPIO_PADREGH_PAD31FNCSEL_Pos      (27UL)                    /*!< PAD31FNCSEL (Bit 27)                                  */
11730 #define GPIO_PADREGH_PAD31FNCSEL_Msk      (0x38000000UL)            /*!< PAD31FNCSEL (Bitfield-Mask: 0x07)                     */
11731 #define GPIO_PADREGH_PAD31STRNG_Pos       (26UL)                    /*!< PAD31STRNG (Bit 26)                                   */
11732 #define GPIO_PADREGH_PAD31STRNG_Msk       (0x4000000UL)             /*!< PAD31STRNG (Bitfield-Mask: 0x01)                      */
11733 #define GPIO_PADREGH_PAD31INPEN_Pos       (25UL)                    /*!< PAD31INPEN (Bit 25)                                   */
11734 #define GPIO_PADREGH_PAD31INPEN_Msk       (0x2000000UL)             /*!< PAD31INPEN (Bitfield-Mask: 0x01)                      */
11735 #define GPIO_PADREGH_PAD31PULL_Pos        (24UL)                    /*!< PAD31PULL (Bit 24)                                    */
11736 #define GPIO_PADREGH_PAD31PULL_Msk        (0x1000000UL)             /*!< PAD31PULL (Bitfield-Mask: 0x01)                       */
11737 #define GPIO_PADREGH_PAD30FNCSEL_Pos      (19UL)                    /*!< PAD30FNCSEL (Bit 19)                                  */
11738 #define GPIO_PADREGH_PAD30FNCSEL_Msk      (0x380000UL)              /*!< PAD30FNCSEL (Bitfield-Mask: 0x07)                     */
11739 #define GPIO_PADREGH_PAD30STRNG_Pos       (18UL)                    /*!< PAD30STRNG (Bit 18)                                   */
11740 #define GPIO_PADREGH_PAD30STRNG_Msk       (0x40000UL)               /*!< PAD30STRNG (Bitfield-Mask: 0x01)                      */
11741 #define GPIO_PADREGH_PAD30INPEN_Pos       (17UL)                    /*!< PAD30INPEN (Bit 17)                                   */
11742 #define GPIO_PADREGH_PAD30INPEN_Msk       (0x20000UL)               /*!< PAD30INPEN (Bitfield-Mask: 0x01)                      */
11743 #define GPIO_PADREGH_PAD30PULL_Pos        (16UL)                    /*!< PAD30PULL (Bit 16)                                    */
11744 #define GPIO_PADREGH_PAD30PULL_Msk        (0x10000UL)               /*!< PAD30PULL (Bitfield-Mask: 0x01)                       */
11745 #define GPIO_PADREGH_PAD29FNCSEL_Pos      (11UL)                    /*!< PAD29FNCSEL (Bit 11)                                  */
11746 #define GPIO_PADREGH_PAD29FNCSEL_Msk      (0x3800UL)                /*!< PAD29FNCSEL (Bitfield-Mask: 0x07)                     */
11747 #define GPIO_PADREGH_PAD29STRNG_Pos       (10UL)                    /*!< PAD29STRNG (Bit 10)                                   */
11748 #define GPIO_PADREGH_PAD29STRNG_Msk       (0x400UL)                 /*!< PAD29STRNG (Bitfield-Mask: 0x01)                      */
11749 #define GPIO_PADREGH_PAD29INPEN_Pos       (9UL)                     /*!< PAD29INPEN (Bit 9)                                    */
11750 #define GPIO_PADREGH_PAD29INPEN_Msk       (0x200UL)                 /*!< PAD29INPEN (Bitfield-Mask: 0x01)                      */
11751 #define GPIO_PADREGH_PAD29PULL_Pos        (8UL)                     /*!< PAD29PULL (Bit 8)                                     */
11752 #define GPIO_PADREGH_PAD29PULL_Msk        (0x100UL)                 /*!< PAD29PULL (Bitfield-Mask: 0x01)                       */
11753 #define GPIO_PADREGH_PAD28FNCSEL_Pos      (3UL)                     /*!< PAD28FNCSEL (Bit 3)                                   */
11754 #define GPIO_PADREGH_PAD28FNCSEL_Msk      (0x38UL)                  /*!< PAD28FNCSEL (Bitfield-Mask: 0x07)                     */
11755 #define GPIO_PADREGH_PAD28STRNG_Pos       (2UL)                     /*!< PAD28STRNG (Bit 2)                                    */
11756 #define GPIO_PADREGH_PAD28STRNG_Msk       (0x4UL)                   /*!< PAD28STRNG (Bitfield-Mask: 0x01)                      */
11757 #define GPIO_PADREGH_PAD28INPEN_Pos       (1UL)                     /*!< PAD28INPEN (Bit 1)                                    */
11758 #define GPIO_PADREGH_PAD28INPEN_Msk       (0x2UL)                   /*!< PAD28INPEN (Bitfield-Mask: 0x01)                      */
11759 #define GPIO_PADREGH_PAD28PULL_Pos        (0UL)                     /*!< PAD28PULL (Bit 0)                                     */
11760 #define GPIO_PADREGH_PAD28PULL_Msk        (0x1UL)                   /*!< PAD28PULL (Bitfield-Mask: 0x01)                       */
11761 /* ========================================================  PADREGI  ======================================================== */
11762 #define GPIO_PADREGI_PAD35FNCSEL_Pos      (27UL)                    /*!< PAD35FNCSEL (Bit 27)                                  */
11763 #define GPIO_PADREGI_PAD35FNCSEL_Msk      (0x38000000UL)            /*!< PAD35FNCSEL (Bitfield-Mask: 0x07)                     */
11764 #define GPIO_PADREGI_PAD35STRNG_Pos       (26UL)                    /*!< PAD35STRNG (Bit 26)                                   */
11765 #define GPIO_PADREGI_PAD35STRNG_Msk       (0x4000000UL)             /*!< PAD35STRNG (Bitfield-Mask: 0x01)                      */
11766 #define GPIO_PADREGI_PAD35INPEN_Pos       (25UL)                    /*!< PAD35INPEN (Bit 25)                                   */
11767 #define GPIO_PADREGI_PAD35INPEN_Msk       (0x2000000UL)             /*!< PAD35INPEN (Bitfield-Mask: 0x01)                      */
11768 #define GPIO_PADREGI_PAD35PULL_Pos        (24UL)                    /*!< PAD35PULL (Bit 24)                                    */
11769 #define GPIO_PADREGI_PAD35PULL_Msk        (0x1000000UL)             /*!< PAD35PULL (Bitfield-Mask: 0x01)                       */
11770 #define GPIO_PADREGI_PAD34FNCSEL_Pos      (19UL)                    /*!< PAD34FNCSEL (Bit 19)                                  */
11771 #define GPIO_PADREGI_PAD34FNCSEL_Msk      (0x380000UL)              /*!< PAD34FNCSEL (Bitfield-Mask: 0x07)                     */
11772 #define GPIO_PADREGI_PAD34STRNG_Pos       (18UL)                    /*!< PAD34STRNG (Bit 18)                                   */
11773 #define GPIO_PADREGI_PAD34STRNG_Msk       (0x40000UL)               /*!< PAD34STRNG (Bitfield-Mask: 0x01)                      */
11774 #define GPIO_PADREGI_PAD34INPEN_Pos       (17UL)                    /*!< PAD34INPEN (Bit 17)                                   */
11775 #define GPIO_PADREGI_PAD34INPEN_Msk       (0x20000UL)               /*!< PAD34INPEN (Bitfield-Mask: 0x01)                      */
11776 #define GPIO_PADREGI_PAD34PULL_Pos        (16UL)                    /*!< PAD34PULL (Bit 16)                                    */
11777 #define GPIO_PADREGI_PAD34PULL_Msk        (0x10000UL)               /*!< PAD34PULL (Bitfield-Mask: 0x01)                       */
11778 #define GPIO_PADREGI_PAD33FNCSEL_Pos      (11UL)                    /*!< PAD33FNCSEL (Bit 11)                                  */
11779 #define GPIO_PADREGI_PAD33FNCSEL_Msk      (0x3800UL)                /*!< PAD33FNCSEL (Bitfield-Mask: 0x07)                     */
11780 #define GPIO_PADREGI_PAD33STRNG_Pos       (10UL)                    /*!< PAD33STRNG (Bit 10)                                   */
11781 #define GPIO_PADREGI_PAD33STRNG_Msk       (0x400UL)                 /*!< PAD33STRNG (Bitfield-Mask: 0x01)                      */
11782 #define GPIO_PADREGI_PAD33INPEN_Pos       (9UL)                     /*!< PAD33INPEN (Bit 9)                                    */
11783 #define GPIO_PADREGI_PAD33INPEN_Msk       (0x200UL)                 /*!< PAD33INPEN (Bitfield-Mask: 0x01)                      */
11784 #define GPIO_PADREGI_PAD33PULL_Pos        (8UL)                     /*!< PAD33PULL (Bit 8)                                     */
11785 #define GPIO_PADREGI_PAD33PULL_Msk        (0x100UL)                 /*!< PAD33PULL (Bitfield-Mask: 0x01)                       */
11786 #define GPIO_PADREGI_PAD32FNCSEL_Pos      (3UL)                     /*!< PAD32FNCSEL (Bit 3)                                   */
11787 #define GPIO_PADREGI_PAD32FNCSEL_Msk      (0x38UL)                  /*!< PAD32FNCSEL (Bitfield-Mask: 0x07)                     */
11788 #define GPIO_PADREGI_PAD32STRNG_Pos       (2UL)                     /*!< PAD32STRNG (Bit 2)                                    */
11789 #define GPIO_PADREGI_PAD32STRNG_Msk       (0x4UL)                   /*!< PAD32STRNG (Bitfield-Mask: 0x01)                      */
11790 #define GPIO_PADREGI_PAD32INPEN_Pos       (1UL)                     /*!< PAD32INPEN (Bit 1)                                    */
11791 #define GPIO_PADREGI_PAD32INPEN_Msk       (0x2UL)                   /*!< PAD32INPEN (Bitfield-Mask: 0x01)                      */
11792 #define GPIO_PADREGI_PAD32PULL_Pos        (0UL)                     /*!< PAD32PULL (Bit 0)                                     */
11793 #define GPIO_PADREGI_PAD32PULL_Msk        (0x1UL)                   /*!< PAD32PULL (Bitfield-Mask: 0x01)                       */
11794 /* ========================================================  PADREGJ  ======================================================== */
11795 #define GPIO_PADREGJ_PAD39RSEL_Pos        (30UL)                    /*!< PAD39RSEL (Bit 30)                                    */
11796 #define GPIO_PADREGJ_PAD39RSEL_Msk        (0xc0000000UL)            /*!< PAD39RSEL (Bitfield-Mask: 0x03)                       */
11797 #define GPIO_PADREGJ_PAD39FNCSEL_Pos      (27UL)                    /*!< PAD39FNCSEL (Bit 27)                                  */
11798 #define GPIO_PADREGJ_PAD39FNCSEL_Msk      (0x38000000UL)            /*!< PAD39FNCSEL (Bitfield-Mask: 0x07)                     */
11799 #define GPIO_PADREGJ_PAD39STRNG_Pos       (26UL)                    /*!< PAD39STRNG (Bit 26)                                   */
11800 #define GPIO_PADREGJ_PAD39STRNG_Msk       (0x4000000UL)             /*!< PAD39STRNG (Bitfield-Mask: 0x01)                      */
11801 #define GPIO_PADREGJ_PAD39INPEN_Pos       (25UL)                    /*!< PAD39INPEN (Bit 25)                                   */
11802 #define GPIO_PADREGJ_PAD39INPEN_Msk       (0x2000000UL)             /*!< PAD39INPEN (Bitfield-Mask: 0x01)                      */
11803 #define GPIO_PADREGJ_PAD39PULL_Pos        (24UL)                    /*!< PAD39PULL (Bit 24)                                    */
11804 #define GPIO_PADREGJ_PAD39PULL_Msk        (0x1000000UL)             /*!< PAD39PULL (Bitfield-Mask: 0x01)                       */
11805 #define GPIO_PADREGJ_PAD38FNCSEL_Pos      (19UL)                    /*!< PAD38FNCSEL (Bit 19)                                  */
11806 #define GPIO_PADREGJ_PAD38FNCSEL_Msk      (0x380000UL)              /*!< PAD38FNCSEL (Bitfield-Mask: 0x07)                     */
11807 #define GPIO_PADREGJ_PAD38STRNG_Pos       (18UL)                    /*!< PAD38STRNG (Bit 18)                                   */
11808 #define GPIO_PADREGJ_PAD38STRNG_Msk       (0x40000UL)               /*!< PAD38STRNG (Bitfield-Mask: 0x01)                      */
11809 #define GPIO_PADREGJ_PAD38INPEN_Pos       (17UL)                    /*!< PAD38INPEN (Bit 17)                                   */
11810 #define GPIO_PADREGJ_PAD38INPEN_Msk       (0x20000UL)               /*!< PAD38INPEN (Bitfield-Mask: 0x01)                      */
11811 #define GPIO_PADREGJ_PAD38PULL_Pos        (16UL)                    /*!< PAD38PULL (Bit 16)                                    */
11812 #define GPIO_PADREGJ_PAD38PULL_Msk        (0x10000UL)               /*!< PAD38PULL (Bitfield-Mask: 0x01)                       */
11813 #define GPIO_PADREGJ_PAD37PWRDN_Pos       (15UL)                    /*!< PAD37PWRDN (Bit 15)                                   */
11814 #define GPIO_PADREGJ_PAD37PWRDN_Msk       (0x8000UL)                /*!< PAD37PWRDN (Bitfield-Mask: 0x01)                      */
11815 #define GPIO_PADREGJ_PAD37FNCSEL_Pos      (11UL)                    /*!< PAD37FNCSEL (Bit 11)                                  */
11816 #define GPIO_PADREGJ_PAD37FNCSEL_Msk      (0x3800UL)                /*!< PAD37FNCSEL (Bitfield-Mask: 0x07)                     */
11817 #define GPIO_PADREGJ_PAD37STRNG_Pos       (10UL)                    /*!< PAD37STRNG (Bit 10)                                   */
11818 #define GPIO_PADREGJ_PAD37STRNG_Msk       (0x400UL)                 /*!< PAD37STRNG (Bitfield-Mask: 0x01)                      */
11819 #define GPIO_PADREGJ_PAD37INPEN_Pos       (9UL)                     /*!< PAD37INPEN (Bit 9)                                    */
11820 #define GPIO_PADREGJ_PAD37INPEN_Msk       (0x200UL)                 /*!< PAD37INPEN (Bitfield-Mask: 0x01)                      */
11821 #define GPIO_PADREGJ_PAD37PULL_Pos        (8UL)                     /*!< PAD37PULL (Bit 8)                                     */
11822 #define GPIO_PADREGJ_PAD37PULL_Msk        (0x100UL)                 /*!< PAD37PULL (Bitfield-Mask: 0x01)                       */
11823 #define GPIO_PADREGJ_PAD36PWRUP_Pos       (6UL)                     /*!< PAD36PWRUP (Bit 6)                                    */
11824 #define GPIO_PADREGJ_PAD36PWRUP_Msk       (0x40UL)                  /*!< PAD36PWRUP (Bitfield-Mask: 0x01)                      */
11825 #define GPIO_PADREGJ_PAD36FNCSEL_Pos      (3UL)                     /*!< PAD36FNCSEL (Bit 3)                                   */
11826 #define GPIO_PADREGJ_PAD36FNCSEL_Msk      (0x38UL)                  /*!< PAD36FNCSEL (Bitfield-Mask: 0x07)                     */
11827 #define GPIO_PADREGJ_PAD36STRNG_Pos       (2UL)                     /*!< PAD36STRNG (Bit 2)                                    */
11828 #define GPIO_PADREGJ_PAD36STRNG_Msk       (0x4UL)                   /*!< PAD36STRNG (Bitfield-Mask: 0x01)                      */
11829 #define GPIO_PADREGJ_PAD36INPEN_Pos       (1UL)                     /*!< PAD36INPEN (Bit 1)                                    */
11830 #define GPIO_PADREGJ_PAD36INPEN_Msk       (0x2UL)                   /*!< PAD36INPEN (Bitfield-Mask: 0x01)                      */
11831 #define GPIO_PADREGJ_PAD36PULL_Pos        (0UL)                     /*!< PAD36PULL (Bit 0)                                     */
11832 #define GPIO_PADREGJ_PAD36PULL_Msk        (0x1UL)                   /*!< PAD36PULL (Bitfield-Mask: 0x01)                       */
11833 /* ========================================================  PADREGK  ======================================================== */
11834 #define GPIO_PADREGK_PAD43RSEL_Pos        (30UL)                    /*!< PAD43RSEL (Bit 30)                                    */
11835 #define GPIO_PADREGK_PAD43RSEL_Msk        (0xc0000000UL)            /*!< PAD43RSEL (Bitfield-Mask: 0x03)                       */
11836 #define GPIO_PADREGK_PAD43FNCSEL_Pos      (27UL)                    /*!< PAD43FNCSEL (Bit 27)                                  */
11837 #define GPIO_PADREGK_PAD43FNCSEL_Msk      (0x38000000UL)            /*!< PAD43FNCSEL (Bitfield-Mask: 0x07)                     */
11838 #define GPIO_PADREGK_PAD43STRNG_Pos       (26UL)                    /*!< PAD43STRNG (Bit 26)                                   */
11839 #define GPIO_PADREGK_PAD43STRNG_Msk       (0x4000000UL)             /*!< PAD43STRNG (Bitfield-Mask: 0x01)                      */
11840 #define GPIO_PADREGK_PAD43INPEN_Pos       (25UL)                    /*!< PAD43INPEN (Bit 25)                                   */
11841 #define GPIO_PADREGK_PAD43INPEN_Msk       (0x2000000UL)             /*!< PAD43INPEN (Bitfield-Mask: 0x01)                      */
11842 #define GPIO_PADREGK_PAD43PULL_Pos        (24UL)                    /*!< PAD43PULL (Bit 24)                                    */
11843 #define GPIO_PADREGK_PAD43PULL_Msk        (0x1000000UL)             /*!< PAD43PULL (Bitfield-Mask: 0x01)                       */
11844 #define GPIO_PADREGK_PAD42RSEL_Pos        (22UL)                    /*!< PAD42RSEL (Bit 22)                                    */
11845 #define GPIO_PADREGK_PAD42RSEL_Msk        (0xc00000UL)              /*!< PAD42RSEL (Bitfield-Mask: 0x03)                       */
11846 #define GPIO_PADREGK_PAD42FNCSEL_Pos      (19UL)                    /*!< PAD42FNCSEL (Bit 19)                                  */
11847 #define GPIO_PADREGK_PAD42FNCSEL_Msk      (0x380000UL)              /*!< PAD42FNCSEL (Bitfield-Mask: 0x07)                     */
11848 #define GPIO_PADREGK_PAD42STRNG_Pos       (18UL)                    /*!< PAD42STRNG (Bit 18)                                   */
11849 #define GPIO_PADREGK_PAD42STRNG_Msk       (0x40000UL)               /*!< PAD42STRNG (Bitfield-Mask: 0x01)                      */
11850 #define GPIO_PADREGK_PAD42INPEN_Pos       (17UL)                    /*!< PAD42INPEN (Bit 17)                                   */
11851 #define GPIO_PADREGK_PAD42INPEN_Msk       (0x20000UL)               /*!< PAD42INPEN (Bitfield-Mask: 0x01)                      */
11852 #define GPIO_PADREGK_PAD42PULL_Pos        (16UL)                    /*!< PAD42PULL (Bit 16)                                    */
11853 #define GPIO_PADREGK_PAD42PULL_Msk        (0x10000UL)               /*!< PAD42PULL (Bitfield-Mask: 0x01)                       */
11854 #define GPIO_PADREGK_PAD41PWRDN_Pos       (15UL)                    /*!< PAD41PWRDN (Bit 15)                                   */
11855 #define GPIO_PADREGK_PAD41PWRDN_Msk       (0x8000UL)                /*!< PAD41PWRDN (Bitfield-Mask: 0x01)                      */
11856 #define GPIO_PADREGK_PAD41FNCSEL_Pos      (11UL)                    /*!< PAD41FNCSEL (Bit 11)                                  */
11857 #define GPIO_PADREGK_PAD41FNCSEL_Msk      (0x3800UL)                /*!< PAD41FNCSEL (Bitfield-Mask: 0x07)                     */
11858 #define GPIO_PADREGK_PAD41STRNG_Pos       (10UL)                    /*!< PAD41STRNG (Bit 10)                                   */
11859 #define GPIO_PADREGK_PAD41STRNG_Msk       (0x400UL)                 /*!< PAD41STRNG (Bitfield-Mask: 0x01)                      */
11860 #define GPIO_PADREGK_PAD41INPEN_Pos       (9UL)                     /*!< PAD41INPEN (Bit 9)                                    */
11861 #define GPIO_PADREGK_PAD41INPEN_Msk       (0x200UL)                 /*!< PAD41INPEN (Bitfield-Mask: 0x01)                      */
11862 #define GPIO_PADREGK_PAD41PULL_Pos        (8UL)                     /*!< PAD41PULL (Bit 8)                                     */
11863 #define GPIO_PADREGK_PAD41PULL_Msk        (0x100UL)                 /*!< PAD41PULL (Bitfield-Mask: 0x01)                       */
11864 #define GPIO_PADREGK_PAD40RSEL_Pos        (6UL)                     /*!< PAD40RSEL (Bit 6)                                     */
11865 #define GPIO_PADREGK_PAD40RSEL_Msk        (0xc0UL)                  /*!< PAD40RSEL (Bitfield-Mask: 0x03)                       */
11866 #define GPIO_PADREGK_PAD40FNCSEL_Pos      (3UL)                     /*!< PAD40FNCSEL (Bit 3)                                   */
11867 #define GPIO_PADREGK_PAD40FNCSEL_Msk      (0x38UL)                  /*!< PAD40FNCSEL (Bitfield-Mask: 0x07)                     */
11868 #define GPIO_PADREGK_PAD40STRNG_Pos       (2UL)                     /*!< PAD40STRNG (Bit 2)                                    */
11869 #define GPIO_PADREGK_PAD40STRNG_Msk       (0x4UL)                   /*!< PAD40STRNG (Bitfield-Mask: 0x01)                      */
11870 #define GPIO_PADREGK_PAD40INPEN_Pos       (1UL)                     /*!< PAD40INPEN (Bit 1)                                    */
11871 #define GPIO_PADREGK_PAD40INPEN_Msk       (0x2UL)                   /*!< PAD40INPEN (Bitfield-Mask: 0x01)                      */
11872 #define GPIO_PADREGK_PAD40PULL_Pos        (0UL)                     /*!< PAD40PULL (Bit 0)                                     */
11873 #define GPIO_PADREGK_PAD40PULL_Msk        (0x1UL)                   /*!< PAD40PULL (Bitfield-Mask: 0x01)                       */
11874 /* ========================================================  PADREGL  ======================================================== */
11875 #define GPIO_PADREGL_PAD47FNCSEL_Pos      (27UL)                    /*!< PAD47FNCSEL (Bit 27)                                  */
11876 #define GPIO_PADREGL_PAD47FNCSEL_Msk      (0x38000000UL)            /*!< PAD47FNCSEL (Bitfield-Mask: 0x07)                     */
11877 #define GPIO_PADREGL_PAD47STRNG_Pos       (26UL)                    /*!< PAD47STRNG (Bit 26)                                   */
11878 #define GPIO_PADREGL_PAD47STRNG_Msk       (0x4000000UL)             /*!< PAD47STRNG (Bitfield-Mask: 0x01)                      */
11879 #define GPIO_PADREGL_PAD47INPEN_Pos       (25UL)                    /*!< PAD47INPEN (Bit 25)                                   */
11880 #define GPIO_PADREGL_PAD47INPEN_Msk       (0x2000000UL)             /*!< PAD47INPEN (Bitfield-Mask: 0x01)                      */
11881 #define GPIO_PADREGL_PAD47PULL_Pos        (24UL)                    /*!< PAD47PULL (Bit 24)                                    */
11882 #define GPIO_PADREGL_PAD47PULL_Msk        (0x1000000UL)             /*!< PAD47PULL (Bitfield-Mask: 0x01)                       */
11883 #define GPIO_PADREGL_PAD46FNCSEL_Pos      (19UL)                    /*!< PAD46FNCSEL (Bit 19)                                  */
11884 #define GPIO_PADREGL_PAD46FNCSEL_Msk      (0x380000UL)              /*!< PAD46FNCSEL (Bitfield-Mask: 0x07)                     */
11885 #define GPIO_PADREGL_PAD46STRNG_Pos       (18UL)                    /*!< PAD46STRNG (Bit 18)                                   */
11886 #define GPIO_PADREGL_PAD46STRNG_Msk       (0x40000UL)               /*!< PAD46STRNG (Bitfield-Mask: 0x01)                      */
11887 #define GPIO_PADREGL_PAD46INPEN_Pos       (17UL)                    /*!< PAD46INPEN (Bit 17)                                   */
11888 #define GPIO_PADREGL_PAD46INPEN_Msk       (0x20000UL)               /*!< PAD46INPEN (Bitfield-Mask: 0x01)                      */
11889 #define GPIO_PADREGL_PAD46PULL_Pos        (16UL)                    /*!< PAD46PULL (Bit 16)                                    */
11890 #define GPIO_PADREGL_PAD46PULL_Msk        (0x10000UL)               /*!< PAD46PULL (Bitfield-Mask: 0x01)                       */
11891 #define GPIO_PADREGL_PAD45FNCSEL_Pos      (11UL)                    /*!< PAD45FNCSEL (Bit 11)                                  */
11892 #define GPIO_PADREGL_PAD45FNCSEL_Msk      (0x3800UL)                /*!< PAD45FNCSEL (Bitfield-Mask: 0x07)                     */
11893 #define GPIO_PADREGL_PAD45STRNG_Pos       (10UL)                    /*!< PAD45STRNG (Bit 10)                                   */
11894 #define GPIO_PADREGL_PAD45STRNG_Msk       (0x400UL)                 /*!< PAD45STRNG (Bitfield-Mask: 0x01)                      */
11895 #define GPIO_PADREGL_PAD45INPEN_Pos       (9UL)                     /*!< PAD45INPEN (Bit 9)                                    */
11896 #define GPIO_PADREGL_PAD45INPEN_Msk       (0x200UL)                 /*!< PAD45INPEN (Bitfield-Mask: 0x01)                      */
11897 #define GPIO_PADREGL_PAD45PULL_Pos        (8UL)                     /*!< PAD45PULL (Bit 8)                                     */
11898 #define GPIO_PADREGL_PAD45PULL_Msk        (0x100UL)                 /*!< PAD45PULL (Bitfield-Mask: 0x01)                       */
11899 #define GPIO_PADREGL_PAD44FNCSEL_Pos      (3UL)                     /*!< PAD44FNCSEL (Bit 3)                                   */
11900 #define GPIO_PADREGL_PAD44FNCSEL_Msk      (0x38UL)                  /*!< PAD44FNCSEL (Bitfield-Mask: 0x07)                     */
11901 #define GPIO_PADREGL_PAD44STRNG_Pos       (2UL)                     /*!< PAD44STRNG (Bit 2)                                    */
11902 #define GPIO_PADREGL_PAD44STRNG_Msk       (0x4UL)                   /*!< PAD44STRNG (Bitfield-Mask: 0x01)                      */
11903 #define GPIO_PADREGL_PAD44INPEN_Pos       (1UL)                     /*!< PAD44INPEN (Bit 1)                                    */
11904 #define GPIO_PADREGL_PAD44INPEN_Msk       (0x2UL)                   /*!< PAD44INPEN (Bitfield-Mask: 0x01)                      */
11905 #define GPIO_PADREGL_PAD44PULL_Pos        (0UL)                     /*!< PAD44PULL (Bit 0)                                     */
11906 #define GPIO_PADREGL_PAD44PULL_Msk        (0x1UL)                   /*!< PAD44PULL (Bitfield-Mask: 0x01)                       */
11907 /* ========================================================  PADREGM  ======================================================== */
11908 #define GPIO_PADREGM_PAD49RSEL_Pos        (14UL)                    /*!< PAD49RSEL (Bit 14)                                    */
11909 #define GPIO_PADREGM_PAD49RSEL_Msk        (0xc000UL)                /*!< PAD49RSEL (Bitfield-Mask: 0x03)                       */
11910 #define GPIO_PADREGM_PAD49FNCSEL_Pos      (11UL)                    /*!< PAD49FNCSEL (Bit 11)                                  */
11911 #define GPIO_PADREGM_PAD49FNCSEL_Msk      (0x3800UL)                /*!< PAD49FNCSEL (Bitfield-Mask: 0x07)                     */
11912 #define GPIO_PADREGM_PAD49STRNG_Pos       (10UL)                    /*!< PAD49STRNG (Bit 10)                                   */
11913 #define GPIO_PADREGM_PAD49STRNG_Msk       (0x400UL)                 /*!< PAD49STRNG (Bitfield-Mask: 0x01)                      */
11914 #define GPIO_PADREGM_PAD49INPEN_Pos       (9UL)                     /*!< PAD49INPEN (Bit 9)                                    */
11915 #define GPIO_PADREGM_PAD49INPEN_Msk       (0x200UL)                 /*!< PAD49INPEN (Bitfield-Mask: 0x01)                      */
11916 #define GPIO_PADREGM_PAD49PULL_Pos        (8UL)                     /*!< PAD49PULL (Bit 8)                                     */
11917 #define GPIO_PADREGM_PAD49PULL_Msk        (0x100UL)                 /*!< PAD49PULL (Bitfield-Mask: 0x01)                       */
11918 #define GPIO_PADREGM_PAD48RSEL_Pos        (6UL)                     /*!< PAD48RSEL (Bit 6)                                     */
11919 #define GPIO_PADREGM_PAD48RSEL_Msk        (0xc0UL)                  /*!< PAD48RSEL (Bitfield-Mask: 0x03)                       */
11920 #define GPIO_PADREGM_PAD48FNCSEL_Pos      (3UL)                     /*!< PAD48FNCSEL (Bit 3)                                   */
11921 #define GPIO_PADREGM_PAD48FNCSEL_Msk      (0x38UL)                  /*!< PAD48FNCSEL (Bitfield-Mask: 0x07)                     */
11922 #define GPIO_PADREGM_PAD48STRNG_Pos       (2UL)                     /*!< PAD48STRNG (Bit 2)                                    */
11923 #define GPIO_PADREGM_PAD48STRNG_Msk       (0x4UL)                   /*!< PAD48STRNG (Bitfield-Mask: 0x01)                      */
11924 #define GPIO_PADREGM_PAD48INPEN_Pos       (1UL)                     /*!< PAD48INPEN (Bit 1)                                    */
11925 #define GPIO_PADREGM_PAD48INPEN_Msk       (0x2UL)                   /*!< PAD48INPEN (Bitfield-Mask: 0x01)                      */
11926 #define GPIO_PADREGM_PAD48PULL_Pos        (0UL)                     /*!< PAD48PULL (Bit 0)                                     */
11927 #define GPIO_PADREGM_PAD48PULL_Msk        (0x1UL)                   /*!< PAD48PULL (Bitfield-Mask: 0x01)                       */
11928 /* =========================================================  CFGA  ========================================================== */
11929 #define GPIO_CFGA_GPIO7INTD_Pos           (31UL)                    /*!< GPIO7INTD (Bit 31)                                    */
11930 #define GPIO_CFGA_GPIO7INTD_Msk           (0x80000000UL)            /*!< GPIO7INTD (Bitfield-Mask: 0x01)                       */
11931 #define GPIO_CFGA_GPIO7OUTCFG_Pos         (29UL)                    /*!< GPIO7OUTCFG (Bit 29)                                  */
11932 #define GPIO_CFGA_GPIO7OUTCFG_Msk         (0x60000000UL)            /*!< GPIO7OUTCFG (Bitfield-Mask: 0x03)                     */
11933 #define GPIO_CFGA_GPIO7INCFG_Pos          (28UL)                    /*!< GPIO7INCFG (Bit 28)                                   */
11934 #define GPIO_CFGA_GPIO7INCFG_Msk          (0x10000000UL)            /*!< GPIO7INCFG (Bitfield-Mask: 0x01)                      */
11935 #define GPIO_CFGA_GPIO6INTD_Pos           (27UL)                    /*!< GPIO6INTD (Bit 27)                                    */
11936 #define GPIO_CFGA_GPIO6INTD_Msk           (0x8000000UL)             /*!< GPIO6INTD (Bitfield-Mask: 0x01)                       */
11937 #define GPIO_CFGA_GPIO6OUTCFG_Pos         (25UL)                    /*!< GPIO6OUTCFG (Bit 25)                                  */
11938 #define GPIO_CFGA_GPIO6OUTCFG_Msk         (0x6000000UL)             /*!< GPIO6OUTCFG (Bitfield-Mask: 0x03)                     */
11939 #define GPIO_CFGA_GPIO6INCFG_Pos          (24UL)                    /*!< GPIO6INCFG (Bit 24)                                   */
11940 #define GPIO_CFGA_GPIO6INCFG_Msk          (0x1000000UL)             /*!< GPIO6INCFG (Bitfield-Mask: 0x01)                      */
11941 #define GPIO_CFGA_GPIO5INTD_Pos           (23UL)                    /*!< GPIO5INTD (Bit 23)                                    */
11942 #define GPIO_CFGA_GPIO5INTD_Msk           (0x800000UL)              /*!< GPIO5INTD (Bitfield-Mask: 0x01)                       */
11943 #define GPIO_CFGA_GPIO5OUTCFG_Pos         (21UL)                    /*!< GPIO5OUTCFG (Bit 21)                                  */
11944 #define GPIO_CFGA_GPIO5OUTCFG_Msk         (0x600000UL)              /*!< GPIO5OUTCFG (Bitfield-Mask: 0x03)                     */
11945 #define GPIO_CFGA_GPIO5INCFG_Pos          (20UL)                    /*!< GPIO5INCFG (Bit 20)                                   */
11946 #define GPIO_CFGA_GPIO5INCFG_Msk          (0x100000UL)              /*!< GPIO5INCFG (Bitfield-Mask: 0x01)                      */
11947 #define GPIO_CFGA_GPIO4INTD_Pos           (19UL)                    /*!< GPIO4INTD (Bit 19)                                    */
11948 #define GPIO_CFGA_GPIO4INTD_Msk           (0x80000UL)               /*!< GPIO4INTD (Bitfield-Mask: 0x01)                       */
11949 #define GPIO_CFGA_GPIO4OUTCFG_Pos         (17UL)                    /*!< GPIO4OUTCFG (Bit 17)                                  */
11950 #define GPIO_CFGA_GPIO4OUTCFG_Msk         (0x60000UL)               /*!< GPIO4OUTCFG (Bitfield-Mask: 0x03)                     */
11951 #define GPIO_CFGA_GPIO4INCFG_Pos          (16UL)                    /*!< GPIO4INCFG (Bit 16)                                   */
11952 #define GPIO_CFGA_GPIO4INCFG_Msk          (0x10000UL)               /*!< GPIO4INCFG (Bitfield-Mask: 0x01)                      */
11953 #define GPIO_CFGA_GPIO3INTD_Pos           (15UL)                    /*!< GPIO3INTD (Bit 15)                                    */
11954 #define GPIO_CFGA_GPIO3INTD_Msk           (0x8000UL)                /*!< GPIO3INTD (Bitfield-Mask: 0x01)                       */
11955 #define GPIO_CFGA_GPIO3OUTCFG_Pos         (13UL)                    /*!< GPIO3OUTCFG (Bit 13)                                  */
11956 #define GPIO_CFGA_GPIO3OUTCFG_Msk         (0x6000UL)                /*!< GPIO3OUTCFG (Bitfield-Mask: 0x03)                     */
11957 #define GPIO_CFGA_GPIO3INCFG_Pos          (12UL)                    /*!< GPIO3INCFG (Bit 12)                                   */
11958 #define GPIO_CFGA_GPIO3INCFG_Msk          (0x1000UL)                /*!< GPIO3INCFG (Bitfield-Mask: 0x01)                      */
11959 #define GPIO_CFGA_GPIO2INTD_Pos           (11UL)                    /*!< GPIO2INTD (Bit 11)                                    */
11960 #define GPIO_CFGA_GPIO2INTD_Msk           (0x800UL)                 /*!< GPIO2INTD (Bitfield-Mask: 0x01)                       */
11961 #define GPIO_CFGA_GPIO2OUTCFG_Pos         (9UL)                     /*!< GPIO2OUTCFG (Bit 9)                                   */
11962 #define GPIO_CFGA_GPIO2OUTCFG_Msk         (0x600UL)                 /*!< GPIO2OUTCFG (Bitfield-Mask: 0x03)                     */
11963 #define GPIO_CFGA_GPIO2INCFG_Pos          (8UL)                     /*!< GPIO2INCFG (Bit 8)                                    */
11964 #define GPIO_CFGA_GPIO2INCFG_Msk          (0x100UL)                 /*!< GPIO2INCFG (Bitfield-Mask: 0x01)                      */
11965 #define GPIO_CFGA_GPIO1INTD_Pos           (7UL)                     /*!< GPIO1INTD (Bit 7)                                     */
11966 #define GPIO_CFGA_GPIO1INTD_Msk           (0x80UL)                  /*!< GPIO1INTD (Bitfield-Mask: 0x01)                       */
11967 #define GPIO_CFGA_GPIO1OUTCFG_Pos         (5UL)                     /*!< GPIO1OUTCFG (Bit 5)                                   */
11968 #define GPIO_CFGA_GPIO1OUTCFG_Msk         (0x60UL)                  /*!< GPIO1OUTCFG (Bitfield-Mask: 0x03)                     */
11969 #define GPIO_CFGA_GPIO1INCFG_Pos          (4UL)                     /*!< GPIO1INCFG (Bit 4)                                    */
11970 #define GPIO_CFGA_GPIO1INCFG_Msk          (0x10UL)                  /*!< GPIO1INCFG (Bitfield-Mask: 0x01)                      */
11971 #define GPIO_CFGA_GPIO0INTD_Pos           (3UL)                     /*!< GPIO0INTD (Bit 3)                                     */
11972 #define GPIO_CFGA_GPIO0INTD_Msk           (0x8UL)                   /*!< GPIO0INTD (Bitfield-Mask: 0x01)                       */
11973 #define GPIO_CFGA_GPIO0OUTCFG_Pos         (1UL)                     /*!< GPIO0OUTCFG (Bit 1)                                   */
11974 #define GPIO_CFGA_GPIO0OUTCFG_Msk         (0x6UL)                   /*!< GPIO0OUTCFG (Bitfield-Mask: 0x03)                     */
11975 #define GPIO_CFGA_GPIO0INCFG_Pos          (0UL)                     /*!< GPIO0INCFG (Bit 0)                                    */
11976 #define GPIO_CFGA_GPIO0INCFG_Msk          (0x1UL)                   /*!< GPIO0INCFG (Bitfield-Mask: 0x01)                      */
11977 /* =========================================================  CFGB  ========================================================== */
11978 #define GPIO_CFGB_GPIO15INTD_Pos          (31UL)                    /*!< GPIO15INTD (Bit 31)                                   */
11979 #define GPIO_CFGB_GPIO15INTD_Msk          (0x80000000UL)            /*!< GPIO15INTD (Bitfield-Mask: 0x01)                      */
11980 #define GPIO_CFGB_GPIO15OUTCFG_Pos        (29UL)                    /*!< GPIO15OUTCFG (Bit 29)                                 */
11981 #define GPIO_CFGB_GPIO15OUTCFG_Msk        (0x60000000UL)            /*!< GPIO15OUTCFG (Bitfield-Mask: 0x03)                    */
11982 #define GPIO_CFGB_GPIO15INCFG_Pos         (28UL)                    /*!< GPIO15INCFG (Bit 28)                                  */
11983 #define GPIO_CFGB_GPIO15INCFG_Msk         (0x10000000UL)            /*!< GPIO15INCFG (Bitfield-Mask: 0x01)                     */
11984 #define GPIO_CFGB_GPIO14INTD_Pos          (27UL)                    /*!< GPIO14INTD (Bit 27)                                   */
11985 #define GPIO_CFGB_GPIO14INTD_Msk          (0x8000000UL)             /*!< GPIO14INTD (Bitfield-Mask: 0x01)                      */
11986 #define GPIO_CFGB_GPIO14OUTCFG_Pos        (25UL)                    /*!< GPIO14OUTCFG (Bit 25)                                 */
11987 #define GPIO_CFGB_GPIO14OUTCFG_Msk        (0x6000000UL)             /*!< GPIO14OUTCFG (Bitfield-Mask: 0x03)                    */
11988 #define GPIO_CFGB_GPIO14INCFG_Pos         (24UL)                    /*!< GPIO14INCFG (Bit 24)                                  */
11989 #define GPIO_CFGB_GPIO14INCFG_Msk         (0x1000000UL)             /*!< GPIO14INCFG (Bitfield-Mask: 0x01)                     */
11990 #define GPIO_CFGB_GPIO13INTD_Pos          (23UL)                    /*!< GPIO13INTD (Bit 23)                                   */
11991 #define GPIO_CFGB_GPIO13INTD_Msk          (0x800000UL)              /*!< GPIO13INTD (Bitfield-Mask: 0x01)                      */
11992 #define GPIO_CFGB_GPIO13OUTCFG_Pos        (21UL)                    /*!< GPIO13OUTCFG (Bit 21)                                 */
11993 #define GPIO_CFGB_GPIO13OUTCFG_Msk        (0x600000UL)              /*!< GPIO13OUTCFG (Bitfield-Mask: 0x03)                    */
11994 #define GPIO_CFGB_GPIO13INCFG_Pos         (20UL)                    /*!< GPIO13INCFG (Bit 20)                                  */
11995 #define GPIO_CFGB_GPIO13INCFG_Msk         (0x100000UL)              /*!< GPIO13INCFG (Bitfield-Mask: 0x01)                     */
11996 #define GPIO_CFGB_GPIO12INTD_Pos          (19UL)                    /*!< GPIO12INTD (Bit 19)                                   */
11997 #define GPIO_CFGB_GPIO12INTD_Msk          (0x80000UL)               /*!< GPIO12INTD (Bitfield-Mask: 0x01)                      */
11998 #define GPIO_CFGB_GPIO12OUTCFG_Pos        (17UL)                    /*!< GPIO12OUTCFG (Bit 17)                                 */
11999 #define GPIO_CFGB_GPIO12OUTCFG_Msk        (0x60000UL)               /*!< GPIO12OUTCFG (Bitfield-Mask: 0x03)                    */
12000 #define GPIO_CFGB_GPIO12INCFG_Pos         (16UL)                    /*!< GPIO12INCFG (Bit 16)                                  */
12001 #define GPIO_CFGB_GPIO12INCFG_Msk         (0x10000UL)               /*!< GPIO12INCFG (Bitfield-Mask: 0x01)                     */
12002 #define GPIO_CFGB_GPIO11INTD_Pos          (15UL)                    /*!< GPIO11INTD (Bit 15)                                   */
12003 #define GPIO_CFGB_GPIO11INTD_Msk          (0x8000UL)                /*!< GPIO11INTD (Bitfield-Mask: 0x01)                      */
12004 #define GPIO_CFGB_GPIO11OUTCFG_Pos        (13UL)                    /*!< GPIO11OUTCFG (Bit 13)                                 */
12005 #define GPIO_CFGB_GPIO11OUTCFG_Msk        (0x6000UL)                /*!< GPIO11OUTCFG (Bitfield-Mask: 0x03)                    */
12006 #define GPIO_CFGB_GPIO11INCFG_Pos         (12UL)                    /*!< GPIO11INCFG (Bit 12)                                  */
12007 #define GPIO_CFGB_GPIO11INCFG_Msk         (0x1000UL)                /*!< GPIO11INCFG (Bitfield-Mask: 0x01)                     */
12008 #define GPIO_CFGB_GPIO10INTD_Pos          (11UL)                    /*!< GPIO10INTD (Bit 11)                                   */
12009 #define GPIO_CFGB_GPIO10INTD_Msk          (0x800UL)                 /*!< GPIO10INTD (Bitfield-Mask: 0x01)                      */
12010 #define GPIO_CFGB_GPIO10OUTCFG_Pos        (9UL)                     /*!< GPIO10OUTCFG (Bit 9)                                  */
12011 #define GPIO_CFGB_GPIO10OUTCFG_Msk        (0x600UL)                 /*!< GPIO10OUTCFG (Bitfield-Mask: 0x03)                    */
12012 #define GPIO_CFGB_GPIO10INCFG_Pos         (8UL)                     /*!< GPIO10INCFG (Bit 8)                                   */
12013 #define GPIO_CFGB_GPIO10INCFG_Msk         (0x100UL)                 /*!< GPIO10INCFG (Bitfield-Mask: 0x01)                     */
12014 #define GPIO_CFGB_GPIO9INTD_Pos           (7UL)                     /*!< GPIO9INTD (Bit 7)                                     */
12015 #define GPIO_CFGB_GPIO9INTD_Msk           (0x80UL)                  /*!< GPIO9INTD (Bitfield-Mask: 0x01)                       */
12016 #define GPIO_CFGB_GPIO9OUTCFG_Pos         (5UL)                     /*!< GPIO9OUTCFG (Bit 5)                                   */
12017 #define GPIO_CFGB_GPIO9OUTCFG_Msk         (0x60UL)                  /*!< GPIO9OUTCFG (Bitfield-Mask: 0x03)                     */
12018 #define GPIO_CFGB_GPIO9INCFG_Pos          (4UL)                     /*!< GPIO9INCFG (Bit 4)                                    */
12019 #define GPIO_CFGB_GPIO9INCFG_Msk          (0x10UL)                  /*!< GPIO9INCFG (Bitfield-Mask: 0x01)                      */
12020 #define GPIO_CFGB_GPIO8INTD_Pos           (3UL)                     /*!< GPIO8INTD (Bit 3)                                     */
12021 #define GPIO_CFGB_GPIO8INTD_Msk           (0x8UL)                   /*!< GPIO8INTD (Bitfield-Mask: 0x01)                       */
12022 #define GPIO_CFGB_GPIO8OUTCFG_Pos         (1UL)                     /*!< GPIO8OUTCFG (Bit 1)                                   */
12023 #define GPIO_CFGB_GPIO8OUTCFG_Msk         (0x6UL)                   /*!< GPIO8OUTCFG (Bitfield-Mask: 0x03)                     */
12024 #define GPIO_CFGB_GPIO8INCFG_Pos          (0UL)                     /*!< GPIO8INCFG (Bit 0)                                    */
12025 #define GPIO_CFGB_GPIO8INCFG_Msk          (0x1UL)                   /*!< GPIO8INCFG (Bitfield-Mask: 0x01)                      */
12026 /* =========================================================  CFGC  ========================================================== */
12027 #define GPIO_CFGC_GPIO23INTD_Pos          (31UL)                    /*!< GPIO23INTD (Bit 31)                                   */
12028 #define GPIO_CFGC_GPIO23INTD_Msk          (0x80000000UL)            /*!< GPIO23INTD (Bitfield-Mask: 0x01)                      */
12029 #define GPIO_CFGC_GPIO23OUTCFG_Pos        (29UL)                    /*!< GPIO23OUTCFG (Bit 29)                                 */
12030 #define GPIO_CFGC_GPIO23OUTCFG_Msk        (0x60000000UL)            /*!< GPIO23OUTCFG (Bitfield-Mask: 0x03)                    */
12031 #define GPIO_CFGC_GPIO23INCFG_Pos         (28UL)                    /*!< GPIO23INCFG (Bit 28)                                  */
12032 #define GPIO_CFGC_GPIO23INCFG_Msk         (0x10000000UL)            /*!< GPIO23INCFG (Bitfield-Mask: 0x01)                     */
12033 #define GPIO_CFGC_GPIO22INTD_Pos          (27UL)                    /*!< GPIO22INTD (Bit 27)                                   */
12034 #define GPIO_CFGC_GPIO22INTD_Msk          (0x8000000UL)             /*!< GPIO22INTD (Bitfield-Mask: 0x01)                      */
12035 #define GPIO_CFGC_GPIO22OUTCFG_Pos        (25UL)                    /*!< GPIO22OUTCFG (Bit 25)                                 */
12036 #define GPIO_CFGC_GPIO22OUTCFG_Msk        (0x6000000UL)             /*!< GPIO22OUTCFG (Bitfield-Mask: 0x03)                    */
12037 #define GPIO_CFGC_GPIO22INCFG_Pos         (24UL)                    /*!< GPIO22INCFG (Bit 24)                                  */
12038 #define GPIO_CFGC_GPIO22INCFG_Msk         (0x1000000UL)             /*!< GPIO22INCFG (Bitfield-Mask: 0x01)                     */
12039 #define GPIO_CFGC_GPIO21INTD_Pos          (23UL)                    /*!< GPIO21INTD (Bit 23)                                   */
12040 #define GPIO_CFGC_GPIO21INTD_Msk          (0x800000UL)              /*!< GPIO21INTD (Bitfield-Mask: 0x01)                      */
12041 #define GPIO_CFGC_GPIO21OUTCFG_Pos        (21UL)                    /*!< GPIO21OUTCFG (Bit 21)                                 */
12042 #define GPIO_CFGC_GPIO21OUTCFG_Msk        (0x600000UL)              /*!< GPIO21OUTCFG (Bitfield-Mask: 0x03)                    */
12043 #define GPIO_CFGC_GPIO21INCFG_Pos         (20UL)                    /*!< GPIO21INCFG (Bit 20)                                  */
12044 #define GPIO_CFGC_GPIO21INCFG_Msk         (0x100000UL)              /*!< GPIO21INCFG (Bitfield-Mask: 0x01)                     */
12045 #define GPIO_CFGC_GPIO20INTD_Pos          (19UL)                    /*!< GPIO20INTD (Bit 19)                                   */
12046 #define GPIO_CFGC_GPIO20INTD_Msk          (0x80000UL)               /*!< GPIO20INTD (Bitfield-Mask: 0x01)                      */
12047 #define GPIO_CFGC_GPIO20OUTCFG_Pos        (17UL)                    /*!< GPIO20OUTCFG (Bit 17)                                 */
12048 #define GPIO_CFGC_GPIO20OUTCFG_Msk        (0x60000UL)               /*!< GPIO20OUTCFG (Bitfield-Mask: 0x03)                    */
12049 #define GPIO_CFGC_GPIO20INCFG_Pos         (16UL)                    /*!< GPIO20INCFG (Bit 16)                                  */
12050 #define GPIO_CFGC_GPIO20INCFG_Msk         (0x10000UL)               /*!< GPIO20INCFG (Bitfield-Mask: 0x01)                     */
12051 #define GPIO_CFGC_GPIO19INTD_Pos          (15UL)                    /*!< GPIO19INTD (Bit 15)                                   */
12052 #define GPIO_CFGC_GPIO19INTD_Msk          (0x8000UL)                /*!< GPIO19INTD (Bitfield-Mask: 0x01)                      */
12053 #define GPIO_CFGC_GPIO19OUTCFG_Pos        (13UL)                    /*!< GPIO19OUTCFG (Bit 13)                                 */
12054 #define GPIO_CFGC_GPIO19OUTCFG_Msk        (0x6000UL)                /*!< GPIO19OUTCFG (Bitfield-Mask: 0x03)                    */
12055 #define GPIO_CFGC_GPIO19INCFG_Pos         (12UL)                    /*!< GPIO19INCFG (Bit 12)                                  */
12056 #define GPIO_CFGC_GPIO19INCFG_Msk         (0x1000UL)                /*!< GPIO19INCFG (Bitfield-Mask: 0x01)                     */
12057 #define GPIO_CFGC_GPIO18INTD_Pos          (11UL)                    /*!< GPIO18INTD (Bit 11)                                   */
12058 #define GPIO_CFGC_GPIO18INTD_Msk          (0x800UL)                 /*!< GPIO18INTD (Bitfield-Mask: 0x01)                      */
12059 #define GPIO_CFGC_GPIO18OUTCFG_Pos        (9UL)                     /*!< GPIO18OUTCFG (Bit 9)                                  */
12060 #define GPIO_CFGC_GPIO18OUTCFG_Msk        (0x600UL)                 /*!< GPIO18OUTCFG (Bitfield-Mask: 0x03)                    */
12061 #define GPIO_CFGC_GPIO18INCFG_Pos         (8UL)                     /*!< GPIO18INCFG (Bit 8)                                   */
12062 #define GPIO_CFGC_GPIO18INCFG_Msk         (0x100UL)                 /*!< GPIO18INCFG (Bitfield-Mask: 0x01)                     */
12063 #define GPIO_CFGC_GPIO17INTD_Pos          (7UL)                     /*!< GPIO17INTD (Bit 7)                                    */
12064 #define GPIO_CFGC_GPIO17INTD_Msk          (0x80UL)                  /*!< GPIO17INTD (Bitfield-Mask: 0x01)                      */
12065 #define GPIO_CFGC_GPIO17OUTCFG_Pos        (5UL)                     /*!< GPIO17OUTCFG (Bit 5)                                  */
12066 #define GPIO_CFGC_GPIO17OUTCFG_Msk        (0x60UL)                  /*!< GPIO17OUTCFG (Bitfield-Mask: 0x03)                    */
12067 #define GPIO_CFGC_GPIO17INCFG_Pos         (4UL)                     /*!< GPIO17INCFG (Bit 4)                                   */
12068 #define GPIO_CFGC_GPIO17INCFG_Msk         (0x10UL)                  /*!< GPIO17INCFG (Bitfield-Mask: 0x01)                     */
12069 #define GPIO_CFGC_GPIO16INTD_Pos          (3UL)                     /*!< GPIO16INTD (Bit 3)                                    */
12070 #define GPIO_CFGC_GPIO16INTD_Msk          (0x8UL)                   /*!< GPIO16INTD (Bitfield-Mask: 0x01)                      */
12071 #define GPIO_CFGC_GPIO16OUTCFG_Pos        (1UL)                     /*!< GPIO16OUTCFG (Bit 1)                                  */
12072 #define GPIO_CFGC_GPIO16OUTCFG_Msk        (0x6UL)                   /*!< GPIO16OUTCFG (Bitfield-Mask: 0x03)                    */
12073 #define GPIO_CFGC_GPIO16INCFG_Pos         (0UL)                     /*!< GPIO16INCFG (Bit 0)                                   */
12074 #define GPIO_CFGC_GPIO16INCFG_Msk         (0x1UL)                   /*!< GPIO16INCFG (Bitfield-Mask: 0x01)                     */
12075 /* =========================================================  CFGD  ========================================================== */
12076 #define GPIO_CFGD_GPIO31INTD_Pos          (31UL)                    /*!< GPIO31INTD (Bit 31)                                   */
12077 #define GPIO_CFGD_GPIO31INTD_Msk          (0x80000000UL)            /*!< GPIO31INTD (Bitfield-Mask: 0x01)                      */
12078 #define GPIO_CFGD_GPIO31OUTCFG_Pos        (29UL)                    /*!< GPIO31OUTCFG (Bit 29)                                 */
12079 #define GPIO_CFGD_GPIO31OUTCFG_Msk        (0x60000000UL)            /*!< GPIO31OUTCFG (Bitfield-Mask: 0x03)                    */
12080 #define GPIO_CFGD_GPIO31INCFG_Pos         (28UL)                    /*!< GPIO31INCFG (Bit 28)                                  */
12081 #define GPIO_CFGD_GPIO31INCFG_Msk         (0x10000000UL)            /*!< GPIO31INCFG (Bitfield-Mask: 0x01)                     */
12082 #define GPIO_CFGD_GPIO30INTD_Pos          (27UL)                    /*!< GPIO30INTD (Bit 27)                                   */
12083 #define GPIO_CFGD_GPIO30INTD_Msk          (0x8000000UL)             /*!< GPIO30INTD (Bitfield-Mask: 0x01)                      */
12084 #define GPIO_CFGD_GPIO30OUTCFG_Pos        (25UL)                    /*!< GPIO30OUTCFG (Bit 25)                                 */
12085 #define GPIO_CFGD_GPIO30OUTCFG_Msk        (0x6000000UL)             /*!< GPIO30OUTCFG (Bitfield-Mask: 0x03)                    */
12086 #define GPIO_CFGD_GPIO30INCFG_Pos         (24UL)                    /*!< GPIO30INCFG (Bit 24)                                  */
12087 #define GPIO_CFGD_GPIO30INCFG_Msk         (0x1000000UL)             /*!< GPIO30INCFG (Bitfield-Mask: 0x01)                     */
12088 #define GPIO_CFGD_GPIO29INTD_Pos          (23UL)                    /*!< GPIO29INTD (Bit 23)                                   */
12089 #define GPIO_CFGD_GPIO29INTD_Msk          (0x800000UL)              /*!< GPIO29INTD (Bitfield-Mask: 0x01)                      */
12090 #define GPIO_CFGD_GPIO29OUTCFG_Pos        (21UL)                    /*!< GPIO29OUTCFG (Bit 21)                                 */
12091 #define GPIO_CFGD_GPIO29OUTCFG_Msk        (0x600000UL)              /*!< GPIO29OUTCFG (Bitfield-Mask: 0x03)                    */
12092 #define GPIO_CFGD_GPIO29INCFG_Pos         (20UL)                    /*!< GPIO29INCFG (Bit 20)                                  */
12093 #define GPIO_CFGD_GPIO29INCFG_Msk         (0x100000UL)              /*!< GPIO29INCFG (Bitfield-Mask: 0x01)                     */
12094 #define GPIO_CFGD_GPIO28INTD_Pos          (19UL)                    /*!< GPIO28INTD (Bit 19)                                   */
12095 #define GPIO_CFGD_GPIO28INTD_Msk          (0x80000UL)               /*!< GPIO28INTD (Bitfield-Mask: 0x01)                      */
12096 #define GPIO_CFGD_GPIO28OUTCFG_Pos        (17UL)                    /*!< GPIO28OUTCFG (Bit 17)                                 */
12097 #define GPIO_CFGD_GPIO28OUTCFG_Msk        (0x60000UL)               /*!< GPIO28OUTCFG (Bitfield-Mask: 0x03)                    */
12098 #define GPIO_CFGD_GPIO28INCFG_Pos         (16UL)                    /*!< GPIO28INCFG (Bit 16)                                  */
12099 #define GPIO_CFGD_GPIO28INCFG_Msk         (0x10000UL)               /*!< GPIO28INCFG (Bitfield-Mask: 0x01)                     */
12100 #define GPIO_CFGD_GPIO27INTD_Pos          (15UL)                    /*!< GPIO27INTD (Bit 15)                                   */
12101 #define GPIO_CFGD_GPIO27INTD_Msk          (0x8000UL)                /*!< GPIO27INTD (Bitfield-Mask: 0x01)                      */
12102 #define GPIO_CFGD_GPIO27OUTCFG_Pos        (13UL)                    /*!< GPIO27OUTCFG (Bit 13)                                 */
12103 #define GPIO_CFGD_GPIO27OUTCFG_Msk        (0x6000UL)                /*!< GPIO27OUTCFG (Bitfield-Mask: 0x03)                    */
12104 #define GPIO_CFGD_GPIO27INCFG_Pos         (12UL)                    /*!< GPIO27INCFG (Bit 12)                                  */
12105 #define GPIO_CFGD_GPIO27INCFG_Msk         (0x1000UL)                /*!< GPIO27INCFG (Bitfield-Mask: 0x01)                     */
12106 #define GPIO_CFGD_GPIO26INTD_Pos          (11UL)                    /*!< GPIO26INTD (Bit 11)                                   */
12107 #define GPIO_CFGD_GPIO26INTD_Msk          (0x800UL)                 /*!< GPIO26INTD (Bitfield-Mask: 0x01)                      */
12108 #define GPIO_CFGD_GPIO26OUTCFG_Pos        (9UL)                     /*!< GPIO26OUTCFG (Bit 9)                                  */
12109 #define GPIO_CFGD_GPIO26OUTCFG_Msk        (0x600UL)                 /*!< GPIO26OUTCFG (Bitfield-Mask: 0x03)                    */
12110 #define GPIO_CFGD_GPIO26INCFG_Pos         (8UL)                     /*!< GPIO26INCFG (Bit 8)                                   */
12111 #define GPIO_CFGD_GPIO26INCFG_Msk         (0x100UL)                 /*!< GPIO26INCFG (Bitfield-Mask: 0x01)                     */
12112 #define GPIO_CFGD_GPIO25INTD_Pos          (7UL)                     /*!< GPIO25INTD (Bit 7)                                    */
12113 #define GPIO_CFGD_GPIO25INTD_Msk          (0x80UL)                  /*!< GPIO25INTD (Bitfield-Mask: 0x01)                      */
12114 #define GPIO_CFGD_GPIO25OUTCFG_Pos        (5UL)                     /*!< GPIO25OUTCFG (Bit 5)                                  */
12115 #define GPIO_CFGD_GPIO25OUTCFG_Msk        (0x60UL)                  /*!< GPIO25OUTCFG (Bitfield-Mask: 0x03)                    */
12116 #define GPIO_CFGD_GPIO25INCFG_Pos         (4UL)                     /*!< GPIO25INCFG (Bit 4)                                   */
12117 #define GPIO_CFGD_GPIO25INCFG_Msk         (0x10UL)                  /*!< GPIO25INCFG (Bitfield-Mask: 0x01)                     */
12118 #define GPIO_CFGD_GPIO24INTD_Pos          (3UL)                     /*!< GPIO24INTD (Bit 3)                                    */
12119 #define GPIO_CFGD_GPIO24INTD_Msk          (0x8UL)                   /*!< GPIO24INTD (Bitfield-Mask: 0x01)                      */
12120 #define GPIO_CFGD_GPIO24OUTCFG_Pos        (1UL)                     /*!< GPIO24OUTCFG (Bit 1)                                  */
12121 #define GPIO_CFGD_GPIO24OUTCFG_Msk        (0x6UL)                   /*!< GPIO24OUTCFG (Bitfield-Mask: 0x03)                    */
12122 #define GPIO_CFGD_GPIO24INCFG_Pos         (0UL)                     /*!< GPIO24INCFG (Bit 0)                                   */
12123 #define GPIO_CFGD_GPIO24INCFG_Msk         (0x1UL)                   /*!< GPIO24INCFG (Bitfield-Mask: 0x01)                     */
12124 /* =========================================================  CFGE  ========================================================== */
12125 #define GPIO_CFGE_GPIO39INTD_Pos          (31UL)                    /*!< GPIO39INTD (Bit 31)                                   */
12126 #define GPIO_CFGE_GPIO39INTD_Msk          (0x80000000UL)            /*!< GPIO39INTD (Bitfield-Mask: 0x01)                      */
12127 #define GPIO_CFGE_GPIO39OUTCFG_Pos        (29UL)                    /*!< GPIO39OUTCFG (Bit 29)                                 */
12128 #define GPIO_CFGE_GPIO39OUTCFG_Msk        (0x60000000UL)            /*!< GPIO39OUTCFG (Bitfield-Mask: 0x03)                    */
12129 #define GPIO_CFGE_GPIO39INCFG_Pos         (28UL)                    /*!< GPIO39INCFG (Bit 28)                                  */
12130 #define GPIO_CFGE_GPIO39INCFG_Msk         (0x10000000UL)            /*!< GPIO39INCFG (Bitfield-Mask: 0x01)                     */
12131 #define GPIO_CFGE_GPIO38INTD_Pos          (27UL)                    /*!< GPIO38INTD (Bit 27)                                   */
12132 #define GPIO_CFGE_GPIO38INTD_Msk          (0x8000000UL)             /*!< GPIO38INTD (Bitfield-Mask: 0x01)                      */
12133 #define GPIO_CFGE_GPIO38OUTCFG_Pos        (25UL)                    /*!< GPIO38OUTCFG (Bit 25)                                 */
12134 #define GPIO_CFGE_GPIO38OUTCFG_Msk        (0x6000000UL)             /*!< GPIO38OUTCFG (Bitfield-Mask: 0x03)                    */
12135 #define GPIO_CFGE_GPIO38INCFG_Pos         (24UL)                    /*!< GPIO38INCFG (Bit 24)                                  */
12136 #define GPIO_CFGE_GPIO38INCFG_Msk         (0x1000000UL)             /*!< GPIO38INCFG (Bitfield-Mask: 0x01)                     */
12137 #define GPIO_CFGE_GPIO37INTD_Pos          (23UL)                    /*!< GPIO37INTD (Bit 23)                                   */
12138 #define GPIO_CFGE_GPIO37INTD_Msk          (0x800000UL)              /*!< GPIO37INTD (Bitfield-Mask: 0x01)                      */
12139 #define GPIO_CFGE_GPIO37OUTCFG_Pos        (21UL)                    /*!< GPIO37OUTCFG (Bit 21)                                 */
12140 #define GPIO_CFGE_GPIO37OUTCFG_Msk        (0x600000UL)              /*!< GPIO37OUTCFG (Bitfield-Mask: 0x03)                    */
12141 #define GPIO_CFGE_GPIO37INCFG_Pos         (20UL)                    /*!< GPIO37INCFG (Bit 20)                                  */
12142 #define GPIO_CFGE_GPIO37INCFG_Msk         (0x100000UL)              /*!< GPIO37INCFG (Bitfield-Mask: 0x01)                     */
12143 #define GPIO_CFGE_GPIO36INTD_Pos          (19UL)                    /*!< GPIO36INTD (Bit 19)                                   */
12144 #define GPIO_CFGE_GPIO36INTD_Msk          (0x80000UL)               /*!< GPIO36INTD (Bitfield-Mask: 0x01)                      */
12145 #define GPIO_CFGE_GPIO36OUTCFG_Pos        (17UL)                    /*!< GPIO36OUTCFG (Bit 17)                                 */
12146 #define GPIO_CFGE_GPIO36OUTCFG_Msk        (0x60000UL)               /*!< GPIO36OUTCFG (Bitfield-Mask: 0x03)                    */
12147 #define GPIO_CFGE_GPIO36INCFG_Pos         (16UL)                    /*!< GPIO36INCFG (Bit 16)                                  */
12148 #define GPIO_CFGE_GPIO36INCFG_Msk         (0x10000UL)               /*!< GPIO36INCFG (Bitfield-Mask: 0x01)                     */
12149 #define GPIO_CFGE_GPIO35INTD_Pos          (15UL)                    /*!< GPIO35INTD (Bit 15)                                   */
12150 #define GPIO_CFGE_GPIO35INTD_Msk          (0x8000UL)                /*!< GPIO35INTD (Bitfield-Mask: 0x01)                      */
12151 #define GPIO_CFGE_GPIO35OUTCFG_Pos        (13UL)                    /*!< GPIO35OUTCFG (Bit 13)                                 */
12152 #define GPIO_CFGE_GPIO35OUTCFG_Msk        (0x6000UL)                /*!< GPIO35OUTCFG (Bitfield-Mask: 0x03)                    */
12153 #define GPIO_CFGE_GPIO35INCFG_Pos         (12UL)                    /*!< GPIO35INCFG (Bit 12)                                  */
12154 #define GPIO_CFGE_GPIO35INCFG_Msk         (0x1000UL)                /*!< GPIO35INCFG (Bitfield-Mask: 0x01)                     */
12155 #define GPIO_CFGE_GPIO34INTD_Pos          (11UL)                    /*!< GPIO34INTD (Bit 11)                                   */
12156 #define GPIO_CFGE_GPIO34INTD_Msk          (0x800UL)                 /*!< GPIO34INTD (Bitfield-Mask: 0x01)                      */
12157 #define GPIO_CFGE_GPIO34OUTCFG_Pos        (9UL)                     /*!< GPIO34OUTCFG (Bit 9)                                  */
12158 #define GPIO_CFGE_GPIO34OUTCFG_Msk        (0x600UL)                 /*!< GPIO34OUTCFG (Bitfield-Mask: 0x03)                    */
12159 #define GPIO_CFGE_GPIO34INCFG_Pos         (8UL)                     /*!< GPIO34INCFG (Bit 8)                                   */
12160 #define GPIO_CFGE_GPIO34INCFG_Msk         (0x100UL)                 /*!< GPIO34INCFG (Bitfield-Mask: 0x01)                     */
12161 #define GPIO_CFGE_GPIO33INTD_Pos          (7UL)                     /*!< GPIO33INTD (Bit 7)                                    */
12162 #define GPIO_CFGE_GPIO33INTD_Msk          (0x80UL)                  /*!< GPIO33INTD (Bitfield-Mask: 0x01)                      */
12163 #define GPIO_CFGE_GPIO33OUTCFG_Pos        (5UL)                     /*!< GPIO33OUTCFG (Bit 5)                                  */
12164 #define GPIO_CFGE_GPIO33OUTCFG_Msk        (0x60UL)                  /*!< GPIO33OUTCFG (Bitfield-Mask: 0x03)                    */
12165 #define GPIO_CFGE_GPIO33INCFG_Pos         (4UL)                     /*!< GPIO33INCFG (Bit 4)                                   */
12166 #define GPIO_CFGE_GPIO33INCFG_Msk         (0x10UL)                  /*!< GPIO33INCFG (Bitfield-Mask: 0x01)                     */
12167 #define GPIO_CFGE_GPIO32INTD_Pos          (3UL)                     /*!< GPIO32INTD (Bit 3)                                    */
12168 #define GPIO_CFGE_GPIO32INTD_Msk          (0x8UL)                   /*!< GPIO32INTD (Bitfield-Mask: 0x01)                      */
12169 #define GPIO_CFGE_GPIO32OUTCFG_Pos        (1UL)                     /*!< GPIO32OUTCFG (Bit 1)                                  */
12170 #define GPIO_CFGE_GPIO32OUTCFG_Msk        (0x6UL)                   /*!< GPIO32OUTCFG (Bitfield-Mask: 0x03)                    */
12171 #define GPIO_CFGE_GPIO32INCFG_Pos         (0UL)                     /*!< GPIO32INCFG (Bit 0)                                   */
12172 #define GPIO_CFGE_GPIO32INCFG_Msk         (0x1UL)                   /*!< GPIO32INCFG (Bitfield-Mask: 0x01)                     */
12173 /* =========================================================  CFGF  ========================================================== */
12174 #define GPIO_CFGF_GPIO47INTD_Pos          (31UL)                    /*!< GPIO47INTD (Bit 31)                                   */
12175 #define GPIO_CFGF_GPIO47INTD_Msk          (0x80000000UL)            /*!< GPIO47INTD (Bitfield-Mask: 0x01)                      */
12176 #define GPIO_CFGF_GPIO47OUTCFG_Pos        (29UL)                    /*!< GPIO47OUTCFG (Bit 29)                                 */
12177 #define GPIO_CFGF_GPIO47OUTCFG_Msk        (0x60000000UL)            /*!< GPIO47OUTCFG (Bitfield-Mask: 0x03)                    */
12178 #define GPIO_CFGF_GPIO47INCFG_Pos         (28UL)                    /*!< GPIO47INCFG (Bit 28)                                  */
12179 #define GPIO_CFGF_GPIO47INCFG_Msk         (0x10000000UL)            /*!< GPIO47INCFG (Bitfield-Mask: 0x01)                     */
12180 #define GPIO_CFGF_GPIO46INTD_Pos          (27UL)                    /*!< GPIO46INTD (Bit 27)                                   */
12181 #define GPIO_CFGF_GPIO46INTD_Msk          (0x8000000UL)             /*!< GPIO46INTD (Bitfield-Mask: 0x01)                      */
12182 #define GPIO_CFGF_GPIO46OUTCFG_Pos        (25UL)                    /*!< GPIO46OUTCFG (Bit 25)                                 */
12183 #define GPIO_CFGF_GPIO46OUTCFG_Msk        (0x6000000UL)             /*!< GPIO46OUTCFG (Bitfield-Mask: 0x03)                    */
12184 #define GPIO_CFGF_GPIO46INCFG_Pos         (24UL)                    /*!< GPIO46INCFG (Bit 24)                                  */
12185 #define GPIO_CFGF_GPIO46INCFG_Msk         (0x1000000UL)             /*!< GPIO46INCFG (Bitfield-Mask: 0x01)                     */
12186 #define GPIO_CFGF_GPIO45INTD_Pos          (23UL)                    /*!< GPIO45INTD (Bit 23)                                   */
12187 #define GPIO_CFGF_GPIO45INTD_Msk          (0x800000UL)              /*!< GPIO45INTD (Bitfield-Mask: 0x01)                      */
12188 #define GPIO_CFGF_GPIO45OUTCFG_Pos        (21UL)                    /*!< GPIO45OUTCFG (Bit 21)                                 */
12189 #define GPIO_CFGF_GPIO45OUTCFG_Msk        (0x600000UL)              /*!< GPIO45OUTCFG (Bitfield-Mask: 0x03)                    */
12190 #define GPIO_CFGF_GPIO45INCFG_Pos         (20UL)                    /*!< GPIO45INCFG (Bit 20)                                  */
12191 #define GPIO_CFGF_GPIO45INCFG_Msk         (0x100000UL)              /*!< GPIO45INCFG (Bitfield-Mask: 0x01)                     */
12192 #define GPIO_CFGF_GPIO44INTD_Pos          (19UL)                    /*!< GPIO44INTD (Bit 19)                                   */
12193 #define GPIO_CFGF_GPIO44INTD_Msk          (0x80000UL)               /*!< GPIO44INTD (Bitfield-Mask: 0x01)                      */
12194 #define GPIO_CFGF_GPIO44OUTCFG_Pos        (17UL)                    /*!< GPIO44OUTCFG (Bit 17)                                 */
12195 #define GPIO_CFGF_GPIO44OUTCFG_Msk        (0x60000UL)               /*!< GPIO44OUTCFG (Bitfield-Mask: 0x03)                    */
12196 #define GPIO_CFGF_GPIO44INCFG_Pos         (16UL)                    /*!< GPIO44INCFG (Bit 16)                                  */
12197 #define GPIO_CFGF_GPIO44INCFG_Msk         (0x10000UL)               /*!< GPIO44INCFG (Bitfield-Mask: 0x01)                     */
12198 #define GPIO_CFGF_GPIO43INTD_Pos          (15UL)                    /*!< GPIO43INTD (Bit 15)                                   */
12199 #define GPIO_CFGF_GPIO43INTD_Msk          (0x8000UL)                /*!< GPIO43INTD (Bitfield-Mask: 0x01)                      */
12200 #define GPIO_CFGF_GPIO43OUTCFG_Pos        (13UL)                    /*!< GPIO43OUTCFG (Bit 13)                                 */
12201 #define GPIO_CFGF_GPIO43OUTCFG_Msk        (0x6000UL)                /*!< GPIO43OUTCFG (Bitfield-Mask: 0x03)                    */
12202 #define GPIO_CFGF_GPIO43INCFG_Pos         (12UL)                    /*!< GPIO43INCFG (Bit 12)                                  */
12203 #define GPIO_CFGF_GPIO43INCFG_Msk         (0x1000UL)                /*!< GPIO43INCFG (Bitfield-Mask: 0x01)                     */
12204 #define GPIO_CFGF_GPIO42INTD_Pos          (11UL)                    /*!< GPIO42INTD (Bit 11)                                   */
12205 #define GPIO_CFGF_GPIO42INTD_Msk          (0x800UL)                 /*!< GPIO42INTD (Bitfield-Mask: 0x01)                      */
12206 #define GPIO_CFGF_GPIO42OUTCFG_Pos        (9UL)                     /*!< GPIO42OUTCFG (Bit 9)                                  */
12207 #define GPIO_CFGF_GPIO42OUTCFG_Msk        (0x600UL)                 /*!< GPIO42OUTCFG (Bitfield-Mask: 0x03)                    */
12208 #define GPIO_CFGF_GPIO42INCFG_Pos         (8UL)                     /*!< GPIO42INCFG (Bit 8)                                   */
12209 #define GPIO_CFGF_GPIO42INCFG_Msk         (0x100UL)                 /*!< GPIO42INCFG (Bitfield-Mask: 0x01)                     */
12210 #define GPIO_CFGF_GPIO41INTD_Pos          (7UL)                     /*!< GPIO41INTD (Bit 7)                                    */
12211 #define GPIO_CFGF_GPIO41INTD_Msk          (0x80UL)                  /*!< GPIO41INTD (Bitfield-Mask: 0x01)                      */
12212 #define GPIO_CFGF_GPIO41OUTCFG_Pos        (5UL)                     /*!< GPIO41OUTCFG (Bit 5)                                  */
12213 #define GPIO_CFGF_GPIO41OUTCFG_Msk        (0x60UL)                  /*!< GPIO41OUTCFG (Bitfield-Mask: 0x03)                    */
12214 #define GPIO_CFGF_GPIO41INCFG_Pos         (4UL)                     /*!< GPIO41INCFG (Bit 4)                                   */
12215 #define GPIO_CFGF_GPIO41INCFG_Msk         (0x10UL)                  /*!< GPIO41INCFG (Bitfield-Mask: 0x01)                     */
12216 #define GPIO_CFGF_GPIO40INTD_Pos          (3UL)                     /*!< GPIO40INTD (Bit 3)                                    */
12217 #define GPIO_CFGF_GPIO40INTD_Msk          (0x8UL)                   /*!< GPIO40INTD (Bitfield-Mask: 0x01)                      */
12218 #define GPIO_CFGF_GPIO40OUTCFG_Pos        (1UL)                     /*!< GPIO40OUTCFG (Bit 1)                                  */
12219 #define GPIO_CFGF_GPIO40OUTCFG_Msk        (0x6UL)                   /*!< GPIO40OUTCFG (Bitfield-Mask: 0x03)                    */
12220 #define GPIO_CFGF_GPIO40INCFG_Pos         (0UL)                     /*!< GPIO40INCFG (Bit 0)                                   */
12221 #define GPIO_CFGF_GPIO40INCFG_Msk         (0x1UL)                   /*!< GPIO40INCFG (Bitfield-Mask: 0x01)                     */
12222 /* =========================================================  CFGG  ========================================================== */
12223 #define GPIO_CFGG_GPIO49INTD_Pos          (7UL)                     /*!< GPIO49INTD (Bit 7)                                    */
12224 #define GPIO_CFGG_GPIO49INTD_Msk          (0x80UL)                  /*!< GPIO49INTD (Bitfield-Mask: 0x01)                      */
12225 #define GPIO_CFGG_GPIO49OUTCFG_Pos        (5UL)                     /*!< GPIO49OUTCFG (Bit 5)                                  */
12226 #define GPIO_CFGG_GPIO49OUTCFG_Msk        (0x60UL)                  /*!< GPIO49OUTCFG (Bitfield-Mask: 0x03)                    */
12227 #define GPIO_CFGG_GPIO49INCFG_Pos         (4UL)                     /*!< GPIO49INCFG (Bit 4)                                   */
12228 #define GPIO_CFGG_GPIO49INCFG_Msk         (0x10UL)                  /*!< GPIO49INCFG (Bitfield-Mask: 0x01)                     */
12229 #define GPIO_CFGG_GPIO48INTD_Pos          (3UL)                     /*!< GPIO48INTD (Bit 3)                                    */
12230 #define GPIO_CFGG_GPIO48INTD_Msk          (0x8UL)                   /*!< GPIO48INTD (Bitfield-Mask: 0x01)                      */
12231 #define GPIO_CFGG_GPIO48OUTCFG_Pos        (1UL)                     /*!< GPIO48OUTCFG (Bit 1)                                  */
12232 #define GPIO_CFGG_GPIO48OUTCFG_Msk        (0x6UL)                   /*!< GPIO48OUTCFG (Bitfield-Mask: 0x03)                    */
12233 #define GPIO_CFGG_GPIO48INCFG_Pos         (0UL)                     /*!< GPIO48INCFG (Bit 0)                                   */
12234 #define GPIO_CFGG_GPIO48INCFG_Msk         (0x1UL)                   /*!< GPIO48INCFG (Bitfield-Mask: 0x01)                     */
12235 /* ========================================================  PADKEY  ========================================================= */
12236 #define GPIO_PADKEY_PADKEY_Pos            (0UL)                     /*!< PADKEY (Bit 0)                                        */
12237 #define GPIO_PADKEY_PADKEY_Msk            (0xffffffffUL)            /*!< PADKEY (Bitfield-Mask: 0xffffffff)                    */
12238 /* ==========================================================  RDA  ========================================================== */
12239 #define GPIO_RDA_RDA_Pos                  (0UL)                     /*!< RDA (Bit 0)                                           */
12240 #define GPIO_RDA_RDA_Msk                  (0xffffffffUL)            /*!< RDA (Bitfield-Mask: 0xffffffff)                       */
12241 /* ==========================================================  RDB  ========================================================== */
12242 #define GPIO_RDB_RDB_Pos                  (0UL)                     /*!< RDB (Bit 0)                                           */
12243 #define GPIO_RDB_RDB_Msk                  (0x3ffffUL)               /*!< RDB (Bitfield-Mask: 0x3ffff)                          */
12244 /* ==========================================================  WTA  ========================================================== */
12245 #define GPIO_WTA_WTA_Pos                  (0UL)                     /*!< WTA (Bit 0)                                           */
12246 #define GPIO_WTA_WTA_Msk                  (0xffffffffUL)            /*!< WTA (Bitfield-Mask: 0xffffffff)                       */
12247 /* ==========================================================  WTB  ========================================================== */
12248 #define GPIO_WTB_WTB_Pos                  (0UL)                     /*!< WTB (Bit 0)                                           */
12249 #define GPIO_WTB_WTB_Msk                  (0x3ffffUL)               /*!< WTB (Bitfield-Mask: 0x3ffff)                          */
12250 /* =========================================================  WTSA  ========================================================== */
12251 #define GPIO_WTSA_WTSA_Pos                (0UL)                     /*!< WTSA (Bit 0)                                          */
12252 #define GPIO_WTSA_WTSA_Msk                (0xffffffffUL)            /*!< WTSA (Bitfield-Mask: 0xffffffff)                      */
12253 /* =========================================================  WTSB  ========================================================== */
12254 #define GPIO_WTSB_WTSB_Pos                (0UL)                     /*!< WTSB (Bit 0)                                          */
12255 #define GPIO_WTSB_WTSB_Msk                (0x3ffffUL)               /*!< WTSB (Bitfield-Mask: 0x3ffff)                         */
12256 /* =========================================================  WTCA  ========================================================== */
12257 #define GPIO_WTCA_WTCA_Pos                (0UL)                     /*!< WTCA (Bit 0)                                          */
12258 #define GPIO_WTCA_WTCA_Msk                (0xffffffffUL)            /*!< WTCA (Bitfield-Mask: 0xffffffff)                      */
12259 /* =========================================================  WTCB  ========================================================== */
12260 #define GPIO_WTCB_WTCB_Pos                (0UL)                     /*!< WTCB (Bit 0)                                          */
12261 #define GPIO_WTCB_WTCB_Msk                (0x3ffffUL)               /*!< WTCB (Bitfield-Mask: 0x3ffff)                         */
12262 /* ==========================================================  ENA  ========================================================== */
12263 #define GPIO_ENA_ENA_Pos                  (0UL)                     /*!< ENA (Bit 0)                                           */
12264 #define GPIO_ENA_ENA_Msk                  (0xffffffffUL)            /*!< ENA (Bitfield-Mask: 0xffffffff)                       */
12265 /* ==========================================================  ENB  ========================================================== */
12266 #define GPIO_ENB_ENB_Pos                  (0UL)                     /*!< ENB (Bit 0)                                           */
12267 #define GPIO_ENB_ENB_Msk                  (0x3ffffUL)               /*!< ENB (Bitfield-Mask: 0x3ffff)                          */
12268 /* =========================================================  ENSA  ========================================================== */
12269 #define GPIO_ENSA_ENSA_Pos                (0UL)                     /*!< ENSA (Bit 0)                                          */
12270 #define GPIO_ENSA_ENSA_Msk                (0xffffffffUL)            /*!< ENSA (Bitfield-Mask: 0xffffffff)                      */
12271 /* =========================================================  ENSB  ========================================================== */
12272 #define GPIO_ENSB_ENSB_Pos                (0UL)                     /*!< ENSB (Bit 0)                                          */
12273 #define GPIO_ENSB_ENSB_Msk                (0x3ffffUL)               /*!< ENSB (Bitfield-Mask: 0x3ffff)                         */
12274 /* =========================================================  ENCA  ========================================================== */
12275 #define GPIO_ENCA_ENCA_Pos                (0UL)                     /*!< ENCA (Bit 0)                                          */
12276 #define GPIO_ENCA_ENCA_Msk                (0xffffffffUL)            /*!< ENCA (Bitfield-Mask: 0xffffffff)                      */
12277 /* =========================================================  ENCB  ========================================================== */
12278 #define GPIO_ENCB_ENCB_Pos                (0UL)                     /*!< ENCB (Bit 0)                                          */
12279 #define GPIO_ENCB_ENCB_Msk                (0x3ffffUL)               /*!< ENCB (Bitfield-Mask: 0x3ffff)                         */
12280 /* ========================================================  STMRCAP  ======================================================== */
12281 #define GPIO_STMRCAP_STPOL3_Pos           (30UL)                    /*!< STPOL3 (Bit 30)                                       */
12282 #define GPIO_STMRCAP_STPOL3_Msk           (0x40000000UL)            /*!< STPOL3 (Bitfield-Mask: 0x01)                          */
12283 #define GPIO_STMRCAP_STSEL3_Pos           (24UL)                    /*!< STSEL3 (Bit 24)                                       */
12284 #define GPIO_STMRCAP_STSEL3_Msk           (0x3f000000UL)            /*!< STSEL3 (Bitfield-Mask: 0x3f)                          */
12285 #define GPIO_STMRCAP_STPOL2_Pos           (22UL)                    /*!< STPOL2 (Bit 22)                                       */
12286 #define GPIO_STMRCAP_STPOL2_Msk           (0x400000UL)              /*!< STPOL2 (Bitfield-Mask: 0x01)                          */
12287 #define GPIO_STMRCAP_STSEL2_Pos           (16UL)                    /*!< STSEL2 (Bit 16)                                       */
12288 #define GPIO_STMRCAP_STSEL2_Msk           (0x3f0000UL)              /*!< STSEL2 (Bitfield-Mask: 0x3f)                          */
12289 #define GPIO_STMRCAP_STPOL1_Pos           (14UL)                    /*!< STPOL1 (Bit 14)                                       */
12290 #define GPIO_STMRCAP_STPOL1_Msk           (0x4000UL)                /*!< STPOL1 (Bitfield-Mask: 0x01)                          */
12291 #define GPIO_STMRCAP_STSEL1_Pos           (8UL)                     /*!< STSEL1 (Bit 8)                                        */
12292 #define GPIO_STMRCAP_STSEL1_Msk           (0x3f00UL)                /*!< STSEL1 (Bitfield-Mask: 0x3f)                          */
12293 #define GPIO_STMRCAP_STPOL0_Pos           (6UL)                     /*!< STPOL0 (Bit 6)                                        */
12294 #define GPIO_STMRCAP_STPOL0_Msk           (0x40UL)                  /*!< STPOL0 (Bitfield-Mask: 0x01)                          */
12295 #define GPIO_STMRCAP_STSEL0_Pos           (0UL)                     /*!< STSEL0 (Bit 0)                                        */
12296 #define GPIO_STMRCAP_STSEL0_Msk           (0x3fUL)                  /*!< STSEL0 (Bitfield-Mask: 0x3f)                          */
12297 /* ========================================================  IOM0IRQ  ======================================================== */
12298 #define GPIO_IOM0IRQ_IOM0IRQ_Pos          (0UL)                     /*!< IOM0IRQ (Bit 0)                                       */
12299 #define GPIO_IOM0IRQ_IOM0IRQ_Msk          (0x3fUL)                  /*!< IOM0IRQ (Bitfield-Mask: 0x3f)                         */
12300 /* ========================================================  IOM1IRQ  ======================================================== */
12301 #define GPIO_IOM1IRQ_IOM1IRQ_Pos          (0UL)                     /*!< IOM1IRQ (Bit 0)                                       */
12302 #define GPIO_IOM1IRQ_IOM1IRQ_Msk          (0x3fUL)                  /*!< IOM1IRQ (Bitfield-Mask: 0x3f)                         */
12303 /* ========================================================  IOM2IRQ  ======================================================== */
12304 #define GPIO_IOM2IRQ_IOM2IRQ_Pos          (0UL)                     /*!< IOM2IRQ (Bit 0)                                       */
12305 #define GPIO_IOM2IRQ_IOM2IRQ_Msk          (0x3fUL)                  /*!< IOM2IRQ (Bitfield-Mask: 0x3f)                         */
12306 /* ========================================================  IOM3IRQ  ======================================================== */
12307 #define GPIO_IOM3IRQ_IOM3IRQ_Pos          (0UL)                     /*!< IOM3IRQ (Bit 0)                                       */
12308 #define GPIO_IOM3IRQ_IOM3IRQ_Msk          (0x3fUL)                  /*!< IOM3IRQ (Bitfield-Mask: 0x3f)                         */
12309 /* ========================================================  IOM4IRQ  ======================================================== */
12310 #define GPIO_IOM4IRQ_IOM4IRQ_Pos          (0UL)                     /*!< IOM4IRQ (Bit 0)                                       */
12311 #define GPIO_IOM4IRQ_IOM4IRQ_Msk          (0x3fUL)                  /*!< IOM4IRQ (Bitfield-Mask: 0x3f)                         */
12312 /* ========================================================  IOM5IRQ  ======================================================== */
12313 #define GPIO_IOM5IRQ_IOM5IRQ_Pos          (0UL)                     /*!< IOM5IRQ (Bit 0)                                       */
12314 #define GPIO_IOM5IRQ_IOM5IRQ_Msk          (0x3fUL)                  /*!< IOM5IRQ (Bitfield-Mask: 0x3f)                         */
12315 /* =======================================================  BLEIFIRQ  ======================================================== */
12316 #define GPIO_BLEIFIRQ_BLEIFIRQ_Pos        (0UL)                     /*!< BLEIFIRQ (Bit 0)                                      */
12317 #define GPIO_BLEIFIRQ_BLEIFIRQ_Msk        (0x3fUL)                  /*!< BLEIFIRQ (Bitfield-Mask: 0x3f)                        */
12318 /* ========================================================  GPIOOBS  ======================================================== */
12319 #define GPIO_GPIOOBS_OBS_DATA_Pos         (0UL)                     /*!< OBS_DATA (Bit 0)                                      */
12320 #define GPIO_GPIOOBS_OBS_DATA_Msk         (0xffffUL)                /*!< OBS_DATA (Bitfield-Mask: 0xffff)                      */
12321 /* ======================================================  ALTPADCFGA  ======================================================= */
12322 #define GPIO_ALTPADCFGA_PAD3_SR_Pos       (28UL)                    /*!< PAD3_SR (Bit 28)                                      */
12323 #define GPIO_ALTPADCFGA_PAD3_SR_Msk       (0x10000000UL)            /*!< PAD3_SR (Bitfield-Mask: 0x01)                         */
12324 #define GPIO_ALTPADCFGA_PAD3_DS1_Pos      (24UL)                    /*!< PAD3_DS1 (Bit 24)                                     */
12325 #define GPIO_ALTPADCFGA_PAD3_DS1_Msk      (0x1000000UL)             /*!< PAD3_DS1 (Bitfield-Mask: 0x01)                        */
12326 #define GPIO_ALTPADCFGA_PAD2_SR_Pos       (20UL)                    /*!< PAD2_SR (Bit 20)                                      */
12327 #define GPIO_ALTPADCFGA_PAD2_SR_Msk       (0x100000UL)              /*!< PAD2_SR (Bitfield-Mask: 0x01)                         */
12328 #define GPIO_ALTPADCFGA_PAD2_DS1_Pos      (16UL)                    /*!< PAD2_DS1 (Bit 16)                                     */
12329 #define GPIO_ALTPADCFGA_PAD2_DS1_Msk      (0x10000UL)               /*!< PAD2_DS1 (Bitfield-Mask: 0x01)                        */
12330 #define GPIO_ALTPADCFGA_PAD1_SR_Pos       (12UL)                    /*!< PAD1_SR (Bit 12)                                      */
12331 #define GPIO_ALTPADCFGA_PAD1_SR_Msk       (0x1000UL)                /*!< PAD1_SR (Bitfield-Mask: 0x01)                         */
12332 #define GPIO_ALTPADCFGA_PAD1_DS1_Pos      (8UL)                     /*!< PAD1_DS1 (Bit 8)                                      */
12333 #define GPIO_ALTPADCFGA_PAD1_DS1_Msk      (0x100UL)                 /*!< PAD1_DS1 (Bitfield-Mask: 0x01)                        */
12334 #define GPIO_ALTPADCFGA_PAD0_SR_Pos       (4UL)                     /*!< PAD0_SR (Bit 4)                                       */
12335 #define GPIO_ALTPADCFGA_PAD0_SR_Msk       (0x10UL)                  /*!< PAD0_SR (Bitfield-Mask: 0x01)                         */
12336 #define GPIO_ALTPADCFGA_PAD0_DS1_Pos      (0UL)                     /*!< PAD0_DS1 (Bit 0)                                      */
12337 #define GPIO_ALTPADCFGA_PAD0_DS1_Msk      (0x1UL)                   /*!< PAD0_DS1 (Bitfield-Mask: 0x01)                        */
12338 /* ======================================================  ALTPADCFGB  ======================================================= */
12339 #define GPIO_ALTPADCFGB_PAD7_SR_Pos       (28UL)                    /*!< PAD7_SR (Bit 28)                                      */
12340 #define GPIO_ALTPADCFGB_PAD7_SR_Msk       (0x10000000UL)            /*!< PAD7_SR (Bitfield-Mask: 0x01)                         */
12341 #define GPIO_ALTPADCFGB_PAD7_DS1_Pos      (24UL)                    /*!< PAD7_DS1 (Bit 24)                                     */
12342 #define GPIO_ALTPADCFGB_PAD7_DS1_Msk      (0x1000000UL)             /*!< PAD7_DS1 (Bitfield-Mask: 0x01)                        */
12343 #define GPIO_ALTPADCFGB_PAD6_SR_Pos       (20UL)                    /*!< PAD6_SR (Bit 20)                                      */
12344 #define GPIO_ALTPADCFGB_PAD6_SR_Msk       (0x100000UL)              /*!< PAD6_SR (Bitfield-Mask: 0x01)                         */
12345 #define GPIO_ALTPADCFGB_PAD6_DS1_Pos      (16UL)                    /*!< PAD6_DS1 (Bit 16)                                     */
12346 #define GPIO_ALTPADCFGB_PAD6_DS1_Msk      (0x10000UL)               /*!< PAD6_DS1 (Bitfield-Mask: 0x01)                        */
12347 #define GPIO_ALTPADCFGB_PAD5_SR_Pos       (12UL)                    /*!< PAD5_SR (Bit 12)                                      */
12348 #define GPIO_ALTPADCFGB_PAD5_SR_Msk       (0x1000UL)                /*!< PAD5_SR (Bitfield-Mask: 0x01)                         */
12349 #define GPIO_ALTPADCFGB_PAD5_DS1_Pos      (8UL)                     /*!< PAD5_DS1 (Bit 8)                                      */
12350 #define GPIO_ALTPADCFGB_PAD5_DS1_Msk      (0x100UL)                 /*!< PAD5_DS1 (Bitfield-Mask: 0x01)                        */
12351 #define GPIO_ALTPADCFGB_PAD4_SR_Pos       (4UL)                     /*!< PAD4_SR (Bit 4)                                       */
12352 #define GPIO_ALTPADCFGB_PAD4_SR_Msk       (0x10UL)                  /*!< PAD4_SR (Bitfield-Mask: 0x01)                         */
12353 #define GPIO_ALTPADCFGB_PAD4_DS1_Pos      (0UL)                     /*!< PAD4_DS1 (Bit 0)                                      */
12354 #define GPIO_ALTPADCFGB_PAD4_DS1_Msk      (0x1UL)                   /*!< PAD4_DS1 (Bitfield-Mask: 0x01)                        */
12355 /* ======================================================  ALTPADCFGC  ======================================================= */
12356 #define GPIO_ALTPADCFGC_PAD11_SR_Pos      (28UL)                    /*!< PAD11_SR (Bit 28)                                     */
12357 #define GPIO_ALTPADCFGC_PAD11_SR_Msk      (0x10000000UL)            /*!< PAD11_SR (Bitfield-Mask: 0x01)                        */
12358 #define GPIO_ALTPADCFGC_PAD11_DS1_Pos     (24UL)                    /*!< PAD11_DS1 (Bit 24)                                    */
12359 #define GPIO_ALTPADCFGC_PAD11_DS1_Msk     (0x1000000UL)             /*!< PAD11_DS1 (Bitfield-Mask: 0x01)                       */
12360 #define GPIO_ALTPADCFGC_PAD10_SR_Pos      (20UL)                    /*!< PAD10_SR (Bit 20)                                     */
12361 #define GPIO_ALTPADCFGC_PAD10_SR_Msk      (0x100000UL)              /*!< PAD10_SR (Bitfield-Mask: 0x01)                        */
12362 #define GPIO_ALTPADCFGC_PAD10_DS1_Pos     (16UL)                    /*!< PAD10_DS1 (Bit 16)                                    */
12363 #define GPIO_ALTPADCFGC_PAD10_DS1_Msk     (0x10000UL)               /*!< PAD10_DS1 (Bitfield-Mask: 0x01)                       */
12364 #define GPIO_ALTPADCFGC_PAD9_SR_Pos       (12UL)                    /*!< PAD9_SR (Bit 12)                                      */
12365 #define GPIO_ALTPADCFGC_PAD9_SR_Msk       (0x1000UL)                /*!< PAD9_SR (Bitfield-Mask: 0x01)                         */
12366 #define GPIO_ALTPADCFGC_PAD9_DS1_Pos      (8UL)                     /*!< PAD9_DS1 (Bit 8)                                      */
12367 #define GPIO_ALTPADCFGC_PAD9_DS1_Msk      (0x100UL)                 /*!< PAD9_DS1 (Bitfield-Mask: 0x01)                        */
12368 #define GPIO_ALTPADCFGC_PAD8_SR_Pos       (4UL)                     /*!< PAD8_SR (Bit 4)                                       */
12369 #define GPIO_ALTPADCFGC_PAD8_SR_Msk       (0x10UL)                  /*!< PAD8_SR (Bitfield-Mask: 0x01)                         */
12370 #define GPIO_ALTPADCFGC_PAD8_DS1_Pos      (0UL)                     /*!< PAD8_DS1 (Bit 0)                                      */
12371 #define GPIO_ALTPADCFGC_PAD8_DS1_Msk      (0x1UL)                   /*!< PAD8_DS1 (Bitfield-Mask: 0x01)                        */
12372 /* ======================================================  ALTPADCFGD  ======================================================= */
12373 #define GPIO_ALTPADCFGD_PAD15_SR_Pos      (28UL)                    /*!< PAD15_SR (Bit 28)                                     */
12374 #define GPIO_ALTPADCFGD_PAD15_SR_Msk      (0x10000000UL)            /*!< PAD15_SR (Bitfield-Mask: 0x01)                        */
12375 #define GPIO_ALTPADCFGD_PAD15_DS1_Pos     (24UL)                    /*!< PAD15_DS1 (Bit 24)                                    */
12376 #define GPIO_ALTPADCFGD_PAD15_DS1_Msk     (0x1000000UL)             /*!< PAD15_DS1 (Bitfield-Mask: 0x01)                       */
12377 #define GPIO_ALTPADCFGD_PAD14_SR_Pos      (20UL)                    /*!< PAD14_SR (Bit 20)                                     */
12378 #define GPIO_ALTPADCFGD_PAD14_SR_Msk      (0x100000UL)              /*!< PAD14_SR (Bitfield-Mask: 0x01)                        */
12379 #define GPIO_ALTPADCFGD_PAD14_DS1_Pos     (16UL)                    /*!< PAD14_DS1 (Bit 16)                                    */
12380 #define GPIO_ALTPADCFGD_PAD14_DS1_Msk     (0x10000UL)               /*!< PAD14_DS1 (Bitfield-Mask: 0x01)                       */
12381 #define GPIO_ALTPADCFGD_PAD13_SR_Pos      (12UL)                    /*!< PAD13_SR (Bit 12)                                     */
12382 #define GPIO_ALTPADCFGD_PAD13_SR_Msk      (0x1000UL)                /*!< PAD13_SR (Bitfield-Mask: 0x01)                        */
12383 #define GPIO_ALTPADCFGD_PAD13_DS1_Pos     (8UL)                     /*!< PAD13_DS1 (Bit 8)                                     */
12384 #define GPIO_ALTPADCFGD_PAD13_DS1_Msk     (0x100UL)                 /*!< PAD13_DS1 (Bitfield-Mask: 0x01)                       */
12385 #define GPIO_ALTPADCFGD_PAD12_SR_Pos      (4UL)                     /*!< PAD12_SR (Bit 4)                                      */
12386 #define GPIO_ALTPADCFGD_PAD12_SR_Msk      (0x10UL)                  /*!< PAD12_SR (Bitfield-Mask: 0x01)                        */
12387 #define GPIO_ALTPADCFGD_PAD12_DS1_Pos     (0UL)                     /*!< PAD12_DS1 (Bit 0)                                     */
12388 #define GPIO_ALTPADCFGD_PAD12_DS1_Msk     (0x1UL)                   /*!< PAD12_DS1 (Bitfield-Mask: 0x01)                       */
12389 /* ======================================================  ALTPADCFGE  ======================================================= */
12390 #define GPIO_ALTPADCFGE_PAD19_SR_Pos      (28UL)                    /*!< PAD19_SR (Bit 28)                                     */
12391 #define GPIO_ALTPADCFGE_PAD19_SR_Msk      (0x10000000UL)            /*!< PAD19_SR (Bitfield-Mask: 0x01)                        */
12392 #define GPIO_ALTPADCFGE_PAD19_DS1_Pos     (24UL)                    /*!< PAD19_DS1 (Bit 24)                                    */
12393 #define GPIO_ALTPADCFGE_PAD19_DS1_Msk     (0x1000000UL)             /*!< PAD19_DS1 (Bitfield-Mask: 0x01)                       */
12394 #define GPIO_ALTPADCFGE_PAD18_SR_Pos      (20UL)                    /*!< PAD18_SR (Bit 20)                                     */
12395 #define GPIO_ALTPADCFGE_PAD18_SR_Msk      (0x100000UL)              /*!< PAD18_SR (Bitfield-Mask: 0x01)                        */
12396 #define GPIO_ALTPADCFGE_PAD18_DS1_Pos     (16UL)                    /*!< PAD18_DS1 (Bit 16)                                    */
12397 #define GPIO_ALTPADCFGE_PAD18_DS1_Msk     (0x10000UL)               /*!< PAD18_DS1 (Bitfield-Mask: 0x01)                       */
12398 #define GPIO_ALTPADCFGE_PAD17_SR_Pos      (12UL)                    /*!< PAD17_SR (Bit 12)                                     */
12399 #define GPIO_ALTPADCFGE_PAD17_SR_Msk      (0x1000UL)                /*!< PAD17_SR (Bitfield-Mask: 0x01)                        */
12400 #define GPIO_ALTPADCFGE_PAD17_DS1_Pos     (8UL)                     /*!< PAD17_DS1 (Bit 8)                                     */
12401 #define GPIO_ALTPADCFGE_PAD17_DS1_Msk     (0x100UL)                 /*!< PAD17_DS1 (Bitfield-Mask: 0x01)                       */
12402 #define GPIO_ALTPADCFGE_PAD16_SR_Pos      (4UL)                     /*!< PAD16_SR (Bit 4)                                      */
12403 #define GPIO_ALTPADCFGE_PAD16_SR_Msk      (0x10UL)                  /*!< PAD16_SR (Bitfield-Mask: 0x01)                        */
12404 #define GPIO_ALTPADCFGE_PAD16_DS1_Pos     (0UL)                     /*!< PAD16_DS1 (Bit 0)                                     */
12405 #define GPIO_ALTPADCFGE_PAD16_DS1_Msk     (0x1UL)                   /*!< PAD16_DS1 (Bitfield-Mask: 0x01)                       */
12406 /* ======================================================  ALTPADCFGF  ======================================================= */
12407 #define GPIO_ALTPADCFGF_PAD23_SR_Pos      (28UL)                    /*!< PAD23_SR (Bit 28)                                     */
12408 #define GPIO_ALTPADCFGF_PAD23_SR_Msk      (0x10000000UL)            /*!< PAD23_SR (Bitfield-Mask: 0x01)                        */
12409 #define GPIO_ALTPADCFGF_PAD23_DS1_Pos     (24UL)                    /*!< PAD23_DS1 (Bit 24)                                    */
12410 #define GPIO_ALTPADCFGF_PAD23_DS1_Msk     (0x1000000UL)             /*!< PAD23_DS1 (Bitfield-Mask: 0x01)                       */
12411 #define GPIO_ALTPADCFGF_PAD22_SR_Pos      (20UL)                    /*!< PAD22_SR (Bit 20)                                     */
12412 #define GPIO_ALTPADCFGF_PAD22_SR_Msk      (0x100000UL)              /*!< PAD22_SR (Bitfield-Mask: 0x01)                        */
12413 #define GPIO_ALTPADCFGF_PAD22_DS1_Pos     (16UL)                    /*!< PAD22_DS1 (Bit 16)                                    */
12414 #define GPIO_ALTPADCFGF_PAD22_DS1_Msk     (0x10000UL)               /*!< PAD22_DS1 (Bitfield-Mask: 0x01)                       */
12415 #define GPIO_ALTPADCFGF_PAD21_SR_Pos      (12UL)                    /*!< PAD21_SR (Bit 12)                                     */
12416 #define GPIO_ALTPADCFGF_PAD21_SR_Msk      (0x1000UL)                /*!< PAD21_SR (Bitfield-Mask: 0x01)                        */
12417 #define GPIO_ALTPADCFGF_PAD21_DS1_Pos     (8UL)                     /*!< PAD21_DS1 (Bit 8)                                     */
12418 #define GPIO_ALTPADCFGF_PAD21_DS1_Msk     (0x100UL)                 /*!< PAD21_DS1 (Bitfield-Mask: 0x01)                       */
12419 #define GPIO_ALTPADCFGF_PAD20_SR_Pos      (4UL)                     /*!< PAD20_SR (Bit 4)                                      */
12420 #define GPIO_ALTPADCFGF_PAD20_SR_Msk      (0x10UL)                  /*!< PAD20_SR (Bitfield-Mask: 0x01)                        */
12421 #define GPIO_ALTPADCFGF_PAD20_DS1_Pos     (0UL)                     /*!< PAD20_DS1 (Bit 0)                                     */
12422 #define GPIO_ALTPADCFGF_PAD20_DS1_Msk     (0x1UL)                   /*!< PAD20_DS1 (Bitfield-Mask: 0x01)                       */
12423 /* ======================================================  ALTPADCFGG  ======================================================= */
12424 #define GPIO_ALTPADCFGG_PAD27_SR_Pos      (28UL)                    /*!< PAD27_SR (Bit 28)                                     */
12425 #define GPIO_ALTPADCFGG_PAD27_SR_Msk      (0x10000000UL)            /*!< PAD27_SR (Bitfield-Mask: 0x01)                        */
12426 #define GPIO_ALTPADCFGG_PAD27_DS1_Pos     (24UL)                    /*!< PAD27_DS1 (Bit 24)                                    */
12427 #define GPIO_ALTPADCFGG_PAD27_DS1_Msk     (0x1000000UL)             /*!< PAD27_DS1 (Bitfield-Mask: 0x01)                       */
12428 #define GPIO_ALTPADCFGG_PAD26_SR_Pos      (20UL)                    /*!< PAD26_SR (Bit 20)                                     */
12429 #define GPIO_ALTPADCFGG_PAD26_SR_Msk      (0x100000UL)              /*!< PAD26_SR (Bitfield-Mask: 0x01)                        */
12430 #define GPIO_ALTPADCFGG_PAD26_DS1_Pos     (16UL)                    /*!< PAD26_DS1 (Bit 16)                                    */
12431 #define GPIO_ALTPADCFGG_PAD26_DS1_Msk     (0x10000UL)               /*!< PAD26_DS1 (Bitfield-Mask: 0x01)                       */
12432 #define GPIO_ALTPADCFGG_PAD25_SR_Pos      (12UL)                    /*!< PAD25_SR (Bit 12)                                     */
12433 #define GPIO_ALTPADCFGG_PAD25_SR_Msk      (0x1000UL)                /*!< PAD25_SR (Bitfield-Mask: 0x01)                        */
12434 #define GPIO_ALTPADCFGG_PAD25_DS1_Pos     (8UL)                     /*!< PAD25_DS1 (Bit 8)                                     */
12435 #define GPIO_ALTPADCFGG_PAD25_DS1_Msk     (0x100UL)                 /*!< PAD25_DS1 (Bitfield-Mask: 0x01)                       */
12436 #define GPIO_ALTPADCFGG_PAD24_SR_Pos      (4UL)                     /*!< PAD24_SR (Bit 4)                                      */
12437 #define GPIO_ALTPADCFGG_PAD24_SR_Msk      (0x10UL)                  /*!< PAD24_SR (Bitfield-Mask: 0x01)                        */
12438 #define GPIO_ALTPADCFGG_PAD24_DS1_Pos     (0UL)                     /*!< PAD24_DS1 (Bit 0)                                     */
12439 #define GPIO_ALTPADCFGG_PAD24_DS1_Msk     (0x1UL)                   /*!< PAD24_DS1 (Bitfield-Mask: 0x01)                       */
12440 /* ======================================================  ALTPADCFGH  ======================================================= */
12441 #define GPIO_ALTPADCFGH_PAD31_SR_Pos      (28UL)                    /*!< PAD31_SR (Bit 28)                                     */
12442 #define GPIO_ALTPADCFGH_PAD31_SR_Msk      (0x10000000UL)            /*!< PAD31_SR (Bitfield-Mask: 0x01)                        */
12443 #define GPIO_ALTPADCFGH_PAD31_DS1_Pos     (24UL)                    /*!< PAD31_DS1 (Bit 24)                                    */
12444 #define GPIO_ALTPADCFGH_PAD31_DS1_Msk     (0x1000000UL)             /*!< PAD31_DS1 (Bitfield-Mask: 0x01)                       */
12445 #define GPIO_ALTPADCFGH_PAD30_SR_Pos      (20UL)                    /*!< PAD30_SR (Bit 20)                                     */
12446 #define GPIO_ALTPADCFGH_PAD30_SR_Msk      (0x100000UL)              /*!< PAD30_SR (Bitfield-Mask: 0x01)                        */
12447 #define GPIO_ALTPADCFGH_PAD30_DS1_Pos     (16UL)                    /*!< PAD30_DS1 (Bit 16)                                    */
12448 #define GPIO_ALTPADCFGH_PAD30_DS1_Msk     (0x10000UL)               /*!< PAD30_DS1 (Bitfield-Mask: 0x01)                       */
12449 #define GPIO_ALTPADCFGH_PAD29_SR_Pos      (12UL)                    /*!< PAD29_SR (Bit 12)                                     */
12450 #define GPIO_ALTPADCFGH_PAD29_SR_Msk      (0x1000UL)                /*!< PAD29_SR (Bitfield-Mask: 0x01)                        */
12451 #define GPIO_ALTPADCFGH_PAD29_DS1_Pos     (8UL)                     /*!< PAD29_DS1 (Bit 8)                                     */
12452 #define GPIO_ALTPADCFGH_PAD29_DS1_Msk     (0x100UL)                 /*!< PAD29_DS1 (Bitfield-Mask: 0x01)                       */
12453 #define GPIO_ALTPADCFGH_PAD28_SR_Pos      (4UL)                     /*!< PAD28_SR (Bit 4)                                      */
12454 #define GPIO_ALTPADCFGH_PAD28_SR_Msk      (0x10UL)                  /*!< PAD28_SR (Bitfield-Mask: 0x01)                        */
12455 #define GPIO_ALTPADCFGH_PAD28_DS1_Pos     (0UL)                     /*!< PAD28_DS1 (Bit 0)                                     */
12456 #define GPIO_ALTPADCFGH_PAD28_DS1_Msk     (0x1UL)                   /*!< PAD28_DS1 (Bitfield-Mask: 0x01)                       */
12457 /* ======================================================  ALTPADCFGI  ======================================================= */
12458 #define GPIO_ALTPADCFGI_PAD35_SR_Pos      (28UL)                    /*!< PAD35_SR (Bit 28)                                     */
12459 #define GPIO_ALTPADCFGI_PAD35_SR_Msk      (0x10000000UL)            /*!< PAD35_SR (Bitfield-Mask: 0x01)                        */
12460 #define GPIO_ALTPADCFGI_PAD35_DS1_Pos     (24UL)                    /*!< PAD35_DS1 (Bit 24)                                    */
12461 #define GPIO_ALTPADCFGI_PAD35_DS1_Msk     (0x1000000UL)             /*!< PAD35_DS1 (Bitfield-Mask: 0x01)                       */
12462 #define GPIO_ALTPADCFGI_PAD34_SR_Pos      (20UL)                    /*!< PAD34_SR (Bit 20)                                     */
12463 #define GPIO_ALTPADCFGI_PAD34_SR_Msk      (0x100000UL)              /*!< PAD34_SR (Bitfield-Mask: 0x01)                        */
12464 #define GPIO_ALTPADCFGI_PAD34_DS1_Pos     (16UL)                    /*!< PAD34_DS1 (Bit 16)                                    */
12465 #define GPIO_ALTPADCFGI_PAD34_DS1_Msk     (0x10000UL)               /*!< PAD34_DS1 (Bitfield-Mask: 0x01)                       */
12466 #define GPIO_ALTPADCFGI_PAD33_SR_Pos      (12UL)                    /*!< PAD33_SR (Bit 12)                                     */
12467 #define GPIO_ALTPADCFGI_PAD33_SR_Msk      (0x1000UL)                /*!< PAD33_SR (Bitfield-Mask: 0x01)                        */
12468 #define GPIO_ALTPADCFGI_PAD33_DS1_Pos     (8UL)                     /*!< PAD33_DS1 (Bit 8)                                     */
12469 #define GPIO_ALTPADCFGI_PAD33_DS1_Msk     (0x100UL)                 /*!< PAD33_DS1 (Bitfield-Mask: 0x01)                       */
12470 #define GPIO_ALTPADCFGI_PAD32_SR_Pos      (4UL)                     /*!< PAD32_SR (Bit 4)                                      */
12471 #define GPIO_ALTPADCFGI_PAD32_SR_Msk      (0x10UL)                  /*!< PAD32_SR (Bitfield-Mask: 0x01)                        */
12472 #define GPIO_ALTPADCFGI_PAD32_DS1_Pos     (0UL)                     /*!< PAD32_DS1 (Bit 0)                                     */
12473 #define GPIO_ALTPADCFGI_PAD32_DS1_Msk     (0x1UL)                   /*!< PAD32_DS1 (Bitfield-Mask: 0x01)                       */
12474 /* ======================================================  ALTPADCFGJ  ======================================================= */
12475 #define GPIO_ALTPADCFGJ_PAD39_SR_Pos      (28UL)                    /*!< PAD39_SR (Bit 28)                                     */
12476 #define GPIO_ALTPADCFGJ_PAD39_SR_Msk      (0x10000000UL)            /*!< PAD39_SR (Bitfield-Mask: 0x01)                        */
12477 #define GPIO_ALTPADCFGJ_PAD39_DS1_Pos     (24UL)                    /*!< PAD39_DS1 (Bit 24)                                    */
12478 #define GPIO_ALTPADCFGJ_PAD39_DS1_Msk     (0x1000000UL)             /*!< PAD39_DS1 (Bitfield-Mask: 0x01)                       */
12479 #define GPIO_ALTPADCFGJ_PAD38_SR_Pos      (20UL)                    /*!< PAD38_SR (Bit 20)                                     */
12480 #define GPIO_ALTPADCFGJ_PAD38_SR_Msk      (0x100000UL)              /*!< PAD38_SR (Bitfield-Mask: 0x01)                        */
12481 #define GPIO_ALTPADCFGJ_PAD38_DS1_Pos     (16UL)                    /*!< PAD38_DS1 (Bit 16)                                    */
12482 #define GPIO_ALTPADCFGJ_PAD38_DS1_Msk     (0x10000UL)               /*!< PAD38_DS1 (Bitfield-Mask: 0x01)                       */
12483 #define GPIO_ALTPADCFGJ_PAD37_SR_Pos      (12UL)                    /*!< PAD37_SR (Bit 12)                                     */
12484 #define GPIO_ALTPADCFGJ_PAD37_SR_Msk      (0x1000UL)                /*!< PAD37_SR (Bitfield-Mask: 0x01)                        */
12485 #define GPIO_ALTPADCFGJ_PAD37_DS1_Pos     (8UL)                     /*!< PAD37_DS1 (Bit 8)                                     */
12486 #define GPIO_ALTPADCFGJ_PAD37_DS1_Msk     (0x100UL)                 /*!< PAD37_DS1 (Bitfield-Mask: 0x01)                       */
12487 #define GPIO_ALTPADCFGJ_PAD36_SR_Pos      (4UL)                     /*!< PAD36_SR (Bit 4)                                      */
12488 #define GPIO_ALTPADCFGJ_PAD36_SR_Msk      (0x10UL)                  /*!< PAD36_SR (Bitfield-Mask: 0x01)                        */
12489 #define GPIO_ALTPADCFGJ_PAD36_DS1_Pos     (0UL)                     /*!< PAD36_DS1 (Bit 0)                                     */
12490 #define GPIO_ALTPADCFGJ_PAD36_DS1_Msk     (0x1UL)                   /*!< PAD36_DS1 (Bitfield-Mask: 0x01)                       */
12491 /* ======================================================  ALTPADCFGK  ======================================================= */
12492 #define GPIO_ALTPADCFGK_PAD43_SR_Pos      (28UL)                    /*!< PAD43_SR (Bit 28)                                     */
12493 #define GPIO_ALTPADCFGK_PAD43_SR_Msk      (0x10000000UL)            /*!< PAD43_SR (Bitfield-Mask: 0x01)                        */
12494 #define GPIO_ALTPADCFGK_PAD43_DS1_Pos     (24UL)                    /*!< PAD43_DS1 (Bit 24)                                    */
12495 #define GPIO_ALTPADCFGK_PAD43_DS1_Msk     (0x1000000UL)             /*!< PAD43_DS1 (Bitfield-Mask: 0x01)                       */
12496 #define GPIO_ALTPADCFGK_PAD42_SR_Pos      (20UL)                    /*!< PAD42_SR (Bit 20)                                     */
12497 #define GPIO_ALTPADCFGK_PAD42_SR_Msk      (0x100000UL)              /*!< PAD42_SR (Bitfield-Mask: 0x01)                        */
12498 #define GPIO_ALTPADCFGK_PAD42_DS1_Pos     (16UL)                    /*!< PAD42_DS1 (Bit 16)                                    */
12499 #define GPIO_ALTPADCFGK_PAD42_DS1_Msk     (0x10000UL)               /*!< PAD42_DS1 (Bitfield-Mask: 0x01)                       */
12500 #define GPIO_ALTPADCFGK_PAD41_SR_Pos      (12UL)                    /*!< PAD41_SR (Bit 12)                                     */
12501 #define GPIO_ALTPADCFGK_PAD41_SR_Msk      (0x1000UL)                /*!< PAD41_SR (Bitfield-Mask: 0x01)                        */
12502 #define GPIO_ALTPADCFGK_PAD41_DS1_Pos     (8UL)                     /*!< PAD41_DS1 (Bit 8)                                     */
12503 #define GPIO_ALTPADCFGK_PAD41_DS1_Msk     (0x100UL)                 /*!< PAD41_DS1 (Bitfield-Mask: 0x01)                       */
12504 #define GPIO_ALTPADCFGK_PAD40_SR_Pos      (4UL)                     /*!< PAD40_SR (Bit 4)                                      */
12505 #define GPIO_ALTPADCFGK_PAD40_SR_Msk      (0x10UL)                  /*!< PAD40_SR (Bitfield-Mask: 0x01)                        */
12506 #define GPIO_ALTPADCFGK_PAD40_DS1_Pos     (0UL)                     /*!< PAD40_DS1 (Bit 0)                                     */
12507 #define GPIO_ALTPADCFGK_PAD40_DS1_Msk     (0x1UL)                   /*!< PAD40_DS1 (Bitfield-Mask: 0x01)                       */
12508 /* ======================================================  ALTPADCFGL  ======================================================= */
12509 #define GPIO_ALTPADCFGL_PAD47_SR_Pos      (28UL)                    /*!< PAD47_SR (Bit 28)                                     */
12510 #define GPIO_ALTPADCFGL_PAD47_SR_Msk      (0x10000000UL)            /*!< PAD47_SR (Bitfield-Mask: 0x01)                        */
12511 #define GPIO_ALTPADCFGL_PAD47_DS1_Pos     (24UL)                    /*!< PAD47_DS1 (Bit 24)                                    */
12512 #define GPIO_ALTPADCFGL_PAD47_DS1_Msk     (0x1000000UL)             /*!< PAD47_DS1 (Bitfield-Mask: 0x01)                       */
12513 #define GPIO_ALTPADCFGL_PAD46_SR_Pos      (20UL)                    /*!< PAD46_SR (Bit 20)                                     */
12514 #define GPIO_ALTPADCFGL_PAD46_SR_Msk      (0x100000UL)              /*!< PAD46_SR (Bitfield-Mask: 0x01)                        */
12515 #define GPIO_ALTPADCFGL_PAD46_DS1_Pos     (16UL)                    /*!< PAD46_DS1 (Bit 16)                                    */
12516 #define GPIO_ALTPADCFGL_PAD46_DS1_Msk     (0x10000UL)               /*!< PAD46_DS1 (Bitfield-Mask: 0x01)                       */
12517 #define GPIO_ALTPADCFGL_PAD45_SR_Pos      (12UL)                    /*!< PAD45_SR (Bit 12)                                     */
12518 #define GPIO_ALTPADCFGL_PAD45_SR_Msk      (0x1000UL)                /*!< PAD45_SR (Bitfield-Mask: 0x01)                        */
12519 #define GPIO_ALTPADCFGL_PAD45_DS1_Pos     (8UL)                     /*!< PAD45_DS1 (Bit 8)                                     */
12520 #define GPIO_ALTPADCFGL_PAD45_DS1_Msk     (0x100UL)                 /*!< PAD45_DS1 (Bitfield-Mask: 0x01)                       */
12521 #define GPIO_ALTPADCFGL_PAD44_SR_Pos      (4UL)                     /*!< PAD44_SR (Bit 4)                                      */
12522 #define GPIO_ALTPADCFGL_PAD44_SR_Msk      (0x10UL)                  /*!< PAD44_SR (Bitfield-Mask: 0x01)                        */
12523 #define GPIO_ALTPADCFGL_PAD44_DS1_Pos     (0UL)                     /*!< PAD44_DS1 (Bit 0)                                     */
12524 #define GPIO_ALTPADCFGL_PAD44_DS1_Msk     (0x1UL)                   /*!< PAD44_DS1 (Bitfield-Mask: 0x01)                       */
12525 /* ======================================================  ALTPADCFGM  ======================================================= */
12526 #define GPIO_ALTPADCFGM_PAD49_SR_Pos      (12UL)                    /*!< PAD49_SR (Bit 12)                                     */
12527 #define GPIO_ALTPADCFGM_PAD49_SR_Msk      (0x1000UL)                /*!< PAD49_SR (Bitfield-Mask: 0x01)                        */
12528 #define GPIO_ALTPADCFGM_PAD49_DS1_Pos     (8UL)                     /*!< PAD49_DS1 (Bit 8)                                     */
12529 #define GPIO_ALTPADCFGM_PAD49_DS1_Msk     (0x100UL)                 /*!< PAD49_DS1 (Bitfield-Mask: 0x01)                       */
12530 #define GPIO_ALTPADCFGM_PAD48_SR_Pos      (4UL)                     /*!< PAD48_SR (Bit 4)                                      */
12531 #define GPIO_ALTPADCFGM_PAD48_SR_Msk      (0x10UL)                  /*!< PAD48_SR (Bitfield-Mask: 0x01)                        */
12532 #define GPIO_ALTPADCFGM_PAD48_DS1_Pos     (0UL)                     /*!< PAD48_DS1 (Bit 0)                                     */
12533 #define GPIO_ALTPADCFGM_PAD48_DS1_Msk     (0x1UL)                   /*!< PAD48_DS1 (Bitfield-Mask: 0x01)                       */
12534 /* =========================================================  SCDET  ========================================================= */
12535 #define GPIO_SCDET_SCDET_Pos              (0UL)                     /*!< SCDET (Bit 0)                                         */
12536 #define GPIO_SCDET_SCDET_Msk              (0x3fUL)                  /*!< SCDET (Bitfield-Mask: 0x3f)                           */
12537 /* ========================================================  CTENCFG  ======================================================== */
12538 #define GPIO_CTENCFG_EN31_Pos             (31UL)                    /*!< EN31 (Bit 31)                                         */
12539 #define GPIO_CTENCFG_EN31_Msk             (0x80000000UL)            /*!< EN31 (Bitfield-Mask: 0x01)                            */
12540 #define GPIO_CTENCFG_EN30_Pos             (30UL)                    /*!< EN30 (Bit 30)                                         */
12541 #define GPIO_CTENCFG_EN30_Msk             (0x40000000UL)            /*!< EN30 (Bitfield-Mask: 0x01)                            */
12542 #define GPIO_CTENCFG_EN29_Pos             (29UL)                    /*!< EN29 (Bit 29)                                         */
12543 #define GPIO_CTENCFG_EN29_Msk             (0x20000000UL)            /*!< EN29 (Bitfield-Mask: 0x01)                            */
12544 #define GPIO_CTENCFG_EN28_Pos             (28UL)                    /*!< EN28 (Bit 28)                                         */
12545 #define GPIO_CTENCFG_EN28_Msk             (0x10000000UL)            /*!< EN28 (Bitfield-Mask: 0x01)                            */
12546 #define GPIO_CTENCFG_EN27_Pos             (27UL)                    /*!< EN27 (Bit 27)                                         */
12547 #define GPIO_CTENCFG_EN27_Msk             (0x8000000UL)             /*!< EN27 (Bitfield-Mask: 0x01)                            */
12548 #define GPIO_CTENCFG_EN26_Pos             (26UL)                    /*!< EN26 (Bit 26)                                         */
12549 #define GPIO_CTENCFG_EN26_Msk             (0x4000000UL)             /*!< EN26 (Bitfield-Mask: 0x01)                            */
12550 #define GPIO_CTENCFG_EN25_Pos             (25UL)                    /*!< EN25 (Bit 25)                                         */
12551 #define GPIO_CTENCFG_EN25_Msk             (0x2000000UL)             /*!< EN25 (Bitfield-Mask: 0x01)                            */
12552 #define GPIO_CTENCFG_EN24_Pos             (24UL)                    /*!< EN24 (Bit 24)                                         */
12553 #define GPIO_CTENCFG_EN24_Msk             (0x1000000UL)             /*!< EN24 (Bitfield-Mask: 0x01)                            */
12554 #define GPIO_CTENCFG_EN23_Pos             (23UL)                    /*!< EN23 (Bit 23)                                         */
12555 #define GPIO_CTENCFG_EN23_Msk             (0x800000UL)              /*!< EN23 (Bitfield-Mask: 0x01)                            */
12556 #define GPIO_CTENCFG_EN22_Pos             (22UL)                    /*!< EN22 (Bit 22)                                         */
12557 #define GPIO_CTENCFG_EN22_Msk             (0x400000UL)              /*!< EN22 (Bitfield-Mask: 0x01)                            */
12558 #define GPIO_CTENCFG_EN21_Pos             (21UL)                    /*!< EN21 (Bit 21)                                         */
12559 #define GPIO_CTENCFG_EN21_Msk             (0x200000UL)              /*!< EN21 (Bitfield-Mask: 0x01)                            */
12560 #define GPIO_CTENCFG_EN20_Pos             (20UL)                    /*!< EN20 (Bit 20)                                         */
12561 #define GPIO_CTENCFG_EN20_Msk             (0x100000UL)              /*!< EN20 (Bitfield-Mask: 0x01)                            */
12562 #define GPIO_CTENCFG_EN19_Pos             (19UL)                    /*!< EN19 (Bit 19)                                         */
12563 #define GPIO_CTENCFG_EN19_Msk             (0x80000UL)               /*!< EN19 (Bitfield-Mask: 0x01)                            */
12564 #define GPIO_CTENCFG_EN18_Pos             (18UL)                    /*!< EN18 (Bit 18)                                         */
12565 #define GPIO_CTENCFG_EN18_Msk             (0x40000UL)               /*!< EN18 (Bitfield-Mask: 0x01)                            */
12566 #define GPIO_CTENCFG_EN17_Pos             (17UL)                    /*!< EN17 (Bit 17)                                         */
12567 #define GPIO_CTENCFG_EN17_Msk             (0x20000UL)               /*!< EN17 (Bitfield-Mask: 0x01)                            */
12568 #define GPIO_CTENCFG_EN16_Pos             (16UL)                    /*!< EN16 (Bit 16)                                         */
12569 #define GPIO_CTENCFG_EN16_Msk             (0x10000UL)               /*!< EN16 (Bitfield-Mask: 0x01)                            */
12570 #define GPIO_CTENCFG_EN15_Pos             (15UL)                    /*!< EN15 (Bit 15)                                         */
12571 #define GPIO_CTENCFG_EN15_Msk             (0x8000UL)                /*!< EN15 (Bitfield-Mask: 0x01)                            */
12572 #define GPIO_CTENCFG_EN14_Pos             (14UL)                    /*!< EN14 (Bit 14)                                         */
12573 #define GPIO_CTENCFG_EN14_Msk             (0x4000UL)                /*!< EN14 (Bitfield-Mask: 0x01)                            */
12574 #define GPIO_CTENCFG_EN13_Pos             (13UL)                    /*!< EN13 (Bit 13)                                         */
12575 #define GPIO_CTENCFG_EN13_Msk             (0x2000UL)                /*!< EN13 (Bitfield-Mask: 0x01)                            */
12576 #define GPIO_CTENCFG_EN12_Pos             (12UL)                    /*!< EN12 (Bit 12)                                         */
12577 #define GPIO_CTENCFG_EN12_Msk             (0x1000UL)                /*!< EN12 (Bitfield-Mask: 0x01)                            */
12578 #define GPIO_CTENCFG_EN11_Pos             (11UL)                    /*!< EN11 (Bit 11)                                         */
12579 #define GPIO_CTENCFG_EN11_Msk             (0x800UL)                 /*!< EN11 (Bitfield-Mask: 0x01)                            */
12580 #define GPIO_CTENCFG_EN10_Pos             (10UL)                    /*!< EN10 (Bit 10)                                         */
12581 #define GPIO_CTENCFG_EN10_Msk             (0x400UL)                 /*!< EN10 (Bitfield-Mask: 0x01)                            */
12582 #define GPIO_CTENCFG_EN9_Pos              (9UL)                     /*!< EN9 (Bit 9)                                           */
12583 #define GPIO_CTENCFG_EN9_Msk              (0x200UL)                 /*!< EN9 (Bitfield-Mask: 0x01)                             */
12584 #define GPIO_CTENCFG_EN8_Pos              (8UL)                     /*!< EN8 (Bit 8)                                           */
12585 #define GPIO_CTENCFG_EN8_Msk              (0x100UL)                 /*!< EN8 (Bitfield-Mask: 0x01)                             */
12586 #define GPIO_CTENCFG_EN7_Pos              (7UL)                     /*!< EN7 (Bit 7)                                           */
12587 #define GPIO_CTENCFG_EN7_Msk              (0x80UL)                  /*!< EN7 (Bitfield-Mask: 0x01)                             */
12588 #define GPIO_CTENCFG_EN6_Pos              (6UL)                     /*!< EN6 (Bit 6)                                           */
12589 #define GPIO_CTENCFG_EN6_Msk              (0x40UL)                  /*!< EN6 (Bitfield-Mask: 0x01)                             */
12590 #define GPIO_CTENCFG_EN5_Pos              (5UL)                     /*!< EN5 (Bit 5)                                           */
12591 #define GPIO_CTENCFG_EN5_Msk              (0x20UL)                  /*!< EN5 (Bitfield-Mask: 0x01)                             */
12592 #define GPIO_CTENCFG_EN4_Pos              (4UL)                     /*!< EN4 (Bit 4)                                           */
12593 #define GPIO_CTENCFG_EN4_Msk              (0x10UL)                  /*!< EN4 (Bitfield-Mask: 0x01)                             */
12594 #define GPIO_CTENCFG_EN3_Pos              (3UL)                     /*!< EN3 (Bit 3)                                           */
12595 #define GPIO_CTENCFG_EN3_Msk              (0x8UL)                   /*!< EN3 (Bitfield-Mask: 0x01)                             */
12596 #define GPIO_CTENCFG_EN2_Pos              (2UL)                     /*!< EN2 (Bit 2)                                           */
12597 #define GPIO_CTENCFG_EN2_Msk              (0x4UL)                   /*!< EN2 (Bitfield-Mask: 0x01)                             */
12598 #define GPIO_CTENCFG_EN1_Pos              (1UL)                     /*!< EN1 (Bit 1)                                           */
12599 #define GPIO_CTENCFG_EN1_Msk              (0x2UL)                   /*!< EN1 (Bitfield-Mask: 0x01)                             */
12600 #define GPIO_CTENCFG_EN0_Pos              (0UL)                     /*!< EN0 (Bit 0)                                           */
12601 #define GPIO_CTENCFG_EN0_Msk              (0x1UL)                   /*!< EN0 (Bitfield-Mask: 0x01)                             */
12602 /* ========================================================  INT0EN  ========================================================= */
12603 #define GPIO_INT0EN_GPIO31_Pos            (31UL)                    /*!< GPIO31 (Bit 31)                                       */
12604 #define GPIO_INT0EN_GPIO31_Msk            (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
12605 #define GPIO_INT0EN_GPIO30_Pos            (30UL)                    /*!< GPIO30 (Bit 30)                                       */
12606 #define GPIO_INT0EN_GPIO30_Msk            (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
12607 #define GPIO_INT0EN_GPIO29_Pos            (29UL)                    /*!< GPIO29 (Bit 29)                                       */
12608 #define GPIO_INT0EN_GPIO29_Msk            (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
12609 #define GPIO_INT0EN_GPIO28_Pos            (28UL)                    /*!< GPIO28 (Bit 28)                                       */
12610 #define GPIO_INT0EN_GPIO28_Msk            (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
12611 #define GPIO_INT0EN_GPIO27_Pos            (27UL)                    /*!< GPIO27 (Bit 27)                                       */
12612 #define GPIO_INT0EN_GPIO27_Msk            (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
12613 #define GPIO_INT0EN_GPIO26_Pos            (26UL)                    /*!< GPIO26 (Bit 26)                                       */
12614 #define GPIO_INT0EN_GPIO26_Msk            (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
12615 #define GPIO_INT0EN_GPIO25_Pos            (25UL)                    /*!< GPIO25 (Bit 25)                                       */
12616 #define GPIO_INT0EN_GPIO25_Msk            (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
12617 #define GPIO_INT0EN_GPIO24_Pos            (24UL)                    /*!< GPIO24 (Bit 24)                                       */
12618 #define GPIO_INT0EN_GPIO24_Msk            (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
12619 #define GPIO_INT0EN_GPIO23_Pos            (23UL)                    /*!< GPIO23 (Bit 23)                                       */
12620 #define GPIO_INT0EN_GPIO23_Msk            (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
12621 #define GPIO_INT0EN_GPIO22_Pos            (22UL)                    /*!< GPIO22 (Bit 22)                                       */
12622 #define GPIO_INT0EN_GPIO22_Msk            (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
12623 #define GPIO_INT0EN_GPIO21_Pos            (21UL)                    /*!< GPIO21 (Bit 21)                                       */
12624 #define GPIO_INT0EN_GPIO21_Msk            (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
12625 #define GPIO_INT0EN_GPIO20_Pos            (20UL)                    /*!< GPIO20 (Bit 20)                                       */
12626 #define GPIO_INT0EN_GPIO20_Msk            (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
12627 #define GPIO_INT0EN_GPIO19_Pos            (19UL)                    /*!< GPIO19 (Bit 19)                                       */
12628 #define GPIO_INT0EN_GPIO19_Msk            (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
12629 #define GPIO_INT0EN_GPIO18_Pos            (18UL)                    /*!< GPIO18 (Bit 18)                                       */
12630 #define GPIO_INT0EN_GPIO18_Msk            (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
12631 #define GPIO_INT0EN_GPIO17_Pos            (17UL)                    /*!< GPIO17 (Bit 17)                                       */
12632 #define GPIO_INT0EN_GPIO17_Msk            (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
12633 #define GPIO_INT0EN_GPIO16_Pos            (16UL)                    /*!< GPIO16 (Bit 16)                                       */
12634 #define GPIO_INT0EN_GPIO16_Msk            (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
12635 #define GPIO_INT0EN_GPIO15_Pos            (15UL)                    /*!< GPIO15 (Bit 15)                                       */
12636 #define GPIO_INT0EN_GPIO15_Msk            (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
12637 #define GPIO_INT0EN_GPIO14_Pos            (14UL)                    /*!< GPIO14 (Bit 14)                                       */
12638 #define GPIO_INT0EN_GPIO14_Msk            (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
12639 #define GPIO_INT0EN_GPIO13_Pos            (13UL)                    /*!< GPIO13 (Bit 13)                                       */
12640 #define GPIO_INT0EN_GPIO13_Msk            (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
12641 #define GPIO_INT0EN_GPIO12_Pos            (12UL)                    /*!< GPIO12 (Bit 12)                                       */
12642 #define GPIO_INT0EN_GPIO12_Msk            (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
12643 #define GPIO_INT0EN_GPIO11_Pos            (11UL)                    /*!< GPIO11 (Bit 11)                                       */
12644 #define GPIO_INT0EN_GPIO11_Msk            (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
12645 #define GPIO_INT0EN_GPIO10_Pos            (10UL)                    /*!< GPIO10 (Bit 10)                                       */
12646 #define GPIO_INT0EN_GPIO10_Msk            (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
12647 #define GPIO_INT0EN_GPIO9_Pos             (9UL)                     /*!< GPIO9 (Bit 9)                                         */
12648 #define GPIO_INT0EN_GPIO9_Msk             (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
12649 #define GPIO_INT0EN_GPIO8_Pos             (8UL)                     /*!< GPIO8 (Bit 8)                                         */
12650 #define GPIO_INT0EN_GPIO8_Msk             (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
12651 #define GPIO_INT0EN_GPIO7_Pos             (7UL)                     /*!< GPIO7 (Bit 7)                                         */
12652 #define GPIO_INT0EN_GPIO7_Msk             (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
12653 #define GPIO_INT0EN_GPIO6_Pos             (6UL)                     /*!< GPIO6 (Bit 6)                                         */
12654 #define GPIO_INT0EN_GPIO6_Msk             (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
12655 #define GPIO_INT0EN_GPIO5_Pos             (5UL)                     /*!< GPIO5 (Bit 5)                                         */
12656 #define GPIO_INT0EN_GPIO5_Msk             (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
12657 #define GPIO_INT0EN_GPIO4_Pos             (4UL)                     /*!< GPIO4 (Bit 4)                                         */
12658 #define GPIO_INT0EN_GPIO4_Msk             (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
12659 #define GPIO_INT0EN_GPIO3_Pos             (3UL)                     /*!< GPIO3 (Bit 3)                                         */
12660 #define GPIO_INT0EN_GPIO3_Msk             (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
12661 #define GPIO_INT0EN_GPIO2_Pos             (2UL)                     /*!< GPIO2 (Bit 2)                                         */
12662 #define GPIO_INT0EN_GPIO2_Msk             (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
12663 #define GPIO_INT0EN_GPIO1_Pos             (1UL)                     /*!< GPIO1 (Bit 1)                                         */
12664 #define GPIO_INT0EN_GPIO1_Msk             (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
12665 #define GPIO_INT0EN_GPIO0_Pos             (0UL)                     /*!< GPIO0 (Bit 0)                                         */
12666 #define GPIO_INT0EN_GPIO0_Msk             (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
12667 /* =======================================================  INT0STAT  ======================================================== */
12668 #define GPIO_INT0STAT_GPIO31_Pos          (31UL)                    /*!< GPIO31 (Bit 31)                                       */
12669 #define GPIO_INT0STAT_GPIO31_Msk          (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
12670 #define GPIO_INT0STAT_GPIO30_Pos          (30UL)                    /*!< GPIO30 (Bit 30)                                       */
12671 #define GPIO_INT0STAT_GPIO30_Msk          (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
12672 #define GPIO_INT0STAT_GPIO29_Pos          (29UL)                    /*!< GPIO29 (Bit 29)                                       */
12673 #define GPIO_INT0STAT_GPIO29_Msk          (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
12674 #define GPIO_INT0STAT_GPIO28_Pos          (28UL)                    /*!< GPIO28 (Bit 28)                                       */
12675 #define GPIO_INT0STAT_GPIO28_Msk          (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
12676 #define GPIO_INT0STAT_GPIO27_Pos          (27UL)                    /*!< GPIO27 (Bit 27)                                       */
12677 #define GPIO_INT0STAT_GPIO27_Msk          (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
12678 #define GPIO_INT0STAT_GPIO26_Pos          (26UL)                    /*!< GPIO26 (Bit 26)                                       */
12679 #define GPIO_INT0STAT_GPIO26_Msk          (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
12680 #define GPIO_INT0STAT_GPIO25_Pos          (25UL)                    /*!< GPIO25 (Bit 25)                                       */
12681 #define GPIO_INT0STAT_GPIO25_Msk          (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
12682 #define GPIO_INT0STAT_GPIO24_Pos          (24UL)                    /*!< GPIO24 (Bit 24)                                       */
12683 #define GPIO_INT0STAT_GPIO24_Msk          (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
12684 #define GPIO_INT0STAT_GPIO23_Pos          (23UL)                    /*!< GPIO23 (Bit 23)                                       */
12685 #define GPIO_INT0STAT_GPIO23_Msk          (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
12686 #define GPIO_INT0STAT_GPIO22_Pos          (22UL)                    /*!< GPIO22 (Bit 22)                                       */
12687 #define GPIO_INT0STAT_GPIO22_Msk          (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
12688 #define GPIO_INT0STAT_GPIO21_Pos          (21UL)                    /*!< GPIO21 (Bit 21)                                       */
12689 #define GPIO_INT0STAT_GPIO21_Msk          (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
12690 #define GPIO_INT0STAT_GPIO20_Pos          (20UL)                    /*!< GPIO20 (Bit 20)                                       */
12691 #define GPIO_INT0STAT_GPIO20_Msk          (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
12692 #define GPIO_INT0STAT_GPIO19_Pos          (19UL)                    /*!< GPIO19 (Bit 19)                                       */
12693 #define GPIO_INT0STAT_GPIO19_Msk          (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
12694 #define GPIO_INT0STAT_GPIO18_Pos          (18UL)                    /*!< GPIO18 (Bit 18)                                       */
12695 #define GPIO_INT0STAT_GPIO18_Msk          (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
12696 #define GPIO_INT0STAT_GPIO17_Pos          (17UL)                    /*!< GPIO17 (Bit 17)                                       */
12697 #define GPIO_INT0STAT_GPIO17_Msk          (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
12698 #define GPIO_INT0STAT_GPIO16_Pos          (16UL)                    /*!< GPIO16 (Bit 16)                                       */
12699 #define GPIO_INT0STAT_GPIO16_Msk          (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
12700 #define GPIO_INT0STAT_GPIO15_Pos          (15UL)                    /*!< GPIO15 (Bit 15)                                       */
12701 #define GPIO_INT0STAT_GPIO15_Msk          (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
12702 #define GPIO_INT0STAT_GPIO14_Pos          (14UL)                    /*!< GPIO14 (Bit 14)                                       */
12703 #define GPIO_INT0STAT_GPIO14_Msk          (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
12704 #define GPIO_INT0STAT_GPIO13_Pos          (13UL)                    /*!< GPIO13 (Bit 13)                                       */
12705 #define GPIO_INT0STAT_GPIO13_Msk          (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
12706 #define GPIO_INT0STAT_GPIO12_Pos          (12UL)                    /*!< GPIO12 (Bit 12)                                       */
12707 #define GPIO_INT0STAT_GPIO12_Msk          (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
12708 #define GPIO_INT0STAT_GPIO11_Pos          (11UL)                    /*!< GPIO11 (Bit 11)                                       */
12709 #define GPIO_INT0STAT_GPIO11_Msk          (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
12710 #define GPIO_INT0STAT_GPIO10_Pos          (10UL)                    /*!< GPIO10 (Bit 10)                                       */
12711 #define GPIO_INT0STAT_GPIO10_Msk          (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
12712 #define GPIO_INT0STAT_GPIO9_Pos           (9UL)                     /*!< GPIO9 (Bit 9)                                         */
12713 #define GPIO_INT0STAT_GPIO9_Msk           (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
12714 #define GPIO_INT0STAT_GPIO8_Pos           (8UL)                     /*!< GPIO8 (Bit 8)                                         */
12715 #define GPIO_INT0STAT_GPIO8_Msk           (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
12716 #define GPIO_INT0STAT_GPIO7_Pos           (7UL)                     /*!< GPIO7 (Bit 7)                                         */
12717 #define GPIO_INT0STAT_GPIO7_Msk           (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
12718 #define GPIO_INT0STAT_GPIO6_Pos           (6UL)                     /*!< GPIO6 (Bit 6)                                         */
12719 #define GPIO_INT0STAT_GPIO6_Msk           (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
12720 #define GPIO_INT0STAT_GPIO5_Pos           (5UL)                     /*!< GPIO5 (Bit 5)                                         */
12721 #define GPIO_INT0STAT_GPIO5_Msk           (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
12722 #define GPIO_INT0STAT_GPIO4_Pos           (4UL)                     /*!< GPIO4 (Bit 4)                                         */
12723 #define GPIO_INT0STAT_GPIO4_Msk           (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
12724 #define GPIO_INT0STAT_GPIO3_Pos           (3UL)                     /*!< GPIO3 (Bit 3)                                         */
12725 #define GPIO_INT0STAT_GPIO3_Msk           (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
12726 #define GPIO_INT0STAT_GPIO2_Pos           (2UL)                     /*!< GPIO2 (Bit 2)                                         */
12727 #define GPIO_INT0STAT_GPIO2_Msk           (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
12728 #define GPIO_INT0STAT_GPIO1_Pos           (1UL)                     /*!< GPIO1 (Bit 1)                                         */
12729 #define GPIO_INT0STAT_GPIO1_Msk           (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
12730 #define GPIO_INT0STAT_GPIO0_Pos           (0UL)                     /*!< GPIO0 (Bit 0)                                         */
12731 #define GPIO_INT0STAT_GPIO0_Msk           (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
12732 /* ========================================================  INT0CLR  ======================================================== */
12733 #define GPIO_INT0CLR_GPIO31_Pos           (31UL)                    /*!< GPIO31 (Bit 31)                                       */
12734 #define GPIO_INT0CLR_GPIO31_Msk           (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
12735 #define GPIO_INT0CLR_GPIO30_Pos           (30UL)                    /*!< GPIO30 (Bit 30)                                       */
12736 #define GPIO_INT0CLR_GPIO30_Msk           (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
12737 #define GPIO_INT0CLR_GPIO29_Pos           (29UL)                    /*!< GPIO29 (Bit 29)                                       */
12738 #define GPIO_INT0CLR_GPIO29_Msk           (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
12739 #define GPIO_INT0CLR_GPIO28_Pos           (28UL)                    /*!< GPIO28 (Bit 28)                                       */
12740 #define GPIO_INT0CLR_GPIO28_Msk           (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
12741 #define GPIO_INT0CLR_GPIO27_Pos           (27UL)                    /*!< GPIO27 (Bit 27)                                       */
12742 #define GPIO_INT0CLR_GPIO27_Msk           (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
12743 #define GPIO_INT0CLR_GPIO26_Pos           (26UL)                    /*!< GPIO26 (Bit 26)                                       */
12744 #define GPIO_INT0CLR_GPIO26_Msk           (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
12745 #define GPIO_INT0CLR_GPIO25_Pos           (25UL)                    /*!< GPIO25 (Bit 25)                                       */
12746 #define GPIO_INT0CLR_GPIO25_Msk           (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
12747 #define GPIO_INT0CLR_GPIO24_Pos           (24UL)                    /*!< GPIO24 (Bit 24)                                       */
12748 #define GPIO_INT0CLR_GPIO24_Msk           (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
12749 #define GPIO_INT0CLR_GPIO23_Pos           (23UL)                    /*!< GPIO23 (Bit 23)                                       */
12750 #define GPIO_INT0CLR_GPIO23_Msk           (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
12751 #define GPIO_INT0CLR_GPIO22_Pos           (22UL)                    /*!< GPIO22 (Bit 22)                                       */
12752 #define GPIO_INT0CLR_GPIO22_Msk           (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
12753 #define GPIO_INT0CLR_GPIO21_Pos           (21UL)                    /*!< GPIO21 (Bit 21)                                       */
12754 #define GPIO_INT0CLR_GPIO21_Msk           (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
12755 #define GPIO_INT0CLR_GPIO20_Pos           (20UL)                    /*!< GPIO20 (Bit 20)                                       */
12756 #define GPIO_INT0CLR_GPIO20_Msk           (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
12757 #define GPIO_INT0CLR_GPIO19_Pos           (19UL)                    /*!< GPIO19 (Bit 19)                                       */
12758 #define GPIO_INT0CLR_GPIO19_Msk           (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
12759 #define GPIO_INT0CLR_GPIO18_Pos           (18UL)                    /*!< GPIO18 (Bit 18)                                       */
12760 #define GPIO_INT0CLR_GPIO18_Msk           (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
12761 #define GPIO_INT0CLR_GPIO17_Pos           (17UL)                    /*!< GPIO17 (Bit 17)                                       */
12762 #define GPIO_INT0CLR_GPIO17_Msk           (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
12763 #define GPIO_INT0CLR_GPIO16_Pos           (16UL)                    /*!< GPIO16 (Bit 16)                                       */
12764 #define GPIO_INT0CLR_GPIO16_Msk           (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
12765 #define GPIO_INT0CLR_GPIO15_Pos           (15UL)                    /*!< GPIO15 (Bit 15)                                       */
12766 #define GPIO_INT0CLR_GPIO15_Msk           (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
12767 #define GPIO_INT0CLR_GPIO14_Pos           (14UL)                    /*!< GPIO14 (Bit 14)                                       */
12768 #define GPIO_INT0CLR_GPIO14_Msk           (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
12769 #define GPIO_INT0CLR_GPIO13_Pos           (13UL)                    /*!< GPIO13 (Bit 13)                                       */
12770 #define GPIO_INT0CLR_GPIO13_Msk           (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
12771 #define GPIO_INT0CLR_GPIO12_Pos           (12UL)                    /*!< GPIO12 (Bit 12)                                       */
12772 #define GPIO_INT0CLR_GPIO12_Msk           (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
12773 #define GPIO_INT0CLR_GPIO11_Pos           (11UL)                    /*!< GPIO11 (Bit 11)                                       */
12774 #define GPIO_INT0CLR_GPIO11_Msk           (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
12775 #define GPIO_INT0CLR_GPIO10_Pos           (10UL)                    /*!< GPIO10 (Bit 10)                                       */
12776 #define GPIO_INT0CLR_GPIO10_Msk           (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
12777 #define GPIO_INT0CLR_GPIO9_Pos            (9UL)                     /*!< GPIO9 (Bit 9)                                         */
12778 #define GPIO_INT0CLR_GPIO9_Msk            (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
12779 #define GPIO_INT0CLR_GPIO8_Pos            (8UL)                     /*!< GPIO8 (Bit 8)                                         */
12780 #define GPIO_INT0CLR_GPIO8_Msk            (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
12781 #define GPIO_INT0CLR_GPIO7_Pos            (7UL)                     /*!< GPIO7 (Bit 7)                                         */
12782 #define GPIO_INT0CLR_GPIO7_Msk            (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
12783 #define GPIO_INT0CLR_GPIO6_Pos            (6UL)                     /*!< GPIO6 (Bit 6)                                         */
12784 #define GPIO_INT0CLR_GPIO6_Msk            (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
12785 #define GPIO_INT0CLR_GPIO5_Pos            (5UL)                     /*!< GPIO5 (Bit 5)                                         */
12786 #define GPIO_INT0CLR_GPIO5_Msk            (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
12787 #define GPIO_INT0CLR_GPIO4_Pos            (4UL)                     /*!< GPIO4 (Bit 4)                                         */
12788 #define GPIO_INT0CLR_GPIO4_Msk            (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
12789 #define GPIO_INT0CLR_GPIO3_Pos            (3UL)                     /*!< GPIO3 (Bit 3)                                         */
12790 #define GPIO_INT0CLR_GPIO3_Msk            (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
12791 #define GPIO_INT0CLR_GPIO2_Pos            (2UL)                     /*!< GPIO2 (Bit 2)                                         */
12792 #define GPIO_INT0CLR_GPIO2_Msk            (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
12793 #define GPIO_INT0CLR_GPIO1_Pos            (1UL)                     /*!< GPIO1 (Bit 1)                                         */
12794 #define GPIO_INT0CLR_GPIO1_Msk            (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
12795 #define GPIO_INT0CLR_GPIO0_Pos            (0UL)                     /*!< GPIO0 (Bit 0)                                         */
12796 #define GPIO_INT0CLR_GPIO0_Msk            (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
12797 /* ========================================================  INT0SET  ======================================================== */
12798 #define GPIO_INT0SET_GPIO31_Pos           (31UL)                    /*!< GPIO31 (Bit 31)                                       */
12799 #define GPIO_INT0SET_GPIO31_Msk           (0x80000000UL)            /*!< GPIO31 (Bitfield-Mask: 0x01)                          */
12800 #define GPIO_INT0SET_GPIO30_Pos           (30UL)                    /*!< GPIO30 (Bit 30)                                       */
12801 #define GPIO_INT0SET_GPIO30_Msk           (0x40000000UL)            /*!< GPIO30 (Bitfield-Mask: 0x01)                          */
12802 #define GPIO_INT0SET_GPIO29_Pos           (29UL)                    /*!< GPIO29 (Bit 29)                                       */
12803 #define GPIO_INT0SET_GPIO29_Msk           (0x20000000UL)            /*!< GPIO29 (Bitfield-Mask: 0x01)                          */
12804 #define GPIO_INT0SET_GPIO28_Pos           (28UL)                    /*!< GPIO28 (Bit 28)                                       */
12805 #define GPIO_INT0SET_GPIO28_Msk           (0x10000000UL)            /*!< GPIO28 (Bitfield-Mask: 0x01)                          */
12806 #define GPIO_INT0SET_GPIO27_Pos           (27UL)                    /*!< GPIO27 (Bit 27)                                       */
12807 #define GPIO_INT0SET_GPIO27_Msk           (0x8000000UL)             /*!< GPIO27 (Bitfield-Mask: 0x01)                          */
12808 #define GPIO_INT0SET_GPIO26_Pos           (26UL)                    /*!< GPIO26 (Bit 26)                                       */
12809 #define GPIO_INT0SET_GPIO26_Msk           (0x4000000UL)             /*!< GPIO26 (Bitfield-Mask: 0x01)                          */
12810 #define GPIO_INT0SET_GPIO25_Pos           (25UL)                    /*!< GPIO25 (Bit 25)                                       */
12811 #define GPIO_INT0SET_GPIO25_Msk           (0x2000000UL)             /*!< GPIO25 (Bitfield-Mask: 0x01)                          */
12812 #define GPIO_INT0SET_GPIO24_Pos           (24UL)                    /*!< GPIO24 (Bit 24)                                       */
12813 #define GPIO_INT0SET_GPIO24_Msk           (0x1000000UL)             /*!< GPIO24 (Bitfield-Mask: 0x01)                          */
12814 #define GPIO_INT0SET_GPIO23_Pos           (23UL)                    /*!< GPIO23 (Bit 23)                                       */
12815 #define GPIO_INT0SET_GPIO23_Msk           (0x800000UL)              /*!< GPIO23 (Bitfield-Mask: 0x01)                          */
12816 #define GPIO_INT0SET_GPIO22_Pos           (22UL)                    /*!< GPIO22 (Bit 22)                                       */
12817 #define GPIO_INT0SET_GPIO22_Msk           (0x400000UL)              /*!< GPIO22 (Bitfield-Mask: 0x01)                          */
12818 #define GPIO_INT0SET_GPIO21_Pos           (21UL)                    /*!< GPIO21 (Bit 21)                                       */
12819 #define GPIO_INT0SET_GPIO21_Msk           (0x200000UL)              /*!< GPIO21 (Bitfield-Mask: 0x01)                          */
12820 #define GPIO_INT0SET_GPIO20_Pos           (20UL)                    /*!< GPIO20 (Bit 20)                                       */
12821 #define GPIO_INT0SET_GPIO20_Msk           (0x100000UL)              /*!< GPIO20 (Bitfield-Mask: 0x01)                          */
12822 #define GPIO_INT0SET_GPIO19_Pos           (19UL)                    /*!< GPIO19 (Bit 19)                                       */
12823 #define GPIO_INT0SET_GPIO19_Msk           (0x80000UL)               /*!< GPIO19 (Bitfield-Mask: 0x01)                          */
12824 #define GPIO_INT0SET_GPIO18_Pos           (18UL)                    /*!< GPIO18 (Bit 18)                                       */
12825 #define GPIO_INT0SET_GPIO18_Msk           (0x40000UL)               /*!< GPIO18 (Bitfield-Mask: 0x01)                          */
12826 #define GPIO_INT0SET_GPIO17_Pos           (17UL)                    /*!< GPIO17 (Bit 17)                                       */
12827 #define GPIO_INT0SET_GPIO17_Msk           (0x20000UL)               /*!< GPIO17 (Bitfield-Mask: 0x01)                          */
12828 #define GPIO_INT0SET_GPIO16_Pos           (16UL)                    /*!< GPIO16 (Bit 16)                                       */
12829 #define GPIO_INT0SET_GPIO16_Msk           (0x10000UL)               /*!< GPIO16 (Bitfield-Mask: 0x01)                          */
12830 #define GPIO_INT0SET_GPIO15_Pos           (15UL)                    /*!< GPIO15 (Bit 15)                                       */
12831 #define GPIO_INT0SET_GPIO15_Msk           (0x8000UL)                /*!< GPIO15 (Bitfield-Mask: 0x01)                          */
12832 #define GPIO_INT0SET_GPIO14_Pos           (14UL)                    /*!< GPIO14 (Bit 14)                                       */
12833 #define GPIO_INT0SET_GPIO14_Msk           (0x4000UL)                /*!< GPIO14 (Bitfield-Mask: 0x01)                          */
12834 #define GPIO_INT0SET_GPIO13_Pos           (13UL)                    /*!< GPIO13 (Bit 13)                                       */
12835 #define GPIO_INT0SET_GPIO13_Msk           (0x2000UL)                /*!< GPIO13 (Bitfield-Mask: 0x01)                          */
12836 #define GPIO_INT0SET_GPIO12_Pos           (12UL)                    /*!< GPIO12 (Bit 12)                                       */
12837 #define GPIO_INT0SET_GPIO12_Msk           (0x1000UL)                /*!< GPIO12 (Bitfield-Mask: 0x01)                          */
12838 #define GPIO_INT0SET_GPIO11_Pos           (11UL)                    /*!< GPIO11 (Bit 11)                                       */
12839 #define GPIO_INT0SET_GPIO11_Msk           (0x800UL)                 /*!< GPIO11 (Bitfield-Mask: 0x01)                          */
12840 #define GPIO_INT0SET_GPIO10_Pos           (10UL)                    /*!< GPIO10 (Bit 10)                                       */
12841 #define GPIO_INT0SET_GPIO10_Msk           (0x400UL)                 /*!< GPIO10 (Bitfield-Mask: 0x01)                          */
12842 #define GPIO_INT0SET_GPIO9_Pos            (9UL)                     /*!< GPIO9 (Bit 9)                                         */
12843 #define GPIO_INT0SET_GPIO9_Msk            (0x200UL)                 /*!< GPIO9 (Bitfield-Mask: 0x01)                           */
12844 #define GPIO_INT0SET_GPIO8_Pos            (8UL)                     /*!< GPIO8 (Bit 8)                                         */
12845 #define GPIO_INT0SET_GPIO8_Msk            (0x100UL)                 /*!< GPIO8 (Bitfield-Mask: 0x01)                           */
12846 #define GPIO_INT0SET_GPIO7_Pos            (7UL)                     /*!< GPIO7 (Bit 7)                                         */
12847 #define GPIO_INT0SET_GPIO7_Msk            (0x80UL)                  /*!< GPIO7 (Bitfield-Mask: 0x01)                           */
12848 #define GPIO_INT0SET_GPIO6_Pos            (6UL)                     /*!< GPIO6 (Bit 6)                                         */
12849 #define GPIO_INT0SET_GPIO6_Msk            (0x40UL)                  /*!< GPIO6 (Bitfield-Mask: 0x01)                           */
12850 #define GPIO_INT0SET_GPIO5_Pos            (5UL)                     /*!< GPIO5 (Bit 5)                                         */
12851 #define GPIO_INT0SET_GPIO5_Msk            (0x20UL)                  /*!< GPIO5 (Bitfield-Mask: 0x01)                           */
12852 #define GPIO_INT0SET_GPIO4_Pos            (4UL)                     /*!< GPIO4 (Bit 4)                                         */
12853 #define GPIO_INT0SET_GPIO4_Msk            (0x10UL)                  /*!< GPIO4 (Bitfield-Mask: 0x01)                           */
12854 #define GPIO_INT0SET_GPIO3_Pos            (3UL)                     /*!< GPIO3 (Bit 3)                                         */
12855 #define GPIO_INT0SET_GPIO3_Msk            (0x8UL)                   /*!< GPIO3 (Bitfield-Mask: 0x01)                           */
12856 #define GPIO_INT0SET_GPIO2_Pos            (2UL)                     /*!< GPIO2 (Bit 2)                                         */
12857 #define GPIO_INT0SET_GPIO2_Msk            (0x4UL)                   /*!< GPIO2 (Bitfield-Mask: 0x01)                           */
12858 #define GPIO_INT0SET_GPIO1_Pos            (1UL)                     /*!< GPIO1 (Bit 1)                                         */
12859 #define GPIO_INT0SET_GPIO1_Msk            (0x2UL)                   /*!< GPIO1 (Bitfield-Mask: 0x01)                           */
12860 #define GPIO_INT0SET_GPIO0_Pos            (0UL)                     /*!< GPIO0 (Bit 0)                                         */
12861 #define GPIO_INT0SET_GPIO0_Msk            (0x1UL)                   /*!< GPIO0 (Bitfield-Mask: 0x01)                           */
12862 /* ========================================================  INT1EN  ========================================================= */
12863 #define GPIO_INT1EN_GPIO49_Pos            (17UL)                    /*!< GPIO49 (Bit 17)                                       */
12864 #define GPIO_INT1EN_GPIO49_Msk            (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
12865 #define GPIO_INT1EN_GPIO48_Pos            (16UL)                    /*!< GPIO48 (Bit 16)                                       */
12866 #define GPIO_INT1EN_GPIO48_Msk            (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
12867 #define GPIO_INT1EN_GPIO47_Pos            (15UL)                    /*!< GPIO47 (Bit 15)                                       */
12868 #define GPIO_INT1EN_GPIO47_Msk            (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
12869 #define GPIO_INT1EN_GPIO46_Pos            (14UL)                    /*!< GPIO46 (Bit 14)                                       */
12870 #define GPIO_INT1EN_GPIO46_Msk            (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
12871 #define GPIO_INT1EN_GPIO45_Pos            (13UL)                    /*!< GPIO45 (Bit 13)                                       */
12872 #define GPIO_INT1EN_GPIO45_Msk            (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
12873 #define GPIO_INT1EN_GPIO44_Pos            (12UL)                    /*!< GPIO44 (Bit 12)                                       */
12874 #define GPIO_INT1EN_GPIO44_Msk            (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
12875 #define GPIO_INT1EN_GPIO43_Pos            (11UL)                    /*!< GPIO43 (Bit 11)                                       */
12876 #define GPIO_INT1EN_GPIO43_Msk            (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
12877 #define GPIO_INT1EN_GPIO42_Pos            (10UL)                    /*!< GPIO42 (Bit 10)                                       */
12878 #define GPIO_INT1EN_GPIO42_Msk            (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
12879 #define GPIO_INT1EN_GPIO41_Pos            (9UL)                     /*!< GPIO41 (Bit 9)                                        */
12880 #define GPIO_INT1EN_GPIO41_Msk            (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
12881 #define GPIO_INT1EN_GPIO40_Pos            (8UL)                     /*!< GPIO40 (Bit 8)                                        */
12882 #define GPIO_INT1EN_GPIO40_Msk            (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
12883 #define GPIO_INT1EN_GPIO39_Pos            (7UL)                     /*!< GPIO39 (Bit 7)                                        */
12884 #define GPIO_INT1EN_GPIO39_Msk            (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
12885 #define GPIO_INT1EN_GPIO38_Pos            (6UL)                     /*!< GPIO38 (Bit 6)                                        */
12886 #define GPIO_INT1EN_GPIO38_Msk            (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
12887 #define GPIO_INT1EN_GPIO37_Pos            (5UL)                     /*!< GPIO37 (Bit 5)                                        */
12888 #define GPIO_INT1EN_GPIO37_Msk            (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
12889 #define GPIO_INT1EN_GPIO36_Pos            (4UL)                     /*!< GPIO36 (Bit 4)                                        */
12890 #define GPIO_INT1EN_GPIO36_Msk            (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
12891 #define GPIO_INT1EN_GPIO35_Pos            (3UL)                     /*!< GPIO35 (Bit 3)                                        */
12892 #define GPIO_INT1EN_GPIO35_Msk            (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
12893 #define GPIO_INT1EN_GPIO34_Pos            (2UL)                     /*!< GPIO34 (Bit 2)                                        */
12894 #define GPIO_INT1EN_GPIO34_Msk            (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
12895 #define GPIO_INT1EN_GPIO33_Pos            (1UL)                     /*!< GPIO33 (Bit 1)                                        */
12896 #define GPIO_INT1EN_GPIO33_Msk            (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
12897 #define GPIO_INT1EN_GPIO32_Pos            (0UL)                     /*!< GPIO32 (Bit 0)                                        */
12898 #define GPIO_INT1EN_GPIO32_Msk            (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
12899 /* =======================================================  INT1STAT  ======================================================== */
12900 #define GPIO_INT1STAT_GPIO49_Pos          (17UL)                    /*!< GPIO49 (Bit 17)                                       */
12901 #define GPIO_INT1STAT_GPIO49_Msk          (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
12902 #define GPIO_INT1STAT_GPIO48_Pos          (16UL)                    /*!< GPIO48 (Bit 16)                                       */
12903 #define GPIO_INT1STAT_GPIO48_Msk          (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
12904 #define GPIO_INT1STAT_GPIO47_Pos          (15UL)                    /*!< GPIO47 (Bit 15)                                       */
12905 #define GPIO_INT1STAT_GPIO47_Msk          (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
12906 #define GPIO_INT1STAT_GPIO46_Pos          (14UL)                    /*!< GPIO46 (Bit 14)                                       */
12907 #define GPIO_INT1STAT_GPIO46_Msk          (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
12908 #define GPIO_INT1STAT_GPIO45_Pos          (13UL)                    /*!< GPIO45 (Bit 13)                                       */
12909 #define GPIO_INT1STAT_GPIO45_Msk          (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
12910 #define GPIO_INT1STAT_GPIO44_Pos          (12UL)                    /*!< GPIO44 (Bit 12)                                       */
12911 #define GPIO_INT1STAT_GPIO44_Msk          (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
12912 #define GPIO_INT1STAT_GPIO43_Pos          (11UL)                    /*!< GPIO43 (Bit 11)                                       */
12913 #define GPIO_INT1STAT_GPIO43_Msk          (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
12914 #define GPIO_INT1STAT_GPIO42_Pos          (10UL)                    /*!< GPIO42 (Bit 10)                                       */
12915 #define GPIO_INT1STAT_GPIO42_Msk          (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
12916 #define GPIO_INT1STAT_GPIO41_Pos          (9UL)                     /*!< GPIO41 (Bit 9)                                        */
12917 #define GPIO_INT1STAT_GPIO41_Msk          (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
12918 #define GPIO_INT1STAT_GPIO40_Pos          (8UL)                     /*!< GPIO40 (Bit 8)                                        */
12919 #define GPIO_INT1STAT_GPIO40_Msk          (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
12920 #define GPIO_INT1STAT_GPIO39_Pos          (7UL)                     /*!< GPIO39 (Bit 7)                                        */
12921 #define GPIO_INT1STAT_GPIO39_Msk          (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
12922 #define GPIO_INT1STAT_GPIO38_Pos          (6UL)                     /*!< GPIO38 (Bit 6)                                        */
12923 #define GPIO_INT1STAT_GPIO38_Msk          (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
12924 #define GPIO_INT1STAT_GPIO37_Pos          (5UL)                     /*!< GPIO37 (Bit 5)                                        */
12925 #define GPIO_INT1STAT_GPIO37_Msk          (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
12926 #define GPIO_INT1STAT_GPIO36_Pos          (4UL)                     /*!< GPIO36 (Bit 4)                                        */
12927 #define GPIO_INT1STAT_GPIO36_Msk          (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
12928 #define GPIO_INT1STAT_GPIO35_Pos          (3UL)                     /*!< GPIO35 (Bit 3)                                        */
12929 #define GPIO_INT1STAT_GPIO35_Msk          (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
12930 #define GPIO_INT1STAT_GPIO34_Pos          (2UL)                     /*!< GPIO34 (Bit 2)                                        */
12931 #define GPIO_INT1STAT_GPIO34_Msk          (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
12932 #define GPIO_INT1STAT_GPIO33_Pos          (1UL)                     /*!< GPIO33 (Bit 1)                                        */
12933 #define GPIO_INT1STAT_GPIO33_Msk          (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
12934 #define GPIO_INT1STAT_GPIO32_Pos          (0UL)                     /*!< GPIO32 (Bit 0)                                        */
12935 #define GPIO_INT1STAT_GPIO32_Msk          (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
12936 /* ========================================================  INT1CLR  ======================================================== */
12937 #define GPIO_INT1CLR_GPIO49_Pos           (17UL)                    /*!< GPIO49 (Bit 17)                                       */
12938 #define GPIO_INT1CLR_GPIO49_Msk           (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
12939 #define GPIO_INT1CLR_GPIO48_Pos           (16UL)                    /*!< GPIO48 (Bit 16)                                       */
12940 #define GPIO_INT1CLR_GPIO48_Msk           (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
12941 #define GPIO_INT1CLR_GPIO47_Pos           (15UL)                    /*!< GPIO47 (Bit 15)                                       */
12942 #define GPIO_INT1CLR_GPIO47_Msk           (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
12943 #define GPIO_INT1CLR_GPIO46_Pos           (14UL)                    /*!< GPIO46 (Bit 14)                                       */
12944 #define GPIO_INT1CLR_GPIO46_Msk           (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
12945 #define GPIO_INT1CLR_GPIO45_Pos           (13UL)                    /*!< GPIO45 (Bit 13)                                       */
12946 #define GPIO_INT1CLR_GPIO45_Msk           (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
12947 #define GPIO_INT1CLR_GPIO44_Pos           (12UL)                    /*!< GPIO44 (Bit 12)                                       */
12948 #define GPIO_INT1CLR_GPIO44_Msk           (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
12949 #define GPIO_INT1CLR_GPIO43_Pos           (11UL)                    /*!< GPIO43 (Bit 11)                                       */
12950 #define GPIO_INT1CLR_GPIO43_Msk           (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
12951 #define GPIO_INT1CLR_GPIO42_Pos           (10UL)                    /*!< GPIO42 (Bit 10)                                       */
12952 #define GPIO_INT1CLR_GPIO42_Msk           (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
12953 #define GPIO_INT1CLR_GPIO41_Pos           (9UL)                     /*!< GPIO41 (Bit 9)                                        */
12954 #define GPIO_INT1CLR_GPIO41_Msk           (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
12955 #define GPIO_INT1CLR_GPIO40_Pos           (8UL)                     /*!< GPIO40 (Bit 8)                                        */
12956 #define GPIO_INT1CLR_GPIO40_Msk           (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
12957 #define GPIO_INT1CLR_GPIO39_Pos           (7UL)                     /*!< GPIO39 (Bit 7)                                        */
12958 #define GPIO_INT1CLR_GPIO39_Msk           (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
12959 #define GPIO_INT1CLR_GPIO38_Pos           (6UL)                     /*!< GPIO38 (Bit 6)                                        */
12960 #define GPIO_INT1CLR_GPIO38_Msk           (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
12961 #define GPIO_INT1CLR_GPIO37_Pos           (5UL)                     /*!< GPIO37 (Bit 5)                                        */
12962 #define GPIO_INT1CLR_GPIO37_Msk           (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
12963 #define GPIO_INT1CLR_GPIO36_Pos           (4UL)                     /*!< GPIO36 (Bit 4)                                        */
12964 #define GPIO_INT1CLR_GPIO36_Msk           (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
12965 #define GPIO_INT1CLR_GPIO35_Pos           (3UL)                     /*!< GPIO35 (Bit 3)                                        */
12966 #define GPIO_INT1CLR_GPIO35_Msk           (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
12967 #define GPIO_INT1CLR_GPIO34_Pos           (2UL)                     /*!< GPIO34 (Bit 2)                                        */
12968 #define GPIO_INT1CLR_GPIO34_Msk           (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
12969 #define GPIO_INT1CLR_GPIO33_Pos           (1UL)                     /*!< GPIO33 (Bit 1)                                        */
12970 #define GPIO_INT1CLR_GPIO33_Msk           (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
12971 #define GPIO_INT1CLR_GPIO32_Pos           (0UL)                     /*!< GPIO32 (Bit 0)                                        */
12972 #define GPIO_INT1CLR_GPIO32_Msk           (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
12973 /* ========================================================  INT1SET  ======================================================== */
12974 #define GPIO_INT1SET_GPIO49_Pos           (17UL)                    /*!< GPIO49 (Bit 17)                                       */
12975 #define GPIO_INT1SET_GPIO49_Msk           (0x20000UL)               /*!< GPIO49 (Bitfield-Mask: 0x01)                          */
12976 #define GPIO_INT1SET_GPIO48_Pos           (16UL)                    /*!< GPIO48 (Bit 16)                                       */
12977 #define GPIO_INT1SET_GPIO48_Msk           (0x10000UL)               /*!< GPIO48 (Bitfield-Mask: 0x01)                          */
12978 #define GPIO_INT1SET_GPIO47_Pos           (15UL)                    /*!< GPIO47 (Bit 15)                                       */
12979 #define GPIO_INT1SET_GPIO47_Msk           (0x8000UL)                /*!< GPIO47 (Bitfield-Mask: 0x01)                          */
12980 #define GPIO_INT1SET_GPIO46_Pos           (14UL)                    /*!< GPIO46 (Bit 14)                                       */
12981 #define GPIO_INT1SET_GPIO46_Msk           (0x4000UL)                /*!< GPIO46 (Bitfield-Mask: 0x01)                          */
12982 #define GPIO_INT1SET_GPIO45_Pos           (13UL)                    /*!< GPIO45 (Bit 13)                                       */
12983 #define GPIO_INT1SET_GPIO45_Msk           (0x2000UL)                /*!< GPIO45 (Bitfield-Mask: 0x01)                          */
12984 #define GPIO_INT1SET_GPIO44_Pos           (12UL)                    /*!< GPIO44 (Bit 12)                                       */
12985 #define GPIO_INT1SET_GPIO44_Msk           (0x1000UL)                /*!< GPIO44 (Bitfield-Mask: 0x01)                          */
12986 #define GPIO_INT1SET_GPIO43_Pos           (11UL)                    /*!< GPIO43 (Bit 11)                                       */
12987 #define GPIO_INT1SET_GPIO43_Msk           (0x800UL)                 /*!< GPIO43 (Bitfield-Mask: 0x01)                          */
12988 #define GPIO_INT1SET_GPIO42_Pos           (10UL)                    /*!< GPIO42 (Bit 10)                                       */
12989 #define GPIO_INT1SET_GPIO42_Msk           (0x400UL)                 /*!< GPIO42 (Bitfield-Mask: 0x01)                          */
12990 #define GPIO_INT1SET_GPIO41_Pos           (9UL)                     /*!< GPIO41 (Bit 9)                                        */
12991 #define GPIO_INT1SET_GPIO41_Msk           (0x200UL)                 /*!< GPIO41 (Bitfield-Mask: 0x01)                          */
12992 #define GPIO_INT1SET_GPIO40_Pos           (8UL)                     /*!< GPIO40 (Bit 8)                                        */
12993 #define GPIO_INT1SET_GPIO40_Msk           (0x100UL)                 /*!< GPIO40 (Bitfield-Mask: 0x01)                          */
12994 #define GPIO_INT1SET_GPIO39_Pos           (7UL)                     /*!< GPIO39 (Bit 7)                                        */
12995 #define GPIO_INT1SET_GPIO39_Msk           (0x80UL)                  /*!< GPIO39 (Bitfield-Mask: 0x01)                          */
12996 #define GPIO_INT1SET_GPIO38_Pos           (6UL)                     /*!< GPIO38 (Bit 6)                                        */
12997 #define GPIO_INT1SET_GPIO38_Msk           (0x40UL)                  /*!< GPIO38 (Bitfield-Mask: 0x01)                          */
12998 #define GPIO_INT1SET_GPIO37_Pos           (5UL)                     /*!< GPIO37 (Bit 5)                                        */
12999 #define GPIO_INT1SET_GPIO37_Msk           (0x20UL)                  /*!< GPIO37 (Bitfield-Mask: 0x01)                          */
13000 #define GPIO_INT1SET_GPIO36_Pos           (4UL)                     /*!< GPIO36 (Bit 4)                                        */
13001 #define GPIO_INT1SET_GPIO36_Msk           (0x10UL)                  /*!< GPIO36 (Bitfield-Mask: 0x01)                          */
13002 #define GPIO_INT1SET_GPIO35_Pos           (3UL)                     /*!< GPIO35 (Bit 3)                                        */
13003 #define GPIO_INT1SET_GPIO35_Msk           (0x8UL)                   /*!< GPIO35 (Bitfield-Mask: 0x01)                          */
13004 #define GPIO_INT1SET_GPIO34_Pos           (2UL)                     /*!< GPIO34 (Bit 2)                                        */
13005 #define GPIO_INT1SET_GPIO34_Msk           (0x4UL)                   /*!< GPIO34 (Bitfield-Mask: 0x01)                          */
13006 #define GPIO_INT1SET_GPIO33_Pos           (1UL)                     /*!< GPIO33 (Bit 1)                                        */
13007 #define GPIO_INT1SET_GPIO33_Msk           (0x2UL)                   /*!< GPIO33 (Bitfield-Mask: 0x01)                          */
13008 #define GPIO_INT1SET_GPIO32_Pos           (0UL)                     /*!< GPIO32 (Bit 0)                                        */
13009 #define GPIO_INT1SET_GPIO32_Msk           (0x1UL)                   /*!< GPIO32 (Bitfield-Mask: 0x01)                          */
13010 
13011 
13012 /* =========================================================================================================================== */
13013 /* ================                                           IOM0                                            ================ */
13014 /* =========================================================================================================================== */
13015 
13016 /* =========================================================  FIFO  ========================================================== */
13017 #define IOM0_FIFO_FIFO_Pos                (0UL)                     /*!< FIFO (Bit 0)                                          */
13018 #define IOM0_FIFO_FIFO_Msk                (0xffffffffUL)            /*!< FIFO (Bitfield-Mask: 0xffffffff)                      */
13019 /* ========================================================  FIFOPTR  ======================================================== */
13020 #define IOM0_FIFOPTR_FIFO1REM_Pos         (24UL)                    /*!< FIFO1REM (Bit 24)                                     */
13021 #define IOM0_FIFOPTR_FIFO1REM_Msk         (0xff000000UL)            /*!< FIFO1REM (Bitfield-Mask: 0xff)                        */
13022 #define IOM0_FIFOPTR_FIFO1SIZ_Pos         (16UL)                    /*!< FIFO1SIZ (Bit 16)                                     */
13023 #define IOM0_FIFOPTR_FIFO1SIZ_Msk         (0xff0000UL)              /*!< FIFO1SIZ (Bitfield-Mask: 0xff)                        */
13024 #define IOM0_FIFOPTR_FIFO0REM_Pos         (8UL)                     /*!< FIFO0REM (Bit 8)                                      */
13025 #define IOM0_FIFOPTR_FIFO0REM_Msk         (0xff00UL)                /*!< FIFO0REM (Bitfield-Mask: 0xff)                        */
13026 #define IOM0_FIFOPTR_FIFO0SIZ_Pos         (0UL)                     /*!< FIFO0SIZ (Bit 0)                                      */
13027 #define IOM0_FIFOPTR_FIFO0SIZ_Msk         (0xffUL)                  /*!< FIFO0SIZ (Bitfield-Mask: 0xff)                        */
13028 /* ========================================================  FIFOTHR  ======================================================== */
13029 #define IOM0_FIFOTHR_FIFOWTHR_Pos         (8UL)                     /*!< FIFOWTHR (Bit 8)                                      */
13030 #define IOM0_FIFOTHR_FIFOWTHR_Msk         (0x3f00UL)                /*!< FIFOWTHR (Bitfield-Mask: 0x3f)                        */
13031 #define IOM0_FIFOTHR_FIFORTHR_Pos         (0UL)                     /*!< FIFORTHR (Bit 0)                                      */
13032 #define IOM0_FIFOTHR_FIFORTHR_Msk         (0x3fUL)                  /*!< FIFORTHR (Bitfield-Mask: 0x3f)                        */
13033 /* ========================================================  FIFOPOP  ======================================================== */
13034 #define IOM0_FIFOPOP_FIFODOUT_Pos         (0UL)                     /*!< FIFODOUT (Bit 0)                                      */
13035 #define IOM0_FIFOPOP_FIFODOUT_Msk         (0xffffffffUL)            /*!< FIFODOUT (Bitfield-Mask: 0xffffffff)                  */
13036 /* =======================================================  FIFOPUSH  ======================================================== */
13037 #define IOM0_FIFOPUSH_FIFODIN_Pos         (0UL)                     /*!< FIFODIN (Bit 0)                                       */
13038 #define IOM0_FIFOPUSH_FIFODIN_Msk         (0xffffffffUL)            /*!< FIFODIN (Bitfield-Mask: 0xffffffff)                   */
13039 /* =======================================================  FIFOCTRL  ======================================================== */
13040 #define IOM0_FIFOCTRL_FIFORSTN_Pos        (1UL)                     /*!< FIFORSTN (Bit 1)                                      */
13041 #define IOM0_FIFOCTRL_FIFORSTN_Msk        (0x2UL)                   /*!< FIFORSTN (Bitfield-Mask: 0x01)                        */
13042 #define IOM0_FIFOCTRL_POPWR_Pos           (0UL)                     /*!< POPWR (Bit 0)                                         */
13043 #define IOM0_FIFOCTRL_POPWR_Msk           (0x1UL)                   /*!< POPWR (Bitfield-Mask: 0x01)                           */
13044 /* ========================================================  FIFOLOC  ======================================================== */
13045 #define IOM0_FIFOLOC_FIFORPTR_Pos         (8UL)                     /*!< FIFORPTR (Bit 8)                                      */
13046 #define IOM0_FIFOLOC_FIFORPTR_Msk         (0xf00UL)                 /*!< FIFORPTR (Bitfield-Mask: 0x0f)                        */
13047 #define IOM0_FIFOLOC_FIFOWPTR_Pos         (0UL)                     /*!< FIFOWPTR (Bit 0)                                      */
13048 #define IOM0_FIFOLOC_FIFOWPTR_Msk         (0xfUL)                   /*!< FIFOWPTR (Bitfield-Mask: 0x0f)                        */
13049 /* =========================================================  INTEN  ========================================================= */
13050 #define IOM0_INTEN_CQERR_Pos              (14UL)                    /*!< CQERR (Bit 14)                                        */
13051 #define IOM0_INTEN_CQERR_Msk              (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
13052 #define IOM0_INTEN_CQUPD_Pos              (13UL)                    /*!< CQUPD (Bit 13)                                        */
13053 #define IOM0_INTEN_CQUPD_Msk              (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
13054 #define IOM0_INTEN_CQPAUSED_Pos           (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
13055 #define IOM0_INTEN_CQPAUSED_Msk           (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13056 #define IOM0_INTEN_DERR_Pos               (11UL)                    /*!< DERR (Bit 11)                                         */
13057 #define IOM0_INTEN_DERR_Msk               (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
13058 #define IOM0_INTEN_DCMP_Pos               (10UL)                    /*!< DCMP (Bit 10)                                         */
13059 #define IOM0_INTEN_DCMP_Msk               (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
13060 #define IOM0_INTEN_ARB_Pos                (9UL)                     /*!< ARB (Bit 9)                                           */
13061 #define IOM0_INTEN_ARB_Msk                (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
13062 #define IOM0_INTEN_STOP_Pos               (8UL)                     /*!< STOP (Bit 8)                                          */
13063 #define IOM0_INTEN_STOP_Msk               (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
13064 #define IOM0_INTEN_START_Pos              (7UL)                     /*!< START (Bit 7)                                         */
13065 #define IOM0_INTEN_START_Msk              (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
13066 #define IOM0_INTEN_ICMD_Pos               (6UL)                     /*!< ICMD (Bit 6)                                          */
13067 #define IOM0_INTEN_ICMD_Msk               (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
13068 #define IOM0_INTEN_IACC_Pos               (5UL)                     /*!< IACC (Bit 5)                                          */
13069 #define IOM0_INTEN_IACC_Msk               (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
13070 #define IOM0_INTEN_NAK_Pos                (4UL)                     /*!< NAK (Bit 4)                                           */
13071 #define IOM0_INTEN_NAK_Msk                (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
13072 #define IOM0_INTEN_FOVFL_Pos              (3UL)                     /*!< FOVFL (Bit 3)                                         */
13073 #define IOM0_INTEN_FOVFL_Msk              (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13074 #define IOM0_INTEN_FUNDFL_Pos             (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13075 #define IOM0_INTEN_FUNDFL_Msk             (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13076 #define IOM0_INTEN_THR_Pos                (1UL)                     /*!< THR (Bit 1)                                           */
13077 #define IOM0_INTEN_THR_Msk                (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
13078 #define IOM0_INTEN_CMDCMP_Pos             (0UL)                     /*!< CMDCMP (Bit 0)                                        */
13079 #define IOM0_INTEN_CMDCMP_Msk             (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
13080 /* ========================================================  INTSTAT  ======================================================== */
13081 #define IOM0_INTSTAT_CQERR_Pos            (14UL)                    /*!< CQERR (Bit 14)                                        */
13082 #define IOM0_INTSTAT_CQERR_Msk            (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
13083 #define IOM0_INTSTAT_CQUPD_Pos            (13UL)                    /*!< CQUPD (Bit 13)                                        */
13084 #define IOM0_INTSTAT_CQUPD_Msk            (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
13085 #define IOM0_INTSTAT_CQPAUSED_Pos         (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
13086 #define IOM0_INTSTAT_CQPAUSED_Msk         (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13087 #define IOM0_INTSTAT_DERR_Pos             (11UL)                    /*!< DERR (Bit 11)                                         */
13088 #define IOM0_INTSTAT_DERR_Msk             (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
13089 #define IOM0_INTSTAT_DCMP_Pos             (10UL)                    /*!< DCMP (Bit 10)                                         */
13090 #define IOM0_INTSTAT_DCMP_Msk             (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
13091 #define IOM0_INTSTAT_ARB_Pos              (9UL)                     /*!< ARB (Bit 9)                                           */
13092 #define IOM0_INTSTAT_ARB_Msk              (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
13093 #define IOM0_INTSTAT_STOP_Pos             (8UL)                     /*!< STOP (Bit 8)                                          */
13094 #define IOM0_INTSTAT_STOP_Msk             (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
13095 #define IOM0_INTSTAT_START_Pos            (7UL)                     /*!< START (Bit 7)                                         */
13096 #define IOM0_INTSTAT_START_Msk            (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
13097 #define IOM0_INTSTAT_ICMD_Pos             (6UL)                     /*!< ICMD (Bit 6)                                          */
13098 #define IOM0_INTSTAT_ICMD_Msk             (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
13099 #define IOM0_INTSTAT_IACC_Pos             (5UL)                     /*!< IACC (Bit 5)                                          */
13100 #define IOM0_INTSTAT_IACC_Msk             (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
13101 #define IOM0_INTSTAT_NAK_Pos              (4UL)                     /*!< NAK (Bit 4)                                           */
13102 #define IOM0_INTSTAT_NAK_Msk              (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
13103 #define IOM0_INTSTAT_FOVFL_Pos            (3UL)                     /*!< FOVFL (Bit 3)                                         */
13104 #define IOM0_INTSTAT_FOVFL_Msk            (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13105 #define IOM0_INTSTAT_FUNDFL_Pos           (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13106 #define IOM0_INTSTAT_FUNDFL_Msk           (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13107 #define IOM0_INTSTAT_THR_Pos              (1UL)                     /*!< THR (Bit 1)                                           */
13108 #define IOM0_INTSTAT_THR_Msk              (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
13109 #define IOM0_INTSTAT_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
13110 #define IOM0_INTSTAT_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
13111 /* ========================================================  INTCLR  ========================================================= */
13112 #define IOM0_INTCLR_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
13113 #define IOM0_INTCLR_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
13114 #define IOM0_INTCLR_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
13115 #define IOM0_INTCLR_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
13116 #define IOM0_INTCLR_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
13117 #define IOM0_INTCLR_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13118 #define IOM0_INTCLR_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
13119 #define IOM0_INTCLR_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
13120 #define IOM0_INTCLR_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
13121 #define IOM0_INTCLR_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
13122 #define IOM0_INTCLR_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
13123 #define IOM0_INTCLR_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
13124 #define IOM0_INTCLR_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
13125 #define IOM0_INTCLR_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
13126 #define IOM0_INTCLR_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
13127 #define IOM0_INTCLR_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
13128 #define IOM0_INTCLR_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
13129 #define IOM0_INTCLR_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
13130 #define IOM0_INTCLR_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
13131 #define IOM0_INTCLR_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
13132 #define IOM0_INTCLR_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
13133 #define IOM0_INTCLR_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
13134 #define IOM0_INTCLR_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
13135 #define IOM0_INTCLR_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13136 #define IOM0_INTCLR_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13137 #define IOM0_INTCLR_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13138 #define IOM0_INTCLR_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
13139 #define IOM0_INTCLR_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
13140 #define IOM0_INTCLR_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
13141 #define IOM0_INTCLR_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
13142 /* ========================================================  INTSET  ========================================================= */
13143 #define IOM0_INTSET_CQERR_Pos             (14UL)                    /*!< CQERR (Bit 14)                                        */
13144 #define IOM0_INTSET_CQERR_Msk             (0x4000UL)                /*!< CQERR (Bitfield-Mask: 0x01)                           */
13145 #define IOM0_INTSET_CQUPD_Pos             (13UL)                    /*!< CQUPD (Bit 13)                                        */
13146 #define IOM0_INTSET_CQUPD_Msk             (0x2000UL)                /*!< CQUPD (Bitfield-Mask: 0x01)                           */
13147 #define IOM0_INTSET_CQPAUSED_Pos          (12UL)                    /*!< CQPAUSED (Bit 12)                                     */
13148 #define IOM0_INTSET_CQPAUSED_Msk          (0x1000UL)                /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13149 #define IOM0_INTSET_DERR_Pos              (11UL)                    /*!< DERR (Bit 11)                                         */
13150 #define IOM0_INTSET_DERR_Msk              (0x800UL)                 /*!< DERR (Bitfield-Mask: 0x01)                            */
13151 #define IOM0_INTSET_DCMP_Pos              (10UL)                    /*!< DCMP (Bit 10)                                         */
13152 #define IOM0_INTSET_DCMP_Msk              (0x400UL)                 /*!< DCMP (Bitfield-Mask: 0x01)                            */
13153 #define IOM0_INTSET_ARB_Pos               (9UL)                     /*!< ARB (Bit 9)                                           */
13154 #define IOM0_INTSET_ARB_Msk               (0x200UL)                 /*!< ARB (Bitfield-Mask: 0x01)                             */
13155 #define IOM0_INTSET_STOP_Pos              (8UL)                     /*!< STOP (Bit 8)                                          */
13156 #define IOM0_INTSET_STOP_Msk              (0x100UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
13157 #define IOM0_INTSET_START_Pos             (7UL)                     /*!< START (Bit 7)                                         */
13158 #define IOM0_INTSET_START_Msk             (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
13159 #define IOM0_INTSET_ICMD_Pos              (6UL)                     /*!< ICMD (Bit 6)                                          */
13160 #define IOM0_INTSET_ICMD_Msk              (0x40UL)                  /*!< ICMD (Bitfield-Mask: 0x01)                            */
13161 #define IOM0_INTSET_IACC_Pos              (5UL)                     /*!< IACC (Bit 5)                                          */
13162 #define IOM0_INTSET_IACC_Msk              (0x20UL)                  /*!< IACC (Bitfield-Mask: 0x01)                            */
13163 #define IOM0_INTSET_NAK_Pos               (4UL)                     /*!< NAK (Bit 4)                                           */
13164 #define IOM0_INTSET_NAK_Msk               (0x10UL)                  /*!< NAK (Bitfield-Mask: 0x01)                             */
13165 #define IOM0_INTSET_FOVFL_Pos             (3UL)                     /*!< FOVFL (Bit 3)                                         */
13166 #define IOM0_INTSET_FOVFL_Msk             (0x8UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13167 #define IOM0_INTSET_FUNDFL_Pos            (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13168 #define IOM0_INTSET_FUNDFL_Msk            (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13169 #define IOM0_INTSET_THR_Pos               (1UL)                     /*!< THR (Bit 1)                                           */
13170 #define IOM0_INTSET_THR_Msk               (0x2UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
13171 #define IOM0_INTSET_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
13172 #define IOM0_INTSET_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
13173 /* ========================================================  CLKCFG  ========================================================= */
13174 #define IOM0_CLKCFG_TOTPER_Pos            (24UL)                    /*!< TOTPER (Bit 24)                                       */
13175 #define IOM0_CLKCFG_TOTPER_Msk            (0xff000000UL)            /*!< TOTPER (Bitfield-Mask: 0xff)                          */
13176 #define IOM0_CLKCFG_LOWPER_Pos            (16UL)                    /*!< LOWPER (Bit 16)                                       */
13177 #define IOM0_CLKCFG_LOWPER_Msk            (0xff0000UL)              /*!< LOWPER (Bitfield-Mask: 0xff)                          */
13178 #define IOM0_CLKCFG_DIVEN_Pos             (12UL)                    /*!< DIVEN (Bit 12)                                        */
13179 #define IOM0_CLKCFG_DIVEN_Msk             (0x1000UL)                /*!< DIVEN (Bitfield-Mask: 0x01)                           */
13180 #define IOM0_CLKCFG_DIV3_Pos              (11UL)                    /*!< DIV3 (Bit 11)                                         */
13181 #define IOM0_CLKCFG_DIV3_Msk              (0x800UL)                 /*!< DIV3 (Bitfield-Mask: 0x01)                            */
13182 #define IOM0_CLKCFG_FSEL_Pos              (8UL)                     /*!< FSEL (Bit 8)                                          */
13183 #define IOM0_CLKCFG_FSEL_Msk              (0x700UL)                 /*!< FSEL (Bitfield-Mask: 0x07)                            */
13184 #define IOM0_CLKCFG_IOCLKEN_Pos           (0UL)                     /*!< IOCLKEN (Bit 0)                                       */
13185 #define IOM0_CLKCFG_IOCLKEN_Msk           (0x1UL)                   /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
13186 /* ======================================================  SUBMODCTRL  ======================================================= */
13187 #define IOM0_SUBMODCTRL_SMOD1TYPE_Pos     (5UL)                     /*!< SMOD1TYPE (Bit 5)                                     */
13188 #define IOM0_SUBMODCTRL_SMOD1TYPE_Msk     (0xe0UL)                  /*!< SMOD1TYPE (Bitfield-Mask: 0x07)                       */
13189 #define IOM0_SUBMODCTRL_SMOD1EN_Pos       (4UL)                     /*!< SMOD1EN (Bit 4)                                       */
13190 #define IOM0_SUBMODCTRL_SMOD1EN_Msk       (0x10UL)                  /*!< SMOD1EN (Bitfield-Mask: 0x01)                         */
13191 #define IOM0_SUBMODCTRL_SMOD0TYPE_Pos     (1UL)                     /*!< SMOD0TYPE (Bit 1)                                     */
13192 #define IOM0_SUBMODCTRL_SMOD0TYPE_Msk     (0xeUL)                   /*!< SMOD0TYPE (Bitfield-Mask: 0x07)                       */
13193 #define IOM0_SUBMODCTRL_SMOD0EN_Pos       (0UL)                     /*!< SMOD0EN (Bit 0)                                       */
13194 #define IOM0_SUBMODCTRL_SMOD0EN_Msk       (0x1UL)                   /*!< SMOD0EN (Bitfield-Mask: 0x01)                         */
13195 /* ==========================================================  CMD  ========================================================== */
13196 #define IOM0_CMD_OFFSETLO_Pos             (24UL)                    /*!< OFFSETLO (Bit 24)                                     */
13197 #define IOM0_CMD_OFFSETLO_Msk             (0xff000000UL)            /*!< OFFSETLO (Bitfield-Mask: 0xff)                        */
13198 #define IOM0_CMD_CMDSEL_Pos               (20UL)                    /*!< CMDSEL (Bit 20)                                       */
13199 #define IOM0_CMD_CMDSEL_Msk               (0x300000UL)              /*!< CMDSEL (Bitfield-Mask: 0x03)                          */
13200 #define IOM0_CMD_TSIZE_Pos                (8UL)                     /*!< TSIZE (Bit 8)                                         */
13201 #define IOM0_CMD_TSIZE_Msk                (0xfff00UL)               /*!< TSIZE (Bitfield-Mask: 0xfff)                          */
13202 #define IOM0_CMD_CONT_Pos                 (7UL)                     /*!< CONT (Bit 7)                                          */
13203 #define IOM0_CMD_CONT_Msk                 (0x80UL)                  /*!< CONT (Bitfield-Mask: 0x01)                            */
13204 #define IOM0_CMD_OFFSETCNT_Pos            (5UL)                     /*!< OFFSETCNT (Bit 5)                                     */
13205 #define IOM0_CMD_OFFSETCNT_Msk            (0x60UL)                  /*!< OFFSETCNT (Bitfield-Mask: 0x03)                       */
13206 #define IOM0_CMD_CMD_Pos                  (0UL)                     /*!< CMD (Bit 0)                                           */
13207 #define IOM0_CMD_CMD_Msk                  (0x1fUL)                  /*!< CMD (Bitfield-Mask: 0x1f)                             */
13208 /* ==========================================================  DCX  ========================================================== */
13209 #define IOM0_DCX_DCXEN_Pos                (4UL)                     /*!< DCXEN (Bit 4)                                         */
13210 #define IOM0_DCX_DCXEN_Msk                (0x10UL)                  /*!< DCXEN (Bitfield-Mask: 0x01)                           */
13211 #define IOM0_DCX_CE3OUT_Pos               (3UL)                     /*!< CE3OUT (Bit 3)                                        */
13212 #define IOM0_DCX_CE3OUT_Msk               (0x8UL)                   /*!< CE3OUT (Bitfield-Mask: 0x01)                          */
13213 #define IOM0_DCX_CE2OUT_Pos               (2UL)                     /*!< CE2OUT (Bit 2)                                        */
13214 #define IOM0_DCX_CE2OUT_Msk               (0x4UL)                   /*!< CE2OUT (Bitfield-Mask: 0x01)                          */
13215 #define IOM0_DCX_CE1OUT_Pos               (1UL)                     /*!< CE1OUT (Bit 1)                                        */
13216 #define IOM0_DCX_CE1OUT_Msk               (0x2UL)                   /*!< CE1OUT (Bitfield-Mask: 0x01)                          */
13217 #define IOM0_DCX_CE0OUT_Pos               (0UL)                     /*!< CE0OUT (Bit 0)                                        */
13218 #define IOM0_DCX_CE0OUT_Msk               (0x1UL)                   /*!< CE0OUT (Bitfield-Mask: 0x01)                          */
13219 /* =======================================================  OFFSETHI  ======================================================== */
13220 #define IOM0_OFFSETHI_OFFSETHI_Pos        (0UL)                     /*!< OFFSETHI (Bit 0)                                      */
13221 #define IOM0_OFFSETHI_OFFSETHI_Msk        (0xffffUL)                /*!< OFFSETHI (Bitfield-Mask: 0xffff)                      */
13222 /* ========================================================  CMDSTAT  ======================================================== */
13223 #define IOM0_CMDSTAT_CTSIZE_Pos           (8UL)                     /*!< CTSIZE (Bit 8)                                        */
13224 #define IOM0_CMDSTAT_CTSIZE_Msk           (0xfff00UL)               /*!< CTSIZE (Bitfield-Mask: 0xfff)                         */
13225 #define IOM0_CMDSTAT_CMDSTAT_Pos          (5UL)                     /*!< CMDSTAT (Bit 5)                                       */
13226 #define IOM0_CMDSTAT_CMDSTAT_Msk          (0xe0UL)                  /*!< CMDSTAT (Bitfield-Mask: 0x07)                         */
13227 #define IOM0_CMDSTAT_CCMD_Pos             (0UL)                     /*!< CCMD (Bit 0)                                          */
13228 #define IOM0_CMDSTAT_CCMD_Msk             (0x1fUL)                  /*!< CCMD (Bitfield-Mask: 0x1f)                            */
13229 /* =======================================================  DMATRIGEN  ======================================================= */
13230 #define IOM0_DMATRIGEN_DTHREN_Pos         (1UL)                     /*!< DTHREN (Bit 1)                                        */
13231 #define IOM0_DMATRIGEN_DTHREN_Msk         (0x2UL)                   /*!< DTHREN (Bitfield-Mask: 0x01)                          */
13232 #define IOM0_DMATRIGEN_DCMDCMPEN_Pos      (0UL)                     /*!< DCMDCMPEN (Bit 0)                                     */
13233 #define IOM0_DMATRIGEN_DCMDCMPEN_Msk      (0x1UL)                   /*!< DCMDCMPEN (Bitfield-Mask: 0x01)                       */
13234 /* ======================================================  DMATRIGSTAT  ====================================================== */
13235 #define IOM0_DMATRIGSTAT_DTOTCMP_Pos      (2UL)                     /*!< DTOTCMP (Bit 2)                                       */
13236 #define IOM0_DMATRIGSTAT_DTOTCMP_Msk      (0x4UL)                   /*!< DTOTCMP (Bitfield-Mask: 0x01)                         */
13237 #define IOM0_DMATRIGSTAT_DTHR_Pos         (1UL)                     /*!< DTHR (Bit 1)                                          */
13238 #define IOM0_DMATRIGSTAT_DTHR_Msk         (0x2UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
13239 #define IOM0_DMATRIGSTAT_DCMDCMP_Pos      (0UL)                     /*!< DCMDCMP (Bit 0)                                       */
13240 #define IOM0_DMATRIGSTAT_DCMDCMP_Msk      (0x1UL)                   /*!< DCMDCMP (Bitfield-Mask: 0x01)                         */
13241 /* ========================================================  DMACFG  ========================================================= */
13242 #define IOM0_DMACFG_DPWROFF_Pos           (9UL)                     /*!< DPWROFF (Bit 9)                                       */
13243 #define IOM0_DMACFG_DPWROFF_Msk           (0x200UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
13244 #define IOM0_DMACFG_DMAPRI_Pos            (8UL)                     /*!< DMAPRI (Bit 8)                                        */
13245 #define IOM0_DMACFG_DMAPRI_Msk            (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
13246 #define IOM0_DMACFG_DMADIR_Pos            (1UL)                     /*!< DMADIR (Bit 1)                                        */
13247 #define IOM0_DMACFG_DMADIR_Msk            (0x2UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
13248 #define IOM0_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
13249 #define IOM0_DMACFG_DMAEN_Msk             (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
13250 /* ======================================================  DMATOTCOUNT  ====================================================== */
13251 #define IOM0_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
13252 #define IOM0_DMATOTCOUNT_TOTCOUNT_Msk     (0xfffUL)                 /*!< TOTCOUNT (Bitfield-Mask: 0xfff)                       */
13253 /* ======================================================  DMATARGADDR  ====================================================== */
13254 #define IOM0_DMATARGADDR_TARGADDR28_Pos   (28UL)                    /*!< TARGADDR28 (Bit 28)                                   */
13255 #define IOM0_DMATARGADDR_TARGADDR28_Msk   (0x10000000UL)            /*!< TARGADDR28 (Bitfield-Mask: 0x01)                      */
13256 #define IOM0_DMATARGADDR_TARGADDR_Pos     (0UL)                     /*!< TARGADDR (Bit 0)                                      */
13257 #define IOM0_DMATARGADDR_TARGADDR_Msk     (0xfffffUL)               /*!< TARGADDR (Bitfield-Mask: 0xfffff)                     */
13258 /* ========================================================  DMASTAT  ======================================================== */
13259 #define IOM0_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
13260 #define IOM0_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
13261 #define IOM0_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
13262 #define IOM0_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
13263 #define IOM0_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
13264 #define IOM0_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
13265 /* =========================================================  CQCFG  ========================================================= */
13266 #define IOM0_CQCFG_CQPRI_Pos              (1UL)                     /*!< CQPRI (Bit 1)                                         */
13267 #define IOM0_CQCFG_CQPRI_Msk              (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
13268 #define IOM0_CQCFG_CQEN_Pos               (0UL)                     /*!< CQEN (Bit 0)                                          */
13269 #define IOM0_CQCFG_CQEN_Msk               (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
13270 /* ========================================================  CQADDR  ========================================================= */
13271 #define IOM0_CQADDR_CQADDR28_Pos          (28UL)                    /*!< CQADDR28 (Bit 28)                                     */
13272 #define IOM0_CQADDR_CQADDR28_Msk          (0x10000000UL)            /*!< CQADDR28 (Bitfield-Mask: 0x01)                        */
13273 #define IOM0_CQADDR_CQADDR_Pos            (2UL)                     /*!< CQADDR (Bit 2)                                        */
13274 #define IOM0_CQADDR_CQADDR_Msk            (0xffffcUL)               /*!< CQADDR (Bitfield-Mask: 0x3ffff)                       */
13275 /* ========================================================  CQSTAT  ========================================================= */
13276 #define IOM0_CQSTAT_CQERR_Pos             (2UL)                     /*!< CQERR (Bit 2)                                         */
13277 #define IOM0_CQSTAT_CQERR_Msk             (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
13278 #define IOM0_CQSTAT_CQPAUSED_Pos          (1UL)                     /*!< CQPAUSED (Bit 1)                                      */
13279 #define IOM0_CQSTAT_CQPAUSED_Msk          (0x2UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13280 #define IOM0_CQSTAT_CQTIP_Pos             (0UL)                     /*!< CQTIP (Bit 0)                                         */
13281 #define IOM0_CQSTAT_CQTIP_Msk             (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
13282 /* ========================================================  CQFLAGS  ======================================================== */
13283 #define IOM0_CQFLAGS_CQIRQMASK_Pos        (16UL)                    /*!< CQIRQMASK (Bit 16)                                    */
13284 #define IOM0_CQFLAGS_CQIRQMASK_Msk        (0xffff0000UL)            /*!< CQIRQMASK (Bitfield-Mask: 0xffff)                     */
13285 #define IOM0_CQFLAGS_CQFLAGS_Pos          (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
13286 #define IOM0_CQFLAGS_CQFLAGS_Msk          (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
13287 /* ======================================================  CQSETCLEAR  ======================================================= */
13288 #define IOM0_CQSETCLEAR_CQFCLR_Pos        (16UL)                    /*!< CQFCLR (Bit 16)                                       */
13289 #define IOM0_CQSETCLEAR_CQFCLR_Msk        (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
13290 #define IOM0_CQSETCLEAR_CQFTGL_Pos        (8UL)                     /*!< CQFTGL (Bit 8)                                        */
13291 #define IOM0_CQSETCLEAR_CQFTGL_Msk        (0xff00UL)                /*!< CQFTGL (Bitfield-Mask: 0xff)                          */
13292 #define IOM0_CQSETCLEAR_CQFSET_Pos        (0UL)                     /*!< CQFSET (Bit 0)                                        */
13293 #define IOM0_CQSETCLEAR_CQFSET_Msk        (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
13294 /* =======================================================  CQPAUSEEN  ======================================================= */
13295 #define IOM0_CQPAUSEEN_CQPEN_Pos          (0UL)                     /*!< CQPEN (Bit 0)                                         */
13296 #define IOM0_CQPAUSEEN_CQPEN_Msk          (0xffffUL)                /*!< CQPEN (Bitfield-Mask: 0xffff)                         */
13297 /* =======================================================  CQCURIDX  ======================================================== */
13298 #define IOM0_CQCURIDX_CQCURIDX_Pos        (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
13299 #define IOM0_CQCURIDX_CQCURIDX_Msk        (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
13300 /* =======================================================  CQENDIDX  ======================================================== */
13301 #define IOM0_CQENDIDX_CQENDIDX_Pos        (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
13302 #define IOM0_CQENDIDX_CQENDIDX_Msk        (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
13303 /* ========================================================  STATUS  ========================================================= */
13304 #define IOM0_STATUS_IDLEST_Pos            (2UL)                     /*!< IDLEST (Bit 2)                                        */
13305 #define IOM0_STATUS_IDLEST_Msk            (0x4UL)                   /*!< IDLEST (Bitfield-Mask: 0x01)                          */
13306 #define IOM0_STATUS_CMDACT_Pos            (1UL)                     /*!< CMDACT (Bit 1)                                        */
13307 #define IOM0_STATUS_CMDACT_Msk            (0x2UL)                   /*!< CMDACT (Bitfield-Mask: 0x01)                          */
13308 #define IOM0_STATUS_ERR_Pos               (0UL)                     /*!< ERR (Bit 0)                                           */
13309 #define IOM0_STATUS_ERR_Msk               (0x1UL)                   /*!< ERR (Bitfield-Mask: 0x01)                             */
13310 /* ========================================================  MSPICFG  ======================================================== */
13311 #define IOM0_MSPICFG_MSPIRST_Pos          (30UL)                    /*!< MSPIRST (Bit 30)                                      */
13312 #define IOM0_MSPICFG_MSPIRST_Msk          (0x40000000UL)            /*!< MSPIRST (Bitfield-Mask: 0x01)                         */
13313 #define IOM0_MSPICFG_DOUTDLY_Pos          (27UL)                    /*!< DOUTDLY (Bit 27)                                      */
13314 #define IOM0_MSPICFG_DOUTDLY_Msk          (0x38000000UL)            /*!< DOUTDLY (Bitfield-Mask: 0x07)                         */
13315 #define IOM0_MSPICFG_DINDLY_Pos           (24UL)                    /*!< DINDLY (Bit 24)                                       */
13316 #define IOM0_MSPICFG_DINDLY_Msk           (0x7000000UL)             /*!< DINDLY (Bitfield-Mask: 0x07)                          */
13317 #define IOM0_MSPICFG_SPILSB_Pos           (23UL)                    /*!< SPILSB (Bit 23)                                       */
13318 #define IOM0_MSPICFG_SPILSB_Msk           (0x800000UL)              /*!< SPILSB (Bitfield-Mask: 0x01)                          */
13319 #define IOM0_MSPICFG_RDFCPOL_Pos          (22UL)                    /*!< RDFCPOL (Bit 22)                                      */
13320 #define IOM0_MSPICFG_RDFCPOL_Msk          (0x400000UL)              /*!< RDFCPOL (Bitfield-Mask: 0x01)                         */
13321 #define IOM0_MSPICFG_WTFCPOL_Pos          (21UL)                    /*!< WTFCPOL (Bit 21)                                      */
13322 #define IOM0_MSPICFG_WTFCPOL_Msk          (0x200000UL)              /*!< WTFCPOL (Bitfield-Mask: 0x01)                         */
13323 #define IOM0_MSPICFG_WTFCIRQ_Pos          (20UL)                    /*!< WTFCIRQ (Bit 20)                                      */
13324 #define IOM0_MSPICFG_WTFCIRQ_Msk          (0x100000UL)              /*!< WTFCIRQ (Bitfield-Mask: 0x01)                         */
13325 #define IOM0_MSPICFG_MOSIINV_Pos          (18UL)                    /*!< MOSIINV (Bit 18)                                      */
13326 #define IOM0_MSPICFG_MOSIINV_Msk          (0x40000UL)               /*!< MOSIINV (Bitfield-Mask: 0x01)                         */
13327 #define IOM0_MSPICFG_RDFC_Pos             (17UL)                    /*!< RDFC (Bit 17)                                         */
13328 #define IOM0_MSPICFG_RDFC_Msk             (0x20000UL)               /*!< RDFC (Bitfield-Mask: 0x01)                            */
13329 #define IOM0_MSPICFG_WTFC_Pos             (16UL)                    /*!< WTFC (Bit 16)                                         */
13330 #define IOM0_MSPICFG_WTFC_Msk             (0x10000UL)               /*!< WTFC (Bitfield-Mask: 0x01)                            */
13331 #define IOM0_MSPICFG_FULLDUP_Pos          (2UL)                     /*!< FULLDUP (Bit 2)                                       */
13332 #define IOM0_MSPICFG_FULLDUP_Msk          (0x4UL)                   /*!< FULLDUP (Bitfield-Mask: 0x01)                         */
13333 #define IOM0_MSPICFG_SPHA_Pos             (1UL)                     /*!< SPHA (Bit 1)                                          */
13334 #define IOM0_MSPICFG_SPHA_Msk             (0x2UL)                   /*!< SPHA (Bitfield-Mask: 0x01)                            */
13335 #define IOM0_MSPICFG_SPOL_Pos             (0UL)                     /*!< SPOL (Bit 0)                                          */
13336 #define IOM0_MSPICFG_SPOL_Msk             (0x1UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
13337 /* ========================================================  MI2CCFG  ======================================================== */
13338 #define IOM0_MI2CCFG_STRDIS_Pos           (24UL)                    /*!< STRDIS (Bit 24)                                       */
13339 #define IOM0_MI2CCFG_STRDIS_Msk           (0x1000000UL)             /*!< STRDIS (Bitfield-Mask: 0x01)                          */
13340 #define IOM0_MI2CCFG_SMPCNT_Pos           (16UL)                    /*!< SMPCNT (Bit 16)                                       */
13341 #define IOM0_MI2CCFG_SMPCNT_Msk           (0xff0000UL)              /*!< SMPCNT (Bitfield-Mask: 0xff)                          */
13342 #define IOM0_MI2CCFG_SDAENDLY_Pos         (12UL)                    /*!< SDAENDLY (Bit 12)                                     */
13343 #define IOM0_MI2CCFG_SDAENDLY_Msk         (0xf000UL)                /*!< SDAENDLY (Bitfield-Mask: 0x0f)                        */
13344 #define IOM0_MI2CCFG_SCLENDLY_Pos         (8UL)                     /*!< SCLENDLY (Bit 8)                                      */
13345 #define IOM0_MI2CCFG_SCLENDLY_Msk         (0xf00UL)                 /*!< SCLENDLY (Bitfield-Mask: 0x0f)                        */
13346 #define IOM0_MI2CCFG_MI2CRST_Pos          (6UL)                     /*!< MI2CRST (Bit 6)                                       */
13347 #define IOM0_MI2CCFG_MI2CRST_Msk          (0x40UL)                  /*!< MI2CRST (Bitfield-Mask: 0x01)                         */
13348 #define IOM0_MI2CCFG_SDADLY_Pos           (4UL)                     /*!< SDADLY (Bit 4)                                        */
13349 #define IOM0_MI2CCFG_SDADLY_Msk           (0x30UL)                  /*!< SDADLY (Bitfield-Mask: 0x03)                          */
13350 #define IOM0_MI2CCFG_ARBEN_Pos            (2UL)                     /*!< ARBEN (Bit 2)                                         */
13351 #define IOM0_MI2CCFG_ARBEN_Msk            (0x4UL)                   /*!< ARBEN (Bitfield-Mask: 0x01)                           */
13352 #define IOM0_MI2CCFG_I2CLSB_Pos           (1UL)                     /*!< I2CLSB (Bit 1)                                        */
13353 #define IOM0_MI2CCFG_I2CLSB_Msk           (0x2UL)                   /*!< I2CLSB (Bitfield-Mask: 0x01)                          */
13354 #define IOM0_MI2CCFG_ADDRSZ_Pos           (0UL)                     /*!< ADDRSZ (Bit 0)                                        */
13355 #define IOM0_MI2CCFG_ADDRSZ_Msk           (0x1UL)                   /*!< ADDRSZ (Bitfield-Mask: 0x01)                          */
13356 /* ========================================================  DEVCFG  ========================================================= */
13357 #define IOM0_DEVCFG_DEVADDR_Pos           (0UL)                     /*!< DEVADDR (Bit 0)                                       */
13358 #define IOM0_DEVCFG_DEVADDR_Msk           (0x3ffUL)                 /*!< DEVADDR (Bitfield-Mask: 0x3ff)                        */
13359 /* ========================================================  IOMDBG  ========================================================= */
13360 #define IOM0_IOMDBG_DBGDATA_Pos           (3UL)                     /*!< DBGDATA (Bit 3)                                       */
13361 #define IOM0_IOMDBG_DBGDATA_Msk           (0xfffffff8UL)            /*!< DBGDATA (Bitfield-Mask: 0x1fffffff)                   */
13362 #define IOM0_IOMDBG_APBCLKON_Pos          (2UL)                     /*!< APBCLKON (Bit 2)                                      */
13363 #define IOM0_IOMDBG_APBCLKON_Msk          (0x4UL)                   /*!< APBCLKON (Bitfield-Mask: 0x01)                        */
13364 #define IOM0_IOMDBG_IOCLKON_Pos           (1UL)                     /*!< IOCLKON (Bit 1)                                       */
13365 #define IOM0_IOMDBG_IOCLKON_Msk           (0x2UL)                   /*!< IOCLKON (Bitfield-Mask: 0x01)                         */
13366 #define IOM0_IOMDBG_DBGEN_Pos             (0UL)                     /*!< DBGEN (Bit 0)                                         */
13367 #define IOM0_IOMDBG_DBGEN_Msk             (0x1UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
13368 
13369 
13370 /* =========================================================================================================================== */
13371 /* ================                                          IOSLAVE                                          ================ */
13372 /* =========================================================================================================================== */
13373 
13374 /* ========================================================  FIFOPTR  ======================================================== */
13375 #define IOSLAVE_FIFOPTR_FIFOSIZ_Pos       (8UL)                     /*!< FIFOSIZ (Bit 8)                                       */
13376 #define IOSLAVE_FIFOPTR_FIFOSIZ_Msk       (0xff00UL)                /*!< FIFOSIZ (Bitfield-Mask: 0xff)                         */
13377 #define IOSLAVE_FIFOPTR_FIFOPTR_Pos       (0UL)                     /*!< FIFOPTR (Bit 0)                                       */
13378 #define IOSLAVE_FIFOPTR_FIFOPTR_Msk       (0xffUL)                  /*!< FIFOPTR (Bitfield-Mask: 0xff)                         */
13379 /* ========================================================  FIFOCFG  ======================================================== */
13380 #define IOSLAVE_FIFOCFG_ROBASE_Pos        (24UL)                    /*!< ROBASE (Bit 24)                                       */
13381 #define IOSLAVE_FIFOCFG_ROBASE_Msk        (0x3f000000UL)            /*!< ROBASE (Bitfield-Mask: 0x3f)                          */
13382 #define IOSLAVE_FIFOCFG_FIFOMAX_Pos       (8UL)                     /*!< FIFOMAX (Bit 8)                                       */
13383 #define IOSLAVE_FIFOCFG_FIFOMAX_Msk       (0x3f00UL)                /*!< FIFOMAX (Bitfield-Mask: 0x3f)                         */
13384 #define IOSLAVE_FIFOCFG_FIFOBASE_Pos      (0UL)                     /*!< FIFOBASE (Bit 0)                                      */
13385 #define IOSLAVE_FIFOCFG_FIFOBASE_Msk      (0x1fUL)                  /*!< FIFOBASE (Bitfield-Mask: 0x1f)                        */
13386 /* ========================================================  FIFOTHR  ======================================================== */
13387 #define IOSLAVE_FIFOTHR_FIFOTHR_Pos       (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
13388 #define IOSLAVE_FIFOTHR_FIFOTHR_Msk       (0xffUL)                  /*!< FIFOTHR (Bitfield-Mask: 0xff)                         */
13389 /* =========================================================  FUPD  ========================================================== */
13390 #define IOSLAVE_FUPD_IOREAD_Pos           (1UL)                     /*!< IOREAD (Bit 1)                                        */
13391 #define IOSLAVE_FUPD_IOREAD_Msk           (0x2UL)                   /*!< IOREAD (Bitfield-Mask: 0x01)                          */
13392 #define IOSLAVE_FUPD_FIFOUPD_Pos          (0UL)                     /*!< FIFOUPD (Bit 0)                                       */
13393 #define IOSLAVE_FUPD_FIFOUPD_Msk          (0x1UL)                   /*!< FIFOUPD (Bitfield-Mask: 0x01)                         */
13394 /* ========================================================  FIFOCTR  ======================================================== */
13395 #define IOSLAVE_FIFOCTR_FIFOCTR_Pos       (0UL)                     /*!< FIFOCTR (Bit 0)                                       */
13396 #define IOSLAVE_FIFOCTR_FIFOCTR_Msk       (0x3ffUL)                 /*!< FIFOCTR (Bitfield-Mask: 0x3ff)                        */
13397 /* ========================================================  FIFOINC  ======================================================== */
13398 #define IOSLAVE_FIFOINC_FIFOINC_Pos       (0UL)                     /*!< FIFOINC (Bit 0)                                       */
13399 #define IOSLAVE_FIFOINC_FIFOINC_Msk       (0x3ffUL)                 /*!< FIFOINC (Bitfield-Mask: 0x3ff)                        */
13400 /* ==========================================================  CFG  ========================================================== */
13401 #define IOSLAVE_CFG_IFCEN_Pos             (31UL)                    /*!< IFCEN (Bit 31)                                        */
13402 #define IOSLAVE_CFG_IFCEN_Msk             (0x80000000UL)            /*!< IFCEN (Bitfield-Mask: 0x01)                           */
13403 #define IOSLAVE_CFG_I2CADDR_Pos           (8UL)                     /*!< I2CADDR (Bit 8)                                       */
13404 #define IOSLAVE_CFG_I2CADDR_Msk           (0xfff00UL)               /*!< I2CADDR (Bitfield-Mask: 0xfff)                        */
13405 #define IOSLAVE_CFG_STARTRD_Pos           (4UL)                     /*!< STARTRD (Bit 4)                                       */
13406 #define IOSLAVE_CFG_STARTRD_Msk           (0x10UL)                  /*!< STARTRD (Bitfield-Mask: 0x01)                         */
13407 #define IOSLAVE_CFG_LSB_Pos               (2UL)                     /*!< LSB (Bit 2)                                           */
13408 #define IOSLAVE_CFG_LSB_Msk               (0x4UL)                   /*!< LSB (Bitfield-Mask: 0x01)                             */
13409 #define IOSLAVE_CFG_SPOL_Pos              (1UL)                     /*!< SPOL (Bit 1)                                          */
13410 #define IOSLAVE_CFG_SPOL_Msk              (0x2UL)                   /*!< SPOL (Bitfield-Mask: 0x01)                            */
13411 #define IOSLAVE_CFG_IFCSEL_Pos            (0UL)                     /*!< IFCSEL (Bit 0)                                        */
13412 #define IOSLAVE_CFG_IFCSEL_Msk            (0x1UL)                   /*!< IFCSEL (Bitfield-Mask: 0x01)                          */
13413 /* =========================================================  PRENC  ========================================================= */
13414 #define IOSLAVE_PRENC_PRENC_Pos           (0UL)                     /*!< PRENC (Bit 0)                                         */
13415 #define IOSLAVE_PRENC_PRENC_Msk           (0x1fUL)                  /*!< PRENC (Bitfield-Mask: 0x1f)                           */
13416 /* =======================================================  IOINTCTL  ======================================================== */
13417 #define IOSLAVE_IOINTCTL_IOINTSET_Pos     (24UL)                    /*!< IOINTSET (Bit 24)                                     */
13418 #define IOSLAVE_IOINTCTL_IOINTSET_Msk     (0xff000000UL)            /*!< IOINTSET (Bitfield-Mask: 0xff)                        */
13419 #define IOSLAVE_IOINTCTL_IOINTCLR_Pos     (16UL)                    /*!< IOINTCLR (Bit 16)                                     */
13420 #define IOSLAVE_IOINTCTL_IOINTCLR_Msk     (0x10000UL)               /*!< IOINTCLR (Bitfield-Mask: 0x01)                        */
13421 #define IOSLAVE_IOINTCTL_IOINT_Pos        (8UL)                     /*!< IOINT (Bit 8)                                         */
13422 #define IOSLAVE_IOINTCTL_IOINT_Msk        (0xff00UL)                /*!< IOINT (Bitfield-Mask: 0xff)                           */
13423 #define IOSLAVE_IOINTCTL_IOINTEN_Pos      (0UL)                     /*!< IOINTEN (Bit 0)                                       */
13424 #define IOSLAVE_IOINTCTL_IOINTEN_Msk      (0xffUL)                  /*!< IOINTEN (Bitfield-Mask: 0xff)                         */
13425 /* ========================================================  GENADD  ========================================================= */
13426 #define IOSLAVE_GENADD_GADATA_Pos         (0UL)                     /*!< GADATA (Bit 0)                                        */
13427 #define IOSLAVE_GENADD_GADATA_Msk         (0xffUL)                  /*!< GADATA (Bitfield-Mask: 0xff)                          */
13428 /* =========================================================  INTEN  ========================================================= */
13429 #define IOSLAVE_INTEN_XCMPWR_Pos          (9UL)                     /*!< XCMPWR (Bit 9)                                        */
13430 #define IOSLAVE_INTEN_XCMPWR_Msk          (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
13431 #define IOSLAVE_INTEN_XCMPWF_Pos          (8UL)                     /*!< XCMPWF (Bit 8)                                        */
13432 #define IOSLAVE_INTEN_XCMPWF_Msk          (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
13433 #define IOSLAVE_INTEN_XCMPRR_Pos          (7UL)                     /*!< XCMPRR (Bit 7)                                        */
13434 #define IOSLAVE_INTEN_XCMPRR_Msk          (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
13435 #define IOSLAVE_INTEN_XCMPRF_Pos          (6UL)                     /*!< XCMPRF (Bit 6)                                        */
13436 #define IOSLAVE_INTEN_XCMPRF_Msk          (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
13437 #define IOSLAVE_INTEN_IOINTW_Pos          (5UL)                     /*!< IOINTW (Bit 5)                                        */
13438 #define IOSLAVE_INTEN_IOINTW_Msk          (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
13439 #define IOSLAVE_INTEN_GENAD_Pos           (4UL)                     /*!< GENAD (Bit 4)                                         */
13440 #define IOSLAVE_INTEN_GENAD_Msk           (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
13441 #define IOSLAVE_INTEN_FRDERR_Pos          (3UL)                     /*!< FRDERR (Bit 3)                                        */
13442 #define IOSLAVE_INTEN_FRDERR_Msk          (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
13443 #define IOSLAVE_INTEN_FUNDFL_Pos          (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13444 #define IOSLAVE_INTEN_FUNDFL_Msk          (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13445 #define IOSLAVE_INTEN_FOVFL_Pos           (1UL)                     /*!< FOVFL (Bit 1)                                         */
13446 #define IOSLAVE_INTEN_FOVFL_Msk           (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13447 #define IOSLAVE_INTEN_FSIZE_Pos           (0UL)                     /*!< FSIZE (Bit 0)                                         */
13448 #define IOSLAVE_INTEN_FSIZE_Msk           (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
13449 /* ========================================================  INTSTAT  ======================================================== */
13450 #define IOSLAVE_INTSTAT_XCMPWR_Pos        (9UL)                     /*!< XCMPWR (Bit 9)                                        */
13451 #define IOSLAVE_INTSTAT_XCMPWR_Msk        (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
13452 #define IOSLAVE_INTSTAT_XCMPWF_Pos        (8UL)                     /*!< XCMPWF (Bit 8)                                        */
13453 #define IOSLAVE_INTSTAT_XCMPWF_Msk        (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
13454 #define IOSLAVE_INTSTAT_XCMPRR_Pos        (7UL)                     /*!< XCMPRR (Bit 7)                                        */
13455 #define IOSLAVE_INTSTAT_XCMPRR_Msk        (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
13456 #define IOSLAVE_INTSTAT_XCMPRF_Pos        (6UL)                     /*!< XCMPRF (Bit 6)                                        */
13457 #define IOSLAVE_INTSTAT_XCMPRF_Msk        (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
13458 #define IOSLAVE_INTSTAT_IOINTW_Pos        (5UL)                     /*!< IOINTW (Bit 5)                                        */
13459 #define IOSLAVE_INTSTAT_IOINTW_Msk        (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
13460 #define IOSLAVE_INTSTAT_GENAD_Pos         (4UL)                     /*!< GENAD (Bit 4)                                         */
13461 #define IOSLAVE_INTSTAT_GENAD_Msk         (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
13462 #define IOSLAVE_INTSTAT_FRDERR_Pos        (3UL)                     /*!< FRDERR (Bit 3)                                        */
13463 #define IOSLAVE_INTSTAT_FRDERR_Msk        (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
13464 #define IOSLAVE_INTSTAT_FUNDFL_Pos        (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13465 #define IOSLAVE_INTSTAT_FUNDFL_Msk        (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13466 #define IOSLAVE_INTSTAT_FOVFL_Pos         (1UL)                     /*!< FOVFL (Bit 1)                                         */
13467 #define IOSLAVE_INTSTAT_FOVFL_Msk         (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13468 #define IOSLAVE_INTSTAT_FSIZE_Pos         (0UL)                     /*!< FSIZE (Bit 0)                                         */
13469 #define IOSLAVE_INTSTAT_FSIZE_Msk         (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
13470 /* ========================================================  INTCLR  ========================================================= */
13471 #define IOSLAVE_INTCLR_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
13472 #define IOSLAVE_INTCLR_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
13473 #define IOSLAVE_INTCLR_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
13474 #define IOSLAVE_INTCLR_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
13475 #define IOSLAVE_INTCLR_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
13476 #define IOSLAVE_INTCLR_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
13477 #define IOSLAVE_INTCLR_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
13478 #define IOSLAVE_INTCLR_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
13479 #define IOSLAVE_INTCLR_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
13480 #define IOSLAVE_INTCLR_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
13481 #define IOSLAVE_INTCLR_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
13482 #define IOSLAVE_INTCLR_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
13483 #define IOSLAVE_INTCLR_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
13484 #define IOSLAVE_INTCLR_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
13485 #define IOSLAVE_INTCLR_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13486 #define IOSLAVE_INTCLR_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13487 #define IOSLAVE_INTCLR_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
13488 #define IOSLAVE_INTCLR_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13489 #define IOSLAVE_INTCLR_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
13490 #define IOSLAVE_INTCLR_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
13491 /* ========================================================  INTSET  ========================================================= */
13492 #define IOSLAVE_INTSET_XCMPWR_Pos         (9UL)                     /*!< XCMPWR (Bit 9)                                        */
13493 #define IOSLAVE_INTSET_XCMPWR_Msk         (0x200UL)                 /*!< XCMPWR (Bitfield-Mask: 0x01)                          */
13494 #define IOSLAVE_INTSET_XCMPWF_Pos         (8UL)                     /*!< XCMPWF (Bit 8)                                        */
13495 #define IOSLAVE_INTSET_XCMPWF_Msk         (0x100UL)                 /*!< XCMPWF (Bitfield-Mask: 0x01)                          */
13496 #define IOSLAVE_INTSET_XCMPRR_Pos         (7UL)                     /*!< XCMPRR (Bit 7)                                        */
13497 #define IOSLAVE_INTSET_XCMPRR_Msk         (0x80UL)                  /*!< XCMPRR (Bitfield-Mask: 0x01)                          */
13498 #define IOSLAVE_INTSET_XCMPRF_Pos         (6UL)                     /*!< XCMPRF (Bit 6)                                        */
13499 #define IOSLAVE_INTSET_XCMPRF_Msk         (0x40UL)                  /*!< XCMPRF (Bitfield-Mask: 0x01)                          */
13500 #define IOSLAVE_INTSET_IOINTW_Pos         (5UL)                     /*!< IOINTW (Bit 5)                                        */
13501 #define IOSLAVE_INTSET_IOINTW_Msk         (0x20UL)                  /*!< IOINTW (Bitfield-Mask: 0x01)                          */
13502 #define IOSLAVE_INTSET_GENAD_Pos          (4UL)                     /*!< GENAD (Bit 4)                                         */
13503 #define IOSLAVE_INTSET_GENAD_Msk          (0x10UL)                  /*!< GENAD (Bitfield-Mask: 0x01)                           */
13504 #define IOSLAVE_INTSET_FRDERR_Pos         (3UL)                     /*!< FRDERR (Bit 3)                                        */
13505 #define IOSLAVE_INTSET_FRDERR_Msk         (0x8UL)                   /*!< FRDERR (Bitfield-Mask: 0x01)                          */
13506 #define IOSLAVE_INTSET_FUNDFL_Pos         (2UL)                     /*!< FUNDFL (Bit 2)                                        */
13507 #define IOSLAVE_INTSET_FUNDFL_Msk         (0x4UL)                   /*!< FUNDFL (Bitfield-Mask: 0x01)                          */
13508 #define IOSLAVE_INTSET_FOVFL_Pos          (1UL)                     /*!< FOVFL (Bit 1)                                         */
13509 #define IOSLAVE_INTSET_FOVFL_Msk          (0x2UL)                   /*!< FOVFL (Bitfield-Mask: 0x01)                           */
13510 #define IOSLAVE_INTSET_FSIZE_Pos          (0UL)                     /*!< FSIZE (Bit 0)                                         */
13511 #define IOSLAVE_INTSET_FSIZE_Msk          (0x1UL)                   /*!< FSIZE (Bitfield-Mask: 0x01)                           */
13512 /* ======================================================  REGACCINTEN  ====================================================== */
13513 #define IOSLAVE_REGACCINTEN_REGACC_Pos    (0UL)                     /*!< REGACC (Bit 0)                                        */
13514 #define IOSLAVE_REGACCINTEN_REGACC_Msk    (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
13515 /* =====================================================  REGACCINTSTAT  ===================================================== */
13516 #define IOSLAVE_REGACCINTSTAT_REGACC_Pos  (0UL)                     /*!< REGACC (Bit 0)                                        */
13517 #define IOSLAVE_REGACCINTSTAT_REGACC_Msk  (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
13518 /* =====================================================  REGACCINTCLR  ====================================================== */
13519 #define IOSLAVE_REGACCINTCLR_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
13520 #define IOSLAVE_REGACCINTCLR_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
13521 /* =====================================================  REGACCINTSET  ====================================================== */
13522 #define IOSLAVE_REGACCINTSET_REGACC_Pos   (0UL)                     /*!< REGACC (Bit 0)                                        */
13523 #define IOSLAVE_REGACCINTSET_REGACC_Msk   (0xffffffffUL)            /*!< REGACC (Bitfield-Mask: 0xffffffff)                    */
13524 
13525 
13526 /* =========================================================================================================================== */
13527 /* ================                                          MCUCTRL                                          ================ */
13528 /* =========================================================================================================================== */
13529 
13530 /* ========================================================  CHIPPN  ========================================================= */
13531 #define MCUCTRL_CHIPPN_PARTNUM_Pos        (0UL)                     /*!< PARTNUM (Bit 0)                                       */
13532 #define MCUCTRL_CHIPPN_PARTNUM_Msk        (0xffffffffUL)            /*!< PARTNUM (Bitfield-Mask: 0xffffffff)                   */
13533 /* ========================================================  CHIPID0  ======================================================== */
13534 #define MCUCTRL_CHIPID0_CHIPID0_Pos       (0UL)                     /*!< CHIPID0 (Bit 0)                                       */
13535 #define MCUCTRL_CHIPID0_CHIPID0_Msk       (0xffffffffUL)            /*!< CHIPID0 (Bitfield-Mask: 0xffffffff)                   */
13536 /* ========================================================  CHIPID1  ======================================================== */
13537 #define MCUCTRL_CHIPID1_CHIPID1_Pos       (0UL)                     /*!< CHIPID1 (Bit 0)                                       */
13538 #define MCUCTRL_CHIPID1_CHIPID1_Msk       (0xffffffffUL)            /*!< CHIPID1 (Bitfield-Mask: 0xffffffff)                   */
13539 /* ========================================================  CHIPREV  ======================================================== */
13540 #define MCUCTRL_CHIPREV_SIPART_Pos        (8UL)                     /*!< SIPART (Bit 8)                                        */
13541 #define MCUCTRL_CHIPREV_SIPART_Msk        (0xfff00UL)               /*!< SIPART (Bitfield-Mask: 0xfff)                         */
13542 #define MCUCTRL_CHIPREV_REVMAJ_Pos        (4UL)                     /*!< REVMAJ (Bit 4)                                        */
13543 #define MCUCTRL_CHIPREV_REVMAJ_Msk        (0xf0UL)                  /*!< REVMAJ (Bitfield-Mask: 0x0f)                          */
13544 #define MCUCTRL_CHIPREV_REVMIN_Pos        (0UL)                     /*!< REVMIN (Bit 0)                                        */
13545 #define MCUCTRL_CHIPREV_REVMIN_Msk        (0xfUL)                   /*!< REVMIN (Bitfield-Mask: 0x0f)                          */
13546 /* =======================================================  VENDORID  ======================================================== */
13547 #define MCUCTRL_VENDORID_VENDORID_Pos     (0UL)                     /*!< VENDORID (Bit 0)                                      */
13548 #define MCUCTRL_VENDORID_VENDORID_Msk     (0xffffffffUL)            /*!< VENDORID (Bitfield-Mask: 0xffffffff)                  */
13549 /* ==========================================================  SKU  ========================================================== */
13550 #define MCUCTRL_SKU_SECBOOT_Pos           (2UL)                     /*!< SECBOOT (Bit 2)                                       */
13551 #define MCUCTRL_SKU_SECBOOT_Msk           (0x4UL)                   /*!< SECBOOT (Bitfield-Mask: 0x01)                         */
13552 #define MCUCTRL_SKU_ALLOWBLE_Pos          (1UL)                     /*!< ALLOWBLE (Bit 1)                                      */
13553 #define MCUCTRL_SKU_ALLOWBLE_Msk          (0x2UL)                   /*!< ALLOWBLE (Bitfield-Mask: 0x01)                        */
13554 #define MCUCTRL_SKU_ALLOWBURST_Pos        (0UL)                     /*!< ALLOWBURST (Bit 0)                                    */
13555 #define MCUCTRL_SKU_ALLOWBURST_Msk        (0x1UL)                   /*!< ALLOWBURST (Bitfield-Mask: 0x01)                      */
13556 /* =====================================================  FEATUREENABLE  ===================================================== */
13557 #define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Pos (6UL)                  /*!< BURSTAVAIL (Bit 6)                                    */
13558 #define MCUCTRL_FEATUREENABLE_BURSTAVAIL_Msk (0x40UL)               /*!< BURSTAVAIL (Bitfield-Mask: 0x01)                      */
13559 #define MCUCTRL_FEATUREENABLE_BURSTACK_Pos (5UL)                    /*!< BURSTACK (Bit 5)                                      */
13560 #define MCUCTRL_FEATUREENABLE_BURSTACK_Msk (0x20UL)                 /*!< BURSTACK (Bitfield-Mask: 0x01)                        */
13561 #define MCUCTRL_FEATUREENABLE_BURSTREQ_Pos (4UL)                    /*!< BURSTREQ (Bit 4)                                      */
13562 #define MCUCTRL_FEATUREENABLE_BURSTREQ_Msk (0x10UL)                 /*!< BURSTREQ (Bitfield-Mask: 0x01)                        */
13563 #define MCUCTRL_FEATUREENABLE_BLEAVAIL_Pos (2UL)                    /*!< BLEAVAIL (Bit 2)                                      */
13564 #define MCUCTRL_FEATUREENABLE_BLEAVAIL_Msk (0x4UL)                  /*!< BLEAVAIL (Bitfield-Mask: 0x01)                        */
13565 #define MCUCTRL_FEATUREENABLE_BLEACK_Pos  (1UL)                     /*!< BLEACK (Bit 1)                                        */
13566 #define MCUCTRL_FEATUREENABLE_BLEACK_Msk  (0x2UL)                   /*!< BLEACK (Bitfield-Mask: 0x01)                          */
13567 #define MCUCTRL_FEATUREENABLE_BLEREQ_Pos  (0UL)                     /*!< BLEREQ (Bit 0)                                        */
13568 #define MCUCTRL_FEATUREENABLE_BLEREQ_Msk  (0x1UL)                   /*!< BLEREQ (Bitfield-Mask: 0x01)                          */
13569 /* =======================================================  DEBUGGER  ======================================================== */
13570 #define MCUCTRL_DEBUGGER_LOCKOUT_Pos      (0UL)                     /*!< LOCKOUT (Bit 0)                                       */
13571 #define MCUCTRL_DEBUGGER_LOCKOUT_Msk      (0x1UL)                   /*!< LOCKOUT (Bitfield-Mask: 0x01)                         */
13572 /* ========================================================  BODCTRL  ======================================================== */
13573 #define MCUCTRL_BODCTRL_BODHVREFSEL_Pos   (5UL)                     /*!< BODHVREFSEL (Bit 5)                                   */
13574 #define MCUCTRL_BODCTRL_BODHVREFSEL_Msk   (0x20UL)                  /*!< BODHVREFSEL (Bitfield-Mask: 0x01)                     */
13575 #define MCUCTRL_BODCTRL_BODLVREFSEL_Pos   (4UL)                     /*!< BODLVREFSEL (Bit 4)                                   */
13576 #define MCUCTRL_BODCTRL_BODLVREFSEL_Msk   (0x10UL)                  /*!< BODLVREFSEL (Bitfield-Mask: 0x01)                     */
13577 #define MCUCTRL_BODCTRL_BODFPWD_Pos       (3UL)                     /*!< BODFPWD (Bit 3)                                       */
13578 #define MCUCTRL_BODCTRL_BODFPWD_Msk       (0x8UL)                   /*!< BODFPWD (Bitfield-Mask: 0x01)                         */
13579 #define MCUCTRL_BODCTRL_BODCPWD_Pos       (2UL)                     /*!< BODCPWD (Bit 2)                                       */
13580 #define MCUCTRL_BODCTRL_BODCPWD_Msk       (0x4UL)                   /*!< BODCPWD (Bitfield-Mask: 0x01)                         */
13581 #define MCUCTRL_BODCTRL_BODHPWD_Pos       (1UL)                     /*!< BODHPWD (Bit 1)                                       */
13582 #define MCUCTRL_BODCTRL_BODHPWD_Msk       (0x2UL)                   /*!< BODHPWD (Bitfield-Mask: 0x01)                         */
13583 #define MCUCTRL_BODCTRL_BODLPWD_Pos       (0UL)                     /*!< BODLPWD (Bit 0)                                       */
13584 #define MCUCTRL_BODCTRL_BODLPWD_Msk       (0x1UL)                   /*!< BODLPWD (Bitfield-Mask: 0x01)                         */
13585 /* =======================================================  ADCPWRDLY  ======================================================= */
13586 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Pos     (8UL)                     /*!< ADCPWR1 (Bit 8)                                       */
13587 #define MCUCTRL_ADCPWRDLY_ADCPWR1_Msk     (0xff00UL)                /*!< ADCPWR1 (Bitfield-Mask: 0xff)                         */
13588 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Pos     (0UL)                     /*!< ADCPWR0 (Bit 0)                                       */
13589 #define MCUCTRL_ADCPWRDLY_ADCPWR0_Msk     (0xffUL)                  /*!< ADCPWR0 (Bitfield-Mask: 0xff)                         */
13590 /* ========================================================  ADCCAL  ========================================================= */
13591 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Pos  (1UL)                     /*!< ADCCALIBRATED (Bit 1)                                 */
13592 #define MCUCTRL_ADCCAL_ADCCALIBRATED_Msk  (0x2UL)                   /*!< ADCCALIBRATED (Bitfield-Mask: 0x01)                   */
13593 #define MCUCTRL_ADCCAL_CALONPWRUP_Pos     (0UL)                     /*!< CALONPWRUP (Bit 0)                                    */
13594 #define MCUCTRL_ADCCAL_CALONPWRUP_Msk     (0x1UL)                   /*!< CALONPWRUP (Bitfield-Mask: 0x01)                      */
13595 /* ======================================================  ADCBATTLOAD  ====================================================== */
13596 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Pos  (0UL)                     /*!< BATTLOAD (Bit 0)                                      */
13597 #define MCUCTRL_ADCBATTLOAD_BATTLOAD_Msk  (0x1UL)                   /*!< BATTLOAD (Bitfield-Mask: 0x01)                        */
13598 /* ========================================================  ADCTRIM  ======================================================== */
13599 #define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Pos (11UL)                   /*!< ADCRFBUFIBTRIM (Bit 11)                               */
13600 #define MCUCTRL_ADCTRIM_ADCRFBUFIBTRIM_Msk (0x1800UL)               /*!< ADCRFBUFIBTRIM (Bitfield-Mask: 0x03)                  */
13601 #define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Pos (6UL)                     /*!< ADCREFBUFTRIM (Bit 6)                                 */
13602 #define MCUCTRL_ADCTRIM_ADCREFBUFTRIM_Msk (0x7c0UL)                 /*!< ADCREFBUFTRIM (Bitfield-Mask: 0x1f)                   */
13603 #define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Pos (0UL)                  /*!< ADCREFKEEPIBTRIM (Bit 0)                              */
13604 #define MCUCTRL_ADCTRIM_ADCREFKEEPIBTRIM_Msk (0x3UL)                /*!< ADCREFKEEPIBTRIM (Bitfield-Mask: 0x03)                */
13605 /* ======================================================  ADCREFCOMP  ======================================================= */
13606 #define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Pos (16UL)                    /*!< ADCRFCMPEN (Bit 16)                                   */
13607 #define MCUCTRL_ADCREFCOMP_ADCRFCMPEN_Msk (0x10000UL)               /*!< ADCRFCMPEN (Bitfield-Mask: 0x01)                      */
13608 #define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Pos (8UL)                 /*!< ADCREFKEEPTRIM (Bit 8)                                */
13609 #define MCUCTRL_ADCREFCOMP_ADCREFKEEPTRIM_Msk (0x1f00UL)            /*!< ADCREFKEEPTRIM (Bitfield-Mask: 0x1f)                  */
13610 #define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Pos (0UL)                /*!< ADC_REFCOMP_OUT (Bit 0)                               */
13611 #define MCUCTRL_ADCREFCOMP_ADC_REFCOMP_OUT_Msk (0x1UL)              /*!< ADC_REFCOMP_OUT (Bitfield-Mask: 0x01)                 */
13612 /* =======================================================  XTALCTRL  ======================================================== */
13613 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Pos (8UL)                    /*!< XTALICOMPTRIM (Bit 8)                                 */
13614 #define MCUCTRL_XTALCTRL_XTALICOMPTRIM_Msk (0x300UL)                /*!< XTALICOMPTRIM (Bitfield-Mask: 0x03)                   */
13615 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Pos (6UL)                     /*!< XTALIBUFTRIM (Bit 6)                                  */
13616 #define MCUCTRL_XTALCTRL_XTALIBUFTRIM_Msk (0xc0UL)                  /*!< XTALIBUFTRIM (Bitfield-Mask: 0x03)                    */
13617 #define MCUCTRL_XTALCTRL_PWDBODXTAL_Pos   (5UL)                     /*!< PWDBODXTAL (Bit 5)                                    */
13618 #define MCUCTRL_XTALCTRL_PWDBODXTAL_Msk   (0x20UL)                  /*!< PWDBODXTAL (Bitfield-Mask: 0x01)                      */
13619 #define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Pos (4UL)                     /*!< PDNBCMPRXTAL (Bit 4)                                  */
13620 #define MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Msk (0x10UL)                  /*!< PDNBCMPRXTAL (Bitfield-Mask: 0x01)                    */
13621 #define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Pos (3UL)                     /*!< PDNBCOREXTAL (Bit 3)                                  */
13622 #define MCUCTRL_XTALCTRL_PDNBCOREXTAL_Msk (0x8UL)                   /*!< PDNBCOREXTAL (Bitfield-Mask: 0x01)                    */
13623 #define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Pos  (2UL)                     /*!< BYPCMPRXTAL (Bit 2)                                   */
13624 #define MCUCTRL_XTALCTRL_BYPCMPRXTAL_Msk  (0x4UL)                   /*!< BYPCMPRXTAL (Bitfield-Mask: 0x01)                     */
13625 #define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Pos (1UL)                     /*!< FDBKDSBLXTAL (Bit 1)                                  */
13626 #define MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Msk (0x2UL)                   /*!< FDBKDSBLXTAL (Bitfield-Mask: 0x01)                    */
13627 #define MCUCTRL_XTALCTRL_XTALSWE_Pos      (0UL)                     /*!< XTALSWE (Bit 0)                                       */
13628 #define MCUCTRL_XTALCTRL_XTALSWE_Msk      (0x1UL)                   /*!< XTALSWE (Bitfield-Mask: 0x01)                         */
13629 /* ======================================================  XTALGENCTRL  ====================================================== */
13630 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Pos (8UL)                /*!< XTALKSBIASTRIM (Bit 8)                                */
13631 #define MCUCTRL_XTALGENCTRL_XTALKSBIASTRIM_Msk (0x3f00UL)           /*!< XTALKSBIASTRIM (Bitfield-Mask: 0x3f)                  */
13632 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Pos (2UL)                  /*!< XTALBIASTRIM (Bit 2)                                  */
13633 #define MCUCTRL_XTALGENCTRL_XTALBIASTRIM_Msk (0xfcUL)               /*!< XTALBIASTRIM (Bitfield-Mask: 0x3f)                    */
13634 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Pos  (0UL)                     /*!< ACWARMUP (Bit 0)                                      */
13635 #define MCUCTRL_XTALGENCTRL_ACWARMUP_Msk  (0x3UL)                   /*!< ACWARMUP (Bitfield-Mask: 0x03)                        */
13636 /* =======================================================  MISCCTRL  ======================================================== */
13637 #define MCUCTRL_MISCCTRL_BLE_RESETN_Pos   (5UL)                     /*!< BLE_RESETN (Bit 5)                                    */
13638 #define MCUCTRL_MISCCTRL_BLE_RESETN_Msk   (0x20UL)                  /*!< BLE_RESETN (Bitfield-Mask: 0x01)                      */
13639 #define MCUCTRL_MISCCTRL_RESERVED_RW_0_Pos (0UL)                    /*!< RESERVED_RW_0 (Bit 0)                                 */
13640 #define MCUCTRL_MISCCTRL_RESERVED_RW_0_Msk (0x1fUL)                 /*!< RESERVED_RW_0 (Bitfield-Mask: 0x1f)                   */
13641 /* ======================================================  BOOTLOADER  ======================================================= */
13642 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Pos (30UL)                  /*!< SECBOOTONRST (Bit 30)                                 */
13643 #define MCUCTRL_BOOTLOADER_SECBOOTONRST_Msk (0xc0000000UL)          /*!< SECBOOTONRST (Bitfield-Mask: 0x03)                    */
13644 #define MCUCTRL_BOOTLOADER_SECBOOT_Pos    (28UL)                    /*!< SECBOOT (Bit 28)                                      */
13645 #define MCUCTRL_BOOTLOADER_SECBOOT_Msk    (0x30000000UL)            /*!< SECBOOT (Bitfield-Mask: 0x03)                         */
13646 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Pos (26UL)                /*!< SECBOOTFEATURE (Bit 26)                               */
13647 #define MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Msk (0xc000000UL)         /*!< SECBOOTFEATURE (Bitfield-Mask: 0x03)                  */
13648 #define MCUCTRL_BOOTLOADER_PROTLOCK_Pos   (2UL)                     /*!< PROTLOCK (Bit 2)                                      */
13649 #define MCUCTRL_BOOTLOADER_PROTLOCK_Msk   (0x4UL)                   /*!< PROTLOCK (Bitfield-Mask: 0x01)                        */
13650 #define MCUCTRL_BOOTLOADER_SBLOCK_Pos     (1UL)                     /*!< SBLOCK (Bit 1)                                        */
13651 #define MCUCTRL_BOOTLOADER_SBLOCK_Msk     (0x2UL)                   /*!< SBLOCK (Bitfield-Mask: 0x01)                          */
13652 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Pos (0UL)                  /*!< BOOTLOADERLOW (Bit 0)                                 */
13653 #define MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Msk (0x1UL)                /*!< BOOTLOADERLOW (Bitfield-Mask: 0x01)                   */
13654 /* ======================================================  SHADOWVALID  ====================================================== */
13655 #define MCUCTRL_SHADOWVALID_INFO0_VALID_Pos (2UL)                   /*!< INFO0_VALID (Bit 2)                                   */
13656 #define MCUCTRL_SHADOWVALID_INFO0_VALID_Msk (0x4UL)                 /*!< INFO0_VALID (Bitfield-Mask: 0x01)                     */
13657 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Pos  (1UL)                     /*!< BLDSLEEP (Bit 1)                                      */
13658 #define MCUCTRL_SHADOWVALID_BLDSLEEP_Msk  (0x2UL)                   /*!< BLDSLEEP (Bitfield-Mask: 0x01)                        */
13659 #define MCUCTRL_SHADOWVALID_VALID_Pos     (0UL)                     /*!< VALID (Bit 0)                                         */
13660 #define MCUCTRL_SHADOWVALID_VALID_Msk     (0x1UL)                   /*!< VALID (Bitfield-Mask: 0x01)                           */
13661 /* =======================================================  SCRATCH0  ======================================================== */
13662 #define MCUCTRL_SCRATCH0_SCRATCH0_Pos     (0UL)                     /*!< SCRATCH0 (Bit 0)                                      */
13663 #define MCUCTRL_SCRATCH0_SCRATCH0_Msk     (0xffffffffUL)            /*!< SCRATCH0 (Bitfield-Mask: 0xffffffff)                  */
13664 /* =======================================================  SCRATCH1  ======================================================== */
13665 #define MCUCTRL_SCRATCH1_SCRATCH1_Pos     (0UL)                     /*!< SCRATCH1 (Bit 0)                                      */
13666 #define MCUCTRL_SCRATCH1_SCRATCH1_Msk     (0xffffffffUL)            /*!< SCRATCH1 (Bitfield-Mask: 0xffffffff)                  */
13667 /* ====================================================  ICODEFAULTADDR  ===================================================== */
13668 #define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Pos (0UL)             /*!< ICODEFAULTADDR (Bit 0)                                */
13669 #define MCUCTRL_ICODEFAULTADDR_ICODEFAULTADDR_Msk (0xffffffffUL)    /*!< ICODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
13670 /* ====================================================  DCODEFAULTADDR  ===================================================== */
13671 #define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Pos (0UL)             /*!< DCODEFAULTADDR (Bit 0)                                */
13672 #define MCUCTRL_DCODEFAULTADDR_DCODEFAULTADDR_Msk (0xffffffffUL)    /*!< DCODEFAULTADDR (Bitfield-Mask: 0xffffffff)            */
13673 /* =====================================================  SYSFAULTADDR  ====================================================== */
13674 #define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Pos (0UL)                 /*!< SYSFAULTADDR (Bit 0)                                  */
13675 #define MCUCTRL_SYSFAULTADDR_SYSFAULTADDR_Msk (0xffffffffUL)        /*!< SYSFAULTADDR (Bitfield-Mask: 0xffffffff)              */
13676 /* ======================================================  FAULTSTATUS  ====================================================== */
13677 #define MCUCTRL_FAULTSTATUS_SYSFAULT_Pos  (2UL)                     /*!< SYSFAULT (Bit 2)                                      */
13678 #define MCUCTRL_FAULTSTATUS_SYSFAULT_Msk  (0x4UL)                   /*!< SYSFAULT (Bitfield-Mask: 0x01)                        */
13679 #define MCUCTRL_FAULTSTATUS_DCODEFAULT_Pos (1UL)                    /*!< DCODEFAULT (Bit 1)                                    */
13680 #define MCUCTRL_FAULTSTATUS_DCODEFAULT_Msk (0x2UL)                  /*!< DCODEFAULT (Bitfield-Mask: 0x01)                      */
13681 #define MCUCTRL_FAULTSTATUS_ICODEFAULT_Pos (0UL)                    /*!< ICODEFAULT (Bit 0)                                    */
13682 #define MCUCTRL_FAULTSTATUS_ICODEFAULT_Msk (0x1UL)                  /*!< ICODEFAULT (Bitfield-Mask: 0x01)                      */
13683 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
13684 #define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Pos (0UL)             /*!< FAULTCAPTUREEN (Bit 0)                                */
13685 #define MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Msk (0x1UL)           /*!< FAULTCAPTUREEN (Bitfield-Mask: 0x01)                  */
13686 /* =========================================================  DBGR1  ========================================================= */
13687 #define MCUCTRL_DBGR1_ONETO8_Pos          (0UL)                     /*!< ONETO8 (Bit 0)                                        */
13688 #define MCUCTRL_DBGR1_ONETO8_Msk          (0xffffffffUL)            /*!< ONETO8 (Bitfield-Mask: 0xffffffff)                    */
13689 /* =========================================================  DBGR2  ========================================================= */
13690 #define MCUCTRL_DBGR2_COOLCODE_Pos        (0UL)                     /*!< COOLCODE (Bit 0)                                      */
13691 #define MCUCTRL_DBGR2_COOLCODE_Msk        (0xffffffffUL)            /*!< COOLCODE (Bitfield-Mask: 0xffffffff)                  */
13692 /* =======================================================  PMUENABLE  ======================================================= */
13693 #define MCUCTRL_PMUENABLE_ENABLE_Pos      (0UL)                     /*!< ENABLE (Bit 0)                                        */
13694 #define MCUCTRL_PMUENABLE_ENABLE_Msk      (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
13695 /* =======================================================  TPIUCTRL  ======================================================== */
13696 #define MCUCTRL_TPIUCTRL_CLKSEL_Pos       (8UL)                     /*!< CLKSEL (Bit 8)                                        */
13697 #define MCUCTRL_TPIUCTRL_CLKSEL_Msk       (0x700UL)                 /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
13698 #define MCUCTRL_TPIUCTRL_ENABLE_Pos       (0UL)                     /*!< ENABLE (Bit 0)                                        */
13699 #define MCUCTRL_TPIUCTRL_ENABLE_Msk       (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
13700 /* ======================================================  OTAPOINTER  ======================================================= */
13701 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Pos (2UL)                     /*!< OTAPOINTER (Bit 2)                                    */
13702 #define MCUCTRL_OTAPOINTER_OTAPOINTER_Msk (0xfffffffcUL)            /*!< OTAPOINTER (Bitfield-Mask: 0x3fffffff)                */
13703 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Pos (1UL)                   /*!< OTASBLUPDATE (Bit 1)                                  */
13704 #define MCUCTRL_OTAPOINTER_OTASBLUPDATE_Msk (0x2UL)                 /*!< OTASBLUPDATE (Bitfield-Mask: 0x01)                    */
13705 #define MCUCTRL_OTAPOINTER_OTAVALID_Pos   (0UL)                     /*!< OTAVALID (Bit 0)                                      */
13706 #define MCUCTRL_OTAPOINTER_OTAVALID_Msk   (0x1UL)                   /*!< OTAVALID (Bitfield-Mask: 0x01)                        */
13707 /* ======================================================  APBDMACTRL  ======================================================= */
13708 #define MCUCTRL_APBDMACTRL_HYSTERESIS_Pos (8UL)                     /*!< HYSTERESIS (Bit 8)                                    */
13709 #define MCUCTRL_APBDMACTRL_HYSTERESIS_Msk (0xff00UL)                /*!< HYSTERESIS (Bitfield-Mask: 0xff)                      */
13710 #define MCUCTRL_APBDMACTRL_DECODEABORT_Pos (1UL)                    /*!< DECODEABORT (Bit 1)                                   */
13711 #define MCUCTRL_APBDMACTRL_DECODEABORT_Msk (0x2UL)                  /*!< DECODEABORT (Bitfield-Mask: 0x01)                     */
13712 #define MCUCTRL_APBDMACTRL_DMA_ENABLE_Pos (0UL)                     /*!< DMA_ENABLE (Bit 0)                                    */
13713 #define MCUCTRL_APBDMACTRL_DMA_ENABLE_Msk (0x1UL)                   /*!< DMA_ENABLE (Bitfield-Mask: 0x01)                      */
13714 /* =======================================================  SRAMMODE  ======================================================== */
13715 #define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Pos (5UL)                  /*!< DPREFETCH_CACHE (Bit 5)                               */
13716 #define MCUCTRL_SRAMMODE_DPREFETCH_CACHE_Msk (0x20UL)               /*!< DPREFETCH_CACHE (Bitfield-Mask: 0x01)                 */
13717 #define MCUCTRL_SRAMMODE_DPREFETCH_Pos    (4UL)                     /*!< DPREFETCH (Bit 4)                                     */
13718 #define MCUCTRL_SRAMMODE_DPREFETCH_Msk    (0x10UL)                  /*!< DPREFETCH (Bitfield-Mask: 0x01)                       */
13719 #define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Pos (1UL)                  /*!< IPREFETCH_CACHE (Bit 1)                               */
13720 #define MCUCTRL_SRAMMODE_IPREFETCH_CACHE_Msk (0x2UL)                /*!< IPREFETCH_CACHE (Bitfield-Mask: 0x01)                 */
13721 #define MCUCTRL_SRAMMODE_IPREFETCH_Pos    (0UL)                     /*!< IPREFETCH (Bit 0)                                     */
13722 #define MCUCTRL_SRAMMODE_IPREFETCH_Msk    (0x1UL)                   /*!< IPREFETCH (Bitfield-Mask: 0x01)                       */
13723 /* ======================================================  KEXTCLKSEL  ======================================================= */
13724 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Pos (0UL)                     /*!< KEXTCLKSEL (Bit 0)                                    */
13725 #define MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Msk (0xffffffffUL)            /*!< KEXTCLKSEL (Bitfield-Mask: 0xffffffff)                */
13726 /* =======================================================  SIMOBUCK1  ======================================================= */
13727 #define MCUCTRL_SIMOBUCK1_CORETEMPCOTRIM_Pos (28UL)                 /*!< CORETEMPCOTRIM (Bit 28)                               */
13728 #define MCUCTRL_SIMOBUCK1_CORETEMPCOTRIM_Msk (0xf0000000UL)         /*!< CORETEMPCOTRIM (Bitfield-Mask: 0x0f)                  */
13729 #define MCUCTRL_SIMOBUCK1_SIMOBUCKMEMLPTRIM_Pos (22UL)              /*!< SIMOBUCKMEMLPTRIM (Bit 22)                            */
13730 #define MCUCTRL_SIMOBUCK1_SIMOBUCKMEMLPTRIM_Msk (0xfc00000UL)       /*!< SIMOBUCKMEMLPTRIM (Bitfield-Mask: 0x3f)               */
13731 #define MCUCTRL_SIMOBUCK1_MEMACTIVETRIM_Pos (16UL)                  /*!< MEMACTIVETRIM (Bit 16)                                */
13732 #define MCUCTRL_SIMOBUCK1_MEMACTIVETRIM_Msk (0x3f0000UL)            /*!< MEMACTIVETRIM (Bitfield-Mask: 0x3f)                   */
13733 #define MCUCTRL_SIMOBUCK1_SIMOBUCKCORELPTRIM_Pos (10UL)             /*!< SIMOBUCKCORELPTRIM (Bit 10)                           */
13734 #define MCUCTRL_SIMOBUCK1_SIMOBUCKCORELPTRIM_Msk (0xfc00UL)         /*!< SIMOBUCKCORELPTRIM (Bitfield-Mask: 0x3f)              */
13735 #define MCUCTRL_SIMOBUCK1_COREACTIVETRIM_Pos (0UL)                  /*!< COREACTIVETRIM (Bit 0)                                */
13736 #define MCUCTRL_SIMOBUCK1_COREACTIVETRIM_Msk (0x3ffUL)              /*!< COREACTIVETRIM (Bitfield-Mask: 0x3ff)                 */
13737 /* =======================================================  SIMOBUCK2  ======================================================= */
13738 #define MCUCTRL_SIMOBUCK2_RESERVED_RW_30_Pos (30UL)                 /*!< RESERVED_RW_30 (Bit 30)                               */
13739 #define MCUCTRL_SIMOBUCK2_RESERVED_RW_30_Msk (0xc0000000UL)         /*!< RESERVED_RW_30 (Bitfield-Mask: 0x03)                  */
13740 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELEAKAGETRIM_Pos (28UL)        /*!< SIMOBUCKCORELEAKAGETRIM (Bit 28)                      */
13741 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELEAKAGETRIM_Msk (0x30000000UL) /*!< SIMOBUCKCORELEAKAGETRIM (Bitfield-Mask: 0x03)        */
13742 #define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Pos (24UL)                 /*!< RESERVED_RW_24 (Bit 24)                               */
13743 #define MCUCTRL_SIMOBUCK2_RESERVED_RW_24_Msk (0xf000000UL)          /*!< RESERVED_RW_24 (Bitfield-Mask: 0x0f)                  */
13744 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Pos (20UL)       /*!< SIMOBUCKCORELPLOWTONTRIM (Bit 20)                     */
13745 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPLOWTONTRIM_Msk (0xf00000UL) /*!< SIMOBUCKCORELPLOWTONTRIM (Bitfield-Mask: 0x0f)        */
13746 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Pos (16UL)      /*!< SIMOBUCKCORELPHIGHTONTRIM (Bit 16)                    */
13747 #define MCUCTRL_SIMOBUCK2_SIMOBUCKCORELPHIGHTONTRIM_Msk (0xf0000UL) /*!< SIMOBUCKCORELPHIGHTONTRIM (Bitfield-Mask: 0x0f)       */
13748 #define MCUCTRL_SIMOBUCK2_RESERVED_RW_5_Pos (5UL)                   /*!< RESERVED_RW_5 (Bit 5)                                 */
13749 #define MCUCTRL_SIMOBUCK2_RESERVED_RW_5_Msk (0xffe0UL)              /*!< RESERVED_RW_5 (Bitfield-Mask: 0x7ff)                  */
13750 #define MCUCTRL_SIMOBUCK2_SIMOBUCKTONGENTRIM_Pos (0UL)              /*!< SIMOBUCKTONGENTRIM (Bit 0)                            */
13751 #define MCUCTRL_SIMOBUCK2_SIMOBUCKTONGENTRIM_Msk (0x1fUL)           /*!< SIMOBUCKTONGENTRIM (Bitfield-Mask: 0x1f)              */
13752 /* =======================================================  SIMOBUCK3  ======================================================= */
13753 #define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Pos (31UL)                 /*!< RESERVED_RW_31 (Bit 31)                               */
13754 #define MCUCTRL_SIMOBUCK3_RESERVED_RW_31_Msk (0x80000000UL)         /*!< RESERVED_RW_31 (Bitfield-Mask: 0x01)                  */
13755 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Pos (27UL)       /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bit 27)                     */
13756 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTONTRIM_Msk (0x78000000UL) /*!< SIMOBUCKMEMLPHIGHTONTRIM (Bitfield-Mask: 0x0f)      */
13757 #define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Pos (16UL)                 /*!< RESERVED_RW_16 (Bit 16)                               */
13758 #define MCUCTRL_SIMOBUCK3_RESERVED_RW_16_Msk (0x7ff0000UL)          /*!< RESERVED_RW_16 (Bitfield-Mask: 0x7ff)                 */
13759 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Pos (12UL)       /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bit 12)                     */
13760 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPLOWTOFFTRIM_Msk (0xf000UL)   /*!< SIMOBUCKMEMLPLOWTOFFTRIM (Bitfield-Mask: 0x0f)        */
13761 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Pos (8UL)       /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bit 8)                     */
13762 #define MCUCTRL_SIMOBUCK3_SIMOBUCKMEMLPHIGHTOFFTRIM_Msk (0xf00UL)   /*!< SIMOBUCKMEMLPHIGHTOFFTRIM (Bitfield-Mask: 0x0f)       */
13763 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Pos (4UL)       /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bit 4)                     */
13764 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPLOWTOFFTRIM_Msk (0xf0UL)    /*!< SIMOBUCKCORELPLOWTOFFTRIM (Bitfield-Mask: 0x0f)       */
13765 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Pos (0UL)      /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bit 0)                    */
13766 #define MCUCTRL_SIMOBUCK3_SIMOBUCKCORELPHIGHTOFFTRIM_Msk (0xfUL)    /*!< SIMOBUCKCORELPHIGHTOFFTRIM (Bitfield-Mask: 0x0f)      */
13767 /* =======================================================  SIMOBUCK4  ======================================================= */
13768 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Pos (24UL)         /*!< SIMOBUCKCOMP2TIMEOUTEN (Bit 24)                       */
13769 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2TIMEOUTEN_Msk (0x1000000UL)  /*!< SIMOBUCKCOMP2TIMEOUTEN (Bitfield-Mask: 0x01)          */
13770 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2LPEN_Pos (23UL)              /*!< SIMOBUCKCOMP2LPEN (Bit 23)                            */
13771 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCOMP2LPEN_Msk (0x800000UL)        /*!< SIMOBUCKCOMP2LPEN (Bitfield-Mask: 0x01)               */
13772 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Pos (21UL)              /*!< SIMOBUCKCLKDIVSEL (Bit 21)                            */
13773 #define MCUCTRL_SIMOBUCK4_SIMOBUCKCLKDIVSEL_Msk (0x600000UL)        /*!< SIMOBUCKCLKDIVSEL (Bitfield-Mask: 0x03)               */
13774 #define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Pos (0UL)         /*!< SIMOBUCKMEMLPLOWTONTRIM (Bit 0)                       */
13775 #define MCUCTRL_SIMOBUCK4_SIMOBUCKMEMLPLOWTONTRIM_Msk (0xfUL)       /*!< SIMOBUCKMEMLPLOWTONTRIM (Bitfield-Mask: 0x0f)         */
13776 /* =======================================================  BLEBUCK2  ======================================================== */
13777 #define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Pos (12UL)               /*!< BLEBUCKTOND2ATRIM (Bit 12)                            */
13778 #define MCUCTRL_BLEBUCK2_BLEBUCKTOND2ATRIM_Msk (0x3f000UL)          /*!< BLEBUCKTOND2ATRIM (Bitfield-Mask: 0x3f)               */
13779 #define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Pos (6UL)                 /*!< BLEBUCKTONHITRIM (Bit 6)                              */
13780 #define MCUCTRL_BLEBUCK2_BLEBUCKTONHITRIM_Msk (0xfc0UL)             /*!< BLEBUCKTONHITRIM (Bitfield-Mask: 0x3f)                */
13781 #define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Pos (0UL)                /*!< BLEBUCKTONLOWTRIM (Bit 0)                             */
13782 #define MCUCTRL_BLEBUCK2_BLEBUCKTONLOWTRIM_Msk (0x3fUL)             /*!< BLEBUCKTONLOWTRIM (Bitfield-Mask: 0x3f)               */
13783 /* ======================================================  FLASHWPROT0  ====================================================== */
13784 #define MCUCTRL_FLASHWPROT0_FW0BITS_Pos   (0UL)                     /*!< FW0BITS (Bit 0)                                       */
13785 #define MCUCTRL_FLASHWPROT0_FW0BITS_Msk   (0xffffffffUL)            /*!< FW0BITS (Bitfield-Mask: 0xffffffff)                   */
13786 /* ======================================================  FLASHWPROT1  ====================================================== */
13787 #define MCUCTRL_FLASHWPROT1_FW1BITS_Pos   (0UL)                     /*!< FW1BITS (Bit 0)                                       */
13788 #define MCUCTRL_FLASHWPROT1_FW1BITS_Msk   (0xffffffffUL)            /*!< FW1BITS (Bitfield-Mask: 0xffffffff)                   */
13789 /* ======================================================  FLASHRPROT0  ====================================================== */
13790 #define MCUCTRL_FLASHRPROT0_FR0BITS_Pos   (0UL)                     /*!< FR0BITS (Bit 0)                                       */
13791 #define MCUCTRL_FLASHRPROT0_FR0BITS_Msk   (0xffffffffUL)            /*!< FR0BITS (Bitfield-Mask: 0xffffffff)                   */
13792 /* ======================================================  FLASHRPROT1  ====================================================== */
13793 #define MCUCTRL_FLASHRPROT1_FR1BITS_Pos   (0UL)                     /*!< FR1BITS (Bit 0)                                       */
13794 #define MCUCTRL_FLASHRPROT1_FR1BITS_Msk   (0xffffffffUL)            /*!< FR1BITS (Bitfield-Mask: 0xffffffff)                   */
13795 /* =================================================  DMASRAMWRITEPROTECT0  ================================================== */
13796 #define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Pos (0UL)           /*!< DMA_WPROT0 (Bit 0)                                    */
13797 #define MCUCTRL_DMASRAMWRITEPROTECT0_DMA_WPROT0_Msk (0xffffffffUL)  /*!< DMA_WPROT0 (Bitfield-Mask: 0xffffffff)                */
13798 /* =================================================  DMASRAMWRITEPROTECT1  ================================================== */
13799 #define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Pos (0UL)           /*!< DMA_WPROT1 (Bit 0)                                    */
13800 #define MCUCTRL_DMASRAMWRITEPROTECT1_DMA_WPROT1_Msk (0xffffUL)      /*!< DMA_WPROT1 (Bitfield-Mask: 0xffff)                    */
13801 /* ==================================================  DMASRAMREADPROTECT0  ================================================== */
13802 #define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Pos (0UL)            /*!< DMA_RPROT0 (Bit 0)                                    */
13803 #define MCUCTRL_DMASRAMREADPROTECT0_DMA_RPROT0_Msk (0xffffffffUL)   /*!< DMA_RPROT0 (Bitfield-Mask: 0xffffffff)                */
13804 /* ==================================================  DMASRAMREADPROTECT1  ================================================== */
13805 #define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Pos (0UL)            /*!< DMA_RPROT1 (Bit 0)                                    */
13806 #define MCUCTRL_DMASRAMREADPROTECT1_DMA_RPROT1_Msk (0xffffUL)       /*!< DMA_RPROT1 (Bitfield-Mask: 0xffff)                    */
13807 
13808 
13809 /* =========================================================================================================================== */
13810 /* ================                                           MSPI                                            ================ */
13811 /* =========================================================================================================================== */
13812 
13813 /* =========================================================  CTRL  ========================================================== */
13814 #define MSPI_CTRL_XFERBYTES_Pos           (16UL)                    /*!< XFERBYTES (Bit 16)                                    */
13815 #define MSPI_CTRL_XFERBYTES_Msk           (0xffff0000UL)            /*!< XFERBYTES (Bitfield-Mask: 0xffff)                     */
13816 #define MSPI_CTRL_PIOSCRAMBLE_Pos         (11UL)                    /*!< PIOSCRAMBLE (Bit 11)                                  */
13817 #define MSPI_CTRL_PIOSCRAMBLE_Msk         (0x800UL)                 /*!< PIOSCRAMBLE (Bitfield-Mask: 0x01)                     */
13818 #define MSPI_CTRL_TXRX_Pos                (10UL)                    /*!< TXRX (Bit 10)                                         */
13819 #define MSPI_CTRL_TXRX_Msk                (0x400UL)                 /*!< TXRX (Bitfield-Mask: 0x01)                            */
13820 #define MSPI_CTRL_SENDI_Pos               (9UL)                     /*!< SENDI (Bit 9)                                         */
13821 #define MSPI_CTRL_SENDI_Msk               (0x200UL)                 /*!< SENDI (Bitfield-Mask: 0x01)                           */
13822 #define MSPI_CTRL_SENDA_Pos               (8UL)                     /*!< SENDA (Bit 8)                                         */
13823 #define MSPI_CTRL_SENDA_Msk               (0x100UL)                 /*!< SENDA (Bitfield-Mask: 0x01)                           */
13824 #define MSPI_CTRL_ENTURN_Pos              (7UL)                     /*!< ENTURN (Bit 7)                                        */
13825 #define MSPI_CTRL_ENTURN_Msk              (0x80UL)                  /*!< ENTURN (Bitfield-Mask: 0x01)                          */
13826 #define MSPI_CTRL_BIGENDIAN_Pos           (6UL)                     /*!< BIGENDIAN (Bit 6)                                     */
13827 #define MSPI_CTRL_BIGENDIAN_Msk           (0x40UL)                  /*!< BIGENDIAN (Bitfield-Mask: 0x01)                       */
13828 #define MSPI_CTRL_QUADCMD_Pos             (3UL)                     /*!< QUADCMD (Bit 3)                                       */
13829 #define MSPI_CTRL_QUADCMD_Msk             (0x8UL)                   /*!< QUADCMD (Bitfield-Mask: 0x01)                         */
13830 #define MSPI_CTRL_BUSY_Pos                (2UL)                     /*!< BUSY (Bit 2)                                          */
13831 #define MSPI_CTRL_BUSY_Msk                (0x4UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
13832 #define MSPI_CTRL_STATUS_Pos              (1UL)                     /*!< STATUS (Bit 1)                                        */
13833 #define MSPI_CTRL_STATUS_Msk              (0x2UL)                   /*!< STATUS (Bitfield-Mask: 0x01)                          */
13834 #define MSPI_CTRL_START_Pos               (0UL)                     /*!< START (Bit 0)                                         */
13835 #define MSPI_CTRL_START_Msk               (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
13836 /* ==========================================================  CFG  ========================================================== */
13837 #define MSPI_CFG_CPOL_Pos                 (17UL)                    /*!< CPOL (Bit 17)                                         */
13838 #define MSPI_CFG_CPOL_Msk                 (0x20000UL)               /*!< CPOL (Bitfield-Mask: 0x01)                            */
13839 #define MSPI_CFG_CPHA_Pos                 (16UL)                    /*!< CPHA (Bit 16)                                         */
13840 #define MSPI_CFG_CPHA_Msk                 (0x10000UL)               /*!< CPHA (Bitfield-Mask: 0x01)                            */
13841 #define MSPI_CFG_TURNAROUND_Pos           (8UL)                     /*!< TURNAROUND (Bit 8)                                    */
13842 #define MSPI_CFG_TURNAROUND_Msk           (0x3f00UL)                /*!< TURNAROUND (Bitfield-Mask: 0x3f)                      */
13843 #define MSPI_CFG_SEPIO_Pos                (7UL)                     /*!< SEPIO (Bit 7)                                         */
13844 #define MSPI_CFG_SEPIO_Msk                (0x80UL)                  /*!< SEPIO (Bitfield-Mask: 0x01)                           */
13845 #define MSPI_CFG_ISIZE_Pos                (6UL)                     /*!< ISIZE (Bit 6)                                         */
13846 #define MSPI_CFG_ISIZE_Msk                (0x40UL)                  /*!< ISIZE (Bitfield-Mask: 0x01)                           */
13847 #define MSPI_CFG_ASIZE_Pos                (4UL)                     /*!< ASIZE (Bit 4)                                         */
13848 #define MSPI_CFG_ASIZE_Msk                (0x30UL)                  /*!< ASIZE (Bitfield-Mask: 0x03)                           */
13849 #define MSPI_CFG_DEVCFG_Pos               (0UL)                     /*!< DEVCFG (Bit 0)                                        */
13850 #define MSPI_CFG_DEVCFG_Msk               (0xfUL)                   /*!< DEVCFG (Bitfield-Mask: 0x0f)                          */
13851 /* =========================================================  ADDR  ========================================================== */
13852 #define MSPI_ADDR_ADDR_Pos                (0UL)                     /*!< ADDR (Bit 0)                                          */
13853 #define MSPI_ADDR_ADDR_Msk                (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
13854 /* =========================================================  INSTR  ========================================================= */
13855 #define MSPI_INSTR_INSTR_Pos              (0UL)                     /*!< INSTR (Bit 0)                                         */
13856 #define MSPI_INSTR_INSTR_Msk              (0xffffUL)                /*!< INSTR (Bitfield-Mask: 0xffff)                         */
13857 /* ========================================================  TXFIFO  ========================================================= */
13858 #define MSPI_TXFIFO_TXFIFO_Pos            (0UL)                     /*!< TXFIFO (Bit 0)                                        */
13859 #define MSPI_TXFIFO_TXFIFO_Msk            (0xffffffffUL)            /*!< TXFIFO (Bitfield-Mask: 0xffffffff)                    */
13860 /* ========================================================  RXFIFO  ========================================================= */
13861 #define MSPI_RXFIFO_RXFIFO_Pos            (0UL)                     /*!< RXFIFO (Bit 0)                                        */
13862 #define MSPI_RXFIFO_RXFIFO_Msk            (0xffffffffUL)            /*!< RXFIFO (Bitfield-Mask: 0xffffffff)                    */
13863 /* =======================================================  TXENTRIES  ======================================================= */
13864 #define MSPI_TXENTRIES_TXENTRIES_Pos      (0UL)                     /*!< TXENTRIES (Bit 0)                                     */
13865 #define MSPI_TXENTRIES_TXENTRIES_Msk      (0x1fUL)                  /*!< TXENTRIES (Bitfield-Mask: 0x1f)                       */
13866 /* =======================================================  RXENTRIES  ======================================================= */
13867 #define MSPI_RXENTRIES_RXENTRIES_Pos      (0UL)                     /*!< RXENTRIES (Bit 0)                                     */
13868 #define MSPI_RXENTRIES_RXENTRIES_Msk      (0x1fUL)                  /*!< RXENTRIES (Bitfield-Mask: 0x1f)                       */
13869 /* =======================================================  THRESHOLD  ======================================================= */
13870 #define MSPI_THRESHOLD_RXTHRESH_Pos       (8UL)                     /*!< RXTHRESH (Bit 8)                                      */
13871 #define MSPI_THRESHOLD_RXTHRESH_Msk       (0x1f00UL)                /*!< RXTHRESH (Bitfield-Mask: 0x1f)                        */
13872 #define MSPI_THRESHOLD_TXTHRESH_Pos       (0UL)                     /*!< TXTHRESH (Bit 0)                                      */
13873 #define MSPI_THRESHOLD_TXTHRESH_Msk       (0x1fUL)                  /*!< TXTHRESH (Bitfield-Mask: 0x1f)                        */
13874 /* ========================================================  MSPICFG  ======================================================== */
13875 #define MSPI_MSPICFG_PRSTN_Pos            (31UL)                    /*!< PRSTN (Bit 31)                                        */
13876 #define MSPI_MSPICFG_PRSTN_Msk            (0x80000000UL)            /*!< PRSTN (Bitfield-Mask: 0x01)                           */
13877 #define MSPI_MSPICFG_IPRSTN_Pos           (30UL)                    /*!< IPRSTN (Bit 30)                                       */
13878 #define MSPI_MSPICFG_IPRSTN_Msk           (0x40000000UL)            /*!< IPRSTN (Bitfield-Mask: 0x01)                          */
13879 #define MSPI_MSPICFG_FIFORESET_Pos        (29UL)                    /*!< FIFORESET (Bit 29)                                    */
13880 #define MSPI_MSPICFG_FIFORESET_Msk        (0x20000000UL)            /*!< FIFORESET (Bitfield-Mask: 0x01)                       */
13881 #define MSPI_MSPICFG_CLKDIV_Pos           (8UL)                     /*!< CLKDIV (Bit 8)                                        */
13882 #define MSPI_MSPICFG_CLKDIV_Msk           (0x3f00UL)                /*!< CLKDIV (Bitfield-Mask: 0x3f)                          */
13883 #define MSPI_MSPICFG_IOMSEL_Pos           (4UL)                     /*!< IOMSEL (Bit 4)                                        */
13884 #define MSPI_MSPICFG_IOMSEL_Msk           (0x70UL)                  /*!< IOMSEL (Bitfield-Mask: 0x07)                          */
13885 #define MSPI_MSPICFG_TXNEG_Pos            (3UL)                     /*!< TXNEG (Bit 3)                                         */
13886 #define MSPI_MSPICFG_TXNEG_Msk            (0x8UL)                   /*!< TXNEG (Bitfield-Mask: 0x01)                           */
13887 #define MSPI_MSPICFG_RXNEG_Pos            (2UL)                     /*!< RXNEG (Bit 2)                                         */
13888 #define MSPI_MSPICFG_RXNEG_Msk            (0x4UL)                   /*!< RXNEG (Bitfield-Mask: 0x01)                           */
13889 #define MSPI_MSPICFG_RXCAP_Pos            (1UL)                     /*!< RXCAP (Bit 1)                                         */
13890 #define MSPI_MSPICFG_RXCAP_Msk            (0x2UL)                   /*!< RXCAP (Bitfield-Mask: 0x01)                           */
13891 #define MSPI_MSPICFG_APBCLK_Pos           (0UL)                     /*!< APBCLK (Bit 0)                                        */
13892 #define MSPI_MSPICFG_APBCLK_Msk           (0x1UL)                   /*!< APBCLK (Bitfield-Mask: 0x01)                          */
13893 /* ========================================================  PADCFG  ========================================================= */
13894 #define MSPI_PADCFG_REVCS_Pos             (21UL)                    /*!< REVCS (Bit 21)                                        */
13895 #define MSPI_PADCFG_REVCS_Msk             (0x200000UL)              /*!< REVCS (Bitfield-Mask: 0x01)                           */
13896 #define MSPI_PADCFG_IN3_Pos               (20UL)                    /*!< IN3 (Bit 20)                                          */
13897 #define MSPI_PADCFG_IN3_Msk               (0x100000UL)              /*!< IN3 (Bitfield-Mask: 0x01)                             */
13898 #define MSPI_PADCFG_IN2_Pos               (19UL)                    /*!< IN2 (Bit 19)                                          */
13899 #define MSPI_PADCFG_IN2_Msk               (0x80000UL)               /*!< IN2 (Bitfield-Mask: 0x01)                             */
13900 #define MSPI_PADCFG_IN1_Pos               (18UL)                    /*!< IN1 (Bit 18)                                          */
13901 #define MSPI_PADCFG_IN1_Msk               (0x40000UL)               /*!< IN1 (Bitfield-Mask: 0x01)                             */
13902 #define MSPI_PADCFG_IN0_Pos               (16UL)                    /*!< IN0 (Bit 16)                                          */
13903 #define MSPI_PADCFG_IN0_Msk               (0x30000UL)               /*!< IN0 (Bitfield-Mask: 0x03)                             */
13904 #define MSPI_PADCFG_OUT7_Pos              (4UL)                     /*!< OUT7 (Bit 4)                                          */
13905 #define MSPI_PADCFG_OUT7_Msk              (0x10UL)                  /*!< OUT7 (Bitfield-Mask: 0x01)                            */
13906 #define MSPI_PADCFG_OUT6_Pos              (3UL)                     /*!< OUT6 (Bit 3)                                          */
13907 #define MSPI_PADCFG_OUT6_Msk              (0x8UL)                   /*!< OUT6 (Bitfield-Mask: 0x01)                            */
13908 #define MSPI_PADCFG_OUT5_Pos              (2UL)                     /*!< OUT5 (Bit 2)                                          */
13909 #define MSPI_PADCFG_OUT5_Msk              (0x4UL)                   /*!< OUT5 (Bitfield-Mask: 0x01)                            */
13910 #define MSPI_PADCFG_OUT4_Pos              (1UL)                     /*!< OUT4 (Bit 1)                                          */
13911 #define MSPI_PADCFG_OUT4_Msk              (0x2UL)                   /*!< OUT4 (Bitfield-Mask: 0x01)                            */
13912 #define MSPI_PADCFG_OUT3_Pos              (0UL)                     /*!< OUT3 (Bit 0)                                          */
13913 #define MSPI_PADCFG_OUT3_Msk              (0x1UL)                   /*!< OUT3 (Bitfield-Mask: 0x01)                            */
13914 /* =======================================================  PADOUTEN  ======================================================== */
13915 #define MSPI_PADOUTEN_OUTEN_Pos           (0UL)                     /*!< OUTEN (Bit 0)                                         */
13916 #define MSPI_PADOUTEN_OUTEN_Msk           (0x1ffUL)                 /*!< OUTEN (Bitfield-Mask: 0x1ff)                          */
13917 /* =========================================================  FLASH  ========================================================= */
13918 #define MSPI_FLASH_READINSTR_Pos          (24UL)                    /*!< READINSTR (Bit 24)                                    */
13919 #define MSPI_FLASH_READINSTR_Msk          (0xff000000UL)            /*!< READINSTR (Bitfield-Mask: 0xff)                       */
13920 #define MSPI_FLASH_WRITEINSTR_Pos         (16UL)                    /*!< WRITEINSTR (Bit 16)                                   */
13921 #define MSPI_FLASH_WRITEINSTR_Msk         (0xff0000UL)              /*!< WRITEINSTR (Bitfield-Mask: 0xff)                      */
13922 #define MSPI_FLASH_XIPMIXED_Pos           (8UL)                     /*!< XIPMIXED (Bit 8)                                      */
13923 #define MSPI_FLASH_XIPMIXED_Msk           (0x700UL)                 /*!< XIPMIXED (Bitfield-Mask: 0x07)                        */
13924 #define MSPI_FLASH_XIPSENDI_Pos           (7UL)                     /*!< XIPSENDI (Bit 7)                                      */
13925 #define MSPI_FLASH_XIPSENDI_Msk           (0x80UL)                  /*!< XIPSENDI (Bitfield-Mask: 0x01)                        */
13926 #define MSPI_FLASH_XIPSENDA_Pos           (6UL)                     /*!< XIPSENDA (Bit 6)                                      */
13927 #define MSPI_FLASH_XIPSENDA_Msk           (0x40UL)                  /*!< XIPSENDA (Bitfield-Mask: 0x01)                        */
13928 #define MSPI_FLASH_XIPENTURN_Pos          (5UL)                     /*!< XIPENTURN (Bit 5)                                     */
13929 #define MSPI_FLASH_XIPENTURN_Msk          (0x20UL)                  /*!< XIPENTURN (Bitfield-Mask: 0x01)                       */
13930 #define MSPI_FLASH_XIPBIGENDIAN_Pos       (4UL)                     /*!< XIPBIGENDIAN (Bit 4)                                  */
13931 #define MSPI_FLASH_XIPBIGENDIAN_Msk       (0x10UL)                  /*!< XIPBIGENDIAN (Bitfield-Mask: 0x01)                    */
13932 #define MSPI_FLASH_XIPACK_Pos             (2UL)                     /*!< XIPACK (Bit 2)                                        */
13933 #define MSPI_FLASH_XIPACK_Msk             (0xcUL)                   /*!< XIPACK (Bitfield-Mask: 0x03)                          */
13934 #define MSPI_FLASH_XIPEN_Pos              (0UL)                     /*!< XIPEN (Bit 0)                                         */
13935 #define MSPI_FLASH_XIPEN_Msk              (0x1UL)                   /*!< XIPEN (Bitfield-Mask: 0x01)                           */
13936 /* ======================================================  SCRAMBLING  ======================================================= */
13937 #define MSPI_SCRAMBLING_SCRENABLE_Pos     (31UL)                    /*!< SCRENABLE (Bit 31)                                    */
13938 #define MSPI_SCRAMBLING_SCRENABLE_Msk     (0x80000000UL)            /*!< SCRENABLE (Bitfield-Mask: 0x01)                       */
13939 #define MSPI_SCRAMBLING_SCREND_Pos        (16UL)                    /*!< SCREND (Bit 16)                                       */
13940 #define MSPI_SCRAMBLING_SCREND_Msk        (0x3ff0000UL)             /*!< SCREND (Bitfield-Mask: 0x3ff)                         */
13941 #define MSPI_SCRAMBLING_SCRSTART_Pos      (0UL)                     /*!< SCRSTART (Bit 0)                                      */
13942 #define MSPI_SCRAMBLING_SCRSTART_Msk      (0x3ffUL)                 /*!< SCRSTART (Bitfield-Mask: 0x3ff)                       */
13943 /* =========================================================  INTEN  ========================================================= */
13944 #define MSPI_INTEN_SCRERR_Pos             (12UL)                    /*!< SCRERR (Bit 12)                                       */
13945 #define MSPI_INTEN_SCRERR_Msk             (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
13946 #define MSPI_INTEN_CQERR_Pos              (11UL)                    /*!< CQERR (Bit 11)                                        */
13947 #define MSPI_INTEN_CQERR_Msk              (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
13948 #define MSPI_INTEN_CQPAUSED_Pos           (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
13949 #define MSPI_INTEN_CQPAUSED_Msk           (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13950 #define MSPI_INTEN_CQUPD_Pos              (9UL)                     /*!< CQUPD (Bit 9)                                         */
13951 #define MSPI_INTEN_CQUPD_Msk              (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
13952 #define MSPI_INTEN_CQCMP_Pos              (8UL)                     /*!< CQCMP (Bit 8)                                         */
13953 #define MSPI_INTEN_CQCMP_Msk              (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
13954 #define MSPI_INTEN_DERR_Pos               (7UL)                     /*!< DERR (Bit 7)                                          */
13955 #define MSPI_INTEN_DERR_Msk               (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
13956 #define MSPI_INTEN_DCMP_Pos               (6UL)                     /*!< DCMP (Bit 6)                                          */
13957 #define MSPI_INTEN_DCMP_Msk               (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
13958 #define MSPI_INTEN_RXF_Pos                (5UL)                     /*!< RXF (Bit 5)                                           */
13959 #define MSPI_INTEN_RXF_Msk                (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
13960 #define MSPI_INTEN_RXO_Pos                (4UL)                     /*!< RXO (Bit 4)                                           */
13961 #define MSPI_INTEN_RXO_Msk                (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
13962 #define MSPI_INTEN_RXU_Pos                (3UL)                     /*!< RXU (Bit 3)                                           */
13963 #define MSPI_INTEN_RXU_Msk                (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
13964 #define MSPI_INTEN_TXO_Pos                (2UL)                     /*!< TXO (Bit 2)                                           */
13965 #define MSPI_INTEN_TXO_Msk                (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
13966 #define MSPI_INTEN_TXE_Pos                (1UL)                     /*!< TXE (Bit 1)                                           */
13967 #define MSPI_INTEN_TXE_Msk                (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
13968 #define MSPI_INTEN_CMDCMP_Pos             (0UL)                     /*!< CMDCMP (Bit 0)                                        */
13969 #define MSPI_INTEN_CMDCMP_Msk             (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
13970 /* ========================================================  INTSTAT  ======================================================== */
13971 #define MSPI_INTSTAT_SCRERR_Pos           (12UL)                    /*!< SCRERR (Bit 12)                                       */
13972 #define MSPI_INTSTAT_SCRERR_Msk           (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
13973 #define MSPI_INTSTAT_CQERR_Pos            (11UL)                    /*!< CQERR (Bit 11)                                        */
13974 #define MSPI_INTSTAT_CQERR_Msk            (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
13975 #define MSPI_INTSTAT_CQPAUSED_Pos         (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
13976 #define MSPI_INTSTAT_CQPAUSED_Msk         (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
13977 #define MSPI_INTSTAT_CQUPD_Pos            (9UL)                     /*!< CQUPD (Bit 9)                                         */
13978 #define MSPI_INTSTAT_CQUPD_Msk            (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
13979 #define MSPI_INTSTAT_CQCMP_Pos            (8UL)                     /*!< CQCMP (Bit 8)                                         */
13980 #define MSPI_INTSTAT_CQCMP_Msk            (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
13981 #define MSPI_INTSTAT_DERR_Pos             (7UL)                     /*!< DERR (Bit 7)                                          */
13982 #define MSPI_INTSTAT_DERR_Msk             (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
13983 #define MSPI_INTSTAT_DCMP_Pos             (6UL)                     /*!< DCMP (Bit 6)                                          */
13984 #define MSPI_INTSTAT_DCMP_Msk             (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
13985 #define MSPI_INTSTAT_RXF_Pos              (5UL)                     /*!< RXF (Bit 5)                                           */
13986 #define MSPI_INTSTAT_RXF_Msk              (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
13987 #define MSPI_INTSTAT_RXO_Pos              (4UL)                     /*!< RXO (Bit 4)                                           */
13988 #define MSPI_INTSTAT_RXO_Msk              (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
13989 #define MSPI_INTSTAT_RXU_Pos              (3UL)                     /*!< RXU (Bit 3)                                           */
13990 #define MSPI_INTSTAT_RXU_Msk              (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
13991 #define MSPI_INTSTAT_TXO_Pos              (2UL)                     /*!< TXO (Bit 2)                                           */
13992 #define MSPI_INTSTAT_TXO_Msk              (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
13993 #define MSPI_INTSTAT_TXE_Pos              (1UL)                     /*!< TXE (Bit 1)                                           */
13994 #define MSPI_INTSTAT_TXE_Msk              (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
13995 #define MSPI_INTSTAT_CMDCMP_Pos           (0UL)                     /*!< CMDCMP (Bit 0)                                        */
13996 #define MSPI_INTSTAT_CMDCMP_Msk           (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
13997 /* ========================================================  INTCLR  ========================================================= */
13998 #define MSPI_INTCLR_SCRERR_Pos            (12UL)                    /*!< SCRERR (Bit 12)                                       */
13999 #define MSPI_INTCLR_SCRERR_Msk            (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
14000 #define MSPI_INTCLR_CQERR_Pos             (11UL)                    /*!< CQERR (Bit 11)                                        */
14001 #define MSPI_INTCLR_CQERR_Msk             (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
14002 #define MSPI_INTCLR_CQPAUSED_Pos          (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
14003 #define MSPI_INTCLR_CQPAUSED_Msk          (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14004 #define MSPI_INTCLR_CQUPD_Pos             (9UL)                     /*!< CQUPD (Bit 9)                                         */
14005 #define MSPI_INTCLR_CQUPD_Msk             (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
14006 #define MSPI_INTCLR_CQCMP_Pos             (8UL)                     /*!< CQCMP (Bit 8)                                         */
14007 #define MSPI_INTCLR_CQCMP_Msk             (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
14008 #define MSPI_INTCLR_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
14009 #define MSPI_INTCLR_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
14010 #define MSPI_INTCLR_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
14011 #define MSPI_INTCLR_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
14012 #define MSPI_INTCLR_RXF_Pos               (5UL)                     /*!< RXF (Bit 5)                                           */
14013 #define MSPI_INTCLR_RXF_Msk               (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
14014 #define MSPI_INTCLR_RXO_Pos               (4UL)                     /*!< RXO (Bit 4)                                           */
14015 #define MSPI_INTCLR_RXO_Msk               (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
14016 #define MSPI_INTCLR_RXU_Pos               (3UL)                     /*!< RXU (Bit 3)                                           */
14017 #define MSPI_INTCLR_RXU_Msk               (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
14018 #define MSPI_INTCLR_TXO_Pos               (2UL)                     /*!< TXO (Bit 2)                                           */
14019 #define MSPI_INTCLR_TXO_Msk               (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
14020 #define MSPI_INTCLR_TXE_Pos               (1UL)                     /*!< TXE (Bit 1)                                           */
14021 #define MSPI_INTCLR_TXE_Msk               (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
14022 #define MSPI_INTCLR_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
14023 #define MSPI_INTCLR_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
14024 /* ========================================================  INTSET  ========================================================= */
14025 #define MSPI_INTSET_SCRERR_Pos            (12UL)                    /*!< SCRERR (Bit 12)                                       */
14026 #define MSPI_INTSET_SCRERR_Msk            (0x1000UL)                /*!< SCRERR (Bitfield-Mask: 0x01)                          */
14027 #define MSPI_INTSET_CQERR_Pos             (11UL)                    /*!< CQERR (Bit 11)                                        */
14028 #define MSPI_INTSET_CQERR_Msk             (0x800UL)                 /*!< CQERR (Bitfield-Mask: 0x01)                           */
14029 #define MSPI_INTSET_CQPAUSED_Pos          (10UL)                    /*!< CQPAUSED (Bit 10)                                     */
14030 #define MSPI_INTSET_CQPAUSED_Msk          (0x400UL)                 /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14031 #define MSPI_INTSET_CQUPD_Pos             (9UL)                     /*!< CQUPD (Bit 9)                                         */
14032 #define MSPI_INTSET_CQUPD_Msk             (0x200UL)                 /*!< CQUPD (Bitfield-Mask: 0x01)                           */
14033 #define MSPI_INTSET_CQCMP_Pos             (8UL)                     /*!< CQCMP (Bit 8)                                         */
14034 #define MSPI_INTSET_CQCMP_Msk             (0x100UL)                 /*!< CQCMP (Bitfield-Mask: 0x01)                           */
14035 #define MSPI_INTSET_DERR_Pos              (7UL)                     /*!< DERR (Bit 7)                                          */
14036 #define MSPI_INTSET_DERR_Msk              (0x80UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
14037 #define MSPI_INTSET_DCMP_Pos              (6UL)                     /*!< DCMP (Bit 6)                                          */
14038 #define MSPI_INTSET_DCMP_Msk              (0x40UL)                  /*!< DCMP (Bitfield-Mask: 0x01)                            */
14039 #define MSPI_INTSET_RXF_Pos               (5UL)                     /*!< RXF (Bit 5)                                           */
14040 #define MSPI_INTSET_RXF_Msk               (0x20UL)                  /*!< RXF (Bitfield-Mask: 0x01)                             */
14041 #define MSPI_INTSET_RXO_Pos               (4UL)                     /*!< RXO (Bit 4)                                           */
14042 #define MSPI_INTSET_RXO_Msk               (0x10UL)                  /*!< RXO (Bitfield-Mask: 0x01)                             */
14043 #define MSPI_INTSET_RXU_Pos               (3UL)                     /*!< RXU (Bit 3)                                           */
14044 #define MSPI_INTSET_RXU_Msk               (0x8UL)                   /*!< RXU (Bitfield-Mask: 0x01)                             */
14045 #define MSPI_INTSET_TXO_Pos               (2UL)                     /*!< TXO (Bit 2)                                           */
14046 #define MSPI_INTSET_TXO_Msk               (0x4UL)                   /*!< TXO (Bitfield-Mask: 0x01)                             */
14047 #define MSPI_INTSET_TXE_Pos               (1UL)                     /*!< TXE (Bit 1)                                           */
14048 #define MSPI_INTSET_TXE_Msk               (0x2UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
14049 #define MSPI_INTSET_CMDCMP_Pos            (0UL)                     /*!< CMDCMP (Bit 0)                                        */
14050 #define MSPI_INTSET_CMDCMP_Msk            (0x1UL)                   /*!< CMDCMP (Bitfield-Mask: 0x01)                          */
14051 /* ========================================================  DMACFG  ========================================================= */
14052 #define MSPI_DMACFG_DMAPWROFF_Pos         (18UL)                    /*!< DMAPWROFF (Bit 18)                                    */
14053 #define MSPI_DMACFG_DMAPWROFF_Msk         (0x40000UL)               /*!< DMAPWROFF (Bitfield-Mask: 0x01)                       */
14054 #define MSPI_DMACFG_DMAPRI_Pos            (3UL)                     /*!< DMAPRI (Bit 3)                                        */
14055 #define MSPI_DMACFG_DMAPRI_Msk            (0x18UL)                  /*!< DMAPRI (Bitfield-Mask: 0x03)                          */
14056 #define MSPI_DMACFG_DMADIR_Pos            (2UL)                     /*!< DMADIR (Bit 2)                                        */
14057 #define MSPI_DMACFG_DMADIR_Msk            (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
14058 #define MSPI_DMACFG_DMAEN_Pos             (0UL)                     /*!< DMAEN (Bit 0)                                         */
14059 #define MSPI_DMACFG_DMAEN_Msk             (0x3UL)                   /*!< DMAEN (Bitfield-Mask: 0x03)                           */
14060 /* ========================================================  DMASTAT  ======================================================== */
14061 #define MSPI_DMASTAT_SCRERR_Pos           (3UL)                     /*!< SCRERR (Bit 3)                                        */
14062 #define MSPI_DMASTAT_SCRERR_Msk           (0x8UL)                   /*!< SCRERR (Bitfield-Mask: 0x01)                          */
14063 #define MSPI_DMASTAT_DMAERR_Pos           (2UL)                     /*!< DMAERR (Bit 2)                                        */
14064 #define MSPI_DMASTAT_DMAERR_Msk           (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
14065 #define MSPI_DMASTAT_DMACPL_Pos           (1UL)                     /*!< DMACPL (Bit 1)                                        */
14066 #define MSPI_DMASTAT_DMACPL_Msk           (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
14067 #define MSPI_DMASTAT_DMATIP_Pos           (0UL)                     /*!< DMATIP (Bit 0)                                        */
14068 #define MSPI_DMASTAT_DMATIP_Msk           (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
14069 /* ======================================================  DMATARGADDR  ====================================================== */
14070 #define MSPI_DMATARGADDR_TARGADDR_Pos     (0UL)                     /*!< TARGADDR (Bit 0)                                      */
14071 #define MSPI_DMATARGADDR_TARGADDR_Msk     (0xffffffffUL)            /*!< TARGADDR (Bitfield-Mask: 0xffffffff)                  */
14072 /* ======================================================  DMADEVADDR  ======================================================= */
14073 #define MSPI_DMADEVADDR_DEVADDR_Pos       (0UL)                     /*!< DEVADDR (Bit 0)                                       */
14074 #define MSPI_DMADEVADDR_DEVADDR_Msk       (0xffffffffUL)            /*!< DEVADDR (Bitfield-Mask: 0xffffffff)                   */
14075 /* ======================================================  DMATOTCOUNT  ====================================================== */
14076 #define MSPI_DMATOTCOUNT_TOTCOUNT_Pos     (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
14077 #define MSPI_DMATOTCOUNT_TOTCOUNT_Msk     (0xffffUL)                /*!< TOTCOUNT (Bitfield-Mask: 0xffff)                      */
14078 /* =======================================================  DMABCOUNT  ======================================================= */
14079 #define MSPI_DMABCOUNT_BCOUNT_Pos         (0UL)                     /*!< BCOUNT (Bit 0)                                        */
14080 #define MSPI_DMABCOUNT_BCOUNT_Msk         (0xffUL)                  /*!< BCOUNT (Bitfield-Mask: 0xff)                          */
14081 /* =======================================================  DMATHRESH  ======================================================= */
14082 #define MSPI_DMATHRESH_DMATHRESH_Pos      (0UL)                     /*!< DMATHRESH (Bit 0)                                     */
14083 #define MSPI_DMATHRESH_DMATHRESH_Msk      (0xfUL)                   /*!< DMATHRESH (Bitfield-Mask: 0x0f)                       */
14084 /* =========================================================  CQCFG  ========================================================= */
14085 #define MSPI_CQCFG_CQAUTOCLEARMASK_Pos    (3UL)                     /*!< CQAUTOCLEARMASK (Bit 3)                               */
14086 #define MSPI_CQCFG_CQAUTOCLEARMASK_Msk    (0x8UL)                   /*!< CQAUTOCLEARMASK (Bitfield-Mask: 0x01)                 */
14087 #define MSPI_CQCFG_CQPWROFF_Pos           (2UL)                     /*!< CQPWROFF (Bit 2)                                      */
14088 #define MSPI_CQCFG_CQPWROFF_Msk           (0x4UL)                   /*!< CQPWROFF (Bitfield-Mask: 0x01)                        */
14089 #define MSPI_CQCFG_CQPRI_Pos              (1UL)                     /*!< CQPRI (Bit 1)                                         */
14090 #define MSPI_CQCFG_CQPRI_Msk              (0x2UL)                   /*!< CQPRI (Bitfield-Mask: 0x01)                           */
14091 #define MSPI_CQCFG_CQEN_Pos               (0UL)                     /*!< CQEN (Bit 0)                                          */
14092 #define MSPI_CQCFG_CQEN_Msk               (0x1UL)                   /*!< CQEN (Bitfield-Mask: 0x01)                            */
14093 /* ========================================================  CQADDR  ========================================================= */
14094 #define MSPI_CQADDR_CQADDR_Pos            (0UL)                     /*!< CQADDR (Bit 0)                                        */
14095 #define MSPI_CQADDR_CQADDR_Msk            (0x1fffffffUL)            /*!< CQADDR (Bitfield-Mask: 0x1fffffff)                    */
14096 /* ========================================================  CQSTAT  ========================================================= */
14097 #define MSPI_CQSTAT_CQPAUSED_Pos          (3UL)                     /*!< CQPAUSED (Bit 3)                                      */
14098 #define MSPI_CQSTAT_CQPAUSED_Msk          (0x8UL)                   /*!< CQPAUSED (Bitfield-Mask: 0x01)                        */
14099 #define MSPI_CQSTAT_CQERR_Pos             (2UL)                     /*!< CQERR (Bit 2)                                         */
14100 #define MSPI_CQSTAT_CQERR_Msk             (0x4UL)                   /*!< CQERR (Bitfield-Mask: 0x01)                           */
14101 #define MSPI_CQSTAT_CQCPL_Pos             (1UL)                     /*!< CQCPL (Bit 1)                                         */
14102 #define MSPI_CQSTAT_CQCPL_Msk             (0x2UL)                   /*!< CQCPL (Bitfield-Mask: 0x01)                           */
14103 #define MSPI_CQSTAT_CQTIP_Pos             (0UL)                     /*!< CQTIP (Bit 0)                                         */
14104 #define MSPI_CQSTAT_CQTIP_Msk             (0x1UL)                   /*!< CQTIP (Bitfield-Mask: 0x01)                           */
14105 /* ========================================================  CQFLAGS  ======================================================== */
14106 #define MSPI_CQFLAGS_CQFLAGS_Pos          (0UL)                     /*!< CQFLAGS (Bit 0)                                       */
14107 #define MSPI_CQFLAGS_CQFLAGS_Msk          (0xffffUL)                /*!< CQFLAGS (Bitfield-Mask: 0xffff)                       */
14108 /* ======================================================  CQSETCLEAR  ======================================================= */
14109 #define MSPI_CQSETCLEAR_CQFCLR_Pos        (16UL)                    /*!< CQFCLR (Bit 16)                                       */
14110 #define MSPI_CQSETCLEAR_CQFCLR_Msk        (0xff0000UL)              /*!< CQFCLR (Bitfield-Mask: 0xff)                          */
14111 #define MSPI_CQSETCLEAR_CQFTOGGLE_Pos     (8UL)                     /*!< CQFTOGGLE (Bit 8)                                     */
14112 #define MSPI_CQSETCLEAR_CQFTOGGLE_Msk     (0xff00UL)                /*!< CQFTOGGLE (Bitfield-Mask: 0xff)                       */
14113 #define MSPI_CQSETCLEAR_CQFSET_Pos        (0UL)                     /*!< CQFSET (Bit 0)                                        */
14114 #define MSPI_CQSETCLEAR_CQFSET_Msk        (0xffUL)                  /*!< CQFSET (Bitfield-Mask: 0xff)                          */
14115 /* ========================================================  CQPAUSE  ======================================================== */
14116 #define MSPI_CQPAUSE_CQMASK_Pos           (0UL)                     /*!< CQMASK (Bit 0)                                        */
14117 #define MSPI_CQPAUSE_CQMASK_Msk           (0xffffUL)                /*!< CQMASK (Bitfield-Mask: 0xffff)                        */
14118 /* =======================================================  CQCURIDX  ======================================================== */
14119 #define MSPI_CQCURIDX_CQCURIDX_Pos        (0UL)                     /*!< CQCURIDX (Bit 0)                                      */
14120 #define MSPI_CQCURIDX_CQCURIDX_Msk        (0xffUL)                  /*!< CQCURIDX (Bitfield-Mask: 0xff)                        */
14121 /* =======================================================  CQENDIDX  ======================================================== */
14122 #define MSPI_CQENDIDX_CQENDIDX_Pos        (0UL)                     /*!< CQENDIDX (Bit 0)                                      */
14123 #define MSPI_CQENDIDX_CQENDIDX_Msk        (0xffUL)                  /*!< CQENDIDX (Bitfield-Mask: 0xff)                        */
14124 
14125 
14126 /* =========================================================================================================================== */
14127 /* ================                                            PDM                                            ================ */
14128 /* =========================================================================================================================== */
14129 
14130 /* =========================================================  PCFG  ========================================================== */
14131 #define PDM_PCFG_LRSWAP_Pos               (31UL)                    /*!< LRSWAP (Bit 31)                                       */
14132 #define PDM_PCFG_LRSWAP_Msk               (0x80000000UL)            /*!< LRSWAP (Bitfield-Mask: 0x01)                          */
14133 #define PDM_PCFG_PGARIGHT_Pos             (26UL)                    /*!< PGARIGHT (Bit 26)                                     */
14134 #define PDM_PCFG_PGARIGHT_Msk             (0x7c000000UL)            /*!< PGARIGHT (Bitfield-Mask: 0x1f)                        */
14135 #define PDM_PCFG_PGALEFT_Pos              (21UL)                    /*!< PGALEFT (Bit 21)                                      */
14136 #define PDM_PCFG_PGALEFT_Msk              (0x3e00000UL)             /*!< PGALEFT (Bitfield-Mask: 0x1f)                         */
14137 #define PDM_PCFG_MCLKDIV_Pos              (17UL)                    /*!< MCLKDIV (Bit 17)                                      */
14138 #define PDM_PCFG_MCLKDIV_Msk              (0x60000UL)               /*!< MCLKDIV (Bitfield-Mask: 0x03)                         */
14139 #define PDM_PCFG_SINCRATE_Pos             (10UL)                    /*!< SINCRATE (Bit 10)                                     */
14140 #define PDM_PCFG_SINCRATE_Msk             (0x1fc00UL)               /*!< SINCRATE (Bitfield-Mask: 0x7f)                        */
14141 #define PDM_PCFG_ADCHPD_Pos               (9UL)                     /*!< ADCHPD (Bit 9)                                        */
14142 #define PDM_PCFG_ADCHPD_Msk               (0x200UL)                 /*!< ADCHPD (Bitfield-Mask: 0x01)                          */
14143 #define PDM_PCFG_HPCUTOFF_Pos             (5UL)                     /*!< HPCUTOFF (Bit 5)                                      */
14144 #define PDM_PCFG_HPCUTOFF_Msk             (0x1e0UL)                 /*!< HPCUTOFF (Bitfield-Mask: 0x0f)                        */
14145 #define PDM_PCFG_CYCLES_Pos               (2UL)                     /*!< CYCLES (Bit 2)                                        */
14146 #define PDM_PCFG_CYCLES_Msk               (0x1cUL)                  /*!< CYCLES (Bitfield-Mask: 0x07)                          */
14147 #define PDM_PCFG_SOFTMUTE_Pos             (1UL)                     /*!< SOFTMUTE (Bit 1)                                      */
14148 #define PDM_PCFG_SOFTMUTE_Msk             (0x2UL)                   /*!< SOFTMUTE (Bitfield-Mask: 0x01)                        */
14149 #define PDM_PCFG_PDMCOREEN_Pos            (0UL)                     /*!< PDMCOREEN (Bit 0)                                     */
14150 #define PDM_PCFG_PDMCOREEN_Msk            (0x1UL)                   /*!< PDMCOREEN (Bitfield-Mask: 0x01)                       */
14151 /* =========================================================  VCFG  ========================================================== */
14152 #define PDM_VCFG_IOCLKEN_Pos              (31UL)                    /*!< IOCLKEN (Bit 31)                                      */
14153 #define PDM_VCFG_IOCLKEN_Msk              (0x80000000UL)            /*!< IOCLKEN (Bitfield-Mask: 0x01)                         */
14154 #define PDM_VCFG_RSTB_Pos                 (30UL)                    /*!< RSTB (Bit 30)                                         */
14155 #define PDM_VCFG_RSTB_Msk                 (0x40000000UL)            /*!< RSTB (Bitfield-Mask: 0x01)                            */
14156 #define PDM_VCFG_PDMCLKSEL_Pos            (27UL)                    /*!< PDMCLKSEL (Bit 27)                                    */
14157 #define PDM_VCFG_PDMCLKSEL_Msk            (0x38000000UL)            /*!< PDMCLKSEL (Bitfield-Mask: 0x07)                       */
14158 #define PDM_VCFG_PDMCLKEN_Pos             (26UL)                    /*!< PDMCLKEN (Bit 26)                                     */
14159 #define PDM_VCFG_PDMCLKEN_Msk             (0x4000000UL)             /*!< PDMCLKEN (Bitfield-Mask: 0x01)                        */
14160 #define PDM_VCFG_I2SEN_Pos                (20UL)                    /*!< I2SEN (Bit 20)                                        */
14161 #define PDM_VCFG_I2SEN_Msk                (0x100000UL)              /*!< I2SEN (Bitfield-Mask: 0x01)                           */
14162 #define PDM_VCFG_BCLKINV_Pos              (19UL)                    /*!< BCLKINV (Bit 19)                                      */
14163 #define PDM_VCFG_BCLKINV_Msk              (0x80000UL)               /*!< BCLKINV (Bitfield-Mask: 0x01)                         */
14164 #define PDM_VCFG_DMICKDEL_Pos             (17UL)                    /*!< DMICKDEL (Bit 17)                                     */
14165 #define PDM_VCFG_DMICKDEL_Msk             (0x20000UL)               /*!< DMICKDEL (Bitfield-Mask: 0x01)                        */
14166 #define PDM_VCFG_SELAP_Pos                (16UL)                    /*!< SELAP (Bit 16)                                        */
14167 #define PDM_VCFG_SELAP_Msk                (0x10000UL)               /*!< SELAP (Bitfield-Mask: 0x01)                           */
14168 #define PDM_VCFG_PCMPACK_Pos              (8UL)                     /*!< PCMPACK (Bit 8)                                       */
14169 #define PDM_VCFG_PCMPACK_Msk              (0x100UL)                 /*!< PCMPACK (Bitfield-Mask: 0x01)                         */
14170 #define PDM_VCFG_CHSET_Pos                (3UL)                     /*!< CHSET (Bit 3)                                         */
14171 #define PDM_VCFG_CHSET_Msk                (0x18UL)                  /*!< CHSET (Bitfield-Mask: 0x03)                           */
14172 /* =======================================================  VOICESTAT  ======================================================= */
14173 #define PDM_VOICESTAT_FIFOCNT_Pos         (0UL)                     /*!< FIFOCNT (Bit 0)                                       */
14174 #define PDM_VOICESTAT_FIFOCNT_Msk         (0x3fUL)                  /*!< FIFOCNT (Bitfield-Mask: 0x3f)                         */
14175 /* =======================================================  FIFOREAD  ======================================================== */
14176 #define PDM_FIFOREAD_FIFOREAD_Pos         (0UL)                     /*!< FIFOREAD (Bit 0)                                      */
14177 #define PDM_FIFOREAD_FIFOREAD_Msk         (0xffffffffUL)            /*!< FIFOREAD (Bitfield-Mask: 0xffffffff)                  */
14178 /* =======================================================  FIFOFLUSH  ======================================================= */
14179 #define PDM_FIFOFLUSH_FIFOFLUSH_Pos       (0UL)                     /*!< FIFOFLUSH (Bit 0)                                     */
14180 #define PDM_FIFOFLUSH_FIFOFLUSH_Msk       (0x1UL)                   /*!< FIFOFLUSH (Bitfield-Mask: 0x01)                       */
14181 /* ========================================================  FIFOTHR  ======================================================== */
14182 #define PDM_FIFOTHR_FIFOTHR_Pos           (0UL)                     /*!< FIFOTHR (Bit 0)                                       */
14183 #define PDM_FIFOTHR_FIFOTHR_Msk           (0x1fUL)                  /*!< FIFOTHR (Bitfield-Mask: 0x1f)                         */
14184 /* =========================================================  INTEN  ========================================================= */
14185 #define PDM_INTEN_DERR_Pos                (4UL)                     /*!< DERR (Bit 4)                                          */
14186 #define PDM_INTEN_DERR_Msk                (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
14187 #define PDM_INTEN_DCMP_Pos                (3UL)                     /*!< DCMP (Bit 3)                                          */
14188 #define PDM_INTEN_DCMP_Msk                (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
14189 #define PDM_INTEN_UNDFL_Pos               (2UL)                     /*!< UNDFL (Bit 2)                                         */
14190 #define PDM_INTEN_UNDFL_Msk               (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
14191 #define PDM_INTEN_OVF_Pos                 (1UL)                     /*!< OVF (Bit 1)                                           */
14192 #define PDM_INTEN_OVF_Msk                 (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
14193 #define PDM_INTEN_THR_Pos                 (0UL)                     /*!< THR (Bit 0)                                           */
14194 #define PDM_INTEN_THR_Msk                 (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14195 /* ========================================================  INTSTAT  ======================================================== */
14196 #define PDM_INTSTAT_DERR_Pos              (4UL)                     /*!< DERR (Bit 4)                                          */
14197 #define PDM_INTSTAT_DERR_Msk              (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
14198 #define PDM_INTSTAT_DCMP_Pos              (3UL)                     /*!< DCMP (Bit 3)                                          */
14199 #define PDM_INTSTAT_DCMP_Msk              (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
14200 #define PDM_INTSTAT_UNDFL_Pos             (2UL)                     /*!< UNDFL (Bit 2)                                         */
14201 #define PDM_INTSTAT_UNDFL_Msk             (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
14202 #define PDM_INTSTAT_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
14203 #define PDM_INTSTAT_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
14204 #define PDM_INTSTAT_THR_Pos               (0UL)                     /*!< THR (Bit 0)                                           */
14205 #define PDM_INTSTAT_THR_Msk               (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14206 /* ========================================================  INTCLR  ========================================================= */
14207 #define PDM_INTCLR_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
14208 #define PDM_INTCLR_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
14209 #define PDM_INTCLR_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
14210 #define PDM_INTCLR_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
14211 #define PDM_INTCLR_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
14212 #define PDM_INTCLR_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
14213 #define PDM_INTCLR_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
14214 #define PDM_INTCLR_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
14215 #define PDM_INTCLR_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
14216 #define PDM_INTCLR_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14217 /* ========================================================  INTSET  ========================================================= */
14218 #define PDM_INTSET_DERR_Pos               (4UL)                     /*!< DERR (Bit 4)                                          */
14219 #define PDM_INTSET_DERR_Msk               (0x10UL)                  /*!< DERR (Bitfield-Mask: 0x01)                            */
14220 #define PDM_INTSET_DCMP_Pos               (3UL)                     /*!< DCMP (Bit 3)                                          */
14221 #define PDM_INTSET_DCMP_Msk               (0x8UL)                   /*!< DCMP (Bitfield-Mask: 0x01)                            */
14222 #define PDM_INTSET_UNDFL_Pos              (2UL)                     /*!< UNDFL (Bit 2)                                         */
14223 #define PDM_INTSET_UNDFL_Msk              (0x4UL)                   /*!< UNDFL (Bitfield-Mask: 0x01)                           */
14224 #define PDM_INTSET_OVF_Pos                (1UL)                     /*!< OVF (Bit 1)                                           */
14225 #define PDM_INTSET_OVF_Msk                (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
14226 #define PDM_INTSET_THR_Pos                (0UL)                     /*!< THR (Bit 0)                                           */
14227 #define PDM_INTSET_THR_Msk                (0x1UL)                   /*!< THR (Bitfield-Mask: 0x01)                             */
14228 /* =======================================================  DMATRIGEN  ======================================================= */
14229 #define PDM_DMATRIGEN_DTHR90_Pos          (1UL)                     /*!< DTHR90 (Bit 1)                                        */
14230 #define PDM_DMATRIGEN_DTHR90_Msk          (0x2UL)                   /*!< DTHR90 (Bitfield-Mask: 0x01)                          */
14231 #define PDM_DMATRIGEN_DTHR_Pos            (0UL)                     /*!< DTHR (Bit 0)                                          */
14232 #define PDM_DMATRIGEN_DTHR_Msk            (0x1UL)                   /*!< DTHR (Bitfield-Mask: 0x01)                            */
14233 /* ======================================================  DMATRIGSTAT  ====================================================== */
14234 #define PDM_DMATRIGSTAT_DTHR90STAT_Pos    (1UL)                     /*!< DTHR90STAT (Bit 1)                                    */
14235 #define PDM_DMATRIGSTAT_DTHR90STAT_Msk    (0x2UL)                   /*!< DTHR90STAT (Bitfield-Mask: 0x01)                      */
14236 #define PDM_DMATRIGSTAT_DTHRSTAT_Pos      (0UL)                     /*!< DTHRSTAT (Bit 0)                                      */
14237 #define PDM_DMATRIGSTAT_DTHRSTAT_Msk      (0x1UL)                   /*!< DTHRSTAT (Bitfield-Mask: 0x01)                        */
14238 /* ========================================================  DMACFG  ========================================================= */
14239 #define PDM_DMACFG_DPWROFF_Pos            (10UL)                    /*!< DPWROFF (Bit 10)                                      */
14240 #define PDM_DMACFG_DPWROFF_Msk            (0x400UL)                 /*!< DPWROFF (Bitfield-Mask: 0x01)                         */
14241 #define PDM_DMACFG_DAUTOHIP_Pos           (9UL)                     /*!< DAUTOHIP (Bit 9)                                      */
14242 #define PDM_DMACFG_DAUTOHIP_Msk           (0x200UL)                 /*!< DAUTOHIP (Bitfield-Mask: 0x01)                        */
14243 #define PDM_DMACFG_DMAPRI_Pos             (8UL)                     /*!< DMAPRI (Bit 8)                                        */
14244 #define PDM_DMACFG_DMAPRI_Msk             (0x100UL)                 /*!< DMAPRI (Bitfield-Mask: 0x01)                          */
14245 #define PDM_DMACFG_DMADIR_Pos             (2UL)                     /*!< DMADIR (Bit 2)                                        */
14246 #define PDM_DMACFG_DMADIR_Msk             (0x4UL)                   /*!< DMADIR (Bitfield-Mask: 0x01)                          */
14247 #define PDM_DMACFG_DMAEN_Pos              (0UL)                     /*!< DMAEN (Bit 0)                                         */
14248 #define PDM_DMACFG_DMAEN_Msk              (0x1UL)                   /*!< DMAEN (Bitfield-Mask: 0x01)                           */
14249 /* ======================================================  DMATOTCOUNT  ====================================================== */
14250 #define PDM_DMATOTCOUNT_TOTCOUNT_Pos      (0UL)                     /*!< TOTCOUNT (Bit 0)                                      */
14251 #define PDM_DMATOTCOUNT_TOTCOUNT_Msk      (0xfffffUL)               /*!< TOTCOUNT (Bitfield-Mask: 0xfffff)                     */
14252 /* ======================================================  DMATARGADDR  ====================================================== */
14253 #define PDM_DMATARGADDR_UTARGADDR_Pos     (20UL)                    /*!< UTARGADDR (Bit 20)                                    */
14254 #define PDM_DMATARGADDR_UTARGADDR_Msk     (0xfff00000UL)            /*!< UTARGADDR (Bitfield-Mask: 0xfff)                      */
14255 #define PDM_DMATARGADDR_LTARGADDR_Pos     (0UL)                     /*!< LTARGADDR (Bit 0)                                     */
14256 #define PDM_DMATARGADDR_LTARGADDR_Msk     (0xfffffUL)               /*!< LTARGADDR (Bitfield-Mask: 0xfffff)                    */
14257 /* ========================================================  DMASTAT  ======================================================== */
14258 #define PDM_DMASTAT_DMAERR_Pos            (2UL)                     /*!< DMAERR (Bit 2)                                        */
14259 #define PDM_DMASTAT_DMAERR_Msk            (0x4UL)                   /*!< DMAERR (Bitfield-Mask: 0x01)                          */
14260 #define PDM_DMASTAT_DMACPL_Pos            (1UL)                     /*!< DMACPL (Bit 1)                                        */
14261 #define PDM_DMASTAT_DMACPL_Msk            (0x2UL)                   /*!< DMACPL (Bitfield-Mask: 0x01)                          */
14262 #define PDM_DMASTAT_DMATIP_Pos            (0UL)                     /*!< DMATIP (Bit 0)                                        */
14263 #define PDM_DMASTAT_DMATIP_Msk            (0x1UL)                   /*!< DMATIP (Bitfield-Mask: 0x01)                          */
14264 
14265 
14266 /* =========================================================================================================================== */
14267 /* ================                                          PWRCTRL                                          ================ */
14268 /* =========================================================================================================================== */
14269 
14270 /* =======================================================  SUPPLYSRC  ======================================================= */
14271 #define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Pos   (0UL)                     /*!< BLEBUCKEN (Bit 0)                                     */
14272 #define PWRCTRL_SUPPLYSRC_BLEBUCKEN_Msk   (0x1UL)                   /*!< BLEBUCKEN (Bitfield-Mask: 0x01)                       */
14273 /* =====================================================  SUPPLYSTATUS  ====================================================== */
14274 #define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Pos (1UL)                    /*!< BLEBUCKON (Bit 1)                                     */
14275 #define PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Msk (0x2UL)                  /*!< BLEBUCKON (Bitfield-Mask: 0x01)                       */
14276 #define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Pos (0UL)                   /*!< SIMOBUCKON (Bit 0)                                    */
14277 #define PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Msk (0x1UL)                 /*!< SIMOBUCKON (Bitfield-Mask: 0x01)                      */
14278 /* =======================================================  DEVPWREN  ======================================================== */
14279 #define PWRCTRL_DEVPWREN_PWRBLEL_Pos      (13UL)                    /*!< PWRBLEL (Bit 13)                                      */
14280 #define PWRCTRL_DEVPWREN_PWRBLEL_Msk      (0x2000UL)                /*!< PWRBLEL (Bitfield-Mask: 0x01)                         */
14281 #define PWRCTRL_DEVPWREN_PWRPDM_Pos       (12UL)                    /*!< PWRPDM (Bit 12)                                       */
14282 #define PWRCTRL_DEVPWREN_PWRPDM_Msk       (0x1000UL)                /*!< PWRPDM (Bitfield-Mask: 0x01)                          */
14283 #define PWRCTRL_DEVPWREN_PWRMSPI_Pos      (11UL)                    /*!< PWRMSPI (Bit 11)                                      */
14284 #define PWRCTRL_DEVPWREN_PWRMSPI_Msk      (0x800UL)                 /*!< PWRMSPI (Bitfield-Mask: 0x01)                         */
14285 #define PWRCTRL_DEVPWREN_PWRSCARD_Pos     (10UL)                    /*!< PWRSCARD (Bit 10)                                     */
14286 #define PWRCTRL_DEVPWREN_PWRSCARD_Msk     (0x400UL)                 /*!< PWRSCARD (Bitfield-Mask: 0x01)                        */
14287 #define PWRCTRL_DEVPWREN_PWRADC_Pos       (9UL)                     /*!< PWRADC (Bit 9)                                        */
14288 #define PWRCTRL_DEVPWREN_PWRADC_Msk       (0x200UL)                 /*!< PWRADC (Bitfield-Mask: 0x01)                          */
14289 #define PWRCTRL_DEVPWREN_PWRUART1_Pos     (8UL)                     /*!< PWRUART1 (Bit 8)                                      */
14290 #define PWRCTRL_DEVPWREN_PWRUART1_Msk     (0x100UL)                 /*!< PWRUART1 (Bitfield-Mask: 0x01)                        */
14291 #define PWRCTRL_DEVPWREN_PWRUART0_Pos     (7UL)                     /*!< PWRUART0 (Bit 7)                                      */
14292 #define PWRCTRL_DEVPWREN_PWRUART0_Msk     (0x80UL)                  /*!< PWRUART0 (Bitfield-Mask: 0x01)                        */
14293 #define PWRCTRL_DEVPWREN_PWRIOM5_Pos      (6UL)                     /*!< PWRIOM5 (Bit 6)                                       */
14294 #define PWRCTRL_DEVPWREN_PWRIOM5_Msk      (0x40UL)                  /*!< PWRIOM5 (Bitfield-Mask: 0x01)                         */
14295 #define PWRCTRL_DEVPWREN_PWRIOM4_Pos      (5UL)                     /*!< PWRIOM4 (Bit 5)                                       */
14296 #define PWRCTRL_DEVPWREN_PWRIOM4_Msk      (0x20UL)                  /*!< PWRIOM4 (Bitfield-Mask: 0x01)                         */
14297 #define PWRCTRL_DEVPWREN_PWRIOM3_Pos      (4UL)                     /*!< PWRIOM3 (Bit 4)                                       */
14298 #define PWRCTRL_DEVPWREN_PWRIOM3_Msk      (0x10UL)                  /*!< PWRIOM3 (Bitfield-Mask: 0x01)                         */
14299 #define PWRCTRL_DEVPWREN_PWRIOM2_Pos      (3UL)                     /*!< PWRIOM2 (Bit 3)                                       */
14300 #define PWRCTRL_DEVPWREN_PWRIOM2_Msk      (0x8UL)                   /*!< PWRIOM2 (Bitfield-Mask: 0x01)                         */
14301 #define PWRCTRL_DEVPWREN_PWRIOM1_Pos      (2UL)                     /*!< PWRIOM1 (Bit 2)                                       */
14302 #define PWRCTRL_DEVPWREN_PWRIOM1_Msk      (0x4UL)                   /*!< PWRIOM1 (Bitfield-Mask: 0x01)                         */
14303 #define PWRCTRL_DEVPWREN_PWRIOM0_Pos      (1UL)                     /*!< PWRIOM0 (Bit 1)                                       */
14304 #define PWRCTRL_DEVPWREN_PWRIOM0_Msk      (0x2UL)                   /*!< PWRIOM0 (Bitfield-Mask: 0x01)                         */
14305 #define PWRCTRL_DEVPWREN_PWRIOS_Pos       (0UL)                     /*!< PWRIOS (Bit 0)                                        */
14306 #define PWRCTRL_DEVPWREN_PWRIOS_Msk       (0x1UL)                   /*!< PWRIOS (Bitfield-Mask: 0x01)                          */
14307 /* =====================================================  MEMPWDINSLEEP  ===================================================== */
14308 #define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Pos (31UL)                /*!< CACHEPWDSLP (Bit 31)                                  */
14309 #define PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Msk (0x80000000UL)        /*!< CACHEPWDSLP (Bitfield-Mask: 0x01)                     */
14310 #define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Pos (14UL)               /*!< FLASH1PWDSLP (Bit 14)                                 */
14311 #define PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Msk (0x4000UL)           /*!< FLASH1PWDSLP (Bitfield-Mask: 0x01)                    */
14312 #define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Pos (13UL)               /*!< FLASH0PWDSLP (Bit 13)                                 */
14313 #define PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Msk (0x2000UL)           /*!< FLASH0PWDSLP (Bitfield-Mask: 0x01)                    */
14314 #define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Pos (3UL)                  /*!< SRAMPWDSLP (Bit 3)                                    */
14315 #define PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Msk (0x1ff8UL)             /*!< SRAMPWDSLP (Bitfield-Mask: 0x3ff)                     */
14316 #define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Pos (0UL)                  /*!< DTCMPWDSLP (Bit 0)                                    */
14317 #define PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Msk (0x7UL)                /*!< DTCMPWDSLP (Bitfield-Mask: 0x07)                      */
14318 /* =======================================================  MEMPWREN  ======================================================== */
14319 #define PWRCTRL_MEMPWREN_CACHEB2_Pos      (31UL)                    /*!< CACHEB2 (Bit 31)                                      */
14320 #define PWRCTRL_MEMPWREN_CACHEB2_Msk      (0x80000000UL)            /*!< CACHEB2 (Bitfield-Mask: 0x01)                         */
14321 #define PWRCTRL_MEMPWREN_CACHEB0_Pos      (30UL)                    /*!< CACHEB0 (Bit 30)                                      */
14322 #define PWRCTRL_MEMPWREN_CACHEB0_Msk      (0x40000000UL)            /*!< CACHEB0 (Bitfield-Mask: 0x01)                         */
14323 #define PWRCTRL_MEMPWREN_FLASH1_Pos       (14UL)                    /*!< FLASH1 (Bit 14)                                       */
14324 #define PWRCTRL_MEMPWREN_FLASH1_Msk       (0x4000UL)                /*!< FLASH1 (Bitfield-Mask: 0x01)                          */
14325 #define PWRCTRL_MEMPWREN_FLASH0_Pos       (13UL)                    /*!< FLASH0 (Bit 13)                                       */
14326 #define PWRCTRL_MEMPWREN_FLASH0_Msk       (0x2000UL)                /*!< FLASH0 (Bitfield-Mask: 0x01)                          */
14327 #define PWRCTRL_MEMPWREN_SRAM_Pos         (3UL)                     /*!< SRAM (Bit 3)                                          */
14328 #define PWRCTRL_MEMPWREN_SRAM_Msk         (0x1ff8UL)                /*!< SRAM (Bitfield-Mask: 0x3ff)                           */
14329 #define PWRCTRL_MEMPWREN_DTCM_Pos         (0UL)                     /*!< DTCM (Bit 0)                                          */
14330 #define PWRCTRL_MEMPWREN_DTCM_Msk         (0x7UL)                   /*!< DTCM (Bitfield-Mask: 0x07)                            */
14331 /* =====================================================  MEMPWRSTATUS  ====================================================== */
14332 #define PWRCTRL_MEMPWRSTATUS_CACHEB2_Pos  (16UL)                    /*!< CACHEB2 (Bit 16)                                      */
14333 #define PWRCTRL_MEMPWRSTATUS_CACHEB2_Msk  (0x10000UL)               /*!< CACHEB2 (Bitfield-Mask: 0x01)                         */
14334 #define PWRCTRL_MEMPWRSTATUS_CACHEB0_Pos  (15UL)                    /*!< CACHEB0 (Bit 15)                                      */
14335 #define PWRCTRL_MEMPWRSTATUS_CACHEB0_Msk  (0x8000UL)                /*!< CACHEB0 (Bitfield-Mask: 0x01)                         */
14336 #define PWRCTRL_MEMPWRSTATUS_FLASH1_Pos   (14UL)                    /*!< FLASH1 (Bit 14)                                       */
14337 #define PWRCTRL_MEMPWRSTATUS_FLASH1_Msk   (0x4000UL)                /*!< FLASH1 (Bitfield-Mask: 0x01)                          */
14338 #define PWRCTRL_MEMPWRSTATUS_FLASH0_Pos   (13UL)                    /*!< FLASH0 (Bit 13)                                       */
14339 #define PWRCTRL_MEMPWRSTATUS_FLASH0_Msk   (0x2000UL)                /*!< FLASH0 (Bitfield-Mask: 0x01)                          */
14340 #define PWRCTRL_MEMPWRSTATUS_SRAM9_Pos    (12UL)                    /*!< SRAM9 (Bit 12)                                        */
14341 #define PWRCTRL_MEMPWRSTATUS_SRAM9_Msk    (0x1000UL)                /*!< SRAM9 (Bitfield-Mask: 0x01)                           */
14342 #define PWRCTRL_MEMPWRSTATUS_SRAM8_Pos    (11UL)                    /*!< SRAM8 (Bit 11)                                        */
14343 #define PWRCTRL_MEMPWRSTATUS_SRAM8_Msk    (0x800UL)                 /*!< SRAM8 (Bitfield-Mask: 0x01)                           */
14344 #define PWRCTRL_MEMPWRSTATUS_SRAM7_Pos    (10UL)                    /*!< SRAM7 (Bit 10)                                        */
14345 #define PWRCTRL_MEMPWRSTATUS_SRAM7_Msk    (0x400UL)                 /*!< SRAM7 (Bitfield-Mask: 0x01)                           */
14346 #define PWRCTRL_MEMPWRSTATUS_SRAM6_Pos    (9UL)                     /*!< SRAM6 (Bit 9)                                         */
14347 #define PWRCTRL_MEMPWRSTATUS_SRAM6_Msk    (0x200UL)                 /*!< SRAM6 (Bitfield-Mask: 0x01)                           */
14348 #define PWRCTRL_MEMPWRSTATUS_SRAM5_Pos    (8UL)                     /*!< SRAM5 (Bit 8)                                         */
14349 #define PWRCTRL_MEMPWRSTATUS_SRAM5_Msk    (0x100UL)                 /*!< SRAM5 (Bitfield-Mask: 0x01)                           */
14350 #define PWRCTRL_MEMPWRSTATUS_SRAM4_Pos    (7UL)                     /*!< SRAM4 (Bit 7)                                         */
14351 #define PWRCTRL_MEMPWRSTATUS_SRAM4_Msk    (0x80UL)                  /*!< SRAM4 (Bitfield-Mask: 0x01)                           */
14352 #define PWRCTRL_MEMPWRSTATUS_SRAM3_Pos    (6UL)                     /*!< SRAM3 (Bit 6)                                         */
14353 #define PWRCTRL_MEMPWRSTATUS_SRAM3_Msk    (0x40UL)                  /*!< SRAM3 (Bitfield-Mask: 0x01)                           */
14354 #define PWRCTRL_MEMPWRSTATUS_SRAM2_Pos    (5UL)                     /*!< SRAM2 (Bit 5)                                         */
14355 #define PWRCTRL_MEMPWRSTATUS_SRAM2_Msk    (0x20UL)                  /*!< SRAM2 (Bitfield-Mask: 0x01)                           */
14356 #define PWRCTRL_MEMPWRSTATUS_SRAM1_Pos    (4UL)                     /*!< SRAM1 (Bit 4)                                         */
14357 #define PWRCTRL_MEMPWRSTATUS_SRAM1_Msk    (0x10UL)                  /*!< SRAM1 (Bitfield-Mask: 0x01)                           */
14358 #define PWRCTRL_MEMPWRSTATUS_SRAM0_Pos    (3UL)                     /*!< SRAM0 (Bit 3)                                         */
14359 #define PWRCTRL_MEMPWRSTATUS_SRAM0_Msk    (0x8UL)                   /*!< SRAM0 (Bitfield-Mask: 0x01)                           */
14360 #define PWRCTRL_MEMPWRSTATUS_DTCM1_Pos    (2UL)                     /*!< DTCM1 (Bit 2)                                         */
14361 #define PWRCTRL_MEMPWRSTATUS_DTCM1_Msk    (0x4UL)                   /*!< DTCM1 (Bitfield-Mask: 0x01)                           */
14362 #define PWRCTRL_MEMPWRSTATUS_DTCM01_Pos   (1UL)                     /*!< DTCM01 (Bit 1)                                        */
14363 #define PWRCTRL_MEMPWRSTATUS_DTCM01_Msk   (0x2UL)                   /*!< DTCM01 (Bitfield-Mask: 0x01)                          */
14364 #define PWRCTRL_MEMPWRSTATUS_DTCM00_Pos   (0UL)                     /*!< DTCM00 (Bit 0)                                        */
14365 #define PWRCTRL_MEMPWRSTATUS_DTCM00_Msk   (0x1UL)                   /*!< DTCM00 (Bitfield-Mask: 0x01)                          */
14366 /* =====================================================  DEVPWRSTATUS  ====================================================== */
14367 #define PWRCTRL_DEVPWRSTATUS_BLEH_Pos     (9UL)                     /*!< BLEH (Bit 9)                                          */
14368 #define PWRCTRL_DEVPWRSTATUS_BLEH_Msk     (0x200UL)                 /*!< BLEH (Bitfield-Mask: 0x01)                            */
14369 #define PWRCTRL_DEVPWRSTATUS_BLEL_Pos     (8UL)                     /*!< BLEL (Bit 8)                                          */
14370 #define PWRCTRL_DEVPWRSTATUS_BLEL_Msk     (0x100UL)                 /*!< BLEL (Bitfield-Mask: 0x01)                            */
14371 #define PWRCTRL_DEVPWRSTATUS_PWRPDM_Pos   (7UL)                     /*!< PWRPDM (Bit 7)                                        */
14372 #define PWRCTRL_DEVPWRSTATUS_PWRPDM_Msk   (0x80UL)                  /*!< PWRPDM (Bitfield-Mask: 0x01)                          */
14373 #define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Pos  (6UL)                     /*!< PWRMSPI (Bit 6)                                       */
14374 #define PWRCTRL_DEVPWRSTATUS_PWRMSPI_Msk  (0x40UL)                  /*!< PWRMSPI (Bitfield-Mask: 0x01)                         */
14375 #define PWRCTRL_DEVPWRSTATUS_PWRADC_Pos   (5UL)                     /*!< PWRADC (Bit 5)                                        */
14376 #define PWRCTRL_DEVPWRSTATUS_PWRADC_Msk   (0x20UL)                  /*!< PWRADC (Bitfield-Mask: 0x01)                          */
14377 #define PWRCTRL_DEVPWRSTATUS_HCPC_Pos     (4UL)                     /*!< HCPC (Bit 4)                                          */
14378 #define PWRCTRL_DEVPWRSTATUS_HCPC_Msk     (0x10UL)                  /*!< HCPC (Bitfield-Mask: 0x01)                            */
14379 #define PWRCTRL_DEVPWRSTATUS_HCPB_Pos     (3UL)                     /*!< HCPB (Bit 3)                                          */
14380 #define PWRCTRL_DEVPWRSTATUS_HCPB_Msk     (0x8UL)                   /*!< HCPB (Bitfield-Mask: 0x01)                            */
14381 #define PWRCTRL_DEVPWRSTATUS_HCPA_Pos     (2UL)                     /*!< HCPA (Bit 2)                                          */
14382 #define PWRCTRL_DEVPWRSTATUS_HCPA_Msk     (0x4UL)                   /*!< HCPA (Bitfield-Mask: 0x01)                            */
14383 #define PWRCTRL_DEVPWRSTATUS_MCUH_Pos     (1UL)                     /*!< MCUH (Bit 1)                                          */
14384 #define PWRCTRL_DEVPWRSTATUS_MCUH_Msk     (0x2UL)                   /*!< MCUH (Bitfield-Mask: 0x01)                            */
14385 #define PWRCTRL_DEVPWRSTATUS_MCUL_Pos     (0UL)                     /*!< MCUL (Bit 0)                                          */
14386 #define PWRCTRL_DEVPWRSTATUS_MCUL_Msk     (0x1UL)                   /*!< MCUL (Bitfield-Mask: 0x01)                            */
14387 /* =======================================================  SRAMCTRL  ======================================================== */
14388 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Pos (8UL)                   /*!< SRAMLIGHTSLEEP (Bit 8)                                */
14389 #define PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Msk (0xfff00UL)             /*!< SRAMLIGHTSLEEP (Bitfield-Mask: 0xfff)                 */
14390 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Pos (2UL)                /*!< SRAMMASTERCLKGATE (Bit 2)                             */
14391 #define PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Msk (0x4UL)              /*!< SRAMMASTERCLKGATE (Bitfield-Mask: 0x01)               */
14392 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Pos  (1UL)                     /*!< SRAMCLKGATE (Bit 1)                                   */
14393 #define PWRCTRL_SRAMCTRL_SRAMCLKGATE_Msk  (0x2UL)                   /*!< SRAMCLKGATE (Bitfield-Mask: 0x01)                     */
14394 /* =======================================================  ADCSTATUS  ======================================================= */
14395 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Pos   (5UL)                     /*!< REFBUFPWD (Bit 5)                                     */
14396 #define PWRCTRL_ADCSTATUS_REFBUFPWD_Msk   (0x20UL)                  /*!< REFBUFPWD (Bitfield-Mask: 0x01)                       */
14397 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Pos  (4UL)                     /*!< REFKEEPPWD (Bit 4)                                    */
14398 #define PWRCTRL_ADCSTATUS_REFKEEPPWD_Msk  (0x10UL)                  /*!< REFKEEPPWD (Bitfield-Mask: 0x01)                      */
14399 #define PWRCTRL_ADCSTATUS_VBATPWD_Pos     (3UL)                     /*!< VBATPWD (Bit 3)                                       */
14400 #define PWRCTRL_ADCSTATUS_VBATPWD_Msk     (0x8UL)                   /*!< VBATPWD (Bitfield-Mask: 0x01)                         */
14401 #define PWRCTRL_ADCSTATUS_VPTATPWD_Pos    (2UL)                     /*!< VPTATPWD (Bit 2)                                      */
14402 #define PWRCTRL_ADCSTATUS_VPTATPWD_Msk    (0x4UL)                   /*!< VPTATPWD (Bitfield-Mask: 0x01)                        */
14403 #define PWRCTRL_ADCSTATUS_BGTPWD_Pos      (1UL)                     /*!< BGTPWD (Bit 1)                                        */
14404 #define PWRCTRL_ADCSTATUS_BGTPWD_Msk      (0x2UL)                   /*!< BGTPWD (Bitfield-Mask: 0x01)                          */
14405 #define PWRCTRL_ADCSTATUS_ADCPWD_Pos      (0UL)                     /*!< ADCPWD (Bit 0)                                        */
14406 #define PWRCTRL_ADCSTATUS_ADCPWD_Msk      (0x1UL)                   /*!< ADCPWD (Bitfield-Mask: 0x01)                          */
14407 /* =========================================================  MISC  ========================================================== */
14408 #define PWRCTRL_MISC_MEMVRLPBLE_Pos       (6UL)                     /*!< MEMVRLPBLE (Bit 6)                                    */
14409 #define PWRCTRL_MISC_MEMVRLPBLE_Msk       (0x40UL)                  /*!< MEMVRLPBLE (Bitfield-Mask: 0x01)                      */
14410 #define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Pos (3UL)                   /*!< FORCEMEMVRLPTIMERS (Bit 3)                            */
14411 #define PWRCTRL_MISC_FORCEMEMVRLPTIMERS_Msk (0x8UL)                 /*!< FORCEMEMVRLPTIMERS (Bitfield-Mask: 0x01)              */
14412 /* =====================================================  DEVPWREVENTEN  ===================================================== */
14413 #define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Pos (31UL)                  /*!< BURSTEVEN (Bit 31)                                    */
14414 #define PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Msk (0x80000000UL)          /*!< BURSTEVEN (Bitfield-Mask: 0x01)                       */
14415 #define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Pos (30UL)           /*!< BURSTFEATUREEVEN (Bit 30)                             */
14416 #define PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Msk (0x40000000UL)   /*!< BURSTFEATUREEVEN (Bitfield-Mask: 0x01)                */
14417 #define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Pos (29UL)             /*!< BLEFEATUREEVEN (Bit 29)                               */
14418 #define PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Msk (0x20000000UL)     /*!< BLEFEATUREEVEN (Bitfield-Mask: 0x01)                  */
14419 #define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Pos (8UL)                    /*!< BLELEVEN (Bit 8)                                      */
14420 #define PWRCTRL_DEVPWREVENTEN_BLELEVEN_Msk (0x100UL)                /*!< BLELEVEN (Bitfield-Mask: 0x01)                        */
14421 #define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Pos (7UL)                     /*!< PDMEVEN (Bit 7)                                       */
14422 #define PWRCTRL_DEVPWREVENTEN_PDMEVEN_Msk (0x80UL)                  /*!< PDMEVEN (Bitfield-Mask: 0x01)                         */
14423 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Pos (6UL)                    /*!< MSPIEVEN (Bit 6)                                      */
14424 #define PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Msk (0x40UL)                 /*!< MSPIEVEN (Bitfield-Mask: 0x01)                        */
14425 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Pos (5UL)                     /*!< ADCEVEN (Bit 5)                                       */
14426 #define PWRCTRL_DEVPWREVENTEN_ADCEVEN_Msk (0x20UL)                  /*!< ADCEVEN (Bitfield-Mask: 0x01)                         */
14427 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Pos (4UL)                    /*!< HCPCEVEN (Bit 4)                                      */
14428 #define PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Msk (0x10UL)                 /*!< HCPCEVEN (Bitfield-Mask: 0x01)                        */
14429 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Pos (3UL)                    /*!< HCPBEVEN (Bit 3)                                      */
14430 #define PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Msk (0x8UL)                  /*!< HCPBEVEN (Bitfield-Mask: 0x01)                        */
14431 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Pos (2UL)                    /*!< HCPAEVEN (Bit 2)                                      */
14432 #define PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Msk (0x4UL)                  /*!< HCPAEVEN (Bitfield-Mask: 0x01)                        */
14433 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Pos (1UL)                    /*!< MCUHEVEN (Bit 1)                                      */
14434 #define PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Msk (0x2UL)                  /*!< MCUHEVEN (Bitfield-Mask: 0x01)                        */
14435 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Pos (0UL)                    /*!< MCULEVEN (Bit 0)                                      */
14436 #define PWRCTRL_DEVPWREVENTEN_MCULEVEN_Msk (0x1UL)                  /*!< MCULEVEN (Bitfield-Mask: 0x01)                        */
14437 /* =====================================================  MEMPWREVENTEN  ===================================================== */
14438 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Pos (31UL)                  /*!< CACHEB2EN (Bit 31)                                    */
14439 #define PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Msk (0x80000000UL)          /*!< CACHEB2EN (Bitfield-Mask: 0x01)                       */
14440 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Pos (30UL)                  /*!< CACHEB0EN (Bit 30)                                    */
14441 #define PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Msk (0x40000000UL)          /*!< CACHEB0EN (Bitfield-Mask: 0x01)                       */
14442 #define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Pos (14UL)                   /*!< FLASH1EN (Bit 14)                                     */
14443 #define PWRCTRL_MEMPWREVENTEN_FLASH1EN_Msk (0x4000UL)               /*!< FLASH1EN (Bitfield-Mask: 0x01)                        */
14444 #define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Pos (13UL)                   /*!< FLASH0EN (Bit 13)                                     */
14445 #define PWRCTRL_MEMPWREVENTEN_FLASH0EN_Msk (0x2000UL)               /*!< FLASH0EN (Bitfield-Mask: 0x01)                        */
14446 #define PWRCTRL_MEMPWREVENTEN_SRAMEN_Pos  (3UL)                     /*!< SRAMEN (Bit 3)                                        */
14447 #define PWRCTRL_MEMPWREVENTEN_SRAMEN_Msk  (0x1ff8UL)                /*!< SRAMEN (Bitfield-Mask: 0x3ff)                         */
14448 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Pos  (0UL)                     /*!< DTCMEN (Bit 0)                                        */
14449 #define PWRCTRL_MEMPWREVENTEN_DTCMEN_Msk  (0x7UL)                   /*!< DTCMEN (Bitfield-Mask: 0x07)                          */
14450 
14451 
14452 /* =========================================================================================================================== */
14453 /* ================                                          RSTGEN                                           ================ */
14454 /* =========================================================================================================================== */
14455 
14456 /* ==========================================================  CFG  ========================================================== */
14457 #define RSTGEN_CFG_WDREN_Pos              (1UL)                     /*!< WDREN (Bit 1)                                         */
14458 #define RSTGEN_CFG_WDREN_Msk              (0x2UL)                   /*!< WDREN (Bitfield-Mask: 0x01)                           */
14459 #define RSTGEN_CFG_BODHREN_Pos            (0UL)                     /*!< BODHREN (Bit 0)                                       */
14460 #define RSTGEN_CFG_BODHREN_Msk            (0x1UL)                   /*!< BODHREN (Bitfield-Mask: 0x01)                         */
14461 /* =========================================================  SWPOI  ========================================================= */
14462 #define RSTGEN_SWPOI_SWPOIKEY_Pos         (0UL)                     /*!< SWPOIKEY (Bit 0)                                      */
14463 #define RSTGEN_SWPOI_SWPOIKEY_Msk         (0xffUL)                  /*!< SWPOIKEY (Bitfield-Mask: 0xff)                        */
14464 /* =========================================================  SWPOR  ========================================================= */
14465 #define RSTGEN_SWPOR_SWPORKEY_Pos         (0UL)                     /*!< SWPORKEY (Bit 0)                                      */
14466 #define RSTGEN_SWPOR_SWPORKEY_Msk         (0xffUL)                  /*!< SWPORKEY (Bitfield-Mask: 0xff)                        */
14467 /* ========================================================  TPIURST  ======================================================== */
14468 #define RSTGEN_TPIURST_TPIURST_Pos        (0UL)                     /*!< TPIURST (Bit 0)                                       */
14469 #define RSTGEN_TPIURST_TPIURST_Msk        (0x1UL)                   /*!< TPIURST (Bitfield-Mask: 0x01)                         */
14470 /* =========================================================  INTEN  ========================================================= */
14471 #define RSTGEN_INTEN_BODH_Pos             (0UL)                     /*!< BODH (Bit 0)                                          */
14472 #define RSTGEN_INTEN_BODH_Msk             (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
14473 /* ========================================================  INTSTAT  ======================================================== */
14474 #define RSTGEN_INTSTAT_BODH_Pos           (0UL)                     /*!< BODH (Bit 0)                                          */
14475 #define RSTGEN_INTSTAT_BODH_Msk           (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
14476 /* ========================================================  INTCLR  ========================================================= */
14477 #define RSTGEN_INTCLR_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
14478 #define RSTGEN_INTCLR_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
14479 /* ========================================================  INTSET  ========================================================= */
14480 #define RSTGEN_INTSET_BODH_Pos            (0UL)                     /*!< BODH (Bit 0)                                          */
14481 #define RSTGEN_INTSET_BODH_Msk            (0x1UL)                   /*!< BODH (Bitfield-Mask: 0x01)                            */
14482 /* =========================================================  STAT  ========================================================== */
14483 #define RSTGEN_STAT_SBOOT_Pos             (31UL)                    /*!< SBOOT (Bit 31)                                        */
14484 #define RSTGEN_STAT_SBOOT_Msk             (0x80000000UL)            /*!< SBOOT (Bitfield-Mask: 0x01)                           */
14485 #define RSTGEN_STAT_FBOOT_Pos             (30UL)                    /*!< FBOOT (Bit 30)                                        */
14486 #define RSTGEN_STAT_FBOOT_Msk             (0x40000000UL)            /*!< FBOOT (Bitfield-Mask: 0x01)                           */
14487 #define RSTGEN_STAT_BOBSTAT_Pos           (10UL)                    /*!< BOBSTAT (Bit 10)                                      */
14488 #define RSTGEN_STAT_BOBSTAT_Msk           (0x400UL)                 /*!< BOBSTAT (Bitfield-Mask: 0x01)                         */
14489 #define RSTGEN_STAT_BOFSTAT_Pos           (9UL)                     /*!< BOFSTAT (Bit 9)                                       */
14490 #define RSTGEN_STAT_BOFSTAT_Msk           (0x200UL)                 /*!< BOFSTAT (Bitfield-Mask: 0x01)                         */
14491 #define RSTGEN_STAT_BOCSTAT_Pos           (8UL)                     /*!< BOCSTAT (Bit 8)                                       */
14492 #define RSTGEN_STAT_BOCSTAT_Msk           (0x100UL)                 /*!< BOCSTAT (Bitfield-Mask: 0x01)                         */
14493 #define RSTGEN_STAT_BOUSTAT_Pos           (7UL)                     /*!< BOUSTAT (Bit 7)                                       */
14494 #define RSTGEN_STAT_BOUSTAT_Msk           (0x80UL)                  /*!< BOUSTAT (Bitfield-Mask: 0x01)                         */
14495 #define RSTGEN_STAT_WDRSTAT_Pos           (6UL)                     /*!< WDRSTAT (Bit 6)                                       */
14496 #define RSTGEN_STAT_WDRSTAT_Msk           (0x40UL)                  /*!< WDRSTAT (Bitfield-Mask: 0x01)                         */
14497 #define RSTGEN_STAT_DBGRSTAT_Pos          (5UL)                     /*!< DBGRSTAT (Bit 5)                                      */
14498 #define RSTGEN_STAT_DBGRSTAT_Msk          (0x20UL)                  /*!< DBGRSTAT (Bitfield-Mask: 0x01)                        */
14499 #define RSTGEN_STAT_POIRSTAT_Pos          (4UL)                     /*!< POIRSTAT (Bit 4)                                      */
14500 #define RSTGEN_STAT_POIRSTAT_Msk          (0x10UL)                  /*!< POIRSTAT (Bitfield-Mask: 0x01)                        */
14501 #define RSTGEN_STAT_SWRSTAT_Pos           (3UL)                     /*!< SWRSTAT (Bit 3)                                       */
14502 #define RSTGEN_STAT_SWRSTAT_Msk           (0x8UL)                   /*!< SWRSTAT (Bitfield-Mask: 0x01)                         */
14503 #define RSTGEN_STAT_BORSTAT_Pos           (2UL)                     /*!< BORSTAT (Bit 2)                                       */
14504 #define RSTGEN_STAT_BORSTAT_Msk           (0x4UL)                   /*!< BORSTAT (Bitfield-Mask: 0x01)                         */
14505 #define RSTGEN_STAT_PORSTAT_Pos           (1UL)                     /*!< PORSTAT (Bit 1)                                       */
14506 #define RSTGEN_STAT_PORSTAT_Msk           (0x2UL)                   /*!< PORSTAT (Bitfield-Mask: 0x01)                         */
14507 #define RSTGEN_STAT_EXRSTAT_Pos           (0UL)                     /*!< EXRSTAT (Bit 0)                                       */
14508 #define RSTGEN_STAT_EXRSTAT_Msk           (0x1UL)                   /*!< EXRSTAT (Bitfield-Mask: 0x01)                         */
14509 
14510 
14511 /* =========================================================================================================================== */
14512 /* ================                                            RTC                                            ================ */
14513 /* =========================================================================================================================== */
14514 
14515 /* ========================================================  CTRLOW  ========================================================= */
14516 #define RTC_CTRLOW_CTRHR_Pos              (24UL)                    /*!< CTRHR (Bit 24)                                        */
14517 #define RTC_CTRLOW_CTRHR_Msk              (0x3f000000UL)            /*!< CTRHR (Bitfield-Mask: 0x3f)                           */
14518 #define RTC_CTRLOW_CTRMIN_Pos             (16UL)                    /*!< CTRMIN (Bit 16)                                       */
14519 #define RTC_CTRLOW_CTRMIN_Msk             (0x7f0000UL)              /*!< CTRMIN (Bitfield-Mask: 0x7f)                          */
14520 #define RTC_CTRLOW_CTRSEC_Pos             (8UL)                     /*!< CTRSEC (Bit 8)                                        */
14521 #define RTC_CTRLOW_CTRSEC_Msk             (0x7f00UL)                /*!< CTRSEC (Bitfield-Mask: 0x7f)                          */
14522 #define RTC_CTRLOW_CTR100_Pos             (0UL)                     /*!< CTR100 (Bit 0)                                        */
14523 #define RTC_CTRLOW_CTR100_Msk             (0xffUL)                  /*!< CTR100 (Bitfield-Mask: 0xff)                          */
14524 /* =========================================================  CTRUP  ========================================================= */
14525 #define RTC_CTRUP_CTERR_Pos               (31UL)                    /*!< CTERR (Bit 31)                                        */
14526 #define RTC_CTRUP_CTERR_Msk               (0x80000000UL)            /*!< CTERR (Bitfield-Mask: 0x01)                           */
14527 #define RTC_CTRUP_CEB_Pos                 (28UL)                    /*!< CEB (Bit 28)                                          */
14528 #define RTC_CTRUP_CEB_Msk                 (0x10000000UL)            /*!< CEB (Bitfield-Mask: 0x01)                             */
14529 #define RTC_CTRUP_CB_Pos                  (27UL)                    /*!< CB (Bit 27)                                           */
14530 #define RTC_CTRUP_CB_Msk                  (0x8000000UL)             /*!< CB (Bitfield-Mask: 0x01)                              */
14531 #define RTC_CTRUP_CTRWKDY_Pos             (24UL)                    /*!< CTRWKDY (Bit 24)                                      */
14532 #define RTC_CTRUP_CTRWKDY_Msk             (0x7000000UL)             /*!< CTRWKDY (Bitfield-Mask: 0x07)                         */
14533 #define RTC_CTRUP_CTRYR_Pos               (16UL)                    /*!< CTRYR (Bit 16)                                        */
14534 #define RTC_CTRUP_CTRYR_Msk               (0xff0000UL)              /*!< CTRYR (Bitfield-Mask: 0xff)                           */
14535 #define RTC_CTRUP_CTRMO_Pos               (8UL)                     /*!< CTRMO (Bit 8)                                         */
14536 #define RTC_CTRUP_CTRMO_Msk               (0x1f00UL)                /*!< CTRMO (Bitfield-Mask: 0x1f)                           */
14537 #define RTC_CTRUP_CTRDATE_Pos             (0UL)                     /*!< CTRDATE (Bit 0)                                       */
14538 #define RTC_CTRUP_CTRDATE_Msk             (0x3fUL)                  /*!< CTRDATE (Bitfield-Mask: 0x3f)                         */
14539 /* ========================================================  ALMLOW  ========================================================= */
14540 #define RTC_ALMLOW_ALMHR_Pos              (24UL)                    /*!< ALMHR (Bit 24)                                        */
14541 #define RTC_ALMLOW_ALMHR_Msk              (0x3f000000UL)            /*!< ALMHR (Bitfield-Mask: 0x3f)                           */
14542 #define RTC_ALMLOW_ALMMIN_Pos             (16UL)                    /*!< ALMMIN (Bit 16)                                       */
14543 #define RTC_ALMLOW_ALMMIN_Msk             (0x7f0000UL)              /*!< ALMMIN (Bitfield-Mask: 0x7f)                          */
14544 #define RTC_ALMLOW_ALMSEC_Pos             (8UL)                     /*!< ALMSEC (Bit 8)                                        */
14545 #define RTC_ALMLOW_ALMSEC_Msk             (0x7f00UL)                /*!< ALMSEC (Bitfield-Mask: 0x7f)                          */
14546 #define RTC_ALMLOW_ALM100_Pos             (0UL)                     /*!< ALM100 (Bit 0)                                        */
14547 #define RTC_ALMLOW_ALM100_Msk             (0xffUL)                  /*!< ALM100 (Bitfield-Mask: 0xff)                          */
14548 /* =========================================================  ALMUP  ========================================================= */
14549 #define RTC_ALMUP_ALMWKDY_Pos             (16UL)                    /*!< ALMWKDY (Bit 16)                                      */
14550 #define RTC_ALMUP_ALMWKDY_Msk             (0x70000UL)               /*!< ALMWKDY (Bitfield-Mask: 0x07)                         */
14551 #define RTC_ALMUP_ALMMO_Pos               (8UL)                     /*!< ALMMO (Bit 8)                                         */
14552 #define RTC_ALMUP_ALMMO_Msk               (0x1f00UL)                /*!< ALMMO (Bitfield-Mask: 0x1f)                           */
14553 #define RTC_ALMUP_ALMDATE_Pos             (0UL)                     /*!< ALMDATE (Bit 0)                                       */
14554 #define RTC_ALMUP_ALMDATE_Msk             (0x3fUL)                  /*!< ALMDATE (Bitfield-Mask: 0x3f)                         */
14555 /* ========================================================  RTCCTL  ========================================================= */
14556 #define RTC_RTCCTL_HR1224_Pos             (5UL)                     /*!< HR1224 (Bit 5)                                        */
14557 #define RTC_RTCCTL_HR1224_Msk             (0x20UL)                  /*!< HR1224 (Bitfield-Mask: 0x01)                          */
14558 #define RTC_RTCCTL_RSTOP_Pos              (4UL)                     /*!< RSTOP (Bit 4)                                         */
14559 #define RTC_RTCCTL_RSTOP_Msk              (0x10UL)                  /*!< RSTOP (Bitfield-Mask: 0x01)                           */
14560 #define RTC_RTCCTL_RPT_Pos                (1UL)                     /*!< RPT (Bit 1)                                           */
14561 #define RTC_RTCCTL_RPT_Msk                (0xeUL)                   /*!< RPT (Bitfield-Mask: 0x07)                             */
14562 #define RTC_RTCCTL_WRTC_Pos               (0UL)                     /*!< WRTC (Bit 0)                                          */
14563 #define RTC_RTCCTL_WRTC_Msk               (0x1UL)                   /*!< WRTC (Bitfield-Mask: 0x01)                            */
14564 /* =========================================================  INTEN  ========================================================= */
14565 #define RTC_INTEN_ALM_Pos                 (0UL)                     /*!< ALM (Bit 0)                                           */
14566 #define RTC_INTEN_ALM_Msk                 (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
14567 /* ========================================================  INTSTAT  ======================================================== */
14568 #define RTC_INTSTAT_ALM_Pos               (0UL)                     /*!< ALM (Bit 0)                                           */
14569 #define RTC_INTSTAT_ALM_Msk               (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
14570 /* ========================================================  INTCLR  ========================================================= */
14571 #define RTC_INTCLR_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
14572 #define RTC_INTCLR_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
14573 /* ========================================================  INTSET  ========================================================= */
14574 #define RTC_INTSET_ALM_Pos                (0UL)                     /*!< ALM (Bit 0)                                           */
14575 #define RTC_INTSET_ALM_Msk                (0x1UL)                   /*!< ALM (Bitfield-Mask: 0x01)                             */
14576 
14577 
14578 /* =========================================================================================================================== */
14579 /* ================                                           SCARD                                           ================ */
14580 /* =========================================================================================================================== */
14581 
14582 /* ==========================================================  SR  =========================================================== */
14583 #define SCARD_SR_FHF_Pos                  (6UL)                     /*!< FHF (Bit 6)                                           */
14584 #define SCARD_SR_FHF_Msk                  (0x40UL)                  /*!< FHF (Bitfield-Mask: 0x01)                             */
14585 #define SCARD_SR_FT2REND_Pos              (5UL)                     /*!< FT2REND (Bit 5)                                       */
14586 #define SCARD_SR_FT2REND_Msk              (0x20UL)                  /*!< FT2REND (Bitfield-Mask: 0x01)                         */
14587 #define SCARD_SR_PE_Pos                   (4UL)                     /*!< PE (Bit 4)                                            */
14588 #define SCARD_SR_PE_Msk                   (0x10UL)                  /*!< PE (Bitfield-Mask: 0x01)                              */
14589 #define SCARD_SR_OVR_Pos                  (3UL)                     /*!< OVR (Bit 3)                                           */
14590 #define SCARD_SR_OVR_Msk                  (0x8UL)                   /*!< OVR (Bitfield-Mask: 0x01)                             */
14591 #define SCARD_SR_FER_Pos                  (2UL)                     /*!< FER (Bit 2)                                           */
14592 #define SCARD_SR_FER_Msk                  (0x4UL)                   /*!< FER (Bitfield-Mask: 0x01)                             */
14593 #define SCARD_SR_TBERBF_Pos               (1UL)                     /*!< TBERBF (Bit 1)                                        */
14594 #define SCARD_SR_TBERBF_Msk               (0x2UL)                   /*!< TBERBF (Bitfield-Mask: 0x01)                          */
14595 #define SCARD_SR_FNE_Pos                  (0UL)                     /*!< FNE (Bit 0)                                           */
14596 #define SCARD_SR_FNE_Msk                  (0x1UL)                   /*!< FNE (Bitfield-Mask: 0x01)                             */
14597 /* ==========================================================  IER  ========================================================== */
14598 #define SCARD_IER_FHFEN_Pos               (6UL)                     /*!< FHFEN (Bit 6)                                         */
14599 #define SCARD_IER_FHFEN_Msk               (0x40UL)                  /*!< FHFEN (Bitfield-Mask: 0x01)                           */
14600 #define SCARD_IER_FT2RENDEN_Pos           (5UL)                     /*!< FT2RENDEN (Bit 5)                                     */
14601 #define SCARD_IER_FT2RENDEN_Msk           (0x20UL)                  /*!< FT2RENDEN (Bitfield-Mask: 0x01)                       */
14602 #define SCARD_IER_PEEN_Pos                (4UL)                     /*!< PEEN (Bit 4)                                          */
14603 #define SCARD_IER_PEEN_Msk                (0x10UL)                  /*!< PEEN (Bitfield-Mask: 0x01)                            */
14604 #define SCARD_IER_OVREN_Pos               (3UL)                     /*!< OVREN (Bit 3)                                         */
14605 #define SCARD_IER_OVREN_Msk               (0x8UL)                   /*!< OVREN (Bitfield-Mask: 0x01)                           */
14606 #define SCARD_IER_FEREN_Pos               (2UL)                     /*!< FEREN (Bit 2)                                         */
14607 #define SCARD_IER_FEREN_Msk               (0x4UL)                   /*!< FEREN (Bitfield-Mask: 0x01)                           */
14608 #define SCARD_IER_TBERBFEN_Pos            (1UL)                     /*!< TBERBFEN (Bit 1)                                      */
14609 #define SCARD_IER_TBERBFEN_Msk            (0x2UL)                   /*!< TBERBFEN (Bitfield-Mask: 0x01)                        */
14610 #define SCARD_IER_FNEEN_Pos               (0UL)                     /*!< FNEEN (Bit 0)                                         */
14611 #define SCARD_IER_FNEEN_Msk               (0x1UL)                   /*!< FNEEN (Bitfield-Mask: 0x01)                           */
14612 /* ==========================================================  TCR  ========================================================== */
14613 #define SCARD_TCR_DMAMD_Pos               (7UL)                     /*!< DMAMD (Bit 7)                                         */
14614 #define SCARD_TCR_DMAMD_Msk               (0x80UL)                  /*!< DMAMD (Bitfield-Mask: 0x01)                           */
14615 #define SCARD_TCR_FIP_Pos                 (6UL)                     /*!< FIP (Bit 6)                                           */
14616 #define SCARD_TCR_FIP_Msk                 (0x40UL)                  /*!< FIP (Bitfield-Mask: 0x01)                             */
14617 #define SCARD_TCR_AUTOCONV_Pos            (5UL)                     /*!< AUTOCONV (Bit 5)                                      */
14618 #define SCARD_TCR_AUTOCONV_Msk            (0x20UL)                  /*!< AUTOCONV (Bitfield-Mask: 0x01)                        */
14619 #define SCARD_TCR_PROT_Pos                (4UL)                     /*!< PROT (Bit 4)                                          */
14620 #define SCARD_TCR_PROT_Msk                (0x10UL)                  /*!< PROT (Bitfield-Mask: 0x01)                            */
14621 #define SCARD_TCR_TR_Pos                  (3UL)                     /*!< TR (Bit 3)                                            */
14622 #define SCARD_TCR_TR_Msk                  (0x8UL)                   /*!< TR (Bitfield-Mask: 0x01)                              */
14623 #define SCARD_TCR_LCT_Pos                 (2UL)                     /*!< LCT (Bit 2)                                           */
14624 #define SCARD_TCR_LCT_Msk                 (0x4UL)                   /*!< LCT (Bitfield-Mask: 0x01)                             */
14625 #define SCARD_TCR_SS_Pos                  (1UL)                     /*!< SS (Bit 1)                                            */
14626 #define SCARD_TCR_SS_Msk                  (0x2UL)                   /*!< SS (Bitfield-Mask: 0x01)                              */
14627 #define SCARD_TCR_CONV_Pos                (0UL)                     /*!< CONV (Bit 0)                                          */
14628 #define SCARD_TCR_CONV_Msk                (0x1UL)                   /*!< CONV (Bitfield-Mask: 0x01)                            */
14629 /* ==========================================================  UCR  ========================================================== */
14630 #define SCARD_UCR_RETXEN_Pos              (3UL)                     /*!< RETXEN (Bit 3)                                        */
14631 #define SCARD_UCR_RETXEN_Msk              (0x8UL)                   /*!< RETXEN (Bitfield-Mask: 0x01)                          */
14632 #define SCARD_UCR_RSTIN_Pos               (2UL)                     /*!< RSTIN (Bit 2)                                         */
14633 #define SCARD_UCR_RSTIN_Msk               (0x4UL)                   /*!< RSTIN (Bitfield-Mask: 0x01)                           */
14634 #define SCARD_UCR_RIU_Pos                 (1UL)                     /*!< RIU (Bit 1)                                           */
14635 #define SCARD_UCR_RIU_Msk                 (0x2UL)                   /*!< RIU (Bitfield-Mask: 0x01)                             */
14636 #define SCARD_UCR_CST_Pos                 (0UL)                     /*!< CST (Bit 0)                                           */
14637 #define SCARD_UCR_CST_Msk                 (0x1UL)                   /*!< CST (Bitfield-Mask: 0x01)                             */
14638 /* ==========================================================  DR  =========================================================== */
14639 #define SCARD_DR_DR_Pos                   (0UL)                     /*!< DR (Bit 0)                                            */
14640 #define SCARD_DR_DR_Msk                   (0xffUL)                  /*!< DR (Bitfield-Mask: 0xff)                              */
14641 /* =========================================================  BPRL  ========================================================== */
14642 #define SCARD_BPRL_BPRL_Pos               (0UL)                     /*!< BPRL (Bit 0)                                          */
14643 #define SCARD_BPRL_BPRL_Msk               (0xffUL)                  /*!< BPRL (Bitfield-Mask: 0xff)                            */
14644 /* =========================================================  BPRH  ========================================================== */
14645 #define SCARD_BPRH_BPRH_Pos               (0UL)                     /*!< BPRH (Bit 0)                                          */
14646 #define SCARD_BPRH_BPRH_Msk               (0xfUL)                   /*!< BPRH (Bitfield-Mask: 0x0f)                            */
14647 /* =========================================================  UCR1  ========================================================== */
14648 #define SCARD_UCR1_ENLASTB_Pos            (5UL)                     /*!< ENLASTB (Bit 5)                                       */
14649 #define SCARD_UCR1_ENLASTB_Msk            (0x20UL)                  /*!< ENLASTB (Bitfield-Mask: 0x01)                         */
14650 #define SCARD_UCR1_CLKIOV_Pos             (4UL)                     /*!< CLKIOV (Bit 4)                                        */
14651 #define SCARD_UCR1_CLKIOV_Msk             (0x10UL)                  /*!< CLKIOV (Bitfield-Mask: 0x01)                          */
14652 #define SCARD_UCR1_T1PAREN_Pos            (3UL)                     /*!< T1PAREN (Bit 3)                                       */
14653 #define SCARD_UCR1_T1PAREN_Msk            (0x8UL)                   /*!< T1PAREN (Bitfield-Mask: 0x01)                         */
14654 #define SCARD_UCR1_STSP_Pos               (2UL)                     /*!< STSP (Bit 2)                                          */
14655 #define SCARD_UCR1_STSP_Msk               (0x4UL)                   /*!< STSP (Bitfield-Mask: 0x01)                            */
14656 #define SCARD_UCR1_PR_Pos                 (0UL)                     /*!< PR (Bit 0)                                            */
14657 #define SCARD_UCR1_PR_Msk                 (0x1UL)                   /*!< PR (Bitfield-Mask: 0x01)                              */
14658 /* ==========================================================  SR1  ========================================================== */
14659 #define SCARD_SR1_IDLE_Pos                (3UL)                     /*!< IDLE (Bit 3)                                          */
14660 #define SCARD_SR1_IDLE_Msk                (0x8UL)                   /*!< IDLE (Bitfield-Mask: 0x01)                            */
14661 #define SCARD_SR1_SYNCEND_Pos             (2UL)                     /*!< SYNCEND (Bit 2)                                       */
14662 #define SCARD_SR1_SYNCEND_Msk             (0x4UL)                   /*!< SYNCEND (Bitfield-Mask: 0x01)                         */
14663 #define SCARD_SR1_PRL_Pos                 (1UL)                     /*!< PRL (Bit 1)                                           */
14664 #define SCARD_SR1_PRL_Msk                 (0x2UL)                   /*!< PRL (Bitfield-Mask: 0x01)                             */
14665 #define SCARD_SR1_ECNTOVER_Pos            (0UL)                     /*!< ECNTOVER (Bit 0)                                      */
14666 #define SCARD_SR1_ECNTOVER_Msk            (0x1UL)                   /*!< ECNTOVER (Bitfield-Mask: 0x01)                        */
14667 /* =========================================================  IER1  ========================================================== */
14668 #define SCARD_IER1_SYNCENDEN_Pos          (2UL)                     /*!< SYNCENDEN (Bit 2)                                     */
14669 #define SCARD_IER1_SYNCENDEN_Msk          (0x4UL)                   /*!< SYNCENDEN (Bitfield-Mask: 0x01)                       */
14670 #define SCARD_IER1_PRLEN_Pos              (1UL)                     /*!< PRLEN (Bit 1)                                         */
14671 #define SCARD_IER1_PRLEN_Msk              (0x2UL)                   /*!< PRLEN (Bitfield-Mask: 0x01)                           */
14672 #define SCARD_IER1_ECNTOVEREN_Pos         (0UL)                     /*!< ECNTOVEREN (Bit 0)                                    */
14673 #define SCARD_IER1_ECNTOVEREN_Msk         (0x1UL)                   /*!< ECNTOVEREN (Bitfield-Mask: 0x01)                      */
14674 /* =========================================================  ECNTL  ========================================================= */
14675 #define SCARD_ECNTL_ECNTL_Pos             (0UL)                     /*!< ECNTL (Bit 0)                                         */
14676 #define SCARD_ECNTL_ECNTL_Msk             (0xffUL)                  /*!< ECNTL (Bitfield-Mask: 0xff)                           */
14677 /* =========================================================  ECNTH  ========================================================= */
14678 #define SCARD_ECNTH_ECNTH_Pos             (0UL)                     /*!< ECNTH (Bit 0)                                         */
14679 #define SCARD_ECNTH_ECNTH_Msk             (0xffUL)                  /*!< ECNTH (Bitfield-Mask: 0xff)                           */
14680 /* ==========================================================  GTR  ========================================================== */
14681 #define SCARD_GTR_GTR_Pos                 (0UL)                     /*!< GTR (Bit 0)                                           */
14682 #define SCARD_GTR_GTR_Msk                 (0xffUL)                  /*!< GTR (Bitfield-Mask: 0xff)                             */
14683 /* ========================================================  RETXCNT  ======================================================== */
14684 #define SCARD_RETXCNT_RETXCNT_Pos         (0UL)                     /*!< RETXCNT (Bit 0)                                       */
14685 #define SCARD_RETXCNT_RETXCNT_Msk         (0xfUL)                   /*!< RETXCNT (Bitfield-Mask: 0x0f)                         */
14686 /* ======================================================  RETXCNTRMI  ======================================================= */
14687 #define SCARD_RETXCNTRMI_RETXCNTRMI_Pos   (0UL)                     /*!< RETXCNTRMI (Bit 0)                                    */
14688 #define SCARD_RETXCNTRMI_RETXCNTRMI_Msk   (0xfUL)                   /*!< RETXCNTRMI (Bitfield-Mask: 0x0f)                      */
14689 /* ========================================================  CLKCTRL  ======================================================== */
14690 #define SCARD_CLKCTRL_APBCLKEN_Pos        (1UL)                     /*!< APBCLKEN (Bit 1)                                      */
14691 #define SCARD_CLKCTRL_APBCLKEN_Msk        (0x2UL)                   /*!< APBCLKEN (Bitfield-Mask: 0x01)                        */
14692 #define SCARD_CLKCTRL_CLKEN_Pos           (0UL)                     /*!< CLKEN (Bit 0)                                         */
14693 #define SCARD_CLKCTRL_CLKEN_Msk           (0x1UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
14694 
14695 
14696 /* =========================================================================================================================== */
14697 /* ================                                         SECURITY                                          ================ */
14698 /* =========================================================================================================================== */
14699 
14700 /* =========================================================  CTRL  ========================================================== */
14701 #define SECURITY_CTRL_CRCERROR_Pos        (31UL)                    /*!< CRCERROR (Bit 31)                                     */
14702 #define SECURITY_CTRL_CRCERROR_Msk        (0x80000000UL)            /*!< CRCERROR (Bitfield-Mask: 0x01)                        */
14703 #define SECURITY_CTRL_FUNCTION_Pos        (4UL)                     /*!< FUNCTION (Bit 4)                                      */
14704 #define SECURITY_CTRL_FUNCTION_Msk        (0xf0UL)                  /*!< FUNCTION (Bitfield-Mask: 0x0f)                        */
14705 #define SECURITY_CTRL_ENABLE_Pos          (0UL)                     /*!< ENABLE (Bit 0)                                        */
14706 #define SECURITY_CTRL_ENABLE_Msk          (0x1UL)                   /*!< ENABLE (Bitfield-Mask: 0x01)                          */
14707 /* ========================================================  SRCADDR  ======================================================== */
14708 #define SECURITY_SRCADDR_ADDR_Pos         (0UL)                     /*!< ADDR (Bit 0)                                          */
14709 #define SECURITY_SRCADDR_ADDR_Msk         (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
14710 /* ==========================================================  LEN  ========================================================== */
14711 #define SECURITY_LEN_LEN_Pos              (2UL)                     /*!< LEN (Bit 2)                                           */
14712 #define SECURITY_LEN_LEN_Msk              (0xffffcUL)               /*!< LEN (Bitfield-Mask: 0x3ffff)                          */
14713 /* ========================================================  RESULT  ========================================================= */
14714 #define SECURITY_RESULT_CRC_Pos           (0UL)                     /*!< CRC (Bit 0)                                           */
14715 #define SECURITY_RESULT_CRC_Msk           (0xffffffffUL)            /*!< CRC (Bitfield-Mask: 0xffffffff)                       */
14716 /* =======================================================  LOCKCTRL  ======================================================== */
14717 #define SECURITY_LOCKCTRL_SELECT_Pos      (0UL)                     /*!< SELECT (Bit 0)                                        */
14718 #define SECURITY_LOCKCTRL_SELECT_Msk      (0xffUL)                  /*!< SELECT (Bitfield-Mask: 0xff)                          */
14719 /* =======================================================  LOCKSTAT  ======================================================== */
14720 #define SECURITY_LOCKSTAT_STATUS_Pos      (0UL)                     /*!< STATUS (Bit 0)                                        */
14721 #define SECURITY_LOCKSTAT_STATUS_Msk      (0xffffffffUL)            /*!< STATUS (Bitfield-Mask: 0xffffffff)                    */
14722 /* =========================================================  KEY0  ========================================================== */
14723 #define SECURITY_KEY0_KEY0_Pos            (0UL)                     /*!< KEY0 (Bit 0)                                          */
14724 #define SECURITY_KEY0_KEY0_Msk            (0xffffffffUL)            /*!< KEY0 (Bitfield-Mask: 0xffffffff)                      */
14725 /* =========================================================  KEY1  ========================================================== */
14726 #define SECURITY_KEY1_KEY1_Pos            (0UL)                     /*!< KEY1 (Bit 0)                                          */
14727 #define SECURITY_KEY1_KEY1_Msk            (0xffffffffUL)            /*!< KEY1 (Bitfield-Mask: 0xffffffff)                      */
14728 /* =========================================================  KEY2  ========================================================== */
14729 #define SECURITY_KEY2_KEY2_Pos            (0UL)                     /*!< KEY2 (Bit 0)                                          */
14730 #define SECURITY_KEY2_KEY2_Msk            (0xffffffffUL)            /*!< KEY2 (Bitfield-Mask: 0xffffffff)                      */
14731 /* =========================================================  KEY3  ========================================================== */
14732 #define SECURITY_KEY3_KEY3_Pos            (0UL)                     /*!< KEY3 (Bit 0)                                          */
14733 #define SECURITY_KEY3_KEY3_Msk            (0xffffffffUL)            /*!< KEY3 (Bitfield-Mask: 0xffffffff)                      */
14734 
14735 
14736 /* =========================================================================================================================== */
14737 /* ================                                           UART0                                           ================ */
14738 /* =========================================================================================================================== */
14739 
14740 /* ==========================================================  DR  =========================================================== */
14741 #define UART0_DR_OEDATA_Pos               (11UL)                    /*!< OEDATA (Bit 11)                                       */
14742 #define UART0_DR_OEDATA_Msk               (0x800UL)                 /*!< OEDATA (Bitfield-Mask: 0x01)                          */
14743 #define UART0_DR_BEDATA_Pos               (10UL)                    /*!< BEDATA (Bit 10)                                       */
14744 #define UART0_DR_BEDATA_Msk               (0x400UL)                 /*!< BEDATA (Bitfield-Mask: 0x01)                          */
14745 #define UART0_DR_PEDATA_Pos               (9UL)                     /*!< PEDATA (Bit 9)                                        */
14746 #define UART0_DR_PEDATA_Msk               (0x200UL)                 /*!< PEDATA (Bitfield-Mask: 0x01)                          */
14747 #define UART0_DR_FEDATA_Pos               (8UL)                     /*!< FEDATA (Bit 8)                                        */
14748 #define UART0_DR_FEDATA_Msk               (0x100UL)                 /*!< FEDATA (Bitfield-Mask: 0x01)                          */
14749 #define UART0_DR_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
14750 #define UART0_DR_DATA_Msk                 (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
14751 /* ==========================================================  RSR  ========================================================== */
14752 #define UART0_RSR_OESTAT_Pos              (3UL)                     /*!< OESTAT (Bit 3)                                        */
14753 #define UART0_RSR_OESTAT_Msk              (0x8UL)                   /*!< OESTAT (Bitfield-Mask: 0x01)                          */
14754 #define UART0_RSR_BESTAT_Pos              (2UL)                     /*!< BESTAT (Bit 2)                                        */
14755 #define UART0_RSR_BESTAT_Msk              (0x4UL)                   /*!< BESTAT (Bitfield-Mask: 0x01)                          */
14756 #define UART0_RSR_PESTAT_Pos              (1UL)                     /*!< PESTAT (Bit 1)                                        */
14757 #define UART0_RSR_PESTAT_Msk              (0x2UL)                   /*!< PESTAT (Bitfield-Mask: 0x01)                          */
14758 #define UART0_RSR_FESTAT_Pos              (0UL)                     /*!< FESTAT (Bit 0)                                        */
14759 #define UART0_RSR_FESTAT_Msk              (0x1UL)                   /*!< FESTAT (Bitfield-Mask: 0x01)                          */
14760 /* ==========================================================  FR  =========================================================== */
14761 #define UART0_FR_TXBUSY_Pos               (8UL)                     /*!< TXBUSY (Bit 8)                                        */
14762 #define UART0_FR_TXBUSY_Msk               (0x100UL)                 /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
14763 #define UART0_FR_TXFE_Pos                 (7UL)                     /*!< TXFE (Bit 7)                                          */
14764 #define UART0_FR_TXFE_Msk                 (0x80UL)                  /*!< TXFE (Bitfield-Mask: 0x01)                            */
14765 #define UART0_FR_RXFF_Pos                 (6UL)                     /*!< RXFF (Bit 6)                                          */
14766 #define UART0_FR_RXFF_Msk                 (0x40UL)                  /*!< RXFF (Bitfield-Mask: 0x01)                            */
14767 #define UART0_FR_TXFF_Pos                 (5UL)                     /*!< TXFF (Bit 5)                                          */
14768 #define UART0_FR_TXFF_Msk                 (0x20UL)                  /*!< TXFF (Bitfield-Mask: 0x01)                            */
14769 #define UART0_FR_RXFE_Pos                 (4UL)                     /*!< RXFE (Bit 4)                                          */
14770 #define UART0_FR_RXFE_Msk                 (0x10UL)                  /*!< RXFE (Bitfield-Mask: 0x01)                            */
14771 #define UART0_FR_BUSY_Pos                 (3UL)                     /*!< BUSY (Bit 3)                                          */
14772 #define UART0_FR_BUSY_Msk                 (0x8UL)                   /*!< BUSY (Bitfield-Mask: 0x01)                            */
14773 #define UART0_FR_DCD_Pos                  (2UL)                     /*!< DCD (Bit 2)                                           */
14774 #define UART0_FR_DCD_Msk                  (0x4UL)                   /*!< DCD (Bitfield-Mask: 0x01)                             */
14775 #define UART0_FR_DSR_Pos                  (1UL)                     /*!< DSR (Bit 1)                                           */
14776 #define UART0_FR_DSR_Msk                  (0x2UL)                   /*!< DSR (Bitfield-Mask: 0x01)                             */
14777 #define UART0_FR_CTS_Pos                  (0UL)                     /*!< CTS (Bit 0)                                           */
14778 #define UART0_FR_CTS_Msk                  (0x1UL)                   /*!< CTS (Bitfield-Mask: 0x01)                             */
14779 /* =========================================================  ILPR  ========================================================== */
14780 #define UART0_ILPR_ILPDVSR_Pos            (0UL)                     /*!< ILPDVSR (Bit 0)                                       */
14781 #define UART0_ILPR_ILPDVSR_Msk            (0xffUL)                  /*!< ILPDVSR (Bitfield-Mask: 0xff)                         */
14782 /* =========================================================  IBRD  ========================================================== */
14783 #define UART0_IBRD_DIVINT_Pos             (0UL)                     /*!< DIVINT (Bit 0)                                        */
14784 #define UART0_IBRD_DIVINT_Msk             (0xffffUL)                /*!< DIVINT (Bitfield-Mask: 0xffff)                        */
14785 /* =========================================================  FBRD  ========================================================== */
14786 #define UART0_FBRD_DIVFRAC_Pos            (0UL)                     /*!< DIVFRAC (Bit 0)                                       */
14787 #define UART0_FBRD_DIVFRAC_Msk            (0x3fUL)                  /*!< DIVFRAC (Bitfield-Mask: 0x3f)                         */
14788 /* =========================================================  LCRH  ========================================================== */
14789 #define UART0_LCRH_SPS_Pos                (7UL)                     /*!< SPS (Bit 7)                                           */
14790 #define UART0_LCRH_SPS_Msk                (0x80UL)                  /*!< SPS (Bitfield-Mask: 0x01)                             */
14791 #define UART0_LCRH_WLEN_Pos               (5UL)                     /*!< WLEN (Bit 5)                                          */
14792 #define UART0_LCRH_WLEN_Msk               (0x60UL)                  /*!< WLEN (Bitfield-Mask: 0x03)                            */
14793 #define UART0_LCRH_FEN_Pos                (4UL)                     /*!< FEN (Bit 4)                                           */
14794 #define UART0_LCRH_FEN_Msk                (0x10UL)                  /*!< FEN (Bitfield-Mask: 0x01)                             */
14795 #define UART0_LCRH_STP2_Pos               (3UL)                     /*!< STP2 (Bit 3)                                          */
14796 #define UART0_LCRH_STP2_Msk               (0x8UL)                   /*!< STP2 (Bitfield-Mask: 0x01)                            */
14797 #define UART0_LCRH_EPS_Pos                (2UL)                     /*!< EPS (Bit 2)                                           */
14798 #define UART0_LCRH_EPS_Msk                (0x4UL)                   /*!< EPS (Bitfield-Mask: 0x01)                             */
14799 #define UART0_LCRH_PEN_Pos                (1UL)                     /*!< PEN (Bit 1)                                           */
14800 #define UART0_LCRH_PEN_Msk                (0x2UL)                   /*!< PEN (Bitfield-Mask: 0x01)                             */
14801 #define UART0_LCRH_BRK_Pos                (0UL)                     /*!< BRK (Bit 0)                                           */
14802 #define UART0_LCRH_BRK_Msk                (0x1UL)                   /*!< BRK (Bitfield-Mask: 0x01)                             */
14803 /* ==========================================================  CR  =========================================================== */
14804 #define UART0_CR_CTSEN_Pos                (15UL)                    /*!< CTSEN (Bit 15)                                        */
14805 #define UART0_CR_CTSEN_Msk                (0x8000UL)                /*!< CTSEN (Bitfield-Mask: 0x01)                           */
14806 #define UART0_CR_RTSEN_Pos                (14UL)                    /*!< RTSEN (Bit 14)                                        */
14807 #define UART0_CR_RTSEN_Msk                (0x4000UL)                /*!< RTSEN (Bitfield-Mask: 0x01)                           */
14808 #define UART0_CR_OUT2_Pos                 (13UL)                    /*!< OUT2 (Bit 13)                                         */
14809 #define UART0_CR_OUT2_Msk                 (0x2000UL)                /*!< OUT2 (Bitfield-Mask: 0x01)                            */
14810 #define UART0_CR_OUT1_Pos                 (12UL)                    /*!< OUT1 (Bit 12)                                         */
14811 #define UART0_CR_OUT1_Msk                 (0x1000UL)                /*!< OUT1 (Bitfield-Mask: 0x01)                            */
14812 #define UART0_CR_RTS_Pos                  (11UL)                    /*!< RTS (Bit 11)                                          */
14813 #define UART0_CR_RTS_Msk                  (0x800UL)                 /*!< RTS (Bitfield-Mask: 0x01)                             */
14814 #define UART0_CR_DTR_Pos                  (10UL)                    /*!< DTR (Bit 10)                                          */
14815 #define UART0_CR_DTR_Msk                  (0x400UL)                 /*!< DTR (Bitfield-Mask: 0x01)                             */
14816 #define UART0_CR_RXE_Pos                  (9UL)                     /*!< RXE (Bit 9)                                           */
14817 #define UART0_CR_RXE_Msk                  (0x200UL)                 /*!< RXE (Bitfield-Mask: 0x01)                             */
14818 #define UART0_CR_TXE_Pos                  (8UL)                     /*!< TXE (Bit 8)                                           */
14819 #define UART0_CR_TXE_Msk                  (0x100UL)                 /*!< TXE (Bitfield-Mask: 0x01)                             */
14820 #define UART0_CR_LBE_Pos                  (7UL)                     /*!< LBE (Bit 7)                                           */
14821 #define UART0_CR_LBE_Msk                  (0x80UL)                  /*!< LBE (Bitfield-Mask: 0x01)                             */
14822 #define UART0_CR_CLKSEL_Pos               (4UL)                     /*!< CLKSEL (Bit 4)                                        */
14823 #define UART0_CR_CLKSEL_Msk               (0x70UL)                  /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
14824 #define UART0_CR_CLKEN_Pos                (3UL)                     /*!< CLKEN (Bit 3)                                         */
14825 #define UART0_CR_CLKEN_Msk                (0x8UL)                   /*!< CLKEN (Bitfield-Mask: 0x01)                           */
14826 #define UART0_CR_SIRLP_Pos                (2UL)                     /*!< SIRLP (Bit 2)                                         */
14827 #define UART0_CR_SIRLP_Msk                (0x4UL)                   /*!< SIRLP (Bitfield-Mask: 0x01)                           */
14828 #define UART0_CR_SIREN_Pos                (1UL)                     /*!< SIREN (Bit 1)                                         */
14829 #define UART0_CR_SIREN_Msk                (0x2UL)                   /*!< SIREN (Bitfield-Mask: 0x01)                           */
14830 #define UART0_CR_UARTEN_Pos               (0UL)                     /*!< UARTEN (Bit 0)                                        */
14831 #define UART0_CR_UARTEN_Msk               (0x1UL)                   /*!< UARTEN (Bitfield-Mask: 0x01)                          */
14832 /* =========================================================  IFLS  ========================================================== */
14833 #define UART0_IFLS_RXIFLSEL_Pos           (3UL)                     /*!< RXIFLSEL (Bit 3)                                      */
14834 #define UART0_IFLS_RXIFLSEL_Msk           (0x38UL)                  /*!< RXIFLSEL (Bitfield-Mask: 0x07)                        */
14835 #define UART0_IFLS_TXIFLSEL_Pos           (0UL)                     /*!< TXIFLSEL (Bit 0)                                      */
14836 #define UART0_IFLS_TXIFLSEL_Msk           (0x7UL)                   /*!< TXIFLSEL (Bitfield-Mask: 0x07)                        */
14837 /* ==========================================================  IER  ========================================================== */
14838 #define UART0_IER_OEIM_Pos                (10UL)                    /*!< OEIM (Bit 10)                                         */
14839 #define UART0_IER_OEIM_Msk                (0x400UL)                 /*!< OEIM (Bitfield-Mask: 0x01)                            */
14840 #define UART0_IER_BEIM_Pos                (9UL)                     /*!< BEIM (Bit 9)                                          */
14841 #define UART0_IER_BEIM_Msk                (0x200UL)                 /*!< BEIM (Bitfield-Mask: 0x01)                            */
14842 #define UART0_IER_PEIM_Pos                (8UL)                     /*!< PEIM (Bit 8)                                          */
14843 #define UART0_IER_PEIM_Msk                (0x100UL)                 /*!< PEIM (Bitfield-Mask: 0x01)                            */
14844 #define UART0_IER_FEIM_Pos                (7UL)                     /*!< FEIM (Bit 7)                                          */
14845 #define UART0_IER_FEIM_Msk                (0x80UL)                  /*!< FEIM (Bitfield-Mask: 0x01)                            */
14846 #define UART0_IER_RTIM_Pos                (6UL)                     /*!< RTIM (Bit 6)                                          */
14847 #define UART0_IER_RTIM_Msk                (0x40UL)                  /*!< RTIM (Bitfield-Mask: 0x01)                            */
14848 #define UART0_IER_TXIM_Pos                (5UL)                     /*!< TXIM (Bit 5)                                          */
14849 #define UART0_IER_TXIM_Msk                (0x20UL)                  /*!< TXIM (Bitfield-Mask: 0x01)                            */
14850 #define UART0_IER_RXIM_Pos                (4UL)                     /*!< RXIM (Bit 4)                                          */
14851 #define UART0_IER_RXIM_Msk                (0x10UL)                  /*!< RXIM (Bitfield-Mask: 0x01)                            */
14852 #define UART0_IER_DSRMIM_Pos              (3UL)                     /*!< DSRMIM (Bit 3)                                        */
14853 #define UART0_IER_DSRMIM_Msk              (0x8UL)                   /*!< DSRMIM (Bitfield-Mask: 0x01)                          */
14854 #define UART0_IER_DCDMIM_Pos              (2UL)                     /*!< DCDMIM (Bit 2)                                        */
14855 #define UART0_IER_DCDMIM_Msk              (0x4UL)                   /*!< DCDMIM (Bitfield-Mask: 0x01)                          */
14856 #define UART0_IER_CTSMIM_Pos              (1UL)                     /*!< CTSMIM (Bit 1)                                        */
14857 #define UART0_IER_CTSMIM_Msk              (0x2UL)                   /*!< CTSMIM (Bitfield-Mask: 0x01)                          */
14858 #define UART0_IER_TXCMPMIM_Pos            (0UL)                     /*!< TXCMPMIM (Bit 0)                                      */
14859 #define UART0_IER_TXCMPMIM_Msk            (0x1UL)                   /*!< TXCMPMIM (Bitfield-Mask: 0x01)                        */
14860 /* ==========================================================  IES  ========================================================== */
14861 #define UART0_IES_OERIS_Pos               (10UL)                    /*!< OERIS (Bit 10)                                        */
14862 #define UART0_IES_OERIS_Msk               (0x400UL)                 /*!< OERIS (Bitfield-Mask: 0x01)                           */
14863 #define UART0_IES_BERIS_Pos               (9UL)                     /*!< BERIS (Bit 9)                                         */
14864 #define UART0_IES_BERIS_Msk               (0x200UL)                 /*!< BERIS (Bitfield-Mask: 0x01)                           */
14865 #define UART0_IES_PERIS_Pos               (8UL)                     /*!< PERIS (Bit 8)                                         */
14866 #define UART0_IES_PERIS_Msk               (0x100UL)                 /*!< PERIS (Bitfield-Mask: 0x01)                           */
14867 #define UART0_IES_FERIS_Pos               (7UL)                     /*!< FERIS (Bit 7)                                         */
14868 #define UART0_IES_FERIS_Msk               (0x80UL)                  /*!< FERIS (Bitfield-Mask: 0x01)                           */
14869 #define UART0_IES_RTRIS_Pos               (6UL)                     /*!< RTRIS (Bit 6)                                         */
14870 #define UART0_IES_RTRIS_Msk               (0x40UL)                  /*!< RTRIS (Bitfield-Mask: 0x01)                           */
14871 #define UART0_IES_TXRIS_Pos               (5UL)                     /*!< TXRIS (Bit 5)                                         */
14872 #define UART0_IES_TXRIS_Msk               (0x20UL)                  /*!< TXRIS (Bitfield-Mask: 0x01)                           */
14873 #define UART0_IES_RXRIS_Pos               (4UL)                     /*!< RXRIS (Bit 4)                                         */
14874 #define UART0_IES_RXRIS_Msk               (0x10UL)                  /*!< RXRIS (Bitfield-Mask: 0x01)                           */
14875 #define UART0_IES_DSRMRIS_Pos             (3UL)                     /*!< DSRMRIS (Bit 3)                                       */
14876 #define UART0_IES_DSRMRIS_Msk             (0x8UL)                   /*!< DSRMRIS (Bitfield-Mask: 0x01)                         */
14877 #define UART0_IES_DCDMRIS_Pos             (2UL)                     /*!< DCDMRIS (Bit 2)                                       */
14878 #define UART0_IES_DCDMRIS_Msk             (0x4UL)                   /*!< DCDMRIS (Bitfield-Mask: 0x01)                         */
14879 #define UART0_IES_CTSMRIS_Pos             (1UL)                     /*!< CTSMRIS (Bit 1)                                       */
14880 #define UART0_IES_CTSMRIS_Msk             (0x2UL)                   /*!< CTSMRIS (Bitfield-Mask: 0x01)                         */
14881 #define UART0_IES_TXCMPMRIS_Pos           (0UL)                     /*!< TXCMPMRIS (Bit 0)                                     */
14882 #define UART0_IES_TXCMPMRIS_Msk           (0x1UL)                   /*!< TXCMPMRIS (Bitfield-Mask: 0x01)                       */
14883 /* ==========================================================  MIS  ========================================================== */
14884 #define UART0_MIS_OEMIS_Pos               (10UL)                    /*!< OEMIS (Bit 10)                                        */
14885 #define UART0_MIS_OEMIS_Msk               (0x400UL)                 /*!< OEMIS (Bitfield-Mask: 0x01)                           */
14886 #define UART0_MIS_BEMIS_Pos               (9UL)                     /*!< BEMIS (Bit 9)                                         */
14887 #define UART0_MIS_BEMIS_Msk               (0x200UL)                 /*!< BEMIS (Bitfield-Mask: 0x01)                           */
14888 #define UART0_MIS_PEMIS_Pos               (8UL)                     /*!< PEMIS (Bit 8)                                         */
14889 #define UART0_MIS_PEMIS_Msk               (0x100UL)                 /*!< PEMIS (Bitfield-Mask: 0x01)                           */
14890 #define UART0_MIS_FEMIS_Pos               (7UL)                     /*!< FEMIS (Bit 7)                                         */
14891 #define UART0_MIS_FEMIS_Msk               (0x80UL)                  /*!< FEMIS (Bitfield-Mask: 0x01)                           */
14892 #define UART0_MIS_RTMIS_Pos               (6UL)                     /*!< RTMIS (Bit 6)                                         */
14893 #define UART0_MIS_RTMIS_Msk               (0x40UL)                  /*!< RTMIS (Bitfield-Mask: 0x01)                           */
14894 #define UART0_MIS_TXMIS_Pos               (5UL)                     /*!< TXMIS (Bit 5)                                         */
14895 #define UART0_MIS_TXMIS_Msk               (0x20UL)                  /*!< TXMIS (Bitfield-Mask: 0x01)                           */
14896 #define UART0_MIS_RXMIS_Pos               (4UL)                     /*!< RXMIS (Bit 4)                                         */
14897 #define UART0_MIS_RXMIS_Msk               (0x10UL)                  /*!< RXMIS (Bitfield-Mask: 0x01)                           */
14898 #define UART0_MIS_DSRMMIS_Pos             (3UL)                     /*!< DSRMMIS (Bit 3)                                       */
14899 #define UART0_MIS_DSRMMIS_Msk             (0x8UL)                   /*!< DSRMMIS (Bitfield-Mask: 0x01)                         */
14900 #define UART0_MIS_DCDMMIS_Pos             (2UL)                     /*!< DCDMMIS (Bit 2)                                       */
14901 #define UART0_MIS_DCDMMIS_Msk             (0x4UL)                   /*!< DCDMMIS (Bitfield-Mask: 0x01)                         */
14902 #define UART0_MIS_CTSMMIS_Pos             (1UL)                     /*!< CTSMMIS (Bit 1)                                       */
14903 #define UART0_MIS_CTSMMIS_Msk             (0x2UL)                   /*!< CTSMMIS (Bitfield-Mask: 0x01)                         */
14904 #define UART0_MIS_TXCMPMMIS_Pos           (0UL)                     /*!< TXCMPMMIS (Bit 0)                                     */
14905 #define UART0_MIS_TXCMPMMIS_Msk           (0x1UL)                   /*!< TXCMPMMIS (Bitfield-Mask: 0x01)                       */
14906 /* ==========================================================  IEC  ========================================================== */
14907 #define UART0_IEC_OEIC_Pos                (10UL)                    /*!< OEIC (Bit 10)                                         */
14908 #define UART0_IEC_OEIC_Msk                (0x400UL)                 /*!< OEIC (Bitfield-Mask: 0x01)                            */
14909 #define UART0_IEC_BEIC_Pos                (9UL)                     /*!< BEIC (Bit 9)                                          */
14910 #define UART0_IEC_BEIC_Msk                (0x200UL)                 /*!< BEIC (Bitfield-Mask: 0x01)                            */
14911 #define UART0_IEC_PEIC_Pos                (8UL)                     /*!< PEIC (Bit 8)                                          */
14912 #define UART0_IEC_PEIC_Msk                (0x100UL)                 /*!< PEIC (Bitfield-Mask: 0x01)                            */
14913 #define UART0_IEC_FEIC_Pos                (7UL)                     /*!< FEIC (Bit 7)                                          */
14914 #define UART0_IEC_FEIC_Msk                (0x80UL)                  /*!< FEIC (Bitfield-Mask: 0x01)                            */
14915 #define UART0_IEC_RTIC_Pos                (6UL)                     /*!< RTIC (Bit 6)                                          */
14916 #define UART0_IEC_RTIC_Msk                (0x40UL)                  /*!< RTIC (Bitfield-Mask: 0x01)                            */
14917 #define UART0_IEC_TXIC_Pos                (5UL)                     /*!< TXIC (Bit 5)                                          */
14918 #define UART0_IEC_TXIC_Msk                (0x20UL)                  /*!< TXIC (Bitfield-Mask: 0x01)                            */
14919 #define UART0_IEC_RXIC_Pos                (4UL)                     /*!< RXIC (Bit 4)                                          */
14920 #define UART0_IEC_RXIC_Msk                (0x10UL)                  /*!< RXIC (Bitfield-Mask: 0x01)                            */
14921 #define UART0_IEC_DSRMIC_Pos              (3UL)                     /*!< DSRMIC (Bit 3)                                        */
14922 #define UART0_IEC_DSRMIC_Msk              (0x8UL)                   /*!< DSRMIC (Bitfield-Mask: 0x01)                          */
14923 #define UART0_IEC_DCDMIC_Pos              (2UL)                     /*!< DCDMIC (Bit 2)                                        */
14924 #define UART0_IEC_DCDMIC_Msk              (0x4UL)                   /*!< DCDMIC (Bitfield-Mask: 0x01)                          */
14925 #define UART0_IEC_CTSMIC_Pos              (1UL)                     /*!< CTSMIC (Bit 1)                                        */
14926 #define UART0_IEC_CTSMIC_Msk              (0x2UL)                   /*!< CTSMIC (Bitfield-Mask: 0x01)                          */
14927 #define UART0_IEC_TXCMPMIC_Pos            (0UL)                     /*!< TXCMPMIC (Bit 0)                                      */
14928 #define UART0_IEC_TXCMPMIC_Msk            (0x1UL)                   /*!< TXCMPMIC (Bitfield-Mask: 0x01)                        */
14929 
14930 
14931 /* =========================================================================================================================== */
14932 /* ================                                           VCOMP                                           ================ */
14933 /* =========================================================================================================================== */
14934 
14935 /* ==========================================================  CFG  ========================================================== */
14936 #define VCOMP_CFG_LVLSEL_Pos              (16UL)                    /*!< LVLSEL (Bit 16)                                       */
14937 #define VCOMP_CFG_LVLSEL_Msk              (0xf0000UL)               /*!< LVLSEL (Bitfield-Mask: 0x0f)                          */
14938 #define VCOMP_CFG_NSEL_Pos                (8UL)                     /*!< NSEL (Bit 8)                                          */
14939 #define VCOMP_CFG_NSEL_Msk                (0x300UL)                 /*!< NSEL (Bitfield-Mask: 0x03)                            */
14940 #define VCOMP_CFG_PSEL_Pos                (0UL)                     /*!< PSEL (Bit 0)                                          */
14941 #define VCOMP_CFG_PSEL_Msk                (0x3UL)                   /*!< PSEL (Bitfield-Mask: 0x03)                            */
14942 /* =========================================================  STAT  ========================================================== */
14943 #define VCOMP_STAT_PWDSTAT_Pos            (1UL)                     /*!< PWDSTAT (Bit 1)                                       */
14944 #define VCOMP_STAT_PWDSTAT_Msk            (0x2UL)                   /*!< PWDSTAT (Bitfield-Mask: 0x01)                         */
14945 #define VCOMP_STAT_CMPOUT_Pos             (0UL)                     /*!< CMPOUT (Bit 0)                                        */
14946 #define VCOMP_STAT_CMPOUT_Msk             (0x1UL)                   /*!< CMPOUT (Bitfield-Mask: 0x01)                          */
14947 /* ========================================================  PWDKEY  ========================================================= */
14948 #define VCOMP_PWDKEY_PWDKEY_Pos           (0UL)                     /*!< PWDKEY (Bit 0)                                        */
14949 #define VCOMP_PWDKEY_PWDKEY_Msk           (0xffffffffUL)            /*!< PWDKEY (Bitfield-Mask: 0xffffffff)                    */
14950 /* =========================================================  INTEN  ========================================================= */
14951 #define VCOMP_INTEN_OUTHI_Pos             (1UL)                     /*!< OUTHI (Bit 1)                                         */
14952 #define VCOMP_INTEN_OUTHI_Msk             (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
14953 #define VCOMP_INTEN_OUTLOW_Pos            (0UL)                     /*!< OUTLOW (Bit 0)                                        */
14954 #define VCOMP_INTEN_OUTLOW_Msk            (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
14955 /* ========================================================  INTSTAT  ======================================================== */
14956 #define VCOMP_INTSTAT_OUTHI_Pos           (1UL)                     /*!< OUTHI (Bit 1)                                         */
14957 #define VCOMP_INTSTAT_OUTHI_Msk           (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
14958 #define VCOMP_INTSTAT_OUTLOW_Pos          (0UL)                     /*!< OUTLOW (Bit 0)                                        */
14959 #define VCOMP_INTSTAT_OUTLOW_Msk          (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
14960 /* ========================================================  INTCLR  ========================================================= */
14961 #define VCOMP_INTCLR_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
14962 #define VCOMP_INTCLR_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
14963 #define VCOMP_INTCLR_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
14964 #define VCOMP_INTCLR_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
14965 /* ========================================================  INTSET  ========================================================= */
14966 #define VCOMP_INTSET_OUTHI_Pos            (1UL)                     /*!< OUTHI (Bit 1)                                         */
14967 #define VCOMP_INTSET_OUTHI_Msk            (0x2UL)                   /*!< OUTHI (Bitfield-Mask: 0x01)                           */
14968 #define VCOMP_INTSET_OUTLOW_Pos           (0UL)                     /*!< OUTLOW (Bit 0)                                        */
14969 #define VCOMP_INTSET_OUTLOW_Msk           (0x1UL)                   /*!< OUTLOW (Bitfield-Mask: 0x01)                          */
14970 
14971 
14972 /* =========================================================================================================================== */
14973 /* ================                                            WDT                                            ================ */
14974 /* =========================================================================================================================== */
14975 
14976 /* ==========================================================  CFG  ========================================================== */
14977 #define WDT_CFG_CLKSEL_Pos                (24UL)                    /*!< CLKSEL (Bit 24)                                       */
14978 #define WDT_CFG_CLKSEL_Msk                (0x7000000UL)             /*!< CLKSEL (Bitfield-Mask: 0x07)                          */
14979 #define WDT_CFG_INTVAL_Pos                (16UL)                    /*!< INTVAL (Bit 16)                                       */
14980 #define WDT_CFG_INTVAL_Msk                (0xff0000UL)              /*!< INTVAL (Bitfield-Mask: 0xff)                          */
14981 #define WDT_CFG_RESVAL_Pos                (8UL)                     /*!< RESVAL (Bit 8)                                        */
14982 #define WDT_CFG_RESVAL_Msk                (0xff00UL)                /*!< RESVAL (Bitfield-Mask: 0xff)                          */
14983 #define WDT_CFG_RESEN_Pos                 (2UL)                     /*!< RESEN (Bit 2)                                         */
14984 #define WDT_CFG_RESEN_Msk                 (0x4UL)                   /*!< RESEN (Bitfield-Mask: 0x01)                           */
14985 #define WDT_CFG_INTEN_Pos                 (1UL)                     /*!< INTEN (Bit 1)                                         */
14986 #define WDT_CFG_INTEN_Msk                 (0x2UL)                   /*!< INTEN (Bitfield-Mask: 0x01)                           */
14987 #define WDT_CFG_WDTEN_Pos                 (0UL)                     /*!< WDTEN (Bit 0)                                         */
14988 #define WDT_CFG_WDTEN_Msk                 (0x1UL)                   /*!< WDTEN (Bitfield-Mask: 0x01)                           */
14989 /* =========================================================  RSTRT  ========================================================= */
14990 #define WDT_RSTRT_RSTRT_Pos               (0UL)                     /*!< RSTRT (Bit 0)                                         */
14991 #define WDT_RSTRT_RSTRT_Msk               (0xffUL)                  /*!< RSTRT (Bitfield-Mask: 0xff)                           */
14992 /* =========================================================  LOCK  ========================================================== */
14993 #define WDT_LOCK_LOCK_Pos                 (0UL)                     /*!< LOCK (Bit 0)                                          */
14994 #define WDT_LOCK_LOCK_Msk                 (0xffUL)                  /*!< LOCK (Bitfield-Mask: 0xff)                            */
14995 /* =========================================================  COUNT  ========================================================= */
14996 #define WDT_COUNT_COUNT_Pos               (0UL)                     /*!< COUNT (Bit 0)                                         */
14997 #define WDT_COUNT_COUNT_Msk               (0xffUL)                  /*!< COUNT (Bitfield-Mask: 0xff)                           */
14998 /* =========================================================  INTEN  ========================================================= */
14999 #define WDT_INTEN_WDTINT_Pos              (0UL)                     /*!< WDTINT (Bit 0)                                        */
15000 #define WDT_INTEN_WDTINT_Msk              (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
15001 /* ========================================================  INTSTAT  ======================================================== */
15002 #define WDT_INTSTAT_WDTINT_Pos            (0UL)                     /*!< WDTINT (Bit 0)                                        */
15003 #define WDT_INTSTAT_WDTINT_Msk            (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
15004 /* ========================================================  INTCLR  ========================================================= */
15005 #define WDT_INTCLR_WDTINT_Pos             (0UL)                     /*!< WDTINT (Bit 0)                                        */
15006 #define WDT_INTCLR_WDTINT_Msk             (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
15007 /* ========================================================  INTSET  ========================================================= */
15008 #define WDT_INTSET_WDTINT_Pos             (0UL)                     /*!< WDTINT (Bit 0)                                        */
15009 #define WDT_INTSET_WDTINT_Msk             (0x1UL)                   /*!< WDTINT (Bitfield-Mask: 0x01)                          */
15010 
15011 /** @} */ /* End of group PosMask_peripherals */
15012 
15013 
15014 /* =========================================================================================================================== */
15015 /* ================                           Enumerated Values Peripheral Section                            ================ */
15016 /* =========================================================================================================================== */
15017 
15018 
15019 /** @addtogroup EnumValue_peripherals
15020   * @{
15021   */
15022 
15023 
15024 
15025 /* =========================================================================================================================== */
15026 /* ================                                            ADC                                            ================ */
15027 /* =========================================================================================================================== */
15028 
15029 /* ==========================================================  CFG  ========================================================== */
15030 /* ================================================  ADC CFG CLKSEL [24..25]  ================================================ */
15031 typedef enum {                                  /*!< ADC_CFG_CLKSEL                                                            */
15032   ADC_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Off mode. The HFRC or HFRC_DIV2 clock must be selected
15033                                                      for the ADC to function. The ADC controller automatically
15034                                                      shuts off the clock in it's low power modes. When setting
15035                                                      ADCEN to '0', the CLKSEL should remain set to one of the
15036                                                      two clock selects for proper power down sequencing.                       */
15037   ADC_CFG_CLKSEL_HFRC                  = 1,     /*!< HFRC : HFRC Core Clock divided by (CORESEL+1)                             */
15038   ADC_CFG_CLKSEL_HFRC_DIV2             = 2,     /*!< HFRC_DIV2 : HFRC Core Clock / 2 further divided by (CORESEL+1)            */
15039 } ADC_CFG_CLKSEL_Enum;
15040 
15041 /* ===============================================  ADC CFG TRIGPOL [19..19]  ================================================ */
15042 typedef enum {                                  /*!< ADC_CFG_TRIGPOL                                                           */
15043   ADC_CFG_TRIGPOL_RISING_EDGE          = 0,     /*!< RISING_EDGE : Trigger on rising edge.                                     */
15044   ADC_CFG_TRIGPOL_FALLING_EDGE         = 1,     /*!< FALLING_EDGE : Trigger on falling edge.                                   */
15045 } ADC_CFG_TRIGPOL_Enum;
15046 
15047 /* ===============================================  ADC CFG TRIGSEL [16..18]  ================================================ */
15048 typedef enum {                                  /*!< ADC_CFG_TRIGSEL                                                           */
15049   ADC_CFG_TRIGSEL_EXT0                 = 0,     /*!< EXT0 : Off chip External Trigger0 (ADC_ET0)                               */
15050   ADC_CFG_TRIGSEL_EXT1                 = 1,     /*!< EXT1 : Off chip External Trigger1 (ADC_ET1)                               */
15051   ADC_CFG_TRIGSEL_EXT2                 = 2,     /*!< EXT2 : Off chip External Trigger2 (ADC_ET2)                               */
15052   ADC_CFG_TRIGSEL_EXT3                 = 3,     /*!< EXT3 : Off chip External Trigger3 (ADC_ET3)                               */
15053   ADC_CFG_TRIGSEL_VCOMP                = 4,     /*!< VCOMP : Voltage Comparator Output                                         */
15054   ADC_CFG_TRIGSEL_SWT                  = 7,     /*!< SWT : Software Trigger                                                    */
15055 } ADC_CFG_TRIGSEL_Enum;
15056 
15057 /* ==============================================  ADC CFG DFIFORDEN [12..12]  =============================================== */
15058 typedef enum {                                  /*!< ADC_CFG_DFIFORDEN                                                         */
15059   ADC_CFG_DFIFORDEN_DIS                = 0,     /*!< DIS : Destructive Reads are prevented. Reads to the FIFOPR register
15060                                                      will not POP an entry off the FIFO.                                       */
15061   ADC_CFG_DFIFORDEN_EN                 = 1,     /*!< EN : Reads to the FIFOPR register will automatically pop an
15062                                                      entry off the FIFO.                                                       */
15063 } ADC_CFG_DFIFORDEN_Enum;
15064 
15065 /* =================================================  ADC CFG REFSEL [8..9]  ================================================= */
15066 typedef enum {                                  /*!< ADC_CFG_REFSEL                                                            */
15067   ADC_CFG_REFSEL_INT2P0                = 0,     /*!< INT2P0 : Internal 2.0V Bandgap Reference Voltage                          */
15068   ADC_CFG_REFSEL_INT1P5                = 1,     /*!< INT1P5 : Internal 1.5V Bandgap Reference Voltage                          */
15069   ADC_CFG_REFSEL_EXT2P0                = 2,     /*!< EXT2P0 : Off Chip 2.0V Reference                                          */
15070   ADC_CFG_REFSEL_EXT1P5                = 3,     /*!< EXT1P5 : Off Chip 1.5V Reference                                          */
15071 } ADC_CFG_REFSEL_Enum;
15072 
15073 /* =================================================  ADC CFG CKMODE [4..4]  ================================================= */
15074 typedef enum {                                  /*!< ADC_CFG_CKMODE                                                            */
15075   ADC_CFG_CKMODE_LPCKMODE              = 0,     /*!< LPCKMODE : Disable the clock between scans for LPMODE0. Set
15076                                                      LPCKMODE to 0x1 while configuring the ADC.                                */
15077   ADC_CFG_CKMODE_LLCKMODE              = 1,     /*!< LLCKMODE : Low Latency Clock Mode. When set, HFRC and the adc_clk
15078                                                      will remain on while in functioning in LPMODE0.                           */
15079 } ADC_CFG_CKMODE_Enum;
15080 
15081 /* =================================================  ADC CFG LPMODE [3..3]  ================================================= */
15082 typedef enum {                                  /*!< ADC_CFG_LPMODE                                                            */
15083   ADC_CFG_LPMODE_MODE0                 = 0,     /*!< MODE0 : Low Power Mode 0. Leaves the ADC fully powered between
15084                                                      scans with minimum latency between a trigger event and
15085                                                      sample data collection.                                                   */
15086   ADC_CFG_LPMODE_MODE1                 = 1,     /*!< MODE1 : Low Power Mode 1. Powers down all circuity and clocks
15087                                                      associated with the ADC until the next trigger event. Between
15088                                                      scans, the reference buffer requires up to 50us of delay
15089                                                      from a scan trigger event before the conversion will commence
15090                                                      while operating in this mode.                                             */
15091 } ADC_CFG_LPMODE_Enum;
15092 
15093 /* =================================================  ADC CFG RPTEN [2..2]  ================================================== */
15094 typedef enum {                                  /*!< ADC_CFG_RPTEN                                                             */
15095   ADC_CFG_RPTEN_SINGLE_SCAN            = 0,     /*!< SINGLE_SCAN : In Single Scan Mode, the ADC will complete a single
15096                                                      scan upon each trigger event.                                             */
15097   ADC_CFG_RPTEN_REPEATING_SCAN         = 1,     /*!< REPEATING_SCAN : In Repeating Scan Mode, the ADC will complete
15098                                                      it's first scan upon the initial trigger event and all
15099                                                      subsequent scans will occur at regular intervals defined
15100                                                      by the configuration programmed for the CTTMRA3 internal
15101                                                      timer until the timer is disabled or the ADC is disabled.
15102                                                      When disabling the ADC (setting ADCEN to '0'), the RPTEN
15103                                                      bit should be cleared.                                                    */
15104 } ADC_CFG_RPTEN_Enum;
15105 
15106 /* =================================================  ADC CFG ADCEN [0..0]  ================================================== */
15107 typedef enum {                                  /*!< ADC_CFG_ADCEN                                                             */
15108   ADC_CFG_ADCEN_DIS                    = 0,     /*!< DIS : Disable the ADC module.                                             */
15109   ADC_CFG_ADCEN_EN                     = 1,     /*!< EN : Enable the ADC module.                                               */
15110 } ADC_CFG_ADCEN_Enum;
15111 
15112 /* =========================================================  STAT  ========================================================== */
15113 /* ================================================  ADC STAT PWDSTAT [0..0]  ================================================ */
15114 typedef enum {                                  /*!< ADC_STAT_PWDSTAT                                                          */
15115   ADC_STAT_PWDSTAT_ON                  = 0,     /*!< ON : Powered on.                                                          */
15116   ADC_STAT_PWDSTAT_POWERED_DOWN        = 1,     /*!< POWERED_DOWN : ADC Low Power Mode 1.                                      */
15117 } ADC_STAT_PWDSTAT_Enum;
15118 
15119 /* ==========================================================  SWT  ========================================================== */
15120 /* ==================================================  ADC SWT SWT [0..7]  =================================================== */
15121 typedef enum {                                  /*!< ADC_SWT_SWT                                                               */
15122   ADC_SWT_SWT_GEN_SW_TRIGGER           = 55,    /*!< GEN_SW_TRIGGER : Writing this value generates a software trigger.         */
15123 } ADC_SWT_SWT_Enum;
15124 
15125 /* ========================================================  SL0CFG  ========================================================= */
15126 /* ==============================================  ADC SL0CFG ADSEL0 [24..26]  =============================================== */
15127 typedef enum {                                  /*!< ADC_SL0CFG_ADSEL0                                                         */
15128   ADC_SL0CFG_ADSEL0_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15129                                                      module for this slot.                                                     */
15130   ADC_SL0CFG_ADSEL0_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15131                                                      module for this slot.                                                     */
15132   ADC_SL0CFG_ADSEL0_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15133                                                      module for this slot.                                                     */
15134   ADC_SL0CFG_ADSEL0_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15135                                                      module for this slot.                                                     */
15136   ADC_SL0CFG_ADSEL0_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15137                                                      divide module for this slot.                                              */
15138   ADC_SL0CFG_ADSEL0_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15139                                                      divide module for this slot.                                              */
15140   ADC_SL0CFG_ADSEL0_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15141                                                      divide module for this slot.                                              */
15142   ADC_SL0CFG_ADSEL0_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15143                                                      divide module for this slot.                                              */
15144 } ADC_SL0CFG_ADSEL0_Enum;
15145 
15146 /* ==============================================  ADC SL0CFG PRMODE0 [16..17]  ============================================== */
15147 typedef enum {                                  /*!< ADC_SL0CFG_PRMODE0                                                        */
15148   ADC_SL0CFG_PRMODE0_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15149   ADC_SL0CFG_PRMODE0_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15150   ADC_SL0CFG_PRMODE0_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15151   ADC_SL0CFG_PRMODE0_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15152 } ADC_SL0CFG_PRMODE0_Enum;
15153 
15154 /* ===============================================  ADC SL0CFG CHSEL0 [8..11]  =============================================== */
15155 typedef enum {                                  /*!< ADC_SL0CFG_CHSEL0                                                         */
15156   ADC_SL0CFG_CHSEL0_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15157   ADC_SL0CFG_CHSEL0_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15158   ADC_SL0CFG_CHSEL0_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15159   ADC_SL0CFG_CHSEL0_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15160   ADC_SL0CFG_CHSEL0_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15161   ADC_SL0CFG_CHSEL0_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15162   ADC_SL0CFG_CHSEL0_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15163   ADC_SL0CFG_CHSEL0_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15164   ADC_SL0CFG_CHSEL0_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15165   ADC_SL0CFG_CHSEL0_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15166   ADC_SL0CFG_CHSEL0_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15167                                                      pad13(P).                                                                 */
15168   ADC_SL0CFG_CHSEL0_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15169                                                      pad14(P).                                                                 */
15170   ADC_SL0CFG_CHSEL0_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15171   ADC_SL0CFG_CHSEL0_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15172   ADC_SL0CFG_CHSEL0_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15173 } ADC_SL0CFG_CHSEL0_Enum;
15174 
15175 /* ================================================  ADC SL0CFG WCEN0 [1..1]  ================================================ */
15176 typedef enum {                                  /*!< ADC_SL0CFG_WCEN0                                                          */
15177   ADC_SL0CFG_WCEN0_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 0.                              */
15178 } ADC_SL0CFG_WCEN0_Enum;
15179 
15180 /* ================================================  ADC SL0CFG SLEN0 [0..0]  ================================================ */
15181 typedef enum {                                  /*!< ADC_SL0CFG_SLEN0                                                          */
15182   ADC_SL0CFG_SLEN0_SLEN                = 1,     /*!< SLEN : Enable slot 0 for ADC conversions.                                 */
15183 } ADC_SL0CFG_SLEN0_Enum;
15184 
15185 /* ========================================================  SL1CFG  ========================================================= */
15186 /* ==============================================  ADC SL1CFG ADSEL1 [24..26]  =============================================== */
15187 typedef enum {                                  /*!< ADC_SL1CFG_ADSEL1                                                         */
15188   ADC_SL1CFG_ADSEL1_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15189                                                      module for this slot.                                                     */
15190   ADC_SL1CFG_ADSEL1_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15191                                                      module for this slot.                                                     */
15192   ADC_SL1CFG_ADSEL1_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15193                                                      module for this slot.                                                     */
15194   ADC_SL1CFG_ADSEL1_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15195                                                      module for this slot.                                                     */
15196   ADC_SL1CFG_ADSEL1_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15197                                                      divide module for this slot.                                              */
15198   ADC_SL1CFG_ADSEL1_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15199                                                      divide module for this slot.                                              */
15200   ADC_SL1CFG_ADSEL1_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15201                                                      divide module for this slot.                                              */
15202   ADC_SL1CFG_ADSEL1_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15203                                                      divide module for this slot.                                              */
15204 } ADC_SL1CFG_ADSEL1_Enum;
15205 
15206 /* ==============================================  ADC SL1CFG PRMODE1 [16..17]  ============================================== */
15207 typedef enum {                                  /*!< ADC_SL1CFG_PRMODE1                                                        */
15208   ADC_SL1CFG_PRMODE1_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15209   ADC_SL1CFG_PRMODE1_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15210   ADC_SL1CFG_PRMODE1_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15211   ADC_SL1CFG_PRMODE1_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15212 } ADC_SL1CFG_PRMODE1_Enum;
15213 
15214 /* ===============================================  ADC SL1CFG CHSEL1 [8..11]  =============================================== */
15215 typedef enum {                                  /*!< ADC_SL1CFG_CHSEL1                                                         */
15216   ADC_SL1CFG_CHSEL1_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15217   ADC_SL1CFG_CHSEL1_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15218   ADC_SL1CFG_CHSEL1_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15219   ADC_SL1CFG_CHSEL1_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15220   ADC_SL1CFG_CHSEL1_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15221   ADC_SL1CFG_CHSEL1_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15222   ADC_SL1CFG_CHSEL1_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15223   ADC_SL1CFG_CHSEL1_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15224   ADC_SL1CFG_CHSEL1_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15225   ADC_SL1CFG_CHSEL1_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15226   ADC_SL1CFG_CHSEL1_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15227                                                      pad13(P).                                                                 */
15228   ADC_SL1CFG_CHSEL1_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15229                                                      pad14(P).                                                                 */
15230   ADC_SL1CFG_CHSEL1_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15231   ADC_SL1CFG_CHSEL1_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15232   ADC_SL1CFG_CHSEL1_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15233 } ADC_SL1CFG_CHSEL1_Enum;
15234 
15235 /* ================================================  ADC SL1CFG WCEN1 [1..1]  ================================================ */
15236 typedef enum {                                  /*!< ADC_SL1CFG_WCEN1                                                          */
15237   ADC_SL1CFG_WCEN1_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 1.                              */
15238 } ADC_SL1CFG_WCEN1_Enum;
15239 
15240 /* ================================================  ADC SL1CFG SLEN1 [0..0]  ================================================ */
15241 typedef enum {                                  /*!< ADC_SL1CFG_SLEN1                                                          */
15242   ADC_SL1CFG_SLEN1_SLEN                = 1,     /*!< SLEN : Enable slot 1 for ADC conversions.                                 */
15243 } ADC_SL1CFG_SLEN1_Enum;
15244 
15245 /* ========================================================  SL2CFG  ========================================================= */
15246 /* ==============================================  ADC SL2CFG ADSEL2 [24..26]  =============================================== */
15247 typedef enum {                                  /*!< ADC_SL2CFG_ADSEL2                                                         */
15248   ADC_SL2CFG_ADSEL2_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15249                                                      module for this slot.                                                     */
15250   ADC_SL2CFG_ADSEL2_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15251                                                      module for this slot.                                                     */
15252   ADC_SL2CFG_ADSEL2_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15253                                                      module for this slot.                                                     */
15254   ADC_SL2CFG_ADSEL2_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15255                                                      module for this slot.                                                     */
15256   ADC_SL2CFG_ADSEL2_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15257                                                      divide module for this slot.                                              */
15258   ADC_SL2CFG_ADSEL2_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15259                                                      divide module for this slot.                                              */
15260   ADC_SL2CFG_ADSEL2_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15261                                                      divide module for this slot.                                              */
15262   ADC_SL2CFG_ADSEL2_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15263                                                      divide module for this slot.                                              */
15264 } ADC_SL2CFG_ADSEL2_Enum;
15265 
15266 /* ==============================================  ADC SL2CFG PRMODE2 [16..17]  ============================================== */
15267 typedef enum {                                  /*!< ADC_SL2CFG_PRMODE2                                                        */
15268   ADC_SL2CFG_PRMODE2_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15269   ADC_SL2CFG_PRMODE2_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15270   ADC_SL2CFG_PRMODE2_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15271   ADC_SL2CFG_PRMODE2_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15272 } ADC_SL2CFG_PRMODE2_Enum;
15273 
15274 /* ===============================================  ADC SL2CFG CHSEL2 [8..11]  =============================================== */
15275 typedef enum {                                  /*!< ADC_SL2CFG_CHSEL2                                                         */
15276   ADC_SL2CFG_CHSEL2_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15277   ADC_SL2CFG_CHSEL2_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15278   ADC_SL2CFG_CHSEL2_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15279   ADC_SL2CFG_CHSEL2_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15280   ADC_SL2CFG_CHSEL2_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15281   ADC_SL2CFG_CHSEL2_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15282   ADC_SL2CFG_CHSEL2_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15283   ADC_SL2CFG_CHSEL2_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15284   ADC_SL2CFG_CHSEL2_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15285   ADC_SL2CFG_CHSEL2_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15286   ADC_SL2CFG_CHSEL2_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15287                                                      pad13(P).                                                                 */
15288   ADC_SL2CFG_CHSEL2_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15289                                                      pad14(P).                                                                 */
15290   ADC_SL2CFG_CHSEL2_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15291   ADC_SL2CFG_CHSEL2_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15292   ADC_SL2CFG_CHSEL2_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15293 } ADC_SL2CFG_CHSEL2_Enum;
15294 
15295 /* ================================================  ADC SL2CFG WCEN2 [1..1]  ================================================ */
15296 typedef enum {                                  /*!< ADC_SL2CFG_WCEN2                                                          */
15297   ADC_SL2CFG_WCEN2_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 2.                              */
15298 } ADC_SL2CFG_WCEN2_Enum;
15299 
15300 /* ================================================  ADC SL2CFG SLEN2 [0..0]  ================================================ */
15301 typedef enum {                                  /*!< ADC_SL2CFG_SLEN2                                                          */
15302   ADC_SL2CFG_SLEN2_SLEN                = 1,     /*!< SLEN : Enable slot 2 for ADC conversions.                                 */
15303 } ADC_SL2CFG_SLEN2_Enum;
15304 
15305 /* ========================================================  SL3CFG  ========================================================= */
15306 /* ==============================================  ADC SL3CFG ADSEL3 [24..26]  =============================================== */
15307 typedef enum {                                  /*!< ADC_SL3CFG_ADSEL3                                                         */
15308   ADC_SL3CFG_ADSEL3_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15309                                                      module for this slot.                                                     */
15310   ADC_SL3CFG_ADSEL3_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15311                                                      module for this slot.                                                     */
15312   ADC_SL3CFG_ADSEL3_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15313                                                      module for this slot.                                                     */
15314   ADC_SL3CFG_ADSEL3_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15315                                                      module for this slot.                                                     */
15316   ADC_SL3CFG_ADSEL3_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15317                                                      divide module for this slot.                                              */
15318   ADC_SL3CFG_ADSEL3_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15319                                                      divide module for this slot.                                              */
15320   ADC_SL3CFG_ADSEL3_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15321                                                      divide module for this slot.                                              */
15322   ADC_SL3CFG_ADSEL3_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15323                                                      divide module for this slot.                                              */
15324 } ADC_SL3CFG_ADSEL3_Enum;
15325 
15326 /* ==============================================  ADC SL3CFG PRMODE3 [16..17]  ============================================== */
15327 typedef enum {                                  /*!< ADC_SL3CFG_PRMODE3                                                        */
15328   ADC_SL3CFG_PRMODE3_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15329   ADC_SL3CFG_PRMODE3_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15330   ADC_SL3CFG_PRMODE3_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15331   ADC_SL3CFG_PRMODE3_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15332 } ADC_SL3CFG_PRMODE3_Enum;
15333 
15334 /* ===============================================  ADC SL3CFG CHSEL3 [8..11]  =============================================== */
15335 typedef enum {                                  /*!< ADC_SL3CFG_CHSEL3                                                         */
15336   ADC_SL3CFG_CHSEL3_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15337   ADC_SL3CFG_CHSEL3_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15338   ADC_SL3CFG_CHSEL3_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15339   ADC_SL3CFG_CHSEL3_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15340   ADC_SL3CFG_CHSEL3_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15341   ADC_SL3CFG_CHSEL3_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15342   ADC_SL3CFG_CHSEL3_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15343   ADC_SL3CFG_CHSEL3_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15344   ADC_SL3CFG_CHSEL3_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15345   ADC_SL3CFG_CHSEL3_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15346   ADC_SL3CFG_CHSEL3_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15347                                                      pad13(P).                                                                 */
15348   ADC_SL3CFG_CHSEL3_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15349                                                      pad14(P).                                                                 */
15350   ADC_SL3CFG_CHSEL3_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15351   ADC_SL3CFG_CHSEL3_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15352   ADC_SL3CFG_CHSEL3_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15353 } ADC_SL3CFG_CHSEL3_Enum;
15354 
15355 /* ================================================  ADC SL3CFG WCEN3 [1..1]  ================================================ */
15356 typedef enum {                                  /*!< ADC_SL3CFG_WCEN3                                                          */
15357   ADC_SL3CFG_WCEN3_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 3.                              */
15358 } ADC_SL3CFG_WCEN3_Enum;
15359 
15360 /* ================================================  ADC SL3CFG SLEN3 [0..0]  ================================================ */
15361 typedef enum {                                  /*!< ADC_SL3CFG_SLEN3                                                          */
15362   ADC_SL3CFG_SLEN3_SLEN                = 1,     /*!< SLEN : Enable slot 3 for ADC conversions.                                 */
15363 } ADC_SL3CFG_SLEN3_Enum;
15364 
15365 /* ========================================================  SL4CFG  ========================================================= */
15366 /* ==============================================  ADC SL4CFG ADSEL4 [24..26]  =============================================== */
15367 typedef enum {                                  /*!< ADC_SL4CFG_ADSEL4                                                         */
15368   ADC_SL4CFG_ADSEL4_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15369                                                      module for this slot.                                                     */
15370   ADC_SL4CFG_ADSEL4_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15371                                                      module for this slot.                                                     */
15372   ADC_SL4CFG_ADSEL4_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15373                                                      module for this slot.                                                     */
15374   ADC_SL4CFG_ADSEL4_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15375                                                      module for this slot.                                                     */
15376   ADC_SL4CFG_ADSEL4_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15377                                                      divide module for this slot.                                              */
15378   ADC_SL4CFG_ADSEL4_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15379                                                      divide module for this slot.                                              */
15380   ADC_SL4CFG_ADSEL4_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15381                                                      divide module for this slot.                                              */
15382   ADC_SL4CFG_ADSEL4_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15383                                                      divide module for this slot.                                              */
15384 } ADC_SL4CFG_ADSEL4_Enum;
15385 
15386 /* ==============================================  ADC SL4CFG PRMODE4 [16..17]  ============================================== */
15387 typedef enum {                                  /*!< ADC_SL4CFG_PRMODE4                                                        */
15388   ADC_SL4CFG_PRMODE4_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15389   ADC_SL4CFG_PRMODE4_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15390   ADC_SL4CFG_PRMODE4_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15391   ADC_SL4CFG_PRMODE4_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15392 } ADC_SL4CFG_PRMODE4_Enum;
15393 
15394 /* ===============================================  ADC SL4CFG CHSEL4 [8..11]  =============================================== */
15395 typedef enum {                                  /*!< ADC_SL4CFG_CHSEL4                                                         */
15396   ADC_SL4CFG_CHSEL4_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15397   ADC_SL4CFG_CHSEL4_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15398   ADC_SL4CFG_CHSEL4_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15399   ADC_SL4CFG_CHSEL4_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15400   ADC_SL4CFG_CHSEL4_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15401   ADC_SL4CFG_CHSEL4_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15402   ADC_SL4CFG_CHSEL4_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15403   ADC_SL4CFG_CHSEL4_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15404   ADC_SL4CFG_CHSEL4_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15405   ADC_SL4CFG_CHSEL4_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15406   ADC_SL4CFG_CHSEL4_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15407                                                      pad13(P).                                                                 */
15408   ADC_SL4CFG_CHSEL4_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15409                                                      pad14(P).                                                                 */
15410   ADC_SL4CFG_CHSEL4_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15411   ADC_SL4CFG_CHSEL4_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15412   ADC_SL4CFG_CHSEL4_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15413 } ADC_SL4CFG_CHSEL4_Enum;
15414 
15415 /* ================================================  ADC SL4CFG WCEN4 [1..1]  ================================================ */
15416 typedef enum {                                  /*!< ADC_SL4CFG_WCEN4                                                          */
15417   ADC_SL4CFG_WCEN4_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 4.                              */
15418 } ADC_SL4CFG_WCEN4_Enum;
15419 
15420 /* ================================================  ADC SL4CFG SLEN4 [0..0]  ================================================ */
15421 typedef enum {                                  /*!< ADC_SL4CFG_SLEN4                                                          */
15422   ADC_SL4CFG_SLEN4_SLEN                = 1,     /*!< SLEN : Enable slot 4 for ADC conversions.                                 */
15423 } ADC_SL4CFG_SLEN4_Enum;
15424 
15425 /* ========================================================  SL5CFG  ========================================================= */
15426 /* ==============================================  ADC SL5CFG ADSEL5 [24..26]  =============================================== */
15427 typedef enum {                                  /*!< ADC_SL5CFG_ADSEL5                                                         */
15428   ADC_SL5CFG_ADSEL5_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15429                                                      module for this slot.                                                     */
15430   ADC_SL5CFG_ADSEL5_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15431                                                      module for this slot.                                                     */
15432   ADC_SL5CFG_ADSEL5_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15433                                                      module for this slot.                                                     */
15434   ADC_SL5CFG_ADSEL5_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15435                                                      module for this slot.                                                     */
15436   ADC_SL5CFG_ADSEL5_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15437                                                      divide module for this slot.                                              */
15438   ADC_SL5CFG_ADSEL5_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15439                                                      divide module for this slot.                                              */
15440   ADC_SL5CFG_ADSEL5_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15441                                                      divide module for this slot.                                              */
15442   ADC_SL5CFG_ADSEL5_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15443                                                      divide module for this slot.                                              */
15444 } ADC_SL5CFG_ADSEL5_Enum;
15445 
15446 /* ==============================================  ADC SL5CFG PRMODE5 [16..17]  ============================================== */
15447 typedef enum {                                  /*!< ADC_SL5CFG_PRMODE5                                                        */
15448   ADC_SL5CFG_PRMODE5_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15449   ADC_SL5CFG_PRMODE5_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15450   ADC_SL5CFG_PRMODE5_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15451   ADC_SL5CFG_PRMODE5_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15452 } ADC_SL5CFG_PRMODE5_Enum;
15453 
15454 /* ===============================================  ADC SL5CFG CHSEL5 [8..11]  =============================================== */
15455 typedef enum {                                  /*!< ADC_SL5CFG_CHSEL5                                                         */
15456   ADC_SL5CFG_CHSEL5_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15457   ADC_SL5CFG_CHSEL5_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15458   ADC_SL5CFG_CHSEL5_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15459   ADC_SL5CFG_CHSEL5_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15460   ADC_SL5CFG_CHSEL5_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15461   ADC_SL5CFG_CHSEL5_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15462   ADC_SL5CFG_CHSEL5_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15463   ADC_SL5CFG_CHSEL5_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15464   ADC_SL5CFG_CHSEL5_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15465   ADC_SL5CFG_CHSEL5_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15466   ADC_SL5CFG_CHSEL5_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15467                                                      pad13(P).                                                                 */
15468   ADC_SL5CFG_CHSEL5_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15469                                                      pad14(P).                                                                 */
15470   ADC_SL5CFG_CHSEL5_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15471   ADC_SL5CFG_CHSEL5_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15472   ADC_SL5CFG_CHSEL5_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15473 } ADC_SL5CFG_CHSEL5_Enum;
15474 
15475 /* ================================================  ADC SL5CFG WCEN5 [1..1]  ================================================ */
15476 typedef enum {                                  /*!< ADC_SL5CFG_WCEN5                                                          */
15477   ADC_SL5CFG_WCEN5_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 5.                              */
15478 } ADC_SL5CFG_WCEN5_Enum;
15479 
15480 /* ================================================  ADC SL5CFG SLEN5 [0..0]  ================================================ */
15481 typedef enum {                                  /*!< ADC_SL5CFG_SLEN5                                                          */
15482   ADC_SL5CFG_SLEN5_SLEN                = 1,     /*!< SLEN : Enable slot 5 for ADC conversions.                                 */
15483 } ADC_SL5CFG_SLEN5_Enum;
15484 
15485 /* ========================================================  SL6CFG  ========================================================= */
15486 /* ==============================================  ADC SL6CFG ADSEL6 [24..26]  =============================================== */
15487 typedef enum {                                  /*!< ADC_SL6CFG_ADSEL6                                                         */
15488   ADC_SL6CFG_ADSEL6_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15489                                                      module for this slot.                                                     */
15490   ADC_SL6CFG_ADSEL6_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15491                                                      module for this slot.                                                     */
15492   ADC_SL6CFG_ADSEL6_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15493                                                      module for this slot.                                                     */
15494   ADC_SL6CFG_ADSEL6_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15495                                                      module for this slot.                                                     */
15496   ADC_SL6CFG_ADSEL6_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15497                                                      divide module for this slot.                                              */
15498   ADC_SL6CFG_ADSEL6_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15499                                                      divide module for this slot.                                              */
15500   ADC_SL6CFG_ADSEL6_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15501                                                      divide module for this slot.                                              */
15502   ADC_SL6CFG_ADSEL6_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15503                                                      divide module for this slot.                                              */
15504 } ADC_SL6CFG_ADSEL6_Enum;
15505 
15506 /* ==============================================  ADC SL6CFG PRMODE6 [16..17]  ============================================== */
15507 typedef enum {                                  /*!< ADC_SL6CFG_PRMODE6                                                        */
15508   ADC_SL6CFG_PRMODE6_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15509   ADC_SL6CFG_PRMODE6_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15510   ADC_SL6CFG_PRMODE6_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15511   ADC_SL6CFG_PRMODE6_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15512 } ADC_SL6CFG_PRMODE6_Enum;
15513 
15514 /* ===============================================  ADC SL6CFG CHSEL6 [8..11]  =============================================== */
15515 typedef enum {                                  /*!< ADC_SL6CFG_CHSEL6                                                         */
15516   ADC_SL6CFG_CHSEL6_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15517   ADC_SL6CFG_CHSEL6_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15518   ADC_SL6CFG_CHSEL6_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15519   ADC_SL6CFG_CHSEL6_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15520   ADC_SL6CFG_CHSEL6_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15521   ADC_SL6CFG_CHSEL6_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15522   ADC_SL6CFG_CHSEL6_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15523   ADC_SL6CFG_CHSEL6_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15524   ADC_SL6CFG_CHSEL6_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15525   ADC_SL6CFG_CHSEL6_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15526   ADC_SL6CFG_CHSEL6_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15527                                                      pad13(P).                                                                 */
15528   ADC_SL6CFG_CHSEL6_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15529                                                      pad14(P).                                                                 */
15530   ADC_SL6CFG_CHSEL6_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15531   ADC_SL6CFG_CHSEL6_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15532   ADC_SL6CFG_CHSEL6_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15533 } ADC_SL6CFG_CHSEL6_Enum;
15534 
15535 /* ================================================  ADC SL6CFG WCEN6 [1..1]  ================================================ */
15536 typedef enum {                                  /*!< ADC_SL6CFG_WCEN6                                                          */
15537   ADC_SL6CFG_WCEN6_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 6.                              */
15538 } ADC_SL6CFG_WCEN6_Enum;
15539 
15540 /* ================================================  ADC SL6CFG SLEN6 [0..0]  ================================================ */
15541 typedef enum {                                  /*!< ADC_SL6CFG_SLEN6                                                          */
15542   ADC_SL6CFG_SLEN6_SLEN                = 1,     /*!< SLEN : Enable slot 6 for ADC conversions.                                 */
15543 } ADC_SL6CFG_SLEN6_Enum;
15544 
15545 /* ========================================================  SL7CFG  ========================================================= */
15546 /* ==============================================  ADC SL7CFG ADSEL7 [24..26]  =============================================== */
15547 typedef enum {                                  /*!< ADC_SL7CFG_ADSEL7                                                         */
15548   ADC_SL7CFG_ADSEL7_AVG_1_MSRMT        = 0,     /*!< AVG_1_MSRMT : Average in 1 measurement in the accumulate divide
15549                                                      module for this slot.                                                     */
15550   ADC_SL7CFG_ADSEL7_AVG_2_MSRMTS       = 1,     /*!< AVG_2_MSRMTS : Average in 2 measurements in the accumulate divide
15551                                                      module for this slot.                                                     */
15552   ADC_SL7CFG_ADSEL7_AVG_4_MSRMTS       = 2,     /*!< AVG_4_MSRMTS : Average in 4 measurements in the accumulate divide
15553                                                      module for this slot.                                                     */
15554   ADC_SL7CFG_ADSEL7_AVG_8_MSRMT        = 3,     /*!< AVG_8_MSRMT : Average in 8 measurements in the accumulate divide
15555                                                      module for this slot.                                                     */
15556   ADC_SL7CFG_ADSEL7_AVG_16_MSRMTS      = 4,     /*!< AVG_16_MSRMTS : Average in 16 measurements in the accumulate
15557                                                      divide module for this slot.                                              */
15558   ADC_SL7CFG_ADSEL7_AVG_32_MSRMTS      = 5,     /*!< AVG_32_MSRMTS : Average in 32 measurements in the accumulate
15559                                                      divide module for this slot.                                              */
15560   ADC_SL7CFG_ADSEL7_AVG_64_MSRMTS      = 6,     /*!< AVG_64_MSRMTS : Average in 64 measurements in the accumulate
15561                                                      divide module for this slot.                                              */
15562   ADC_SL7CFG_ADSEL7_AVG_128_MSRMTS     = 7,     /*!< AVG_128_MSRMTS : Average in 128 measurements in the accumulate
15563                                                      divide module for this slot.                                              */
15564 } ADC_SL7CFG_ADSEL7_Enum;
15565 
15566 /* ==============================================  ADC SL7CFG PRMODE7 [16..17]  ============================================== */
15567 typedef enum {                                  /*!< ADC_SL7CFG_PRMODE7                                                        */
15568   ADC_SL7CFG_PRMODE7_P14B              = 0,     /*!< P14B : 14-bit precision mode                                              */
15569   ADC_SL7CFG_PRMODE7_P12B              = 1,     /*!< P12B : 12-bit precision mode                                              */
15570   ADC_SL7CFG_PRMODE7_P10B              = 2,     /*!< P10B : 10-bit precision mode                                              */
15571   ADC_SL7CFG_PRMODE7_P8B               = 3,     /*!< P8B : 8-bit precision mode                                                */
15572 } ADC_SL7CFG_PRMODE7_Enum;
15573 
15574 /* ===============================================  ADC SL7CFG CHSEL7 [8..11]  =============================================== */
15575 typedef enum {                                  /*!< ADC_SL7CFG_CHSEL7                                                         */
15576   ADC_SL7CFG_CHSEL7_SE0                = 0,     /*!< SE0 : single ended external GPIO connection to pad16.                     */
15577   ADC_SL7CFG_CHSEL7_SE1                = 1,     /*!< SE1 : single ended external GPIO connection to pad29.                     */
15578   ADC_SL7CFG_CHSEL7_SE2                = 2,     /*!< SE2 : single ended external GPIO connection to pad11.                     */
15579   ADC_SL7CFG_CHSEL7_SE3                = 3,     /*!< SE3 : single ended external GPIO connection to pad31.                     */
15580   ADC_SL7CFG_CHSEL7_SE4                = 4,     /*!< SE4 : single ended external GPIO connection to pad32.                     */
15581   ADC_SL7CFG_CHSEL7_SE5                = 5,     /*!< SE5 : single ended external GPIO connection to pad33.                     */
15582   ADC_SL7CFG_CHSEL7_SE6                = 6,     /*!< SE6 : single ended external GPIO connection to pad34.                     */
15583   ADC_SL7CFG_CHSEL7_SE7                = 7,     /*!< SE7 : single ended external GPIO connection to pad35.                     */
15584   ADC_SL7CFG_CHSEL7_SE8                = 8,     /*!< SE8 : single ended external GPIO connection to pad13.                     */
15585   ADC_SL7CFG_CHSEL7_SE9                = 9,     /*!< SE9 : single ended external GPIO connection to pad12.                     */
15586   ADC_SL7CFG_CHSEL7_DF0                = 10,    /*!< DF0 : differential external GPIO connections to pad12(N) and
15587                                                      pad13(P).                                                                 */
15588   ADC_SL7CFG_CHSEL7_DF1                = 11,    /*!< DF1 : differential external GPIO connections to pad15(N) and
15589                                                      pad14(P).                                                                 */
15590   ADC_SL7CFG_CHSEL7_TEMP               = 12,    /*!< TEMP : internal temperature sensor.                                       */
15591   ADC_SL7CFG_CHSEL7_BATT               = 13,    /*!< BATT : internal voltage divide-by-3 connection.                           */
15592   ADC_SL7CFG_CHSEL7_VSS                = 14,    /*!< VSS : Input VSS                                                           */
15593 } ADC_SL7CFG_CHSEL7_Enum;
15594 
15595 /* ================================================  ADC SL7CFG WCEN7 [1..1]  ================================================ */
15596 typedef enum {                                  /*!< ADC_SL7CFG_WCEN7                                                          */
15597   ADC_SL7CFG_WCEN7_WCEN                = 1,     /*!< WCEN : Enable the window compare for slot 7.                              */
15598 } ADC_SL7CFG_WCEN7_Enum;
15599 
15600 /* ================================================  ADC SL7CFG SLEN7 [0..0]  ================================================ */
15601 typedef enum {                                  /*!< ADC_SL7CFG_SLEN7                                                          */
15602   ADC_SL7CFG_SLEN7_SLEN                = 1,     /*!< SLEN : Enable slot 7 for ADC conversions.                                 */
15603 } ADC_SL7CFG_SLEN7_Enum;
15604 
15605 /* =========================================================  WULIM  ========================================================= */
15606 /* =========================================================  WLLIM  ========================================================= */
15607 /* ========================================================  SCWLIM  ========================================================= */
15608 /* =========================================================  FIFO  ========================================================== */
15609 /* ========================================================  FIFOPR  ========================================================= */
15610 /* =========================================================  INTEN  ========================================================= */
15611 /* =================================================  ADC INTEN DERR [7..7]  ================================================= */
15612 typedef enum {                                  /*!< ADC_INTEN_DERR                                                            */
15613   ADC_INTEN_DERR_DMAERROR              = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
15614 } ADC_INTEN_DERR_Enum;
15615 
15616 /* =================================================  ADC INTEN DCMP [6..6]  ================================================= */
15617 typedef enum {                                  /*!< ADC_INTEN_DCMP                                                            */
15618   ADC_INTEN_DCMP_DMACOMPLETE           = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
15619 } ADC_INTEN_DCMP_Enum;
15620 
15621 /* ================================================  ADC INTEN WCINC [5..5]  ================================================= */
15622 typedef enum {                                  /*!< ADC_INTEN_WCINC                                                           */
15623   ADC_INTEN_WCINC_WCINCINT             = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
15624 } ADC_INTEN_WCINC_Enum;
15625 
15626 /* ================================================  ADC INTEN WCEXC [4..4]  ================================================= */
15627 typedef enum {                                  /*!< ADC_INTEN_WCEXC                                                           */
15628   ADC_INTEN_WCEXC_WCEXCINT             = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
15629 } ADC_INTEN_WCEXC_Enum;
15630 
15631 /* ===============================================  ADC INTEN FIFOOVR2 [3..3]  =============================================== */
15632 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR2                                                        */
15633   ADC_INTEN_FIFOOVR2_FIFOFULLINT       = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
15634 } ADC_INTEN_FIFOOVR2_Enum;
15635 
15636 /* ===============================================  ADC INTEN FIFOOVR1 [2..2]  =============================================== */
15637 typedef enum {                                  /*!< ADC_INTEN_FIFOOVR1                                                        */
15638   ADC_INTEN_FIFOOVR1_FIFO75INT         = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
15639 } ADC_INTEN_FIFOOVR1_Enum;
15640 
15641 /* ================================================  ADC INTEN SCNCMP [1..1]  ================================================ */
15642 typedef enum {                                  /*!< ADC_INTEN_SCNCMP                                                          */
15643   ADC_INTEN_SCNCMP_SCNCMPINT           = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
15644 } ADC_INTEN_SCNCMP_Enum;
15645 
15646 /* ================================================  ADC INTEN CNVCMP [0..0]  ================================================ */
15647 typedef enum {                                  /*!< ADC_INTEN_CNVCMP                                                          */
15648   ADC_INTEN_CNVCMP_CNVCMPINT           = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
15649 } ADC_INTEN_CNVCMP_Enum;
15650 
15651 /* ========================================================  INTSTAT  ======================================================== */
15652 /* ================================================  ADC INTSTAT DERR [7..7]  ================================================ */
15653 typedef enum {                                  /*!< ADC_INTSTAT_DERR                                                          */
15654   ADC_INTSTAT_DERR_DMAERROR            = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
15655 } ADC_INTSTAT_DERR_Enum;
15656 
15657 /* ================================================  ADC INTSTAT DCMP [6..6]  ================================================ */
15658 typedef enum {                                  /*!< ADC_INTSTAT_DCMP                                                          */
15659   ADC_INTSTAT_DCMP_DMACOMPLETE         = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
15660 } ADC_INTSTAT_DCMP_Enum;
15661 
15662 /* ===============================================  ADC INTSTAT WCINC [5..5]  ================================================ */
15663 typedef enum {                                  /*!< ADC_INTSTAT_WCINC                                                         */
15664   ADC_INTSTAT_WCINC_WCINCINT           = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
15665 } ADC_INTSTAT_WCINC_Enum;
15666 
15667 /* ===============================================  ADC INTSTAT WCEXC [4..4]  ================================================ */
15668 typedef enum {                                  /*!< ADC_INTSTAT_WCEXC                                                         */
15669   ADC_INTSTAT_WCEXC_WCEXCINT           = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
15670 } ADC_INTSTAT_WCEXC_Enum;
15671 
15672 /* ==============================================  ADC INTSTAT FIFOOVR2 [3..3]  ============================================== */
15673 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR2                                                      */
15674   ADC_INTSTAT_FIFOOVR2_FIFOFULLINT     = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
15675 } ADC_INTSTAT_FIFOOVR2_Enum;
15676 
15677 /* ==============================================  ADC INTSTAT FIFOOVR1 [2..2]  ============================================== */
15678 typedef enum {                                  /*!< ADC_INTSTAT_FIFOOVR1                                                      */
15679   ADC_INTSTAT_FIFOOVR1_FIFO75INT       = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
15680 } ADC_INTSTAT_FIFOOVR1_Enum;
15681 
15682 /* ===============================================  ADC INTSTAT SCNCMP [1..1]  =============================================== */
15683 typedef enum {                                  /*!< ADC_INTSTAT_SCNCMP                                                        */
15684   ADC_INTSTAT_SCNCMP_SCNCMPINT         = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
15685 } ADC_INTSTAT_SCNCMP_Enum;
15686 
15687 /* ===============================================  ADC INTSTAT CNVCMP [0..0]  =============================================== */
15688 typedef enum {                                  /*!< ADC_INTSTAT_CNVCMP                                                        */
15689   ADC_INTSTAT_CNVCMP_CNVCMPINT         = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
15690 } ADC_INTSTAT_CNVCMP_Enum;
15691 
15692 /* ========================================================  INTCLR  ========================================================= */
15693 /* ================================================  ADC INTCLR DERR [7..7]  ================================================= */
15694 typedef enum {                                  /*!< ADC_INTCLR_DERR                                                           */
15695   ADC_INTCLR_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
15696 } ADC_INTCLR_DERR_Enum;
15697 
15698 /* ================================================  ADC INTCLR DCMP [6..6]  ================================================= */
15699 typedef enum {                                  /*!< ADC_INTCLR_DCMP                                                           */
15700   ADC_INTCLR_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
15701 } ADC_INTCLR_DCMP_Enum;
15702 
15703 /* ================================================  ADC INTCLR WCINC [5..5]  ================================================ */
15704 typedef enum {                                  /*!< ADC_INTCLR_WCINC                                                          */
15705   ADC_INTCLR_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
15706 } ADC_INTCLR_WCINC_Enum;
15707 
15708 /* ================================================  ADC INTCLR WCEXC [4..4]  ================================================ */
15709 typedef enum {                                  /*!< ADC_INTCLR_WCEXC                                                          */
15710   ADC_INTCLR_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
15711 } ADC_INTCLR_WCEXC_Enum;
15712 
15713 /* ==============================================  ADC INTCLR FIFOOVR2 [3..3]  =============================================== */
15714 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR2                                                       */
15715   ADC_INTCLR_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
15716 } ADC_INTCLR_FIFOOVR2_Enum;
15717 
15718 /* ==============================================  ADC INTCLR FIFOOVR1 [2..2]  =============================================== */
15719 typedef enum {                                  /*!< ADC_INTCLR_FIFOOVR1                                                       */
15720   ADC_INTCLR_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
15721 } ADC_INTCLR_FIFOOVR1_Enum;
15722 
15723 /* ===============================================  ADC INTCLR SCNCMP [1..1]  ================================================ */
15724 typedef enum {                                  /*!< ADC_INTCLR_SCNCMP                                                         */
15725   ADC_INTCLR_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
15726 } ADC_INTCLR_SCNCMP_Enum;
15727 
15728 /* ===============================================  ADC INTCLR CNVCMP [0..0]  ================================================ */
15729 typedef enum {                                  /*!< ADC_INTCLR_CNVCMP                                                         */
15730   ADC_INTCLR_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
15731 } ADC_INTCLR_CNVCMP_Enum;
15732 
15733 /* ========================================================  INTSET  ========================================================= */
15734 /* ================================================  ADC INTSET DERR [7..7]  ================================================= */
15735 typedef enum {                                  /*!< ADC_INTSET_DERR                                                           */
15736   ADC_INTSET_DERR_DMAERROR             = 1,     /*!< DMAERROR : DMA Error Condition Occurred                                   */
15737 } ADC_INTSET_DERR_Enum;
15738 
15739 /* ================================================  ADC INTSET DCMP [6..6]  ================================================= */
15740 typedef enum {                                  /*!< ADC_INTSET_DCMP                                                           */
15741   ADC_INTSET_DCMP_DMACOMPLETE          = 1,     /*!< DMACOMPLETE : DMA Completed a transfer                                    */
15742 } ADC_INTSET_DCMP_Enum;
15743 
15744 /* ================================================  ADC INTSET WCINC [5..5]  ================================================ */
15745 typedef enum {                                  /*!< ADC_INTSET_WCINC                                                          */
15746   ADC_INTSET_WCINC_WCINCINT            = 1,     /*!< WCINCINT : Window comparator voltage incursion interrupt.                 */
15747 } ADC_INTSET_WCINC_Enum;
15748 
15749 /* ================================================  ADC INTSET WCEXC [4..4]  ================================================ */
15750 typedef enum {                                  /*!< ADC_INTSET_WCEXC                                                          */
15751   ADC_INTSET_WCEXC_WCEXCINT            = 1,     /*!< WCEXCINT : Window comparator voltage excursion interrupt.                 */
15752 } ADC_INTSET_WCEXC_Enum;
15753 
15754 /* ==============================================  ADC INTSET FIFOOVR2 [3..3]  =============================================== */
15755 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR2                                                       */
15756   ADC_INTSET_FIFOOVR2_FIFOFULLINT      = 1,     /*!< FIFOFULLINT : FIFO 100 percent full interrupt.                            */
15757 } ADC_INTSET_FIFOOVR2_Enum;
15758 
15759 /* ==============================================  ADC INTSET FIFOOVR1 [2..2]  =============================================== */
15760 typedef enum {                                  /*!< ADC_INTSET_FIFOOVR1                                                       */
15761   ADC_INTSET_FIFOOVR1_FIFO75INT        = 1,     /*!< FIFO75INT : FIFO 75 percent full interrupt.                               */
15762 } ADC_INTSET_FIFOOVR1_Enum;
15763 
15764 /* ===============================================  ADC INTSET SCNCMP [1..1]  ================================================ */
15765 typedef enum {                                  /*!< ADC_INTSET_SCNCMP                                                         */
15766   ADC_INTSET_SCNCMP_SCNCMPINT          = 1,     /*!< SCNCMPINT : ADC scan complete interrupt.                                  */
15767 } ADC_INTSET_SCNCMP_Enum;
15768 
15769 /* ===============================================  ADC INTSET CNVCMP [0..0]  ================================================ */
15770 typedef enum {                                  /*!< ADC_INTSET_CNVCMP                                                         */
15771   ADC_INTSET_CNVCMP_CNVCMPINT          = 1,     /*!< CNVCMPINT : ADC conversion complete interrupt.                            */
15772 } ADC_INTSET_CNVCMP_Enum;
15773 
15774 /* =======================================================  DMATRIGEN  ======================================================= */
15775 /* ======================================================  DMATRIGSTAT  ====================================================== */
15776 /* ========================================================  DMACFG  ========================================================= */
15777 /* ==============================================  ADC DMACFG DMAMSK [17..17]  =============================================== */
15778 typedef enum {                                  /*!< ADC_DMACFG_DMAMSK                                                         */
15779   ADC_DMACFG_DMAMSK_DIS                = 0,     /*!< DIS : FIFO Contents are copied directly to memory without modification.   */
15780   ADC_DMACFG_DMAMSK_EN                 = 1,     /*!< EN : Only the FIFODATA contents are copied to memory on DMA
15781                                                      transfers. The SLOTNUM and FIFOCNT contents are cleared
15782                                                      to zero.                                                                  */
15783 } ADC_DMACFG_DMAMSK_Enum;
15784 
15785 /* ============================================  ADC DMACFG DMAHONSTAT [16..16]  ============================================= */
15786 typedef enum {                                  /*!< ADC_DMACFG_DMAHONSTAT                                                     */
15787   ADC_DMACFG_DMAHONSTAT_DIS            = 0,     /*!< DIS : ADC conversions will continue regardless of DMA status
15788                                                      register                                                                  */
15789   ADC_DMACFG_DMAHONSTAT_EN             = 1,     /*!< EN : ADC conversions will not progress if DMAERR or DMACPL bits
15790                                                      in DMA status register are set.                                           */
15791 } ADC_DMACFG_DMAHONSTAT_Enum;
15792 
15793 /* ==============================================  ADC DMACFG DMADYNPRI [9..9]  ============================================== */
15794 typedef enum {                                  /*!< ADC_DMACFG_DMADYNPRI                                                      */
15795   ADC_DMACFG_DMADYNPRI_DIS             = 0,     /*!< DIS : Disable dynamic priority (use DMAPRI setting only)                  */
15796   ADC_DMACFG_DMADYNPRI_EN              = 1,     /*!< EN : Enable dynamic priority                                              */
15797 } ADC_DMACFG_DMADYNPRI_Enum;
15798 
15799 /* ===============================================  ADC DMACFG DMAPRI [8..8]  ================================================ */
15800 typedef enum {                                  /*!< ADC_DMACFG_DMAPRI                                                         */
15801   ADC_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
15802   ADC_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
15803 } ADC_DMACFG_DMAPRI_Enum;
15804 
15805 /* ===============================================  ADC DMACFG DMADIR [2..2]  ================================================ */
15806 typedef enum {                                  /*!< ADC_DMACFG_DMADIR                                                         */
15807   ADC_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
15808   ADC_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
15809 } ADC_DMACFG_DMADIR_Enum;
15810 
15811 /* ================================================  ADC DMACFG DMAEN [0..0]  ================================================ */
15812 typedef enum {                                  /*!< ADC_DMACFG_DMAEN                                                          */
15813   ADC_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
15814   ADC_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
15815 } ADC_DMACFG_DMAEN_Enum;
15816 
15817 /* ======================================================  DMATOTCOUNT  ====================================================== */
15818 /* ======================================================  DMATARGADDR  ====================================================== */
15819 /* ========================================================  DMASTAT  ======================================================== */
15820 
15821 
15822 /* =========================================================================================================================== */
15823 /* ================                                          APBDMA                                           ================ */
15824 /* =========================================================================================================================== */
15825 
15826 /* ========================================================  BBVALUE  ======================================================== */
15827 /* ======================================================  BBSETCLEAR  ======================================================= */
15828 /* ========================================================  BBINPUT  ======================================================== */
15829 /* =======================================================  DEBUGDATA  ======================================================= */
15830 /* =========================================================  DEBUG  ========================================================= */
15831 /* ==============================================  APBDMA DEBUG DEBUGEN [0..3]  ============================================== */
15832 typedef enum {                                  /*!< APBDMA_DEBUG_DEBUGEN                                                      */
15833   APBDMA_DEBUG_DEBUGEN_OFF             = 0,     /*!< OFF : Debug Disabled                                                      */
15834   APBDMA_DEBUG_DEBUGEN_ARB             = 1,     /*!< ARB : Debug ARB values                                                    */
15835 } APBDMA_DEBUG_DEBUGEN_Enum;
15836 
15837 
15838 
15839 /* =========================================================================================================================== */
15840 /* ================                                           BLEIF                                           ================ */
15841 /* =========================================================================================================================== */
15842 
15843 /* =========================================================  FIFO  ========================================================== */
15844 /* ========================================================  FIFOPTR  ======================================================== */
15845 /* ========================================================  FIFOTHR  ======================================================== */
15846 /* ========================================================  FIFOPOP  ======================================================== */
15847 /* =======================================================  FIFOPUSH  ======================================================== */
15848 /* =======================================================  FIFOCTRL  ======================================================== */
15849 /* ========================================================  FIFOLOC  ======================================================== */
15850 /* ========================================================  CLKCFG  ========================================================= */
15851 /* ===============================================  BLEIF CLKCFG FSEL [8..10]  =============================================== */
15852 typedef enum {                                  /*!< BLEIF_CLKCFG_FSEL                                                         */
15853   BLEIF_CLKCFG_FSEL_MIN_PWR            = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
15854                                                      be used whenever the IOM is not active.                                   */
15855   BLEIF_CLKCFG_FSEL_HFRC               = 1,     /*!< HFRC : Selects the HFRC as the input clock.                               */
15856   BLEIF_CLKCFG_FSEL_HFRC_DIV2          = 2,     /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock.                      */
15857   BLEIF_CLKCFG_FSEL_HFRC_DIV4          = 3,     /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock.                      */
15858   BLEIF_CLKCFG_FSEL_HFRC_DIV8          = 4,     /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock.                      */
15859   BLEIF_CLKCFG_FSEL_HFRC_DIV16         = 5,     /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock.                    */
15860   BLEIF_CLKCFG_FSEL_HFRC_DIV32         = 6,     /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock.                    */
15861   BLEIF_CLKCFG_FSEL_HFRC_DIV64         = 7,     /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock.                    */
15862 } BLEIF_CLKCFG_FSEL_Enum;
15863 
15864 /* ==========================================================  CMD  ========================================================== */
15865 /* =================================================  BLEIF CMD CMD [0..4]  ================================================== */
15866 typedef enum {                                  /*!< BLEIF_CMD_CMD                                                             */
15867   BLEIF_CMD_CMD_WRITE                  = 1,     /*!< WRITE : Write command using count of offset bytes specified
15868                                                      in the OFFSETCNT field                                                    */
15869   BLEIF_CMD_CMD_READ                   = 2,     /*!< READ : Read command using count of offset bytes specified in
15870                                                      the OFFSETCNT field                                                       */
15871 } BLEIF_CMD_CMD_Enum;
15872 
15873 /* ========================================================  CMDRPT  ========================================================= */
15874 /* =======================================================  OFFSETHI  ======================================================== */
15875 /* ========================================================  CMDSTAT  ======================================================== */
15876 /* =============================================  BLEIF CMDSTAT CMDSTAT [5..7]  ============================================== */
15877 typedef enum {                                  /*!< BLEIF_CMDSTAT_CMDSTAT                                                     */
15878   BLEIF_CMDSTAT_CMDSTAT_ERR            = 1,     /*!< ERR : Error encountered with command                                      */
15879   BLEIF_CMDSTAT_CMDSTAT_ACTIVE         = 2,     /*!< ACTIVE : Actively processing command                                      */
15880   BLEIF_CMDSTAT_CMDSTAT_IDLE           = 4,     /*!< IDLE : Idle state, no active command, no error                            */
15881   BLEIF_CMDSTAT_CMDSTAT_WAIT           = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
15882 } BLEIF_CMDSTAT_CMDSTAT_Enum;
15883 
15884 /* =========================================================  INTEN  ========================================================= */
15885 /* ========================================================  INTSTAT  ======================================================== */
15886 /* ========================================================  INTCLR  ========================================================= */
15887 /* ========================================================  INTSET  ========================================================= */
15888 /* =======================================================  DMATRIGEN  ======================================================= */
15889 /* ======================================================  DMATRIGSTAT  ====================================================== */
15890 /* ========================================================  DMACFG  ========================================================= */
15891 /* ==============================================  BLEIF DMACFG DPWROFF [9..9]  ============================================== */
15892 typedef enum {                                  /*!< BLEIF_DMACFG_DPWROFF                                                      */
15893   BLEIF_DMACFG_DPWROFF_DIS             = 0,     /*!< DIS : Power off disabled                                                  */
15894   BLEIF_DMACFG_DPWROFF_EN              = 1,     /*!< EN : Power off enabled                                                    */
15895 } BLEIF_DMACFG_DPWROFF_Enum;
15896 
15897 /* ==============================================  BLEIF DMACFG DMAPRI [8..8]  =============================================== */
15898 typedef enum {                                  /*!< BLEIF_DMACFG_DMAPRI                                                       */
15899   BLEIF_DMACFG_DMAPRI_LOW              = 0,     /*!< LOW : Low Priority (service as best effort)                               */
15900   BLEIF_DMACFG_DMAPRI_HIGH             = 1,     /*!< HIGH : High Priority (service immediately)                                */
15901 } BLEIF_DMACFG_DMAPRI_Enum;
15902 
15903 /* ==============================================  BLEIF DMACFG DMADIR [1..1]  =============================================== */
15904 typedef enum {                                  /*!< BLEIF_DMACFG_DMADIR                                                       */
15905   BLEIF_DMACFG_DMADIR_P2M              = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
15906                                                      doing IOM read operations, i.e., reading data from external
15907                                                      devices.                                                                  */
15908   BLEIF_DMACFG_DMADIR_M2P              = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
15909                                                      IOM write operations, i.e., writing data to external devices.             */
15910 } BLEIF_DMACFG_DMADIR_Enum;
15911 
15912 /* ===============================================  BLEIF DMACFG DMAEN [0..0]  =============================================== */
15913 typedef enum {                                  /*!< BLEIF_DMACFG_DMAEN                                                        */
15914   BLEIF_DMACFG_DMAEN_DIS               = 0,     /*!< DIS : Disable DMA Function                                                */
15915   BLEIF_DMACFG_DMAEN_EN                = 1,     /*!< EN : Enable DMA Function                                                  */
15916 } BLEIF_DMACFG_DMAEN_Enum;
15917 
15918 /* ======================================================  DMATOTCOUNT  ====================================================== */
15919 /* ======================================================  DMATARGADDR  ====================================================== */
15920 /* ========================================================  DMASTAT  ======================================================== */
15921 /* =========================================================  CQCFG  ========================================================= */
15922 /* ===============================================  BLEIF CQCFG CQPRI [1..1]  ================================================ */
15923 typedef enum {                                  /*!< BLEIF_CQCFG_CQPRI                                                         */
15924   BLEIF_CQCFG_CQPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
15925   BLEIF_CQCFG_CQPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
15926 } BLEIF_CQCFG_CQPRI_Enum;
15927 
15928 /* ================================================  BLEIF CQCFG CQEN [0..0]  ================================================ */
15929 typedef enum {                                  /*!< BLEIF_CQCFG_CQEN                                                          */
15930   BLEIF_CQCFG_CQEN_DIS                 = 0,     /*!< DIS : Disable CQ Function                                                 */
15931   BLEIF_CQCFG_CQEN_EN                  = 1,     /*!< EN : Enable CQ Function                                                   */
15932 } BLEIF_CQCFG_CQEN_Enum;
15933 
15934 /* ========================================================  CQADDR  ========================================================= */
15935 /* ========================================================  CQSTAT  ========================================================= */
15936 /* ========================================================  CQFLAGS  ======================================================== */
15937 /* ======================================================  CQSETCLEAR  ======================================================= */
15938 /* =======================================================  CQPAUSEEN  ======================================================= */
15939 /* =============================================  BLEIF CQPAUSEEN CQPEN [0..15]  ============================================= */
15940 typedef enum {                                  /*!< BLEIF_CQPAUSEEN_CQPEN                                                     */
15941   BLEIF_CQPAUSEEN_CQPEN_CNTEQ          = 32768, /*!< CNTEQ : Pauses command queue processing when HWCNT matches SWCNT          */
15942   BLEIF_CQPAUSEEN_CQPEN_BLEXOREN       = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
15943                                                      SWFLAG4 is '1'                                                            */
15944   BLEIF_CQPAUSEEN_CQPEN_IOMXOREN       = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
15945                                                      SWFLAG3 is '1'                                                            */
15946   BLEIF_CQPAUSEEN_CQPEN_GPIOXOREN      = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
15947                                                      with SWFLAG2 is '1'                                                       */
15948   BLEIF_CQPAUSEEN_CQPEN_MSPI1XNOREN    = 2048,  /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
15949                                                      with SWFLAG1 is '1'                                                       */
15950   BLEIF_CQPAUSEEN_CQPEN_MSPI0XNOREN    = 1024,  /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
15951                                                      with SWFLAG0 is '1'                                                       */
15952   BLEIF_CQPAUSEEN_CQPEN_MSPI1XOREN     = 512,   /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
15953                                                      with SWFLAG1 is '1'                                                       */
15954   BLEIF_CQPAUSEEN_CQPEN_MSPI0XOREN     = 256,   /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
15955                                                      with SWFLAG0 is '1'                                                       */
15956   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN7      = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
15957                                                      is '1'.                                                                   */
15958   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN6      = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 7
15959                                                      is '1'                                                                    */
15960   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN5      = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 7
15961                                                      is '1'                                                                    */
15962   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN4      = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 7
15963                                                      is '1'                                                                    */
15964   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN3      = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 7
15965                                                      is '1'                                                                    */
15966   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN2      = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 7
15967                                                      is '1'                                                                    */
15968   BLEIF_CQPAUSEEN_CQPEN_SWFLAGEN1      = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 7
15969                                                      is '1'                                                                    */
15970   BLEIF_CQPAUSEEN_CQPEN_SWFLGEN0       = 1,     /*!< SWFLGEN0 : Pause the command queue when software flag bit 7
15971                                                      is '1'                                                                    */
15972 } BLEIF_CQPAUSEEN_CQPEN_Enum;
15973 
15974 /* =======================================================  CQCURIDX  ======================================================== */
15975 /* =======================================================  CQENDIDX  ======================================================== */
15976 /* ========================================================  STATUS  ========================================================= */
15977 /* ==============================================  BLEIF STATUS IDLEST [2..2]  =============================================== */
15978 typedef enum {                                  /*!< BLEIF_STATUS_IDLEST                                                       */
15979   BLEIF_STATUS_IDLEST_IDLE             = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
15980 } BLEIF_STATUS_IDLEST_Enum;
15981 
15982 /* ==============================================  BLEIF STATUS CMDACT [1..1]  =============================================== */
15983 typedef enum {                                  /*!< BLEIF_STATUS_CMDACT                                                       */
15984   BLEIF_STATUS_CMDACT_ACTIVE           = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
15985                                                      has an active command and is processing this. Deasserted
15986                                                      when the command is completed.                                            */
15987 } BLEIF_STATUS_CMDACT_Enum;
15988 
15989 /* ================================================  BLEIF STATUS ERR [0..0]  ================================================ */
15990 typedef enum {                                  /*!< BLEIF_STATUS_ERR                                                          */
15991   BLEIF_STATUS_ERR_ERROR               = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
15992 } BLEIF_STATUS_ERR_Enum;
15993 
15994 /* ========================================================  MSPICFG  ======================================================== */
15995 /* =============================================  BLEIF MSPICFG SPILSB [23..23]  ============================================= */
15996 typedef enum {                                  /*!< BLEIF_MSPICFG_SPILSB                                                      */
15997   BLEIF_MSPICFG_SPILSB_MSB             = 0,     /*!< MSB : Send and receive MSB bit first                                      */
15998   BLEIF_MSPICFG_SPILSB_LSB             = 1,     /*!< LSB : Send and receive LSB bit first                                      */
15999 } BLEIF_MSPICFG_SPILSB_Enum;
16000 
16001 /* ============================================  BLEIF MSPICFG RDFCPOL [22..22]  ============================================= */
16002 typedef enum {                                  /*!< BLEIF_MSPICFG_RDFCPOL                                                     */
16003   BLEIF_MSPICFG_RDFCPOL_NORMAL         = 0,     /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow
16004                                                      control and new read SPI transactions will not be started
16005                                                      until the signal goes low.(default)                                       */
16006   BLEIF_MSPICFG_RDFCPOL_INVERTED       = 1,     /*!< INVERTED : SPI_STATUS signal from BLE Core low(0) creates flow
16007                                                      control and new read SPI transactions will not be started
16008                                                      until the signal goes high.                                               */
16009 } BLEIF_MSPICFG_RDFCPOL_Enum;
16010 
16011 /* ============================================  BLEIF MSPICFG WTFCPOL [21..21]  ============================================= */
16012 typedef enum {                                  /*!< BLEIF_MSPICFG_WTFCPOL                                                     */
16013   BLEIF_MSPICFG_WTFCPOL_NORMAL         = 0,     /*!< NORMAL : SPI_STATUS signal from BLE Core high(1) creates flow
16014                                                      control and new write SPI transactions will not be started
16015                                                      until the signal goes low.(default)                                       */
16016   BLEIF_MSPICFG_WTFCPOL_INVERTED       = 1,     /*!< INVERTED : SPI_STATUS signal from BLE Core high(1) creates low(0)
16017                                                      control and new write SPI transactions will not be started
16018                                                      until the signal goes high.                                               */
16019 } BLEIF_MSPICFG_WTFCPOL_Enum;
16020 
16021 /* ==============================================  BLEIF MSPICFG RDFC [17..17]  ============================================== */
16022 typedef enum {                                  /*!< BLEIF_MSPICFG_RDFC                                                        */
16023   BLEIF_MSPICFG_RDFC_DIS               = 0,     /*!< DIS : Read mode flow control disabled.                                    */
16024   BLEIF_MSPICFG_RDFC_EN                = 1,     /*!< EN : Read mode flow control enabled.                                      */
16025 } BLEIF_MSPICFG_RDFC_Enum;
16026 
16027 /* ==============================================  BLEIF MSPICFG WTFC [16..16]  ============================================== */
16028 typedef enum {                                  /*!< BLEIF_MSPICFG_WTFC                                                        */
16029   BLEIF_MSPICFG_WTFC_DIS               = 0,     /*!< DIS : Write mode flow control disabled.                                   */
16030   BLEIF_MSPICFG_WTFC_EN                = 1,     /*!< EN : Write mode flow control enabled.                                     */
16031 } BLEIF_MSPICFG_WTFC_Enum;
16032 
16033 /* ===============================================  BLEIF MSPICFG SPHA [1..1]  =============================================== */
16034 typedef enum {                                  /*!< BLEIF_MSPICFG_SPHA                                                        */
16035   BLEIF_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,   /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge,
16036                                                      rising or falling dependent on the value of SPOL                          */
16037   BLEIF_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,  /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
16038                                                      edge, rising of falling dependent on the value of SPOL                    */
16039 } BLEIF_MSPICFG_SPHA_Enum;
16040 
16041 /* ===============================================  BLEIF MSPICFG SPOL [0..0]  =============================================== */
16042 typedef enum {                                  /*!< BLEIF_MSPICFG_SPOL                                                        */
16043   BLEIF_MSPICFG_SPOL_CLK_BASE_0        = 0,     /*!< CLK_BASE_0 : The initial value of the clock is 0.                         */
16044   BLEIF_MSPICFG_SPOL_CLK_BASE_1        = 1,     /*!< CLK_BASE_1 : The initial value of the clock is 1.                         */
16045 } BLEIF_MSPICFG_SPOL_Enum;
16046 
16047 /* ========================================================  BLECFG  ========================================================= */
16048 /* ============================================  BLEIF BLECFG SPIISOCTL [14..15]  ============================================ */
16049 typedef enum {                                  /*!< BLEIF_BLECFG_SPIISOCTL                                                    */
16050   BLEIF_BLECFG_SPIISOCTL_ON            = 3,     /*!< ON : SPI signals from BLE Core to/from MCU Core are isolated.             */
16051   BLEIF_BLECFG_SPIISOCTL_OFF           = 2,     /*!< OFF : SPI signals from BLE Core to/from MCU Core are not isolated.        */
16052   BLEIF_BLECFG_SPIISOCTL_AUTO          = 0,     /*!< AUTO : SPI signals from BLE Core to/from MCU Core are automatically
16053                                                      isolated by the logic                                                     */
16054 } BLEIF_BLECFG_SPIISOCTL_Enum;
16055 
16056 /* ============================================  BLEIF BLECFG PWRISOCTL [12..13]  ============================================ */
16057 typedef enum {                                  /*!< BLEIF_BLECFG_PWRISOCTL                                                    */
16058   BLEIF_BLECFG_PWRISOCTL_ON            = 3,     /*!< ON : BLEH power signal isolation to on (isolated).                        */
16059   BLEIF_BLECFG_PWRISOCTL_OFF           = 2,     /*!< OFF : BLEH power signal isolation to off (not isolated).                  */
16060   BLEIF_BLECFG_PWRISOCTL_AUTO          = 0,     /*!< AUTO : BLEH Power signal isolation is controlled automatically
16061                                                      through the interface logic                                               */
16062 } BLEIF_BLECFG_PWRISOCTL_Enum;
16063 
16064 /* ============================================  BLEIF BLECFG BLEHREQCTL [6..7]  ============================================= */
16065 typedef enum {                                  /*!< BLEIF_BLECFG_BLEHREQCTL                                                   */
16066   BLEIF_BLECFG_BLEHREQCTL_ON           = 3,     /*!< ON : BLEH Power-on reg signal is set to on (1).                           */
16067   BLEIF_BLECFG_BLEHREQCTL_OFF          = 2,     /*!< OFF : BLEH Power-on signal is set to off (0).                             */
16068   BLEIF_BLECFG_BLEHREQCTL_AUTO         = 0,     /*!< AUTO : BLEH Power-on signal is controlled by the PWRSM logic
16069                                                      and automatically controlled                                              */
16070 } BLEIF_BLECFG_BLEHREQCTL_Enum;
16071 
16072 /* ============================================  BLEIF BLECFG DCDCFLGCTL [4..5]  ============================================= */
16073 typedef enum {                                  /*!< BLEIF_BLECFG_DCDCFLGCTL                                                   */
16074   BLEIF_BLECFG_DCDCFLGCTL_ON           = 3,     /*!< ON : DCDC Flag signal is set to on (1).                                   */
16075   BLEIF_BLECFG_DCDCFLGCTL_OFF          = 2,     /*!< OFF : DCDC Flag signal is set to off (0).                                 */
16076   BLEIF_BLECFG_DCDCFLGCTL_AUTO         = 0,     /*!< AUTO : DCDC Flag signal is controlled by the PWRSM logic and
16077                                                      automatically controlled                                                  */
16078 } BLEIF_BLECFG_DCDCFLGCTL_Enum;
16079 
16080 /* =============================================  BLEIF BLECFG WAKEUPCTL [2..3]  ============================================= */
16081 typedef enum {                                  /*!< BLEIF_BLECFG_WAKEUPCTL                                                    */
16082   BLEIF_BLECFG_WAKEUPCTL_ON            = 3,     /*!< ON : Wake signal is set to on (1).                                        */
16083   BLEIF_BLECFG_WAKEUPCTL_OFF           = 2,     /*!< OFF : Wake signal is set to off (0).                                      */
16084   BLEIF_BLECFG_WAKEUPCTL_AUTO          = 0,     /*!< AUTO : Wake signal is controlled by the PWRSM logic and automatically
16085                                                      controlled                                                                */
16086 } BLEIF_BLECFG_WAKEUPCTL_Enum;
16087 
16088 /* ==============================================  BLEIF BLECFG BLERSTN [1..1]  ============================================== */
16089 typedef enum {                                  /*!< BLEIF_BLECFG_BLERSTN                                                      */
16090   BLEIF_BLECFG_BLERSTN_ACTIVE          = 1,     /*!< ACTIVE : The reset signal is active (0)                                   */
16091   BLEIF_BLECFG_BLERSTN_INACTIVE        = 0,     /*!< INACTIVE : The reset signal is inactive (1)                               */
16092 } BLEIF_BLECFG_BLERSTN_Enum;
16093 
16094 /* ==============================================  BLEIF BLECFG PWRSMEN [0..0]  ============================================== */
16095 typedef enum {                                  /*!< BLEIF_BLECFG_PWRSMEN                                                      */
16096   BLEIF_BLECFG_PWRSMEN_ON              = 1,     /*!< ON : Internal power state machine is enabled and will sequence
16097                                                      the BLEH power domain as indicated in the design document.
16098                                                      Overrides for the power signals are not enabled.                          */
16099   BLEIF_BLECFG_PWRSMEN_OFF             = 0,     /*!< OFF : Internal power state machine is disabled and will not
16100                                                      sequence the BLEH power domain. The values of the overrides
16101                                                      will be used to drive the output sequencing signals                       */
16102 } BLEIF_BLECFG_PWRSMEN_Enum;
16103 
16104 /* ========================================================  PWRCMD  ========================================================= */
16105 /* ========================================================  BSTATUS  ======================================================== */
16106 /* ==============================================  BLEIF BSTATUS PWRST [8..10]  ============================================== */
16107 typedef enum {                                  /*!< BLEIF_BSTATUS_PWRST                                                       */
16108   BLEIF_BSTATUS_PWRST_OFF              = 0,     /*!< OFF : Internal power state machine is disabled and will not
16109                                                      sequence the BLEH power domain. The values of the overrides
16110                                                      will be used to drive the output sequencing signals                       */
16111   BLEIF_BSTATUS_PWRST_INIT             = 1,     /*!< INIT : Initialization state. BLEH not powered                             */
16112   BLEIF_BSTATUS_PWRST_PWRON            = 2,     /*!< PWRON : Waiting for the power-up of the BLEH                              */
16113   BLEIF_BSTATUS_PWRST_ACTIVE           = 3,     /*!< ACTIVE : The BLE Core is powered and active                               */
16114   BLEIF_BSTATUS_PWRST_SLEEP            = 6,     /*!< SLEEP : The BLE Core has entered sleep mode and the power request
16115                                                      is inactive                                                               */
16116   BLEIF_BSTATUS_PWRST_SHUTDOWN         = 4,     /*!< SHUTDOWN : The BLE Core is in shutdown mode                               */
16117 } BLEIF_BSTATUS_PWRST_Enum;
16118 
16119 /* =============================================  BLEIF BSTATUS B2MSTATE [0..2]  ============================================= */
16120 typedef enum {                                  /*!< BLEIF_BSTATUS_B2MSTATE                                                    */
16121   BLEIF_BSTATUS_B2MSTATE_RESET         = 0,     /*!< RESET : Reset State                                                       */
16122   BLEIF_BSTATUS_B2MSTATE_Sleep         = 1,     /*!< Sleep : Sleep state.                                                      */
16123   BLEIF_BSTATUS_B2MSTATE_Standby       = 2,     /*!< Standby : Standby State                                                   */
16124   BLEIF_BSTATUS_B2MSTATE_Idle          = 3,     /*!< Idle : Idle state                                                         */
16125   BLEIF_BSTATUS_B2MSTATE_Active        = 4,     /*!< Active : Active state.                                                    */
16126 } BLEIF_BSTATUS_B2MSTATE_Enum;
16127 
16128 /* ========================================================  BLEDBG  ========================================================= */
16129 
16130 
16131 /* =========================================================================================================================== */
16132 /* ================                                         CACHECTRL                                         ================ */
16133 /* =========================================================================================================================== */
16134 
16135 /* =======================================================  CACHECFG  ======================================================== */
16136 /* ===========================================  CACHECTRL CACHECFG CONFIG [4..7]  ============================================ */
16137 typedef enum {                                  /*!< CACHECTRL_CACHECFG_CONFIG                                                 */
16138   CACHECTRL_CACHECFG_CONFIG_W1_128B_512E = 4,   /*!< W1_128B_512E : Direct mapped, 128-bit line size, 512 entries
16139                                                      (4 SRAMs active)                                                          */
16140   CACHECTRL_CACHECFG_CONFIG_W2_128B_512E = 5,   /*!< W2_128B_512E : Two-way set associative, 128-bit line size, 512
16141                                                      entries (8 SRAMs active)                                                  */
16142   CACHECTRL_CACHECFG_CONFIG_W1_128B_1024E = 8,  /*!< W1_128B_1024E : Direct mapped, 128-bit line size, 1024 entries
16143                                                      (8 SRAMs active)                                                          */
16144 } CACHECTRL_CACHECFG_CONFIG_Enum;
16145 
16146 /* =======================================================  FLASHCFG  ======================================================== */
16147 /* ==========================================  CACHECTRL FLASHCFG LPMMODE [12..13]  ========================================== */
16148 typedef enum {                                  /*!< CACHECTRL_FLASHCFG_LPMMODE                                                */
16149   CACHECTRL_FLASHCFG_LPMMODE_NEVER     = 0,     /*!< NEVER : High power mode (LPM not used).                                   */
16150   CACHECTRL_FLASHCFG_LPMMODE_STANDBY   = 1,     /*!< STANDBY : Fast Standby mode. LPM deasserted for read operations,
16151                                                      but asserted while FLASH IDLE.                                            */
16152   CACHECTRL_FLASHCFG_LPMMODE_ALWAYS    = 2,     /*!< ALWAYS : Low Power mode. LPM always asserted for reads. LPM_RD_WAIT
16153                                                      must be programmed to accomodate longer read access times.                */
16154 } CACHECTRL_FLASHCFG_LPMMODE_Enum;
16155 
16156 /* =========================================================  CTRL  ========================================================== */
16157 /* ===========================================  CACHECTRL CTRL RESET_STAT [1..1]  ============================================ */
16158 typedef enum {                                  /*!< CACHECTRL_CTRL_RESET_STAT                                                 */
16159   CACHECTRL_CTRL_RESET_STAT_CLEAR      = 1,     /*!< CLEAR : Clear Cache Stats                                                 */
16160 } CACHECTRL_CTRL_RESET_STAT_Enum;
16161 
16162 /* =======================================================  NCR0START  ======================================================= */
16163 /* ========================================================  NCR0END  ======================================================== */
16164 /* =======================================================  NCR1START  ======================================================= */
16165 /* ========================================================  NCR1END  ======================================================== */
16166 /* =========================================================  DMON0  ========================================================= */
16167 /* =========================================================  DMON1  ========================================================= */
16168 /* =========================================================  DMON2  ========================================================= */
16169 /* =========================================================  DMON3  ========================================================= */
16170 /* =========================================================  IMON0  ========================================================= */
16171 /* =========================================================  IMON1  ========================================================= */
16172 /* =========================================================  IMON2  ========================================================= */
16173 /* =========================================================  IMON3  ========================================================= */
16174 
16175 
16176 /* =========================================================================================================================== */
16177 /* ================                                          CLKGEN                                           ================ */
16178 /* =========================================================================================================================== */
16179 
16180 /* =========================================================  CALXT  ========================================================= */
16181 /* =========================================================  CALRC  ========================================================= */
16182 /* ========================================================  ACALCTR  ======================================================== */
16183 /* =========================================================  OCTRL  ========================================================= */
16184 /* ===============================================  CLKGEN OCTRL ACAL [8..10]  =============================================== */
16185 typedef enum {                                  /*!< CLKGEN_OCTRL_ACAL                                                         */
16186   CLKGEN_OCTRL_ACAL_DIS                = 0,     /*!< DIS : Disable Autocalibration                                             */
16187   CLKGEN_OCTRL_ACAL_1024SEC            = 2,     /*!< 1024SEC : Autocalibrate every 1024 seconds. Once autocalibration
16188                                                      is done, an interrupt will be triggered at the end of 1024
16189                                                      seconds.                                                                  */
16190   CLKGEN_OCTRL_ACAL_512SEC             = 3,     /*!< 512SEC : Autocalibrate every 512 seconds. Once autocalibration
16191                                                      is done, an interrupt will be trigged at the end of 512
16192                                                      seconds.                                                                  */
16193   CLKGEN_OCTRL_ACAL_XTFREQ             = 6,     /*!< XTFREQ : Frequency measurement using XT. The XT clock is normally
16194                                                      considered much more accurate than the LFRC clock source.                 */
16195   CLKGEN_OCTRL_ACAL_EXTFREQ            = 7,     /*!< EXTFREQ : Frequency measurement using external clock.                     */
16196 } CLKGEN_OCTRL_ACAL_Enum;
16197 
16198 /* ===============================================  CLKGEN OCTRL OSEL [7..7]  ================================================ */
16199 typedef enum {                                  /*!< CLKGEN_OCTRL_OSEL                                                         */
16200   CLKGEN_OCTRL_OSEL_RTC_XT             = 0,     /*!< RTC_XT : RTC uses the XT                                                  */
16201   CLKGEN_OCTRL_OSEL_RTC_LFRC           = 1,     /*!< RTC_LFRC : RTC uses the LFRC                                              */
16202 } CLKGEN_OCTRL_OSEL_Enum;
16203 
16204 /* ================================================  CLKGEN OCTRL FOS [6..6]  ================================================ */
16205 typedef enum {                                  /*!< CLKGEN_OCTRL_FOS                                                          */
16206   CLKGEN_OCTRL_FOS_DIS                 = 0,     /*!< DIS : Disable the oscillator switch on failure function.                  */
16207   CLKGEN_OCTRL_FOS_EN                  = 1,     /*!< EN : Enable the oscillator switch on failure function.                    */
16208 } CLKGEN_OCTRL_FOS_Enum;
16209 
16210 /* ==============================================  CLKGEN OCTRL STOPRC [1..1]  =============================================== */
16211 typedef enum {                                  /*!< CLKGEN_OCTRL_STOPRC                                                       */
16212   CLKGEN_OCTRL_STOPRC_EN               = 0,     /*!< EN : Enable the LFRC Oscillator to drive the RTC                          */
16213   CLKGEN_OCTRL_STOPRC_STOP             = 1,     /*!< STOP : Stop the LFRC Oscillator when driving the RTC                      */
16214 } CLKGEN_OCTRL_STOPRC_Enum;
16215 
16216 /* ==============================================  CLKGEN OCTRL STOPXT [0..0]  =============================================== */
16217 typedef enum {                                  /*!< CLKGEN_OCTRL_STOPXT                                                       */
16218   CLKGEN_OCTRL_STOPXT_EN               = 0,     /*!< EN : Enable the XT Oscillator to drive the RTC                            */
16219   CLKGEN_OCTRL_STOPXT_STOP             = 1,     /*!< STOP : Stop the XT Oscillator when driving the RTC                        */
16220 } CLKGEN_OCTRL_STOPXT_Enum;
16221 
16222 /* ========================================================  CLKOUT  ========================================================= */
16223 /* ===============================================  CLKGEN CLKOUT CKEN [7..7]  =============================================== */
16224 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKEN                                                        */
16225   CLKGEN_CLKOUT_CKEN_DIS               = 0,     /*!< DIS : Disable CLKOUT                                                      */
16226   CLKGEN_CLKOUT_CKEN_EN                = 1,     /*!< EN : Enable CLKOUT                                                        */
16227 } CLKGEN_CLKOUT_CKEN_Enum;
16228 
16229 /* ==============================================  CLKGEN CLKOUT CKSEL [0..5]  =============================================== */
16230 typedef enum {                                  /*!< CLKGEN_CLKOUT_CKSEL                                                       */
16231   CLKGEN_CLKOUT_CKSEL_LFRC             = 0,     /*!< LFRC : LFRC Low Frequency RC                                              */
16232   CLKGEN_CLKOUT_CKSEL_XT_DIV2          = 1,     /*!< XT_DIV2 : XT / 2                                                          */
16233   CLKGEN_CLKOUT_CKSEL_XT_DIV4          = 2,     /*!< XT_DIV4 : XT / 4                                                          */
16234   CLKGEN_CLKOUT_CKSEL_XT_DIV8          = 3,     /*!< XT_DIV8 : XT / 8                                                          */
16235   CLKGEN_CLKOUT_CKSEL_XT_DIV16         = 4,     /*!< XT_DIV16 : XT / 16                                                        */
16236   CLKGEN_CLKOUT_CKSEL_XT_DIV32         = 5,     /*!< XT_DIV32 : XT / 32                                                        */
16237   CLKGEN_CLKOUT_CKSEL_RTC_1Hz          = 16,    /*!< RTC_1Hz : 1 Hz as selected in RTC                                         */
16238   CLKGEN_CLKOUT_CKSEL_XT_DIV2M         = 22,    /*!< XT_DIV2M : XT / 2^21                                                      */
16239   CLKGEN_CLKOUT_CKSEL_XT               = 23,    /*!< XT : Crystal                                                              */
16240   CLKGEN_CLKOUT_CKSEL_CG_100Hz         = 24,    /*!< CG_100Hz : 100 Hz as selected in CLKGEN                                   */
16241   CLKGEN_CLKOUT_CKSEL_HFRC             = 25,    /*!< HFRC : High Frequency RC                                                  */
16242   CLKGEN_CLKOUT_CKSEL_HFRC_DIV4        = 26,    /*!< HFRC_DIV4 : HFRC / 4                                                      */
16243   CLKGEN_CLKOUT_CKSEL_HFRC_DIV8        = 27,    /*!< HFRC_DIV8 : HFRC / 8                                                      */
16244   CLKGEN_CLKOUT_CKSEL_HFRC_DIV16       = 28,    /*!< HFRC_DIV16 : HFRC / 16                                                    */
16245   CLKGEN_CLKOUT_CKSEL_HFRC_DIV64       = 29,    /*!< HFRC_DIV64 : HFRC / 64                                                    */
16246   CLKGEN_CLKOUT_CKSEL_HFRC_DIV128      = 30,    /*!< HFRC_DIV128 : HFRC / 128                                                  */
16247   CLKGEN_CLKOUT_CKSEL_HFRC_DIV256      = 31,    /*!< HFRC_DIV256 : HFRC / 256                                                  */
16248   CLKGEN_CLKOUT_CKSEL_HFRC_DIV512      = 32,    /*!< HFRC_DIV512 : HFRC / 512                                                  */
16249   CLKGEN_CLKOUT_CKSEL_FLASH_CLK        = 34,    /*!< FLASH_CLK : Flash Clock                                                   */
16250   CLKGEN_CLKOUT_CKSEL_LFRC_DIV2        = 35,    /*!< LFRC_DIV2 : LFRC / 2                                                      */
16251   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32       = 36,    /*!< LFRC_DIV32 : LFRC / 32                                                    */
16252   CLKGEN_CLKOUT_CKSEL_LFRC_DIV512      = 37,    /*!< LFRC_DIV512 : LFRC / 512                                                  */
16253   CLKGEN_CLKOUT_CKSEL_LFRC_DIV32K      = 38,    /*!< LFRC_DIV32K : LFRC / 32768                                                */
16254   CLKGEN_CLKOUT_CKSEL_XT_DIV256        = 39,    /*!< XT_DIV256 : XT / 256                                                      */
16255   CLKGEN_CLKOUT_CKSEL_XT_DIV8K         = 40,    /*!< XT_DIV8K : XT / 8192                                                      */
16256   CLKGEN_CLKOUT_CKSEL_XT_DIV64K        = 41,    /*!< XT_DIV64K : XT / 2^16                                                     */
16257   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV16      = 42,    /*!< ULFRC_DIV16 : Uncal LFRC / 16                                             */
16258   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV128     = 43,    /*!< ULFRC_DIV128 : Uncal LFRC / 128                                           */
16259   CLKGEN_CLKOUT_CKSEL_ULFRC_1Hz        = 44,    /*!< ULFRC_1Hz : Uncal LFRC / 1024                                             */
16260   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV4K      = 45,    /*!< ULFRC_DIV4K : Uncal LFRC / 4096                                           */
16261   CLKGEN_CLKOUT_CKSEL_ULFRC_DIV1M      = 46,    /*!< ULFRC_DIV1M : Uncal LFRC / 2^20                                           */
16262   CLKGEN_CLKOUT_CKSEL_HFRC_DIV64K      = 47,    /*!< HFRC_DIV64K : HFRC / 2^16                                                 */
16263   CLKGEN_CLKOUT_CKSEL_HFRC_DIV16M      = 48,    /*!< HFRC_DIV16M : HFRC / 2^24                                                 */
16264   CLKGEN_CLKOUT_CKSEL_LFRC_DIV1M       = 49,    /*!< LFRC_DIV1M : LFRC / 2^20                                                  */
16265   CLKGEN_CLKOUT_CKSEL_HFRCNE           = 50,    /*!< HFRCNE : HFRC (not autoenabled)                                           */
16266   CLKGEN_CLKOUT_CKSEL_HFRCNE_DIV8      = 51,    /*!< HFRCNE_DIV8 : HFRC / 8 (not autoenabled)                                  */
16267   CLKGEN_CLKOUT_CKSEL_XTNE             = 53,    /*!< XTNE : XT (not autoenabled)                                               */
16268   CLKGEN_CLKOUT_CKSEL_XTNE_DIV16       = 54,    /*!< XTNE_DIV16 : XT / 16 (not autoenabled)                                    */
16269   CLKGEN_CLKOUT_CKSEL_LFRCNE_DIV32     = 55,    /*!< LFRCNE_DIV32 : LFRC / 32 (not autoenabled)                                */
16270   CLKGEN_CLKOUT_CKSEL_LFRCNE           = 57,    /*!< LFRCNE : LFRC (not autoenabled) - Default for undefined values            */
16271 } CLKGEN_CLKOUT_CKSEL_Enum;
16272 
16273 /* ========================================================  CLKKEY  ========================================================= */
16274 /* =============================================  CLKGEN CLKKEY CLKKEY [0..31]  ============================================== */
16275 typedef enum {                                  /*!< CLKGEN_CLKKEY_CLKKEY                                                      */
16276   CLKGEN_CLKKEY_CLKKEY_Key             = 71,    /*!< Key : Key value to unlock the register.                                   */
16277 } CLKGEN_CLKKEY_CLKKEY_Enum;
16278 
16279 /* =========================================================  CCTRL  ========================================================= */
16280 /* ==============================================  CLKGEN CCTRL CORESEL [0..0]  ============================================== */
16281 typedef enum {                                  /*!< CLKGEN_CCTRL_CORESEL                                                      */
16282   CLKGEN_CCTRL_CORESEL_HFRC            = 0,     /*!< HFRC : Core Clock is HFRC                                                 */
16283   CLKGEN_CCTRL_CORESEL_HFRC_DIV2       = 1,     /*!< HFRC_DIV2 : Core Clock is HFRC / 2                                        */
16284 } CLKGEN_CCTRL_CORESEL_Enum;
16285 
16286 /* ========================================================  STATUS  ========================================================= */
16287 /* =========================================================  HFADJ  ========================================================= */
16288 /* ============================================  CLKGEN HFADJ HFADJGAIN [21..23]  ============================================ */
16289 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJGAIN                                                    */
16290   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1     = 0,     /*!< Gain_of_1 : HF Adjust with Gain of 1                                      */
16291   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_2 = 1,    /*!< Gain_of_1_in_2 : HF Adjust with Gain of 0.5                               */
16292   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_4 = 2,    /*!< Gain_of_1_in_4 : HF Adjust with Gain of 0.25                              */
16293   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_8 = 3,    /*!< Gain_of_1_in_8 : HF Adjust with Gain of 0.125                             */
16294   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_16 = 4,   /*!< Gain_of_1_in_16 : HF Adjust with Gain of 0.0625                           */
16295   CLKGEN_HFADJ_HFADJGAIN_Gain_of_1_in_32 = 5,   /*!< Gain_of_1_in_32 : HF Adjust with Gain of 0.03125                          */
16296 } CLKGEN_HFADJ_HFADJGAIN_Enum;
16297 
16298 /* ============================================  CLKGEN HFADJ HFWARMUP [20..20]  ============================================= */
16299 typedef enum {                                  /*!< CLKGEN_HFADJ_HFWARMUP                                                     */
16300   CLKGEN_HFADJ_HFWARMUP_1SEC           = 0,     /*!< 1SEC : Autoadjust XT warm-up period = 1-2 seconds                         */
16301   CLKGEN_HFADJ_HFWARMUP_2SEC           = 1,     /*!< 2SEC : Autoadjust XT warm-up period = 2-4 seconds                         */
16302 } CLKGEN_HFADJ_HFWARMUP_Enum;
16303 
16304 /* ==============================================  CLKGEN HFADJ HFADJCK [1..3]  ============================================== */
16305 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJCK                                                      */
16306   CLKGEN_HFADJ_HFADJCK_4SEC            = 0,     /*!< 4SEC : Autoadjust repeat period = 4 seconds                               */
16307   CLKGEN_HFADJ_HFADJCK_16SEC           = 1,     /*!< 16SEC : Autoadjust repeat period = 16 seconds                             */
16308   CLKGEN_HFADJ_HFADJCK_32SEC           = 2,     /*!< 32SEC : Autoadjust repeat period = 32 seconds                             */
16309   CLKGEN_HFADJ_HFADJCK_64SEC           = 3,     /*!< 64SEC : Autoadjust repeat period = 64 seconds                             */
16310   CLKGEN_HFADJ_HFADJCK_128SEC          = 4,     /*!< 128SEC : Autoadjust repeat period = 128 seconds                           */
16311   CLKGEN_HFADJ_HFADJCK_256SEC          = 5,     /*!< 256SEC : Autoadjust repeat period = 256 seconds                           */
16312   CLKGEN_HFADJ_HFADJCK_512SEC          = 6,     /*!< 512SEC : Autoadjust repeat period = 512 seconds                           */
16313   CLKGEN_HFADJ_HFADJCK_1024SEC         = 7,     /*!< 1024SEC : Autoadjust repeat period = 1024 seconds                         */
16314 } CLKGEN_HFADJ_HFADJCK_Enum;
16315 
16316 /* ==============================================  CLKGEN HFADJ HFADJEN [0..0]  ============================================== */
16317 typedef enum {                                  /*!< CLKGEN_HFADJ_HFADJEN                                                      */
16318   CLKGEN_HFADJ_HFADJEN_DIS             = 0,     /*!< DIS : Disable the HFRC adjustment                                         */
16319   CLKGEN_HFADJ_HFADJEN_EN              = 1,     /*!< EN : Enable the HFRC adjustment                                           */
16320 } CLKGEN_HFADJ_HFADJEN_Enum;
16321 
16322 /* ======================================================  CLOCKENSTAT  ====================================================== */
16323 /* ========================================  CLKGEN CLOCKENSTAT CLOCKENSTAT [0..31]  ========================================= */
16324 typedef enum {                                  /*!< CLKGEN_CLOCKENSTAT_CLOCKENSTAT                                            */
16325   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_ADC_CLKEN = 0x1,/*!< ADC_CLKEN : Clock enable for the ADC.                                     */
16326   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_ACTIVITY_CLKEN = 0x2,/*!< APBDMA_ACTIVITY_CLKEN : Clock enable for the APBDMA ACTIVITY   */
16327   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOH_CLKEN = 0x4,/*!< APBDMA_AOH_CLKEN : Clock enable for the APBDMA AOH DOMAIN           */
16328   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_AOL_CLKEN = 0x8,/*!< APBDMA_AOL_CLKEN : Clock enable for the APBDMA AOL DOMAIN           */
16329   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_APB_CLKEN = 0x10,/*!< APBDMA_APB_CLKEN : Clock enable for the APBDMA_APB                 */
16330   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_BLEL_CLKEN = 0x20,/*!< APBDMA_BLEL_CLKEN : Clock enable for the APBDMA_BLEL              */
16331   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPA_CLKEN = 0x40,/*!< APBDMA_HCPA_CLKEN : Clock enable for the APBDMA_HCPA              */
16332   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPB_CLKEN = 0x80,/*!< APBDMA_HCPB_CLKEN : Clock enable for the APBDMA_HCPB             */
16333   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_HCPC_CLKEN = 0x100,/*!< APBDMA_HCPC_CLKEN : Clock enable for the APBDMA_HCPC             */
16334   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_MSPI_CLKEN = 0x200,/*!< APBDMA_MSPI_CLKEN : Clock enable for the APBDMA_MSPI             */
16335   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_APBDMA_PDM_CLKEN = 0x400,/*!< APBDMA_PDM_CLKEN : Clock enable for the APBDMA_PDM               */
16336   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK_CLKEN = 0x800,/*!< BLEIF_CLK_CLKEN : Clock enable for the BLEIF                      */
16337   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_BLEIF_CLK32K_CLKEN = 0x1000,/*!< BLEIF_CLK32K_CLKEN : Clock enable for the BLEIF 32khZ CLOCK    */
16338   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER_CLKEN = 0x2000,/*!< CTIMER_CLKEN : Clock enable for the CTIMER BLOCK                     */
16339   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0A_CLKEN = 0x4000,/*!< CTIMER0A_CLKEN : Clock enable for the CTIMER0A                    */
16340   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER0B_CLKEN = 0x8000,/*!< CTIMER0B_CLKEN : Clock enable for the CTIMER0B                    */
16341   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1A_CLKEN = 0x10000,/*!< CTIMER1A_CLKEN : Clock enable for the CTIMER1A                    */
16342   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER1B_CLKEN = 0x20000,/*!< CTIMER1B_CLKEN : Clock enable for the CTIMER1B                   */
16343   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2A_CLKEN = 0x40000,/*!< CTIMER2A_CLKEN : Clock enable for the CTIMER2A                   */
16344   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER2B_CLKEN = 0x80000,/*!< CTIMER2B_CLKEN : Clock enable for the CTIMER2B                   */
16345   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3A_CLKEN = 0x100000,/*!< CTIMER3A_CLKEN : Clock enable for the CTIMER3A                  */
16346   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER3B_CLKEN = 0x200000,/*!< CTIMER3B_CLKEN : Clock enable for the CTIMER3B                  */
16347   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4A_CLKEN = 0x400000,/*!< CTIMER4A_CLKEN : Clock enable for the CTIMER4A                  */
16348   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER4B_CLKEN = 0x800000,/*!< CTIMER4B_CLKEN : Clock enable for the CTIMER4B                  */
16349   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5A_CLKEN = 0x1000000,/*!< CTIMER5A_CLKEN : Clock enable for the CTIMER5A                 */
16350   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER5B_CLKEN = 0x2000000,/*!< CTIMER5B_CLKEN : Clock enable for the CTIMER5B                 */
16351   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6A_CLKEN = 0x4000000,/*!< CTIMER6A_CLKEN : Clock enable for the CTIMER6A                 */
16352   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER6B_CLKEN = 0x8000000,/*!< CTIMER6B_CLKEN : Clock enable for the CTIMER6B                */
16353   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7A_CLKEN = 0x10000000,/*!< CTIMER7A_CLKEN : Clock enable for the CTIMER7A                */
16354   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_CTIMER7B_CLKEN = 0x20000000,/*!< CTIMER7B_CLKEN : Clock enable for the CTIMER7B                */
16355   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_DAP_CLKEN = 0x40000000,/*!< DAP_CLKEN : Clock enable for the DAP                              */
16356   CLKGEN_CLOCKENSTAT_CLOCKENSTAT_IOMSTRIFC0_CLKEN = 0x80000000,/*!< IOMSTRIFC0_CLKEN : Clock enable for the IOMSTRIFC0        */
16357 } CLKGEN_CLOCKENSTAT_CLOCKENSTAT_Enum;
16358 
16359 /* =====================================================  CLOCKEN2STAT  ====================================================== */
16360 /* =======================================  CLKGEN CLOCKEN2STAT CLOCKEN2STAT [0..31]  ======================================== */
16361 typedef enum {                                  /*!< CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT                                          */
16362   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC1_CLKEN = 0x1,/*!< IOMSTRIFC1_CLKEN : Clock enable for the IO MASTER 0x01 IFC INTERFACE */
16363   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC2_CLKEN = 0x2,/*!< IOMSTRIFC2_CLKEN : Clock enable for the IO MASTER 0x02 IFC INTERFACE */
16364   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC3_CLKEN = 0x4,/*!< IOMSTRIFC3_CLKEN : Clock enable for the IO MASTER 0x03 IFC INTERFACE */
16365   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC4_CLKEN = 0x8,/*!< IOMSTRIFC4_CLKEN : Clock enable for the IO MASTER 0x04 IFC INTERFACE */
16366   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_IOMSTRIFC5_CLKEN = 0x10,/*!< IOMSTRIFC5_CLKEN : Clock enable for the IO MASTER 0x05 IFC INTERFACE */
16367   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDM_CLKEN = 0x20,/*!< PDM_CLKEN : Clock enable for the PDM                                    */
16368   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PDMIFC_CLKEN = 0x40,/*!< PDMIFC_CLKEN : Clock enable for the PDM INTERFACE                    */
16369   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_CLKEN = 0x80,/*!< PWRCTRL_CLKEN : Clock enable for the PWRCTRL                       */
16370   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_PWRCTRL_COUNT_CLKEN = 0x100,/*!< PWRCTRL_COUNT_CLKEN : Clock enable for the PWRCTRL counter   */
16371   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_RSTGEN_CLKEN = 0x200,/*!< RSTGEN_CLKEN : Clock enable for the RSTGEN                          */
16372   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_CLKEN = 0x400,/*!< SCARD_CLKEN : Clock enable for the SCARD                            */
16373   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_SCARD_ALTAPB_CLKEN = 0x800,/*!< SCARD_ALTAPB_CLKEN : Clock enable for the SCARD ALTAPB       */
16374   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_STIMER_CNT_CLKEN = 0x1000,/*!< STIMER_CNT_CLKEN : Clock enable for the STIMER_CNT_CLKEN       */
16375   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_TPIU_CLKEN = 0x2000,/*!< TPIU_CLKEN : Clock enable for the TPIU_CLKEN                         */
16376   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART0HF_CLKEN = 0x4000,/*!< UART0HF_CLKEN : Clock enable for the UART0 HF                    */
16377   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_UART1HF_CLKEN = 0x8000,/*!< UART1HF_CLKEN : Clock enable for the UART1 HF                    */
16378   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_WDT_CLKEN = 0x10000,/*!< WDT_CLKEN : Clock enable for the Watchdog timer                      */
16379   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_XT_32KHZ_EN = 0x40000000,/*!< XT_32KHZ_EN : Clock enable for the XT 32KHZ                   */
16380   CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_FORCEHFRC = 0x80000000,/*!< FORCEHFRC : HFRC is forced on Status.                          */
16381 } CLKGEN_CLOCKEN2STAT_CLOCKEN2STAT_Enum;
16382 
16383 /* =====================================================  CLOCKEN3STAT  ====================================================== */
16384 /* =======================================  CLKGEN CLOCKEN3STAT CLOCKEN3STAT [0..31]  ======================================== */
16385 typedef enum {                                  /*!< CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT                                          */
16386   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_DAP_enabled = 0x20000,/*!< DAP_enabled : DAP clock is enabled [0x11]                           */
16387   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_VCOMP_enabled = 0x40000,/*!< VCOMP_enabled : VCOMP power-down indicator [0x12]                 */
16388   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_XTAL_enabled = 0x1000000,/*!< XTAL_enabled : XTAL is enabled [0x18]                            */
16389   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_enabled = 0x2000000,/*!< HFRC_enabled : HFRC is enabled [0x19]                            */
16390   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFADJEN = 0x4000000,/*!< HFADJEN : HFRC Adjust enabled [0x1a]                                  */
16391   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_HFRC_en_out = 0x8000000,/*!< HFRC_en_out : HFRC Enabled out [0x1b]                            */
16392   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_RTC_XT = 0x10000000,/*!< RTC_XT : RTC use XT [0x1c]                                            */
16393   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_xtal_en = 0x20000000,/*!< clkout_xtal_en : XTAL clkout enabled [0x1d]                   */
16394   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_clkout_hfrc_en = 0x40000000,/*!< clkout_hfrc_en : HFRC clkout enabled [0x1e]                  */
16395   CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_flashclk_en = 0x80000000,/*!< flashclk_en : Flash clk is enabled [31]                      */
16396 } CLKGEN_CLOCKEN3STAT_CLOCKEN3STAT_Enum;
16397 
16398 /* =======================================================  FREQCTRL  ======================================================== */
16399 /* ============================================  CLKGEN FREQCTRL BURSTREQ [0..0]  ============================================ */
16400 typedef enum {                                  /*!< CLKGEN_FREQCTRL_BURSTREQ                                                  */
16401   CLKGEN_FREQCTRL_BURSTREQ_DIS         = 0,     /*!< DIS : Frequency for ARM core stays at 48MHz                               */
16402   CLKGEN_FREQCTRL_BURSTREQ_EN          = 1,     /*!< EN : Frequency for ARM core is increased to 96MHz                         */
16403 } CLKGEN_FREQCTRL_BURSTREQ_Enum;
16404 
16405 /* =====================================================  BLEBUCKTONADJ  ===================================================== */
16406 /* =====================================  CLKGEN BLEBUCKTONADJ ZEROLENDETECTEN [27..27]  ===================================== */
16407 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN                                      */
16408   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_DIS = 0, /*!< DIS : Disable Zero Length Detect                                          */
16409   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_EN = 1,  /*!< EN : Enable Zero Length Detect                                            */
16410 } CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTEN_Enum;
16411 
16412 /* ====================================  CLKGEN BLEBUCKTONADJ ZEROLENDETECTTRIM [23..26]  ==================================== */
16413 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM                                    */
16414   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetF = 15,/*!< SetF : Indicator send when the BLE BUCK asserts blebuck_comp1
16415                                                      for about 81 us (10 percent margin of error) or more                      */
16416   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetE = 14,/*!< SetE : Indicator send when the BLE BUCK asserts blebuck_comp1
16417                                                      for about 75.6 us (10 percent margin of error) or more                    */
16418   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetD = 13,/*!< SetD : Indicator send when the BLE BUCK asserts blebuck_comp1
16419                                                      for about 70.2 us (10 percent margin of error) or more                    */
16420   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetC = 12,/*!< SetC : Indicator send when the BLE BUCK asserts blebuck_comp1
16421                                                      for about 64.8 us (10 percent margin of error) or more                    */
16422   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetB = 11,/*!< SetB : Indicator send when the BLE BUCK asserts blebuck_comp1
16423                                                      for about 59.4 us (10 percent margin of error) or more                    */
16424   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_SetA = 10,/*!< SetA : Indicator send when the BLE BUCK asserts blebuck_comp1
16425                                                      for about 54.0 us (10 percent margin of error) or more                    */
16426   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set9 = 9,/*!< Set9 : Indicator send when the BLE BUCK asserts blebuck_comp1
16427                                                      for about 48.6 us (10 percent margin of error) or more                    */
16428   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set8 = 8,/*!< Set8 : Indicator send when the BLE BUCK asserts blebuck_comp1
16429                                                      for about 43.2 us (10 percent margin of error) or more                    */
16430   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set7 = 7,/*!< Set7 : Indicator send when the BLE BUCK asserts blebuck_comp1
16431                                                      for about 37.8 us (10 percent margin of error) or more                    */
16432   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set6 = 6,/*!< Set6 : Indicator send when the BLE BUCK asserts blebuck_comp1
16433                                                      for about 32.4 us (10 percent margin of error) or more                    */
16434   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set5 = 5,/*!< Set5 : Indicator send when the BLE BUCK asserts blebuck_comp1
16435                                                      for about 27.0 us (10 percent margin of error) or more                    */
16436   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set4 = 4,/*!< Set4 : Indicator send when the BLE BUCK asserts blebuck_comp1
16437                                                      for about 21.6 us (10 percent margin of error) or more                    */
16438   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set3 = 3,/*!< Set3 : Indicator send when the BLE BUCK asserts blebuck_comp1
16439                                                      for about 16.2 us (10 percent margin of error) or more                    */
16440   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set2 = 2,/*!< Set2 : Indicator send when the BLE BUCK asserts blebuck_comp1
16441                                                      for about 10.8 us (10 percent margin of error) or more                    */
16442   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set1 = 1,/*!< Set1 : Indicator send when the BLE BUCK asserts blebuck_comp1
16443                                                      for about 5.4 us (10 percent margin of error) or more                     */
16444   CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Set0 = 0,/*!< Set0 : Indicator send when the BLE BUCK asserts blebuck_comp1
16445                                                      for about 2.0 us (10 percent margin of error) or more                     */
16446 } CLKGEN_BLEBUCKTONADJ_ZEROLENDETECTTRIM_Enum;
16447 
16448 /* =======================================  CLKGEN BLEBUCKTONADJ TONADJUSTEN [22..22]  ======================================= */
16449 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTEN                                          */
16450   CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_DIS = 0,     /*!< DIS : Disable Adjust for BLE BUCK TON trim                                */
16451   CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_EN  = 1,     /*!< EN : Enable Adjust for BLE BUCK TON trim                                  */
16452 } CLKGEN_BLEBUCKTONADJ_TONADJUSTEN_Enum;
16453 
16454 /* =====================================  CLKGEN BLEBUCKTONADJ TONADJUSTPERIOD [20..21]  ===================================== */
16455 typedef enum {                                  /*!< CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD                                      */
16456   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_3KHz = 3,/*!< HFRC_3KHz : Adjust done for every 1 3KHz period                      */
16457   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_12KHz = 2,/*!< HFRC_12KHz : Adjust done for every 1 12KHz period                   */
16458   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_47KHz = 1,/*!< HFRC_47KHz : Adjust done for every 1 47KHz period                   */
16459   CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_HFRC_94KHz = 0,/*!< HFRC_94KHz : Adjust done for every 1 94KHz period                   */
16460 } CLKGEN_BLEBUCKTONADJ_TONADJUSTPERIOD_Enum;
16461 
16462 /* =======================================================  INTRPTEN  ======================================================== */
16463 /* ======================================================  INTRPTSTAT  ======================================================= */
16464 /* =======================================================  INTRPTCLR  ======================================================= */
16465 /* =======================================================  INTRPTSET  ======================================================= */
16466 
16467 
16468 /* =========================================================================================================================== */
16469 /* ================                                          CTIMER                                           ================ */
16470 /* =========================================================================================================================== */
16471 
16472 /* =========================================================  TMR0  ========================================================== */
16473 /* ========================================================  CMPRA0  ========================================================= */
16474 /* ========================================================  CMPRB0  ========================================================= */
16475 /* =========================================================  CTRL0  ========================================================= */
16476 /* =============================================  CTIMER CTRL0 CTLINK0 [31..31]  ============================================= */
16477 typedef enum {                                  /*!< CTIMER_CTRL0_CTLINK0                                                      */
16478   CTIMER_CTRL0_CTLINK0_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A0/B0 timers as two independent 16-bit
16479                                                      timers (default).                                                         */
16480   CTIMER_CTRL0_CTLINK0_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A0/B0 timers into a single 32-bit timer.               */
16481 } CTIMER_CTRL0_CTLINK0_Enum;
16482 
16483 /* ============================================  CTIMER CTRL0 TMRB0POL [28..28]  ============================================= */
16484 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0POL                                                     */
16485   CTIMER_CTRL0_TMRB0POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB0 pin is the same as the
16486                                                      timer output.                                                             */
16487   CTIMER_CTRL0_TMRB0POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB0 pin is the inverse of
16488                                                      the timer output.                                                         */
16489 } CTIMER_CTRL0_TMRB0POL_Enum;
16490 
16491 /* ============================================  CTIMER CTRL0 TMRB0CLR [27..27]  ============================================= */
16492 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0CLR                                                     */
16493   CTIMER_CTRL0_TMRB0CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B0 to run                                       */
16494   CTIMER_CTRL0_TMRB0CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B0 at 0x0000.                                 */
16495 } CTIMER_CTRL0_TMRB0CLR_Enum;
16496 
16497 /* ============================================  CTIMER CTRL0 TMRB0IE1 [26..26]  ============================================= */
16498 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0IE1                                                     */
16499   CTIMER_CTRL0_TMRB0IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B0 from generating an interrupt
16500                                                      based on COMPR1.                                                          */
16501   CTIMER_CTRL0_TMRB0IE1_EN             = 1,     /*!< EN : Enable counter/timer B0 to generate an interrupt based
16502                                                      on COMPR1.                                                                */
16503 } CTIMER_CTRL0_TMRB0IE1_Enum;
16504 
16505 /* ============================================  CTIMER CTRL0 TMRB0IE0 [25..25]  ============================================= */
16506 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0IE0                                                     */
16507   CTIMER_CTRL0_TMRB0IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B0 from generating an interrupt
16508                                                      based on COMPR0.                                                          */
16509   CTIMER_CTRL0_TMRB0IE0_EN             = 1,     /*!< EN : Enable counter/timer B0 to generate an interrupt based
16510                                                      on COMPR0                                                                 */
16511 } CTIMER_CTRL0_TMRB0IE0_Enum;
16512 
16513 /* =============================================  CTIMER CTRL0 TMRB0FN [22..24]  ============================================= */
16514 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0FN                                                      */
16515   CTIMER_CTRL0_TMRB0FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
16516                                                      to CMPR0B0, stop.                                                         */
16517   CTIMER_CTRL0_TMRB0FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
16518                                                      pulses). Count to CMPR0B0, restart.                                       */
16519   CTIMER_CTRL0_TMRB0FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B0, assert,
16520                                                      count to CMPR1B0, deassert, stop.                                         */
16521   CTIMER_CTRL0_TMRB0FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B0, assert, count
16522                                                      to CMPR1B0, deassert, restart.                                            */
16523   CTIMER_CTRL0_TMRB0FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
16524   CTIMER_CTRL0_TMRB0FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
16525   CTIMER_CTRL0_TMRB0FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
16526   CTIMER_CTRL0_TMRB0FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
16527 } CTIMER_CTRL0_TMRB0FN_Enum;
16528 
16529 /* ============================================  CTIMER CTRL0 TMRB0CLK [17..21]  ============================================= */
16530 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0CLK                                                     */
16531   CTIMER_CTRL0_TMRB0CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
16532   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
16533   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
16534   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
16535   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
16536   CTIMER_CTRL0_TMRB0CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
16537   CTIMER_CTRL0_TMRB0CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
16538   CTIMER_CTRL0_TMRB0CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
16539   CTIMER_CTRL0_TMRB0CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
16540   CTIMER_CTRL0_TMRB0CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
16541   CTIMER_CTRL0_TMRB0CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
16542   CTIMER_CTRL0_TMRB0CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
16543   CTIMER_CTRL0_TMRB0CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
16544   CTIMER_CTRL0_TMRB0CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
16545   CTIMER_CTRL0_TMRB0CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
16546   CTIMER_CTRL0_TMRB0CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
16547                                                      available when MCU is in active mode)                                     */
16548   CTIMER_CTRL0_TMRB0CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
16549   CTIMER_CTRL0_TMRB0CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
16550   CTIMER_CTRL0_TMRB0CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
16551   CTIMER_CTRL0_TMRB0CLK_CTMRA0         = 20,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
16552   CTIMER_CTRL0_TMRB0CLK_CTMRB1         = 21,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
16553   CTIMER_CTRL0_TMRB0CLK_CTMRA1         = 22,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
16554   CTIMER_CTRL0_TMRB0CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
16555   CTIMER_CTRL0_TMRB0CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
16556   CTIMER_CTRL0_TMRB0CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
16557   CTIMER_CTRL0_TMRB0CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
16558   CTIMER_CTRL0_TMRB0CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
16559   CTIMER_CTRL0_TMRB0CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
16560   CTIMER_CTRL0_TMRB0CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
16561   CTIMER_CTRL0_TMRB0CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
16562   CTIMER_CTRL0_TMRB0CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
16563 } CTIMER_CTRL0_TMRB0CLK_Enum;
16564 
16565 /* =============================================  CTIMER CTRL0 TMRB0EN [16..16]  ============================================= */
16566 typedef enum {                                  /*!< CTIMER_CTRL0_TMRB0EN                                                      */
16567   CTIMER_CTRL0_TMRB0EN_DIS             = 0,     /*!< DIS : Counter/Timer B0 Disable.                                           */
16568   CTIMER_CTRL0_TMRB0EN_EN              = 1,     /*!< EN : Counter/Timer B0 Enable.                                             */
16569 } CTIMER_CTRL0_TMRB0EN_Enum;
16570 
16571 /* ============================================  CTIMER CTRL0 TMRA0POL [12..12]  ============================================= */
16572 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0POL                                                     */
16573   CTIMER_CTRL0_TMRA0POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA0 pin is the same as the
16574                                                      timer output.                                                             */
16575   CTIMER_CTRL0_TMRA0POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA0 pin is the inverse of
16576                                                      the timer output.                                                         */
16577 } CTIMER_CTRL0_TMRA0POL_Enum;
16578 
16579 /* ============================================  CTIMER CTRL0 TMRA0CLR [11..11]  ============================================= */
16580 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0CLR                                                     */
16581   CTIMER_CTRL0_TMRA0CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A0 to run                                       */
16582   CTIMER_CTRL0_TMRA0CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A0 at 0x0000.                                 */
16583 } CTIMER_CTRL0_TMRA0CLR_Enum;
16584 
16585 /* ============================================  CTIMER CTRL0 TMRA0IE1 [10..10]  ============================================= */
16586 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0IE1                                                     */
16587   CTIMER_CTRL0_TMRA0IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A0 from generating an interrupt
16588                                                      based on COMPR1.                                                          */
16589   CTIMER_CTRL0_TMRA0IE1_EN             = 1,     /*!< EN : Enable counter/timer A0 to generate an interrupt based
16590                                                      on COMPR1.                                                                */
16591 } CTIMER_CTRL0_TMRA0IE1_Enum;
16592 
16593 /* =============================================  CTIMER CTRL0 TMRA0IE0 [9..9]  ============================================== */
16594 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0IE0                                                     */
16595   CTIMER_CTRL0_TMRA0IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A0 from generating an interrupt
16596                                                      based on COMPR0.                                                          */
16597   CTIMER_CTRL0_TMRA0IE0_EN             = 1,     /*!< EN : Enable counter/timer A0 to generate an interrupt based
16598                                                      on COMPR0.                                                                */
16599 } CTIMER_CTRL0_TMRA0IE0_Enum;
16600 
16601 /* ==============================================  CTIMER CTRL0 TMRA0FN [6..8]  ============================================== */
16602 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0FN                                                      */
16603   CTIMER_CTRL0_TMRA0FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
16604                                                      to CMPR0A0, stop.                                                         */
16605   CTIMER_CTRL0_TMRA0FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
16606                                                      pulses). Count to CMPR0A0, restart.                                       */
16607   CTIMER_CTRL0_TMRA0FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A0, assert,
16608                                                      count to CMPR1A0, deassert, stop.                                         */
16609   CTIMER_CTRL0_TMRA0FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A0, assert, count
16610                                                      to CMPR1A0, deassert, restart.                                            */
16611   CTIMER_CTRL0_TMRA0FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
16612   CTIMER_CTRL0_TMRA0FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
16613   CTIMER_CTRL0_TMRA0FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
16614   CTIMER_CTRL0_TMRA0FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
16615 } CTIMER_CTRL0_TMRA0FN_Enum;
16616 
16617 /* =============================================  CTIMER CTRL0 TMRA0CLK [1..5]  ============================================== */
16618 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0CLK                                                     */
16619   CTIMER_CTRL0_TMRA0CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
16620   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
16621   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
16622   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
16623   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
16624   CTIMER_CTRL0_TMRA0CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
16625   CTIMER_CTRL0_TMRA0CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
16626   CTIMER_CTRL0_TMRA0CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
16627   CTIMER_CTRL0_TMRA0CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
16628   CTIMER_CTRL0_TMRA0CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
16629   CTIMER_CTRL0_TMRA0CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
16630   CTIMER_CTRL0_TMRA0CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
16631   CTIMER_CTRL0_TMRA0CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
16632   CTIMER_CTRL0_TMRA0CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
16633   CTIMER_CTRL0_TMRA0CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
16634   CTIMER_CTRL0_TMRA0CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
16635                                                      available when MCU is in active mode)                                     */
16636   CTIMER_CTRL0_TMRA0CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
16637   CTIMER_CTRL0_TMRA0CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
16638   CTIMER_CTRL0_TMRA0CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
16639   CTIMER_CTRL0_TMRA0CLK_CTMRB0         = 20,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
16640   CTIMER_CTRL0_TMRA0CLK_CTMRA1         = 21,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
16641   CTIMER_CTRL0_TMRA0CLK_CTMRB1         = 22,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
16642   CTIMER_CTRL0_TMRA0CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
16643   CTIMER_CTRL0_TMRA0CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
16644   CTIMER_CTRL0_TMRA0CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
16645   CTIMER_CTRL0_TMRA0CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
16646   CTIMER_CTRL0_TMRA0CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
16647   CTIMER_CTRL0_TMRA0CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
16648   CTIMER_CTRL0_TMRA0CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
16649   CTIMER_CTRL0_TMRA0CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
16650   CTIMER_CTRL0_TMRA0CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
16651 } CTIMER_CTRL0_TMRA0CLK_Enum;
16652 
16653 /* ==============================================  CTIMER CTRL0 TMRA0EN [0..0]  ============================================== */
16654 typedef enum {                                  /*!< CTIMER_CTRL0_TMRA0EN                                                      */
16655   CTIMER_CTRL0_TMRA0EN_DIS             = 0,     /*!< DIS : Counter/Timer A0 Disable.                                           */
16656   CTIMER_CTRL0_TMRA0EN_EN              = 1,     /*!< EN : Counter/Timer A0 Enable.                                             */
16657 } CTIMER_CTRL0_TMRA0EN_Enum;
16658 
16659 /* =======================================================  CMPRAUXA0  ======================================================= */
16660 /* =======================================================  CMPRAUXB0  ======================================================= */
16661 /* =========================================================  AUX0  ========================================================== */
16662 /* ============================================  CTIMER AUX0 TMRB0EN23 [30..30]  ============================================= */
16663 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0EN23                                                     */
16664   CTIMER_AUX0_TMRB0EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
16665   CTIMER_AUX0_TMRB0EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
16666 } CTIMER_AUX0_TMRB0EN23_Enum;
16667 
16668 /* ============================================  CTIMER AUX0 TMRB0POL23 [29..29]  ============================================ */
16669 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0POL23                                                    */
16670   CTIMER_AUX0_TMRB0POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
16671   CTIMER_AUX0_TMRB0POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
16672 } CTIMER_AUX0_TMRB0POL23_Enum;
16673 
16674 /* ============================================  CTIMER AUX0 TMRB0TINV [28..28]  ============================================= */
16675 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0TINV                                                     */
16676   CTIMER_AUX0_TMRB0TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
16677   CTIMER_AUX0_TMRB0TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
16678 } CTIMER_AUX0_TMRB0TINV_Enum;
16679 
16680 /* ===========================================  CTIMER AUX0 TMRB0NOSYNC [27..27]  ============================================ */
16681 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0NOSYNC                                                   */
16682   CTIMER_AUX0_TMRB0NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
16683   CTIMER_AUX0_TMRB0NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
16684 } CTIMER_AUX0_TMRB0NOSYNC_Enum;
16685 
16686 /* ============================================  CTIMER AUX0 TMRB0TRIG [23..26]  ============================================= */
16687 typedef enum {                                  /*!< CTIMER_AUX0_TMRB0TRIG                                                     */
16688   CTIMER_AUX0_TMRB0TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
16689   CTIMER_AUX0_TMRB0TRIG_A0OUT          = 1,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
16690   CTIMER_AUX0_TMRB0TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
16691   CTIMER_AUX0_TMRB0TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
16692   CTIMER_AUX0_TMRB0TRIG_B2OUT          = 4,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
16693   CTIMER_AUX0_TMRB0TRIG_B5OUT          = 5,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
16694   CTIMER_AUX0_TMRB0TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
16695   CTIMER_AUX0_TMRB0TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
16696   CTIMER_AUX0_TMRB0TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
16697   CTIMER_AUX0_TMRB0TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
16698   CTIMER_AUX0_TMRB0TRIG_B7OUT2         = 10,    /*!< B7OUT2 : Trigger source is CTIMERB7 OUT2.                                 */
16699   CTIMER_AUX0_TMRB0TRIG_A2OUT2         = 11,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
16700   CTIMER_AUX0_TMRB0TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
16701   CTIMER_AUX0_TMRB0TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
16702   CTIMER_AUX0_TMRB0TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
16703   CTIMER_AUX0_TMRB0TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
16704 } CTIMER_AUX0_TMRB0TRIG_Enum;
16705 
16706 /* ============================================  CTIMER AUX0 TMRA0EN23 [14..14]  ============================================= */
16707 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0EN23                                                     */
16708   CTIMER_AUX0_TMRA0EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
16709   CTIMER_AUX0_TMRA0EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
16710 } CTIMER_AUX0_TMRA0EN23_Enum;
16711 
16712 /* ============================================  CTIMER AUX0 TMRA0POL23 [13..13]  ============================================ */
16713 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0POL23                                                    */
16714   CTIMER_AUX0_TMRA0POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
16715   CTIMER_AUX0_TMRA0POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
16716 } CTIMER_AUX0_TMRA0POL23_Enum;
16717 
16718 /* ============================================  CTIMER AUX0 TMRA0TINV [12..12]  ============================================= */
16719 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0TINV                                                     */
16720   CTIMER_AUX0_TMRA0TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
16721   CTIMER_AUX0_TMRA0TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
16722 } CTIMER_AUX0_TMRA0TINV_Enum;
16723 
16724 /* ===========================================  CTIMER AUX0 TMRA0NOSYNC [11..11]  ============================================ */
16725 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0NOSYNC                                                   */
16726   CTIMER_AUX0_TMRA0NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
16727   CTIMER_AUX0_TMRA0NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
16728 } CTIMER_AUX0_TMRA0NOSYNC_Enum;
16729 
16730 /* =============================================  CTIMER AUX0 TMRA0TRIG [7..10]  ============================================= */
16731 typedef enum {                                  /*!< CTIMER_AUX0_TMRA0TRIG                                                     */
16732   CTIMER_AUX0_TMRA0TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
16733   CTIMER_AUX0_TMRA0TRIG_B0OUT          = 1,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
16734   CTIMER_AUX0_TMRA0TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
16735   CTIMER_AUX0_TMRA0TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
16736   CTIMER_AUX0_TMRA0TRIG_A1OUT          = 4,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
16737   CTIMER_AUX0_TMRA0TRIG_B1OUT          = 5,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
16738   CTIMER_AUX0_TMRA0TRIG_A5OUT          = 6,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
16739   CTIMER_AUX0_TMRA0TRIG_B5OUT          = 7,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
16740   CTIMER_AUX0_TMRA0TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
16741   CTIMER_AUX0_TMRA0TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
16742   CTIMER_AUX0_TMRA0TRIG_B6OUT2         = 10,    /*!< B6OUT2 : Trigger source is CTIMERB6 OUT2.                                 */
16743   CTIMER_AUX0_TMRA0TRIG_A2OUT2         = 11,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
16744   CTIMER_AUX0_TMRA0TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
16745   CTIMER_AUX0_TMRA0TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
16746   CTIMER_AUX0_TMRA0TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
16747   CTIMER_AUX0_TMRA0TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
16748 } CTIMER_AUX0_TMRA0TRIG_Enum;
16749 
16750 /* =========================================================  TMR1  ========================================================== */
16751 /* ========================================================  CMPRA1  ========================================================= */
16752 /* ========================================================  CMPRB1  ========================================================= */
16753 /* =========================================================  CTRL1  ========================================================= */
16754 /* =============================================  CTIMER CTRL1 CTLINK1 [31..31]  ============================================= */
16755 typedef enum {                                  /*!< CTIMER_CTRL1_CTLINK1                                                      */
16756   CTIMER_CTRL1_CTLINK1_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A1/B1 timers as two independent 16-bit
16757                                                      timers (default).                                                         */
16758   CTIMER_CTRL1_CTLINK1_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A1/B1 timers into a single 32-bit timer.               */
16759 } CTIMER_CTRL1_CTLINK1_Enum;
16760 
16761 /* ============================================  CTIMER CTRL1 TMRB1POL [28..28]  ============================================= */
16762 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1POL                                                     */
16763   CTIMER_CTRL1_TMRB1POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB1 pin is the same as the
16764                                                      timer output.                                                             */
16765   CTIMER_CTRL1_TMRB1POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB1 pin is the inverse of
16766                                                      the timer output.                                                         */
16767 } CTIMER_CTRL1_TMRB1POL_Enum;
16768 
16769 /* ============================================  CTIMER CTRL1 TMRB1CLR [27..27]  ============================================= */
16770 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1CLR                                                     */
16771   CTIMER_CTRL1_TMRB1CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B1 to run                                       */
16772   CTIMER_CTRL1_TMRB1CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B1 at 0x0000.                                 */
16773 } CTIMER_CTRL1_TMRB1CLR_Enum;
16774 
16775 /* ============================================  CTIMER CTRL1 TMRB1IE1 [26..26]  ============================================= */
16776 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1IE1                                                     */
16777   CTIMER_CTRL1_TMRB1IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B1 from generating an interrupt
16778                                                      based on COMPR1.                                                          */
16779   CTIMER_CTRL1_TMRB1IE1_EN             = 1,     /*!< EN : Enable counter/timer B1 to generate an interrupt based
16780                                                      on COMPR1.                                                                */
16781 } CTIMER_CTRL1_TMRB1IE1_Enum;
16782 
16783 /* ============================================  CTIMER CTRL1 TMRB1IE0 [25..25]  ============================================= */
16784 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1IE0                                                     */
16785   CTIMER_CTRL1_TMRB1IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B1 from generating an interrupt
16786                                                      based on COMPR0.                                                          */
16787   CTIMER_CTRL1_TMRB1IE0_EN             = 1,     /*!< EN : Enable counter/timer B1 to generate an interrupt based
16788                                                      on COMPR0                                                                 */
16789 } CTIMER_CTRL1_TMRB1IE0_Enum;
16790 
16791 /* =============================================  CTIMER CTRL1 TMRB1FN [22..24]  ============================================= */
16792 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1FN                                                      */
16793   CTIMER_CTRL1_TMRB1FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
16794                                                      to CMPR0B1, stop.                                                         */
16795   CTIMER_CTRL1_TMRB1FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
16796                                                      pulses). Count to CMPR0B1, restart.                                       */
16797   CTIMER_CTRL1_TMRB1FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B1, assert,
16798                                                      count to CMPR1B1, deassert, stop.                                         */
16799   CTIMER_CTRL1_TMRB1FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B1, assert, count
16800                                                      to CMPR1B1, deassert, restart.                                            */
16801   CTIMER_CTRL1_TMRB1FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
16802   CTIMER_CTRL1_TMRB1FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
16803   CTIMER_CTRL1_TMRB1FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
16804   CTIMER_CTRL1_TMRB1FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
16805 } CTIMER_CTRL1_TMRB1FN_Enum;
16806 
16807 /* ============================================  CTIMER CTRL1 TMRB1CLK [17..21]  ============================================= */
16808 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1CLK                                                     */
16809   CTIMER_CTRL1_TMRB1CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
16810   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
16811   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
16812   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
16813   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
16814   CTIMER_CTRL1_TMRB1CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
16815   CTIMER_CTRL1_TMRB1CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
16816   CTIMER_CTRL1_TMRB1CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
16817   CTIMER_CTRL1_TMRB1CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
16818   CTIMER_CTRL1_TMRB1CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
16819   CTIMER_CTRL1_TMRB1CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
16820   CTIMER_CTRL1_TMRB1CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
16821   CTIMER_CTRL1_TMRB1CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
16822   CTIMER_CTRL1_TMRB1CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
16823   CTIMER_CTRL1_TMRB1CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
16824   CTIMER_CTRL1_TMRB1CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
16825                                                      available when MCU is in active mode)                                     */
16826   CTIMER_CTRL1_TMRB1CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
16827   CTIMER_CTRL1_TMRB1CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
16828   CTIMER_CTRL1_TMRB1CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
16829   CTIMER_CTRL1_TMRB1CLK_CTMRA1         = 20,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
16830   CTIMER_CTRL1_TMRB1CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
16831   CTIMER_CTRL1_TMRB1CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
16832   CTIMER_CTRL1_TMRB1CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
16833   CTIMER_CTRL1_TMRB1CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
16834   CTIMER_CTRL1_TMRB1CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
16835   CTIMER_CTRL1_TMRB1CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
16836   CTIMER_CTRL1_TMRB1CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
16837   CTIMER_CTRL1_TMRB1CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
16838   CTIMER_CTRL1_TMRB1CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
16839   CTIMER_CTRL1_TMRB1CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
16840   CTIMER_CTRL1_TMRB1CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
16841 } CTIMER_CTRL1_TMRB1CLK_Enum;
16842 
16843 /* =============================================  CTIMER CTRL1 TMRB1EN [16..16]  ============================================= */
16844 typedef enum {                                  /*!< CTIMER_CTRL1_TMRB1EN                                                      */
16845   CTIMER_CTRL1_TMRB1EN_DIS             = 0,     /*!< DIS : Counter/Timer B1 Disable.                                           */
16846   CTIMER_CTRL1_TMRB1EN_EN              = 1,     /*!< EN : Counter/Timer B1 Enable.                                             */
16847 } CTIMER_CTRL1_TMRB1EN_Enum;
16848 
16849 /* ============================================  CTIMER CTRL1 TMRA1POL [12..12]  ============================================= */
16850 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1POL                                                     */
16851   CTIMER_CTRL1_TMRA1POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA1 pin is the same as the
16852                                                      timer output.                                                             */
16853   CTIMER_CTRL1_TMRA1POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA1 pin is the inverse of
16854                                                      the timer output.                                                         */
16855 } CTIMER_CTRL1_TMRA1POL_Enum;
16856 
16857 /* ============================================  CTIMER CTRL1 TMRA1CLR [11..11]  ============================================= */
16858 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1CLR                                                     */
16859   CTIMER_CTRL1_TMRA1CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A1 to run                                       */
16860   CTIMER_CTRL1_TMRA1CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A1 at 0x0000.                                 */
16861 } CTIMER_CTRL1_TMRA1CLR_Enum;
16862 
16863 /* ============================================  CTIMER CTRL1 TMRA1IE1 [10..10]  ============================================= */
16864 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1IE1                                                     */
16865   CTIMER_CTRL1_TMRA1IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A1 from generating an interrupt
16866                                                      based on COMPR1.                                                          */
16867   CTIMER_CTRL1_TMRA1IE1_EN             = 1,     /*!< EN : Enable counter/timer A1 to generate an interrupt based
16868                                                      on COMPR1.                                                                */
16869 } CTIMER_CTRL1_TMRA1IE1_Enum;
16870 
16871 /* =============================================  CTIMER CTRL1 TMRA1IE0 [9..9]  ============================================== */
16872 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1IE0                                                     */
16873   CTIMER_CTRL1_TMRA1IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A1 from generating an interrupt
16874                                                      based on COMPR0.                                                          */
16875   CTIMER_CTRL1_TMRA1IE0_EN             = 1,     /*!< EN : Enable counter/timer A1 to generate an interrupt based
16876                                                      on COMPR0.                                                                */
16877 } CTIMER_CTRL1_TMRA1IE0_Enum;
16878 
16879 /* ==============================================  CTIMER CTRL1 TMRA1FN [6..8]  ============================================== */
16880 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1FN                                                      */
16881   CTIMER_CTRL1_TMRA1FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
16882                                                      to CMPR0A1, stop.                                                         */
16883   CTIMER_CTRL1_TMRA1FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
16884                                                      pulses). Count to CMPR0A1, restart.                                       */
16885   CTIMER_CTRL1_TMRA1FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A1, assert,
16886                                                      count to CMPR1A1, deassert, stop.                                         */
16887   CTIMER_CTRL1_TMRA1FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A1, assert, count
16888                                                      to CMPR1A1, deassert, restart.                                            */
16889   CTIMER_CTRL1_TMRA1FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
16890   CTIMER_CTRL1_TMRA1FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
16891   CTIMER_CTRL1_TMRA1FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
16892   CTIMER_CTRL1_TMRA1FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
16893 } CTIMER_CTRL1_TMRA1FN_Enum;
16894 
16895 /* =============================================  CTIMER CTRL1 TMRA1CLK [1..5]  ============================================== */
16896 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1CLK                                                     */
16897   CTIMER_CTRL1_TMRA1CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
16898   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
16899   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
16900   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
16901   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
16902   CTIMER_CTRL1_TMRA1CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
16903   CTIMER_CTRL1_TMRA1CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
16904   CTIMER_CTRL1_TMRA1CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
16905   CTIMER_CTRL1_TMRA1CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
16906   CTIMER_CTRL1_TMRA1CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
16907   CTIMER_CTRL1_TMRA1CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
16908   CTIMER_CTRL1_TMRA1CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
16909   CTIMER_CTRL1_TMRA1CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
16910   CTIMER_CTRL1_TMRA1CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
16911   CTIMER_CTRL1_TMRA1CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
16912   CTIMER_CTRL1_TMRA1CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
16913                                                      available when MCU is in active mode)                                     */
16914   CTIMER_CTRL1_TMRA1CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
16915   CTIMER_CTRL1_TMRA1CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
16916   CTIMER_CTRL1_TMRA1CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
16917   CTIMER_CTRL1_TMRA1CLK_CTMRB1         = 20,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
16918   CTIMER_CTRL1_TMRA1CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
16919   CTIMER_CTRL1_TMRA1CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
16920   CTIMER_CTRL1_TMRA1CLK_CTMRA2         = 23,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
16921   CTIMER_CTRL1_TMRA1CLK_CTMRB2         = 24,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
16922   CTIMER_CTRL1_TMRA1CLK_CTMRB3         = 25,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
16923   CTIMER_CTRL1_TMRA1CLK_CTMRB4         = 26,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
16924   CTIMER_CTRL1_TMRA1CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
16925   CTIMER_CTRL1_TMRA1CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
16926   CTIMER_CTRL1_TMRA1CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
16927   CTIMER_CTRL1_TMRA1CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
16928   CTIMER_CTRL1_TMRA1CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
16929 } CTIMER_CTRL1_TMRA1CLK_Enum;
16930 
16931 /* ==============================================  CTIMER CTRL1 TMRA1EN [0..0]  ============================================== */
16932 typedef enum {                                  /*!< CTIMER_CTRL1_TMRA1EN                                                      */
16933   CTIMER_CTRL1_TMRA1EN_DIS             = 0,     /*!< DIS : Counter/Timer A1 Disable.                                           */
16934   CTIMER_CTRL1_TMRA1EN_EN              = 1,     /*!< EN : Counter/Timer A1 Enable.                                             */
16935 } CTIMER_CTRL1_TMRA1EN_Enum;
16936 
16937 /* =======================================================  CMPRAUXA1  ======================================================= */
16938 /* =======================================================  CMPRAUXB1  ======================================================= */
16939 /* =========================================================  AUX1  ========================================================== */
16940 /* ============================================  CTIMER AUX1 TMRB1EN23 [30..30]  ============================================= */
16941 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1EN23                                                     */
16942   CTIMER_AUX1_TMRB1EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
16943   CTIMER_AUX1_TMRB1EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
16944 } CTIMER_AUX1_TMRB1EN23_Enum;
16945 
16946 /* ============================================  CTIMER AUX1 TMRB1POL23 [29..29]  ============================================ */
16947 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1POL23                                                    */
16948   CTIMER_AUX1_TMRB1POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
16949   CTIMER_AUX1_TMRB1POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
16950 } CTIMER_AUX1_TMRB1POL23_Enum;
16951 
16952 /* ============================================  CTIMER AUX1 TMRB1TINV [28..28]  ============================================= */
16953 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1TINV                                                     */
16954   CTIMER_AUX1_TMRB1TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
16955   CTIMER_AUX1_TMRB1TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
16956 } CTIMER_AUX1_TMRB1TINV_Enum;
16957 
16958 /* ===========================================  CTIMER AUX1 TMRB1NOSYNC [27..27]  ============================================ */
16959 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1NOSYNC                                                   */
16960   CTIMER_AUX1_TMRB1NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
16961   CTIMER_AUX1_TMRB1NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
16962 } CTIMER_AUX1_TMRB1NOSYNC_Enum;
16963 
16964 /* ============================================  CTIMER AUX1 TMRB1TRIG [23..26]  ============================================= */
16965 typedef enum {                                  /*!< CTIMER_AUX1_TMRB1TRIG                                                     */
16966   CTIMER_AUX1_TMRB1TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
16967   CTIMER_AUX1_TMRB1TRIG_A1OUT          = 1,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
16968   CTIMER_AUX1_TMRB1TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
16969   CTIMER_AUX1_TMRB1TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
16970   CTIMER_AUX1_TMRB1TRIG_A6OUT          = 4,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
16971   CTIMER_AUX1_TMRB1TRIG_B6OUT          = 5,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
16972   CTIMER_AUX1_TMRB1TRIG_A0OUT          = 6,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
16973   CTIMER_AUX1_TMRB1TRIG_B0OUT          = 7,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
16974   CTIMER_AUX1_TMRB1TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
16975   CTIMER_AUX1_TMRB1TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
16976   CTIMER_AUX1_TMRB1TRIG_A4OUT2         = 10,    /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2.                                 */
16977   CTIMER_AUX1_TMRB1TRIG_B4OUT2         = 11,    /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2.                                 */
16978   CTIMER_AUX1_TMRB1TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
16979   CTIMER_AUX1_TMRB1TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
16980   CTIMER_AUX1_TMRB1TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
16981   CTIMER_AUX1_TMRB1TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
16982 } CTIMER_AUX1_TMRB1TRIG_Enum;
16983 
16984 /* ============================================  CTIMER AUX1 TMRA1EN23 [14..14]  ============================================= */
16985 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1EN23                                                     */
16986   CTIMER_AUX1_TMRA1EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
16987   CTIMER_AUX1_TMRA1EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
16988 } CTIMER_AUX1_TMRA1EN23_Enum;
16989 
16990 /* ============================================  CTIMER AUX1 TMRA1POL23 [13..13]  ============================================ */
16991 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1POL23                                                    */
16992   CTIMER_AUX1_TMRA1POL23_NORMAL        = 0,     /*!< NORMAL : Upper output normal polarity                                     */
16993   CTIMER_AUX1_TMRA1POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
16994 } CTIMER_AUX1_TMRA1POL23_Enum;
16995 
16996 /* ============================================  CTIMER AUX1 TMRA1TINV [12..12]  ============================================= */
16997 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1TINV                                                     */
16998   CTIMER_AUX1_TMRA1TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
16999   CTIMER_AUX1_TMRA1TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17000 } CTIMER_AUX1_TMRA1TINV_Enum;
17001 
17002 /* ===========================================  CTIMER AUX1 TMRA1NOSYNC [11..11]  ============================================ */
17003 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1NOSYNC                                                   */
17004   CTIMER_AUX1_TMRA1NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17005   CTIMER_AUX1_TMRA1NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17006 } CTIMER_AUX1_TMRA1NOSYNC_Enum;
17007 
17008 /* =============================================  CTIMER AUX1 TMRA1TRIG [7..10]  ============================================= */
17009 typedef enum {                                  /*!< CTIMER_AUX1_TMRA1TRIG                                                     */
17010   CTIMER_AUX1_TMRA1TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17011   CTIMER_AUX1_TMRA1TRIG_B1OUT          = 1,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
17012   CTIMER_AUX1_TMRA1TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
17013   CTIMER_AUX1_TMRA1TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
17014   CTIMER_AUX1_TMRA1TRIG_A0OUT          = 4,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
17015   CTIMER_AUX1_TMRA1TRIG_B0OUT          = 5,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
17016   CTIMER_AUX1_TMRA1TRIG_A5OUT          = 6,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
17017   CTIMER_AUX1_TMRA1TRIG_B5OUT          = 7,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
17018   CTIMER_AUX1_TMRA1TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
17019   CTIMER_AUX1_TMRA1TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
17020   CTIMER_AUX1_TMRA1TRIG_A4OUT2         = 10,    /*!< A4OUT2 : Trigger source is CTIMERA4 OUT2.                                 */
17021   CTIMER_AUX1_TMRA1TRIG_B4OUT2         = 11,    /*!< B4OUT2 : Trigger source is CTIMERB4 OUT2.                                 */
17022   CTIMER_AUX1_TMRA1TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17023   CTIMER_AUX1_TMRA1TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17024   CTIMER_AUX1_TMRA1TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
17025   CTIMER_AUX1_TMRA1TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
17026 } CTIMER_AUX1_TMRA1TRIG_Enum;
17027 
17028 /* =========================================================  TMR2  ========================================================== */
17029 /* ========================================================  CMPRA2  ========================================================= */
17030 /* ========================================================  CMPRB2  ========================================================= */
17031 /* =========================================================  CTRL2  ========================================================= */
17032 /* =============================================  CTIMER CTRL2 CTLINK2 [31..31]  ============================================= */
17033 typedef enum {                                  /*!< CTIMER_CTRL2_CTLINK2                                                      */
17034   CTIMER_CTRL2_CTLINK2_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A2/B2 timers as two independent 16-bit
17035                                                      timers (default).                                                         */
17036   CTIMER_CTRL2_CTLINK2_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A2/B2 timers into a single 32-bit timer.               */
17037 } CTIMER_CTRL2_CTLINK2_Enum;
17038 
17039 /* ============================================  CTIMER CTRL2 TMRB2POL [28..28]  ============================================= */
17040 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2POL                                                     */
17041   CTIMER_CTRL2_TMRB2POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB2 pin is the same as the
17042                                                      timer output.                                                             */
17043   CTIMER_CTRL2_TMRB2POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB2 pin is the inverse of
17044                                                      the timer output.                                                         */
17045 } CTIMER_CTRL2_TMRB2POL_Enum;
17046 
17047 /* ============================================  CTIMER CTRL2 TMRB2CLR [27..27]  ============================================= */
17048 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2CLR                                                     */
17049   CTIMER_CTRL2_TMRB2CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B2 to run                                       */
17050   CTIMER_CTRL2_TMRB2CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B2 at 0x0000.                                 */
17051 } CTIMER_CTRL2_TMRB2CLR_Enum;
17052 
17053 /* ============================================  CTIMER CTRL2 TMRB2IE1 [26..26]  ============================================= */
17054 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2IE1                                                     */
17055   CTIMER_CTRL2_TMRB2IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B2 from generating an interrupt
17056                                                      based on COMPR1.                                                          */
17057   CTIMER_CTRL2_TMRB2IE1_EN             = 1,     /*!< EN : Enable counter/timer B2 to generate an interrupt based
17058                                                      on COMPR1.                                                                */
17059 } CTIMER_CTRL2_TMRB2IE1_Enum;
17060 
17061 /* ============================================  CTIMER CTRL2 TMRB2IE0 [25..25]  ============================================= */
17062 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2IE0                                                     */
17063   CTIMER_CTRL2_TMRB2IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B2 from generating an interrupt
17064                                                      based on COMPR0.                                                          */
17065   CTIMER_CTRL2_TMRB2IE0_EN             = 1,     /*!< EN : Enable counter/timer B2 to generate an interrupt based
17066                                                      on COMPR0                                                                 */
17067 } CTIMER_CTRL2_TMRB2IE0_Enum;
17068 
17069 /* =============================================  CTIMER CTRL2 TMRB2FN [22..24]  ============================================= */
17070 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2FN                                                      */
17071   CTIMER_CTRL2_TMRB2FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17072                                                      to CMPR0B2, stop.                                                         */
17073   CTIMER_CTRL2_TMRB2FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17074                                                      pulses). Count to CMPR0B2, restart.                                       */
17075   CTIMER_CTRL2_TMRB2FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B2, assert,
17076                                                      count to CMPR1B2, deassert, stop.                                         */
17077   CTIMER_CTRL2_TMRB2FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B2, assert, count
17078                                                      to CMPR1B2, deassert, restart.                                            */
17079   CTIMER_CTRL2_TMRB2FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17080   CTIMER_CTRL2_TMRB2FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17081   CTIMER_CTRL2_TMRB2FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17082   CTIMER_CTRL2_TMRB2FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17083 } CTIMER_CTRL2_TMRB2FN_Enum;
17084 
17085 /* ============================================  CTIMER CTRL2 TMRB2CLK [17..21]  ============================================= */
17086 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2CLK                                                     */
17087   CTIMER_CTRL2_TMRB2CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
17088   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17089   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17090   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17091   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17092   CTIMER_CTRL2_TMRB2CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17093   CTIMER_CTRL2_TMRB2CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17094   CTIMER_CTRL2_TMRB2CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17095   CTIMER_CTRL2_TMRB2CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17096   CTIMER_CTRL2_TMRB2CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17097   CTIMER_CTRL2_TMRB2CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17098   CTIMER_CTRL2_TMRB2CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17099   CTIMER_CTRL2_TMRB2CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17100   CTIMER_CTRL2_TMRB2CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17101   CTIMER_CTRL2_TMRB2CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17102   CTIMER_CTRL2_TMRB2CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
17103                                                      available when MCU is in active mode)                                     */
17104   CTIMER_CTRL2_TMRB2CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17105   CTIMER_CTRL2_TMRB2CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17106   CTIMER_CTRL2_TMRB2CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17107   CTIMER_CTRL2_TMRB2CLK_CTMRA2         = 20,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
17108   CTIMER_CTRL2_TMRB2CLK_CTMRB3         = 21,    /*!< CTMRB3 : Clock source is CTIMERA3 OUT.                                    */
17109   CTIMER_CTRL2_TMRB2CLK_CTMRA3         = 22,    /*!< CTMRA3 : Clock source is CTIMERB3 OUT.                                    */
17110   CTIMER_CTRL2_TMRB2CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
17111   CTIMER_CTRL2_TMRB2CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
17112   CTIMER_CTRL2_TMRB2CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17113   CTIMER_CTRL2_TMRB2CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17114   CTIMER_CTRL2_TMRB2CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
17115   CTIMER_CTRL2_TMRB2CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17116   CTIMER_CTRL2_TMRB2CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17117   CTIMER_CTRL2_TMRB2CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17118   CTIMER_CTRL2_TMRB2CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17119 } CTIMER_CTRL2_TMRB2CLK_Enum;
17120 
17121 /* =============================================  CTIMER CTRL2 TMRB2EN [16..16]  ============================================= */
17122 typedef enum {                                  /*!< CTIMER_CTRL2_TMRB2EN                                                      */
17123   CTIMER_CTRL2_TMRB2EN_DIS             = 0,     /*!< DIS : Counter/Timer B2 Disable.                                           */
17124   CTIMER_CTRL2_TMRB2EN_EN              = 1,     /*!< EN : Counter/Timer B2 Enable.                                             */
17125 } CTIMER_CTRL2_TMRB2EN_Enum;
17126 
17127 /* ============================================  CTIMER CTRL2 TMRA2POL [12..12]  ============================================= */
17128 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2POL                                                     */
17129   CTIMER_CTRL2_TMRA2POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA2 pin is the same as the
17130                                                      timer output.                                                             */
17131   CTIMER_CTRL2_TMRA2POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA2 pin is the inverse of
17132                                                      the timer output.                                                         */
17133 } CTIMER_CTRL2_TMRA2POL_Enum;
17134 
17135 /* ============================================  CTIMER CTRL2 TMRA2CLR [11..11]  ============================================= */
17136 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2CLR                                                     */
17137   CTIMER_CTRL2_TMRA2CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A2 to run                                       */
17138   CTIMER_CTRL2_TMRA2CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A2 at 0x0000.                                 */
17139 } CTIMER_CTRL2_TMRA2CLR_Enum;
17140 
17141 /* ============================================  CTIMER CTRL2 TMRA2IE1 [10..10]  ============================================= */
17142 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2IE1                                                     */
17143   CTIMER_CTRL2_TMRA2IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A2 from generating an interrupt
17144                                                      based on COMPR1.                                                          */
17145   CTIMER_CTRL2_TMRA2IE1_EN             = 1,     /*!< EN : Enable counter/timer A2 to generate an interrupt based
17146                                                      on COMPR1.                                                                */
17147 } CTIMER_CTRL2_TMRA2IE1_Enum;
17148 
17149 /* =============================================  CTIMER CTRL2 TMRA2IE0 [9..9]  ============================================== */
17150 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2IE0                                                     */
17151   CTIMER_CTRL2_TMRA2IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A2 from generating an interrupt
17152                                                      based on COMPR0.                                                          */
17153   CTIMER_CTRL2_TMRA2IE0_EN             = 1,     /*!< EN : Enable counter/timer A2 to generate an interrupt based
17154                                                      on COMPR0.                                                                */
17155 } CTIMER_CTRL2_TMRA2IE0_Enum;
17156 
17157 /* ==============================================  CTIMER CTRL2 TMRA2FN [6..8]  ============================================== */
17158 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2FN                                                      */
17159   CTIMER_CTRL2_TMRA2FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17160                                                      to CMPR0A2, stop.                                                         */
17161   CTIMER_CTRL2_TMRA2FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17162                                                      pulses). Count to CMPR0A2, restart.                                       */
17163   CTIMER_CTRL2_TMRA2FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A2, assert,
17164                                                      count to CMPR1A2, deassert, stop.                                         */
17165   CTIMER_CTRL2_TMRA2FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A2, assert, count
17166                                                      to CMPR1A2, deassert, restart.                                            */
17167   CTIMER_CTRL2_TMRA2FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17168   CTIMER_CTRL2_TMRA2FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17169   CTIMER_CTRL2_TMRA2FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17170   CTIMER_CTRL2_TMRA2FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17171 } CTIMER_CTRL2_TMRA2FN_Enum;
17172 
17173 /* =============================================  CTIMER CTRL2 TMRA2CLK [1..5]  ============================================== */
17174 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2CLK                                                     */
17175   CTIMER_CTRL2_TMRA2CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
17176   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17177   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17178   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17179   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17180   CTIMER_CTRL2_TMRA2CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17181   CTIMER_CTRL2_TMRA2CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17182   CTIMER_CTRL2_TMRA2CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17183   CTIMER_CTRL2_TMRA2CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17184   CTIMER_CTRL2_TMRA2CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17185   CTIMER_CTRL2_TMRA2CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17186   CTIMER_CTRL2_TMRA2CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17187   CTIMER_CTRL2_TMRA2CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17188   CTIMER_CTRL2_TMRA2CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17189   CTIMER_CTRL2_TMRA2CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17190   CTIMER_CTRL2_TMRA2CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
17191                                                      available when MCU is in active mode)                                     */
17192   CTIMER_CTRL2_TMRA2CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17193   CTIMER_CTRL2_TMRA2CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17194   CTIMER_CTRL2_TMRA2CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17195   CTIMER_CTRL2_TMRA2CLK_CTMRB2         = 20,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
17196   CTIMER_CTRL2_TMRA2CLK_CTMRB3         = 21,    /*!< CTMRB3 : Clock source is CTIMERA3 OUT.                                    */
17197   CTIMER_CTRL2_TMRA2CLK_CTMRA3         = 22,    /*!< CTMRA3 : Clock source is CTIMERB3 OUT.                                    */
17198   CTIMER_CTRL2_TMRA2CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
17199   CTIMER_CTRL2_TMRA2CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
17200   CTIMER_CTRL2_TMRA2CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17201   CTIMER_CTRL2_TMRA2CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17202   CTIMER_CTRL2_TMRA2CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
17203   CTIMER_CTRL2_TMRA2CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17204   CTIMER_CTRL2_TMRA2CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17205   CTIMER_CTRL2_TMRA2CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17206   CTIMER_CTRL2_TMRA2CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17207 } CTIMER_CTRL2_TMRA2CLK_Enum;
17208 
17209 /* ==============================================  CTIMER CTRL2 TMRA2EN [0..0]  ============================================== */
17210 typedef enum {                                  /*!< CTIMER_CTRL2_TMRA2EN                                                      */
17211   CTIMER_CTRL2_TMRA2EN_DIS             = 0,     /*!< DIS : Counter/Timer A2 Disable.                                           */
17212   CTIMER_CTRL2_TMRA2EN_EN              = 1,     /*!< EN : Counter/Timer A2 Enable.                                             */
17213 } CTIMER_CTRL2_TMRA2EN_Enum;
17214 
17215 /* =======================================================  CMPRAUXA2  ======================================================= */
17216 /* =======================================================  CMPRAUXB2  ======================================================= */
17217 /* =========================================================  AUX2  ========================================================== */
17218 /* ============================================  CTIMER AUX2 TMRB2EN23 [30..30]  ============================================= */
17219 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2EN23                                                     */
17220   CTIMER_AUX2_TMRB2EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
17221   CTIMER_AUX2_TMRB2EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
17222 } CTIMER_AUX2_TMRB2EN23_Enum;
17223 
17224 /* ============================================  CTIMER AUX2 TMRB2POL23 [29..29]  ============================================ */
17225 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2POL23                                                    */
17226   CTIMER_AUX2_TMRB2POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
17227   CTIMER_AUX2_TMRB2POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
17228 } CTIMER_AUX2_TMRB2POL23_Enum;
17229 
17230 /* ============================================  CTIMER AUX2 TMRB2TINV [28..28]  ============================================= */
17231 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2TINV                                                     */
17232   CTIMER_AUX2_TMRB2TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
17233   CTIMER_AUX2_TMRB2TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17234 } CTIMER_AUX2_TMRB2TINV_Enum;
17235 
17236 /* ===========================================  CTIMER AUX2 TMRB2NOSYNC [27..27]  ============================================ */
17237 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2NOSYNC                                                   */
17238   CTIMER_AUX2_TMRB2NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17239   CTIMER_AUX2_TMRB2NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17240 } CTIMER_AUX2_TMRB2NOSYNC_Enum;
17241 
17242 /* ============================================  CTIMER AUX2 TMRB2TRIG [23..26]  ============================================= */
17243 typedef enum {                                  /*!< CTIMER_AUX2_TMRB2TRIG                                                     */
17244   CTIMER_AUX2_TMRB2TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17245   CTIMER_AUX2_TMRB2TRIG_A2OUT          = 1,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
17246   CTIMER_AUX2_TMRB2TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
17247   CTIMER_AUX2_TMRB2TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
17248   CTIMER_AUX2_TMRB2TRIG_A1OUT          = 4,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
17249   CTIMER_AUX2_TMRB2TRIG_B1OUT          = 5,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
17250   CTIMER_AUX2_TMRB2TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
17251   CTIMER_AUX2_TMRB2TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
17252   CTIMER_AUX2_TMRB2TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
17253   CTIMER_AUX2_TMRB2TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
17254   CTIMER_AUX2_TMRB2TRIG_A5OUT2         = 10,    /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
17255   CTIMER_AUX2_TMRB2TRIG_B5OUT2         = 11,    /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
17256   CTIMER_AUX2_TMRB2TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17257   CTIMER_AUX2_TMRB2TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17258   CTIMER_AUX2_TMRB2TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
17259   CTIMER_AUX2_TMRB2TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
17260 } CTIMER_AUX2_TMRB2TRIG_Enum;
17261 
17262 /* ============================================  CTIMER AUX2 TMRA2EN23 [14..14]  ============================================= */
17263 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2EN23                                                     */
17264   CTIMER_AUX2_TMRA2EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
17265   CTIMER_AUX2_TMRA2EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
17266 } CTIMER_AUX2_TMRA2EN23_Enum;
17267 
17268 /* ============================================  CTIMER AUX2 TMRA2POL23 [13..13]  ============================================ */
17269 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2POL23                                                    */
17270   CTIMER_AUX2_TMRA2POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
17271   CTIMER_AUX2_TMRA2POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
17272 } CTIMER_AUX2_TMRA2POL23_Enum;
17273 
17274 /* ============================================  CTIMER AUX2 TMRA2TINV [12..12]  ============================================= */
17275 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2TINV                                                     */
17276   CTIMER_AUX2_TMRA2TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
17277   CTIMER_AUX2_TMRA2TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17278 } CTIMER_AUX2_TMRA2TINV_Enum;
17279 
17280 /* ===========================================  CTIMER AUX2 TMRA2NOSYNC [11..11]  ============================================ */
17281 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2NOSYNC                                                   */
17282   CTIMER_AUX2_TMRA2NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17283   CTIMER_AUX2_TMRA2NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17284 } CTIMER_AUX2_TMRA2NOSYNC_Enum;
17285 
17286 /* =============================================  CTIMER AUX2 TMRA2TRIG [7..10]  ============================================= */
17287 typedef enum {                                  /*!< CTIMER_AUX2_TMRA2TRIG                                                     */
17288   CTIMER_AUX2_TMRA2TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17289   CTIMER_AUX2_TMRA2TRIG_B2OUT          = 1,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
17290   CTIMER_AUX2_TMRA2TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
17291   CTIMER_AUX2_TMRA2TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
17292   CTIMER_AUX2_TMRA2TRIG_A0OUT          = 4,     /*!< A0OUT : Trigger source is CTIMERA0 OUT.                                   */
17293   CTIMER_AUX2_TMRA2TRIG_B0OUT          = 5,     /*!< B0OUT : Trigger source is CTIMERB0 OUT.                                   */
17294   CTIMER_AUX2_TMRA2TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
17295   CTIMER_AUX2_TMRA2TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
17296   CTIMER_AUX2_TMRA2TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
17297   CTIMER_AUX2_TMRA2TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
17298   CTIMER_AUX2_TMRA2TRIG_A5OUT2         = 10,    /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
17299   CTIMER_AUX2_TMRA2TRIG_B5OUT2         = 11,    /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
17300   CTIMER_AUX2_TMRA2TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17301   CTIMER_AUX2_TMRA2TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17302   CTIMER_AUX2_TMRA2TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
17303   CTIMER_AUX2_TMRA2TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
17304 } CTIMER_AUX2_TMRA2TRIG_Enum;
17305 
17306 /* =========================================================  TMR3  ========================================================== */
17307 /* ========================================================  CMPRA3  ========================================================= */
17308 /* ========================================================  CMPRB3  ========================================================= */
17309 /* =========================================================  CTRL3  ========================================================= */
17310 /* =============================================  CTIMER CTRL3 CTLINK3 [31..31]  ============================================= */
17311 typedef enum {                                  /*!< CTIMER_CTRL3_CTLINK3                                                      */
17312   CTIMER_CTRL3_CTLINK3_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A3/B3 timers as two independent 16-bit
17313                                                      timers (default).                                                         */
17314   CTIMER_CTRL3_CTLINK3_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A3/B3 timers into a single 32-bit timer.               */
17315 } CTIMER_CTRL3_CTLINK3_Enum;
17316 
17317 /* ============================================  CTIMER CTRL3 TMRB3POL [28..28]  ============================================= */
17318 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3POL                                                     */
17319   CTIMER_CTRL3_TMRB3POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB3 pin is the same as the
17320                                                      timer output.                                                             */
17321   CTIMER_CTRL3_TMRB3POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB3 pin is the inverse of
17322                                                      the timer output.                                                         */
17323 } CTIMER_CTRL3_TMRB3POL_Enum;
17324 
17325 /* ============================================  CTIMER CTRL3 TMRB3CLR [27..27]  ============================================= */
17326 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3CLR                                                     */
17327   CTIMER_CTRL3_TMRB3CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B3 to run                                       */
17328   CTIMER_CTRL3_TMRB3CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B3 at 0x0000.                                 */
17329 } CTIMER_CTRL3_TMRB3CLR_Enum;
17330 
17331 /* ============================================  CTIMER CTRL3 TMRB3IE1 [26..26]  ============================================= */
17332 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3IE1                                                     */
17333   CTIMER_CTRL3_TMRB3IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B3 from generating an interrupt
17334                                                      based on COMPR1.                                                          */
17335   CTIMER_CTRL3_TMRB3IE1_EN             = 1,     /*!< EN : Enable counter/timer B3 to generate an interrupt based
17336                                                      on COMPR1.                                                                */
17337 } CTIMER_CTRL3_TMRB3IE1_Enum;
17338 
17339 /* ============================================  CTIMER CTRL3 TMRB3IE0 [25..25]  ============================================= */
17340 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3IE0                                                     */
17341   CTIMER_CTRL3_TMRB3IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B3 from generating an interrupt
17342                                                      based on COMPR0.                                                          */
17343   CTIMER_CTRL3_TMRB3IE0_EN             = 1,     /*!< EN : Enable counter/timer B3 to generate an interrupt based
17344                                                      on COMPR0                                                                 */
17345 } CTIMER_CTRL3_TMRB3IE0_Enum;
17346 
17347 /* =============================================  CTIMER CTRL3 TMRB3FN [22..24]  ============================================= */
17348 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3FN                                                      */
17349   CTIMER_CTRL3_TMRB3FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17350                                                      to CMPR0B3, stop.                                                         */
17351   CTIMER_CTRL3_TMRB3FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17352                                                      pulses). Count to CMPR0B3, restart.                                       */
17353   CTIMER_CTRL3_TMRB3FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B3, assert,
17354                                                      count to CMPR1B3, deassert, stop.                                         */
17355   CTIMER_CTRL3_TMRB3FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B3, assert, count
17356                                                      to CMPR1B3, deassert, restart.                                            */
17357   CTIMER_CTRL3_TMRB3FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17358   CTIMER_CTRL3_TMRB3FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17359   CTIMER_CTRL3_TMRB3FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17360   CTIMER_CTRL3_TMRB3FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17361 } CTIMER_CTRL3_TMRB3FN_Enum;
17362 
17363 /* ============================================  CTIMER CTRL3 TMRB3CLK [17..21]  ============================================= */
17364 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3CLK                                                     */
17365   CTIMER_CTRL3_TMRB3CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
17366   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17367   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17368   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17369   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17370   CTIMER_CTRL3_TMRB3CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17371   CTIMER_CTRL3_TMRB3CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17372   CTIMER_CTRL3_TMRB3CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17373   CTIMER_CTRL3_TMRB3CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17374   CTIMER_CTRL3_TMRB3CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17375   CTIMER_CTRL3_TMRB3CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17376   CTIMER_CTRL3_TMRB3CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17377   CTIMER_CTRL3_TMRB3CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17378   CTIMER_CTRL3_TMRB3CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17379   CTIMER_CTRL3_TMRB3CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17380   CTIMER_CTRL3_TMRB3CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
17381                                                      available when MCU is in active mode)                                     */
17382   CTIMER_CTRL3_TMRB3CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17383   CTIMER_CTRL3_TMRB3CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17384   CTIMER_CTRL3_TMRB3CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17385   CTIMER_CTRL3_TMRB3CLK_CTMRA3         = 20,    /*!< CTMRA3 : Clock source is CTIMERA3 OUT.                                    */
17386   CTIMER_CTRL3_TMRB3CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
17387   CTIMER_CTRL3_TMRB3CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
17388   CTIMER_CTRL3_TMRB3CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
17389   CTIMER_CTRL3_TMRB3CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
17390   CTIMER_CTRL3_TMRB3CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17391   CTIMER_CTRL3_TMRB3CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17392   CTIMER_CTRL3_TMRB3CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
17393   CTIMER_CTRL3_TMRB3CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17394   CTIMER_CTRL3_TMRB3CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17395   CTIMER_CTRL3_TMRB3CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17396   CTIMER_CTRL3_TMRB3CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17397 } CTIMER_CTRL3_TMRB3CLK_Enum;
17398 
17399 /* =============================================  CTIMER CTRL3 TMRB3EN [16..16]  ============================================= */
17400 typedef enum {                                  /*!< CTIMER_CTRL3_TMRB3EN                                                      */
17401   CTIMER_CTRL3_TMRB3EN_DIS             = 0,     /*!< DIS : Counter/Timer B3 Disable.                                           */
17402   CTIMER_CTRL3_TMRB3EN_EN              = 1,     /*!< EN : Counter/Timer B3 Enable.                                             */
17403 } CTIMER_CTRL3_TMRB3EN_Enum;
17404 
17405 /* ============================================  CTIMER CTRL3 TMRA3POL [12..12]  ============================================= */
17406 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3POL                                                     */
17407   CTIMER_CTRL3_TMRA3POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA3 pin is the same as the
17408                                                      timer output.                                                             */
17409   CTIMER_CTRL3_TMRA3POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA3 pin is the inverse of
17410                                                      the timer output.                                                         */
17411 } CTIMER_CTRL3_TMRA3POL_Enum;
17412 
17413 /* ============================================  CTIMER CTRL3 TMRA3CLR [11..11]  ============================================= */
17414 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3CLR                                                     */
17415   CTIMER_CTRL3_TMRA3CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A3 to run                                       */
17416   CTIMER_CTRL3_TMRA3CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A3 at 0x0000.                                 */
17417 } CTIMER_CTRL3_TMRA3CLR_Enum;
17418 
17419 /* ============================================  CTIMER CTRL3 TMRA3IE1 [10..10]  ============================================= */
17420 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3IE1                                                     */
17421   CTIMER_CTRL3_TMRA3IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A3 from generating an interrupt
17422                                                      based on COMPR1.                                                          */
17423   CTIMER_CTRL3_TMRA3IE1_EN             = 1,     /*!< EN : Enable counter/timer A3 to generate an interrupt based
17424                                                      on COMPR1.                                                                */
17425 } CTIMER_CTRL3_TMRA3IE1_Enum;
17426 
17427 /* =============================================  CTIMER CTRL3 TMRA3IE0 [9..9]  ============================================== */
17428 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3IE0                                                     */
17429   CTIMER_CTRL3_TMRA3IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A3 from generating an interrupt
17430                                                      based on COMPR0.                                                          */
17431   CTIMER_CTRL3_TMRA3IE0_EN             = 1,     /*!< EN : Enable counter/timer A3 to generate an interrupt based
17432                                                      on COMPR0.                                                                */
17433 } CTIMER_CTRL3_TMRA3IE0_Enum;
17434 
17435 /* ==============================================  CTIMER CTRL3 TMRA3FN [6..8]  ============================================== */
17436 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3FN                                                      */
17437   CTIMER_CTRL3_TMRA3FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17438                                                      to CMPR0A3, stop.                                                         */
17439   CTIMER_CTRL3_TMRA3FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17440                                                      pulses). Count to CMPR0A3, restart.                                       */
17441   CTIMER_CTRL3_TMRA3FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A3, assert,
17442                                                      count to CMPR1A3, deassert, stop.                                         */
17443   CTIMER_CTRL3_TMRA3FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A3, assert, count
17444                                                      to CMPR1A3, deassert, restart.                                            */
17445   CTIMER_CTRL3_TMRA3FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17446   CTIMER_CTRL3_TMRA3FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17447   CTIMER_CTRL3_TMRA3FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17448   CTIMER_CTRL3_TMRA3FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17449 } CTIMER_CTRL3_TMRA3FN_Enum;
17450 
17451 /* =============================================  CTIMER CTRL3 TMRA3CLK [1..5]  ============================================== */
17452 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3CLK                                                     */
17453   CTIMER_CTRL3_TMRA3CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
17454   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17455   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17456   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17457   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17458   CTIMER_CTRL3_TMRA3CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17459   CTIMER_CTRL3_TMRA3CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17460   CTIMER_CTRL3_TMRA3CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17461   CTIMER_CTRL3_TMRA3CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17462   CTIMER_CTRL3_TMRA3CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17463   CTIMER_CTRL3_TMRA3CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17464   CTIMER_CTRL3_TMRA3CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17465   CTIMER_CTRL3_TMRA3CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17466   CTIMER_CTRL3_TMRA3CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17467   CTIMER_CTRL3_TMRA3CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17468   CTIMER_CTRL3_TMRA3CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
17469                                                      available when MCU is in active mode)                                     */
17470   CTIMER_CTRL3_TMRA3CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17471   CTIMER_CTRL3_TMRA3CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17472   CTIMER_CTRL3_TMRA3CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17473   CTIMER_CTRL3_TMRA3CLK_CTMRB3         = 20,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
17474   CTIMER_CTRL3_TMRA3CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
17475   CTIMER_CTRL3_TMRA3CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
17476   CTIMER_CTRL3_TMRA3CLK_CTMRA4         = 23,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
17477   CTIMER_CTRL3_TMRA3CLK_CTMRB4         = 24,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
17478   CTIMER_CTRL3_TMRA3CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17479   CTIMER_CTRL3_TMRA3CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17480   CTIMER_CTRL3_TMRA3CLK_CTMRB5         = 27,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
17481   CTIMER_CTRL3_TMRA3CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17482   CTIMER_CTRL3_TMRA3CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17483   CTIMER_CTRL3_TMRA3CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17484   CTIMER_CTRL3_TMRA3CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17485 } CTIMER_CTRL3_TMRA3CLK_Enum;
17486 
17487 /* ==============================================  CTIMER CTRL3 TMRA3EN [0..0]  ============================================== */
17488 typedef enum {                                  /*!< CTIMER_CTRL3_TMRA3EN                                                      */
17489   CTIMER_CTRL3_TMRA3EN_DIS             = 0,     /*!< DIS : Counter/Timer A3 Disable.                                           */
17490   CTIMER_CTRL3_TMRA3EN_EN              = 1,     /*!< EN : Counter/Timer A3 Enable.                                             */
17491 } CTIMER_CTRL3_TMRA3EN_Enum;
17492 
17493 /* =======================================================  CMPRAUXA3  ======================================================= */
17494 /* =======================================================  CMPRAUXB3  ======================================================= */
17495 /* =========================================================  AUX3  ========================================================== */
17496 /* ============================================  CTIMER AUX3 TMRB3EN23 [30..30]  ============================================= */
17497 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3EN23                                                     */
17498   CTIMER_AUX3_TMRB3EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
17499   CTIMER_AUX3_TMRB3EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
17500 } CTIMER_AUX3_TMRB3EN23_Enum;
17501 
17502 /* ============================================  CTIMER AUX3 TMRB3POL23 [29..29]  ============================================ */
17503 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3POL23                                                    */
17504   CTIMER_AUX3_TMRB3POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
17505   CTIMER_AUX3_TMRB3POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
17506 } CTIMER_AUX3_TMRB3POL23_Enum;
17507 
17508 /* ============================================  CTIMER AUX3 TMRB3TINV [28..28]  ============================================= */
17509 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3TINV                                                     */
17510   CTIMER_AUX3_TMRB3TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
17511   CTIMER_AUX3_TMRB3TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17512 } CTIMER_AUX3_TMRB3TINV_Enum;
17513 
17514 /* ===========================================  CTIMER AUX3 TMRB3NOSYNC [27..27]  ============================================ */
17515 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3NOSYNC                                                   */
17516   CTIMER_AUX3_TMRB3NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17517   CTIMER_AUX3_TMRB3NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17518 } CTIMER_AUX3_TMRB3NOSYNC_Enum;
17519 
17520 /* ============================================  CTIMER AUX3 TMRB3TRIG [23..26]  ============================================= */
17521 typedef enum {                                  /*!< CTIMER_AUX3_TMRB3TRIG                                                     */
17522   CTIMER_AUX3_TMRB3TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17523   CTIMER_AUX3_TMRB3TRIG_A3OUT          = 1,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
17524   CTIMER_AUX3_TMRB3TRIG_B2OUT          = 2,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
17525   CTIMER_AUX3_TMRB3TRIG_A2OUT          = 3,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
17526   CTIMER_AUX3_TMRB3TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
17527   CTIMER_AUX3_TMRB3TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
17528   CTIMER_AUX3_TMRB3TRIG_A6OUT          = 6,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
17529   CTIMER_AUX3_TMRB3TRIG_B6OUT          = 7,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
17530   CTIMER_AUX3_TMRB3TRIG_B5OUT2         = 8,     /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
17531   CTIMER_AUX3_TMRB3TRIG_A5OUT2         = 9,     /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
17532   CTIMER_AUX3_TMRB3TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
17533   CTIMER_AUX3_TMRB3TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
17534   CTIMER_AUX3_TMRB3TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17535   CTIMER_AUX3_TMRB3TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17536   CTIMER_AUX3_TMRB3TRIG_B2OUT2DUAL     = 14,    /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge.                  */
17537   CTIMER_AUX3_TMRB3TRIG_A2OUT2DUAL     = 15,    /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge.                  */
17538 } CTIMER_AUX3_TMRB3TRIG_Enum;
17539 
17540 /* ============================================  CTIMER AUX3 TMRA3EN23 [14..14]  ============================================= */
17541 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3EN23                                                     */
17542   CTIMER_AUX3_TMRA3EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
17543   CTIMER_AUX3_TMRA3EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
17544 } CTIMER_AUX3_TMRA3EN23_Enum;
17545 
17546 /* ============================================  CTIMER AUX3 TMRA3POL23 [13..13]  ============================================ */
17547 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3POL23                                                    */
17548   CTIMER_AUX3_TMRA3POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
17549   CTIMER_AUX3_TMRA3POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
17550 } CTIMER_AUX3_TMRA3POL23_Enum;
17551 
17552 /* ============================================  CTIMER AUX3 TMRA3TINV [12..12]  ============================================= */
17553 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3TINV                                                     */
17554   CTIMER_AUX3_TMRA3TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
17555   CTIMER_AUX3_TMRA3TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17556 } CTIMER_AUX3_TMRA3TINV_Enum;
17557 
17558 /* ===========================================  CTIMER AUX3 TMRA3NOSYNC [11..11]  ============================================ */
17559 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3NOSYNC                                                   */
17560   CTIMER_AUX3_TMRA3NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17561   CTIMER_AUX3_TMRA3NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17562 } CTIMER_AUX3_TMRA3NOSYNC_Enum;
17563 
17564 /* =============================================  CTIMER AUX3 TMRA3TRIG [7..10]  ============================================= */
17565 typedef enum {                                  /*!< CTIMER_AUX3_TMRA3TRIG                                                     */
17566   CTIMER_AUX3_TMRA3TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17567   CTIMER_AUX3_TMRA3TRIG_B3OUT          = 1,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
17568   CTIMER_AUX3_TMRA3TRIG_B2OUT          = 2,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
17569   CTIMER_AUX3_TMRA3TRIG_A2OUT          = 3,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
17570   CTIMER_AUX3_TMRA3TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
17571   CTIMER_AUX3_TMRA3TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
17572   CTIMER_AUX3_TMRA3TRIG_A7OUT          = 6,     /*!< A7OUT : Trigger source is CTIMERA7 OUT.                                   */
17573   CTIMER_AUX3_TMRA3TRIG_B7OUT          = 7,     /*!< B7OUT : Trigger source is CTIMERB7 OUT.                                   */
17574   CTIMER_AUX3_TMRA3TRIG_B5OUT2         = 8,     /*!< B5OUT2 : Trigger source is CTIMERB5 OUT2.                                 */
17575   CTIMER_AUX3_TMRA3TRIG_A5OUT2         = 9,     /*!< A5OUT2 : Trigger source is CTIMERA5 OUT2.                                 */
17576   CTIMER_AUX3_TMRA3TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
17577   CTIMER_AUX3_TMRA3TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
17578   CTIMER_AUX3_TMRA3TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17579   CTIMER_AUX3_TMRA3TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17580   CTIMER_AUX3_TMRA3TRIG_B2OUT2DUAL     = 14,    /*!< B2OUT2DUAL : Trigger source is CTIMERB2 OUT2, dual edge.                  */
17581   CTIMER_AUX3_TMRA3TRIG_A2OUT2DUAL     = 15,    /*!< A2OUT2DUAL : Trigger source is CTIMERA2 OUT2, dual edge.                  */
17582 } CTIMER_AUX3_TMRA3TRIG_Enum;
17583 
17584 /* =========================================================  TMR4  ========================================================== */
17585 /* ========================================================  CMPRA4  ========================================================= */
17586 /* ========================================================  CMPRB4  ========================================================= */
17587 /* =========================================================  CTRL4  ========================================================= */
17588 /* =============================================  CTIMER CTRL4 CTLINK4 [31..31]  ============================================= */
17589 typedef enum {                                  /*!< CTIMER_CTRL4_CTLINK4                                                      */
17590   CTIMER_CTRL4_CTLINK4_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A4/B4 timers as two independent 16-bit
17591                                                      timers (default).                                                         */
17592   CTIMER_CTRL4_CTLINK4_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A4/B4 timers into a single 32-bit timer.               */
17593 } CTIMER_CTRL4_CTLINK4_Enum;
17594 
17595 /* ============================================  CTIMER CTRL4 TMRB4POL [28..28]  ============================================= */
17596 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4POL                                                     */
17597   CTIMER_CTRL4_TMRB4POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB4 pin is the same as the
17598                                                      timer output.                                                             */
17599   CTIMER_CTRL4_TMRB4POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB4 pin is the inverse of
17600                                                      the timer output.                                                         */
17601 } CTIMER_CTRL4_TMRB4POL_Enum;
17602 
17603 /* ============================================  CTIMER CTRL4 TMRB4CLR [27..27]  ============================================= */
17604 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4CLR                                                     */
17605   CTIMER_CTRL4_TMRB4CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B4 to run                                       */
17606   CTIMER_CTRL4_TMRB4CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B4 at 0x0000.                                 */
17607 } CTIMER_CTRL4_TMRB4CLR_Enum;
17608 
17609 /* ============================================  CTIMER CTRL4 TMRB4IE1 [26..26]  ============================================= */
17610 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4IE1                                                     */
17611   CTIMER_CTRL4_TMRB4IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B4 from generating an interrupt
17612                                                      based on COMPR1.                                                          */
17613   CTIMER_CTRL4_TMRB4IE1_EN             = 1,     /*!< EN : Enable counter/timer B4 to generate an interrupt based
17614                                                      on COMPR1.                                                                */
17615 } CTIMER_CTRL4_TMRB4IE1_Enum;
17616 
17617 /* ============================================  CTIMER CTRL4 TMRB4IE0 [25..25]  ============================================= */
17618 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4IE0                                                     */
17619   CTIMER_CTRL4_TMRB4IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B4 from generating an interrupt
17620                                                      based on COMPR0.                                                          */
17621   CTIMER_CTRL4_TMRB4IE0_EN             = 1,     /*!< EN : Enable counter/timer B4 to generate an interrupt based
17622                                                      on COMPR0                                                                 */
17623 } CTIMER_CTRL4_TMRB4IE0_Enum;
17624 
17625 /* =============================================  CTIMER CTRL4 TMRB4FN [22..24]  ============================================= */
17626 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4FN                                                      */
17627   CTIMER_CTRL4_TMRB4FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17628                                                      to CMPR0B4, stop.                                                         */
17629   CTIMER_CTRL4_TMRB4FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17630                                                      pulses). Count to CMPR0B4, restart.                                       */
17631   CTIMER_CTRL4_TMRB4FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B4, assert,
17632                                                      count to CMPR1B4, deassert, stop.                                         */
17633   CTIMER_CTRL4_TMRB4FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B4, assert, count
17634                                                      to CMPR1B4, deassert, restart.                                            */
17635   CTIMER_CTRL4_TMRB4FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17636   CTIMER_CTRL4_TMRB4FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17637   CTIMER_CTRL4_TMRB4FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17638   CTIMER_CTRL4_TMRB4FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17639 } CTIMER_CTRL4_TMRB4FN_Enum;
17640 
17641 /* ============================================  CTIMER CTRL4 TMRB4CLK [17..21]  ============================================= */
17642 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4CLK                                                     */
17643   CTIMER_CTRL4_TMRB4CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
17644   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17645   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17646   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17647   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17648   CTIMER_CTRL4_TMRB4CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17649   CTIMER_CTRL4_TMRB4CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17650   CTIMER_CTRL4_TMRB4CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17651   CTIMER_CTRL4_TMRB4CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17652   CTIMER_CTRL4_TMRB4CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17653   CTIMER_CTRL4_TMRB4CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17654   CTIMER_CTRL4_TMRB4CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17655   CTIMER_CTRL4_TMRB4CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17656   CTIMER_CTRL4_TMRB4CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17657   CTIMER_CTRL4_TMRB4CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17658   CTIMER_CTRL4_TMRB4CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
17659                                                      available when MCU is in active mode)                                     */
17660   CTIMER_CTRL4_TMRB4CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17661   CTIMER_CTRL4_TMRB4CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17662   CTIMER_CTRL4_TMRB4CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17663   CTIMER_CTRL4_TMRB4CLK_CTMRA4         = 20,    /*!< CTMRA4 : Clock source is CTIMERA4 OUT.                                    */
17664   CTIMER_CTRL4_TMRB4CLK_CTMRA1         = 21,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
17665   CTIMER_CTRL4_TMRB4CLK_CTMRB1         = 22,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17666   CTIMER_CTRL4_TMRB4CLK_CTMRA5         = 23,    /*!< CTMRA5 : Clock source is CTIMERA5 OUT.                                    */
17667   CTIMER_CTRL4_TMRB4CLK_CTMRB5         = 24,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
17668   CTIMER_CTRL4_TMRB4CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17669   CTIMER_CTRL4_TMRB4CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
17670   CTIMER_CTRL4_TMRB4CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
17671   CTIMER_CTRL4_TMRB4CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17672   CTIMER_CTRL4_TMRB4CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17673   CTIMER_CTRL4_TMRB4CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17674   CTIMER_CTRL4_TMRB4CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17675 } CTIMER_CTRL4_TMRB4CLK_Enum;
17676 
17677 /* =============================================  CTIMER CTRL4 TMRB4EN [16..16]  ============================================= */
17678 typedef enum {                                  /*!< CTIMER_CTRL4_TMRB4EN                                                      */
17679   CTIMER_CTRL4_TMRB4EN_DIS             = 0,     /*!< DIS : Counter/Timer B4 Disable.                                           */
17680   CTIMER_CTRL4_TMRB4EN_EN              = 1,     /*!< EN : Counter/Timer B4 Enable.                                             */
17681 } CTIMER_CTRL4_TMRB4EN_Enum;
17682 
17683 /* ============================================  CTIMER CTRL4 TMRA4POL [12..12]  ============================================= */
17684 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4POL                                                     */
17685   CTIMER_CTRL4_TMRA4POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA4 pin is the same as the
17686                                                      timer output.                                                             */
17687   CTIMER_CTRL4_TMRA4POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA4 pin is the inverse of
17688                                                      the timer output.                                                         */
17689 } CTIMER_CTRL4_TMRA4POL_Enum;
17690 
17691 /* ============================================  CTIMER CTRL4 TMRA4CLR [11..11]  ============================================= */
17692 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4CLR                                                     */
17693   CTIMER_CTRL4_TMRA4CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A4 to run                                       */
17694   CTIMER_CTRL4_TMRA4CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A4 at 0x0000.                                 */
17695 } CTIMER_CTRL4_TMRA4CLR_Enum;
17696 
17697 /* ============================================  CTIMER CTRL4 TMRA4IE1 [10..10]  ============================================= */
17698 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4IE1                                                     */
17699   CTIMER_CTRL4_TMRA4IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A4 from generating an interrupt
17700                                                      based on COMPR1.                                                          */
17701   CTIMER_CTRL4_TMRA4IE1_EN             = 1,     /*!< EN : Enable counter/timer A4 to generate an interrupt based
17702                                                      on COMPR1.                                                                */
17703 } CTIMER_CTRL4_TMRA4IE1_Enum;
17704 
17705 /* =============================================  CTIMER CTRL4 TMRA4IE0 [9..9]  ============================================== */
17706 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4IE0                                                     */
17707   CTIMER_CTRL4_TMRA4IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A4 from generating an interrupt
17708                                                      based on COMPR0.                                                          */
17709   CTIMER_CTRL4_TMRA4IE0_EN             = 1,     /*!< EN : Enable counter/timer A4 to generate an interrupt based
17710                                                      on COMPR0.                                                                */
17711 } CTIMER_CTRL4_TMRA4IE0_Enum;
17712 
17713 /* ==============================================  CTIMER CTRL4 TMRA4FN [6..8]  ============================================== */
17714 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4FN                                                      */
17715   CTIMER_CTRL4_TMRA4FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17716                                                      to CMPR0A4, stop.                                                         */
17717   CTIMER_CTRL4_TMRA4FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17718                                                      pulses). Count to CMPR0A4, restart.                                       */
17719   CTIMER_CTRL4_TMRA4FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A4, assert,
17720                                                      count to CMPR1A4, deassert, stop.                                         */
17721   CTIMER_CTRL4_TMRA4FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A4, assert, count
17722                                                      to CMPR1A4, deassert, restart.                                            */
17723   CTIMER_CTRL4_TMRA4FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17724   CTIMER_CTRL4_TMRA4FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17725   CTIMER_CTRL4_TMRA4FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17726   CTIMER_CTRL4_TMRA4FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17727 } CTIMER_CTRL4_TMRA4FN_Enum;
17728 
17729 /* =============================================  CTIMER CTRL4 TMRA4CLK [1..5]  ============================================== */
17730 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4CLK                                                     */
17731   CTIMER_CTRL4_TMRA4CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
17732   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17733   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17734   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17735   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17736   CTIMER_CTRL4_TMRA4CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17737   CTIMER_CTRL4_TMRA4CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17738   CTIMER_CTRL4_TMRA4CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17739   CTIMER_CTRL4_TMRA4CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17740   CTIMER_CTRL4_TMRA4CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17741   CTIMER_CTRL4_TMRA4CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17742   CTIMER_CTRL4_TMRA4CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17743   CTIMER_CTRL4_TMRA4CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17744   CTIMER_CTRL4_TMRA4CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17745   CTIMER_CTRL4_TMRA4CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17746   CTIMER_CTRL4_TMRA4CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4. (note: this clock is only
17747                                                      available when MCU is in active mode)                                     */
17748   CTIMER_CTRL4_TMRA4CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17749   CTIMER_CTRL4_TMRA4CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17750   CTIMER_CTRL4_TMRA4CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17751   CTIMER_CTRL4_TMRA4CLK_CTMRB4         = 20,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
17752   CTIMER_CTRL4_TMRA4CLK_CTMRA1         = 21,    /*!< CTMRA1 : Clock source is CTIMERA1 OUT.                                    */
17753   CTIMER_CTRL4_TMRA4CLK_CTMRB1         = 22,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17754   CTIMER_CTRL4_TMRA4CLK_CTMRA5         = 23,    /*!< CTMRA5 : Clock source is CTIMERA5 OUT.                                    */
17755   CTIMER_CTRL4_TMRA4CLK_CTMRB5         = 24,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
17756   CTIMER_CTRL4_TMRA4CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17757   CTIMER_CTRL4_TMRA4CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
17758   CTIMER_CTRL4_TMRA4CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
17759   CTIMER_CTRL4_TMRA4CLK_CTMRB6         = 28,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17760   CTIMER_CTRL4_TMRA4CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17761   CTIMER_CTRL4_TMRA4CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17762   CTIMER_CTRL4_TMRA4CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17763 } CTIMER_CTRL4_TMRA4CLK_Enum;
17764 
17765 /* ==============================================  CTIMER CTRL4 TMRA4EN [0..0]  ============================================== */
17766 typedef enum {                                  /*!< CTIMER_CTRL4_TMRA4EN                                                      */
17767   CTIMER_CTRL4_TMRA4EN_DIS             = 0,     /*!< DIS : Counter/Timer A4 Disable.                                           */
17768   CTIMER_CTRL4_TMRA4EN_EN              = 1,     /*!< EN : Counter/Timer A4 Enable.                                             */
17769 } CTIMER_CTRL4_TMRA4EN_Enum;
17770 
17771 /* =======================================================  CMPRAUXA4  ======================================================= */
17772 /* =======================================================  CMPRAUXB4  ======================================================= */
17773 /* =========================================================  AUX4  ========================================================== */
17774 /* ============================================  CTIMER AUX4 TMRB4EN23 [30..30]  ============================================= */
17775 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4EN23                                                     */
17776   CTIMER_AUX4_TMRB4EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
17777   CTIMER_AUX4_TMRB4EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
17778 } CTIMER_AUX4_TMRB4EN23_Enum;
17779 
17780 /* ============================================  CTIMER AUX4 TMRB4POL23 [29..29]  ============================================ */
17781 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4POL23                                                    */
17782   CTIMER_AUX4_TMRB4POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
17783   CTIMER_AUX4_TMRB4POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
17784 } CTIMER_AUX4_TMRB4POL23_Enum;
17785 
17786 /* ============================================  CTIMER AUX4 TMRB4TINV [28..28]  ============================================= */
17787 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4TINV                                                     */
17788   CTIMER_AUX4_TMRB4TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
17789   CTIMER_AUX4_TMRB4TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17790 } CTIMER_AUX4_TMRB4TINV_Enum;
17791 
17792 /* ===========================================  CTIMER AUX4 TMRB4NOSYNC [27..27]  ============================================ */
17793 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4NOSYNC                                                   */
17794   CTIMER_AUX4_TMRB4NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17795   CTIMER_AUX4_TMRB4NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17796 } CTIMER_AUX4_TMRB4NOSYNC_Enum;
17797 
17798 /* ============================================  CTIMER AUX4 TMRB4TRIG [23..26]  ============================================= */
17799 typedef enum {                                  /*!< CTIMER_AUX4_TMRB4TRIG                                                     */
17800   CTIMER_AUX4_TMRB4TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17801   CTIMER_AUX4_TMRB4TRIG_A4OUT          = 1,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
17802   CTIMER_AUX4_TMRB4TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
17803   CTIMER_AUX4_TMRB4TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
17804   CTIMER_AUX4_TMRB4TRIG_A7OUT          = 4,     /*!< A7OUT : Trigger source is CTIMERA7 OUT.                                   */
17805   CTIMER_AUX4_TMRB4TRIG_B7OUT          = 5,     /*!< B7OUT : Trigger source is CTIMERB7 OUT.                                   */
17806   CTIMER_AUX4_TMRB4TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
17807   CTIMER_AUX4_TMRB4TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
17808   CTIMER_AUX4_TMRB4TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
17809   CTIMER_AUX4_TMRB4TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
17810   CTIMER_AUX4_TMRB4TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
17811   CTIMER_AUX4_TMRB4TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
17812   CTIMER_AUX4_TMRB4TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17813   CTIMER_AUX4_TMRB4TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17814   CTIMER_AUX4_TMRB4TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
17815   CTIMER_AUX4_TMRB4TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
17816 } CTIMER_AUX4_TMRB4TRIG_Enum;
17817 
17818 /* ============================================  CTIMER AUX4 TMRA4EN23 [14..14]  ============================================= */
17819 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4EN23                                                     */
17820   CTIMER_AUX4_TMRA4EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
17821   CTIMER_AUX4_TMRA4EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
17822 } CTIMER_AUX4_TMRA4EN23_Enum;
17823 
17824 /* ============================================  CTIMER AUX4 TMRA4POL23 [13..13]  ============================================ */
17825 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4POL23                                                    */
17826   CTIMER_AUX4_TMRA4POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
17827   CTIMER_AUX4_TMRA4POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
17828 } CTIMER_AUX4_TMRA4POL23_Enum;
17829 
17830 /* ============================================  CTIMER AUX4 TMRA4TINV [12..12]  ============================================= */
17831 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4TINV                                                     */
17832   CTIMER_AUX4_TMRA4TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
17833   CTIMER_AUX4_TMRA4TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
17834 } CTIMER_AUX4_TMRA4TINV_Enum;
17835 
17836 /* ===========================================  CTIMER AUX4 TMRA4NOSYNC [11..11]  ============================================ */
17837 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4NOSYNC                                                   */
17838   CTIMER_AUX4_TMRA4NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
17839   CTIMER_AUX4_TMRA4NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
17840 } CTIMER_AUX4_TMRA4NOSYNC_Enum;
17841 
17842 /* =============================================  CTIMER AUX4 TMRA4TRIG [7..10]  ============================================= */
17843 typedef enum {                                  /*!< CTIMER_AUX4_TMRA4TRIG                                                     */
17844   CTIMER_AUX4_TMRA4TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
17845   CTIMER_AUX4_TMRA4TRIG_STIMER         = 1,     /*!< STIMER : Trigger source is STimer Interrupt. Only Active When
17846                                                      CTLINK==1 and TMRB4TRIG!=0. TMRB4TRIG selects an STIMER
17847                                                      interrupt                                                                 */
17848   CTIMER_AUX4_TMRA4TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
17849   CTIMER_AUX4_TMRA4TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
17850   CTIMER_AUX4_TMRA4TRIG_A6OUT          = 4,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
17851   CTIMER_AUX4_TMRA4TRIG_B6OUT          = 5,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
17852   CTIMER_AUX4_TMRA4TRIG_A2OUT          = 6,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
17853   CTIMER_AUX4_TMRA4TRIG_B2OUT          = 7,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
17854   CTIMER_AUX4_TMRA4TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
17855   CTIMER_AUX4_TMRA4TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
17856   CTIMER_AUX4_TMRA4TRIG_A1OUT2         = 10,    /*!< A1OUT2 : Trigger source is CTIMERA1 OUT2.                                 */
17857   CTIMER_AUX4_TMRA4TRIG_B1OUT2         = 11,    /*!< B1OUT2 : Trigger source is CTIMERB1 OUT2.                                 */
17858   CTIMER_AUX4_TMRA4TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
17859   CTIMER_AUX4_TMRA4TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
17860   CTIMER_AUX4_TMRA4TRIG_B5OUT2DUAL     = 14,    /*!< B5OUT2DUAL : Trigger source is CTIMERB5 OUT2, dual edge.                  */
17861   CTIMER_AUX4_TMRA4TRIG_A5OUT2DUAL     = 15,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
17862 } CTIMER_AUX4_TMRA4TRIG_Enum;
17863 
17864 /* =========================================================  TMR5  ========================================================== */
17865 /* ========================================================  CMPRA5  ========================================================= */
17866 /* ========================================================  CMPRB5  ========================================================= */
17867 /* =========================================================  CTRL5  ========================================================= */
17868 /* =============================================  CTIMER CTRL5 CTLINK5 [31..31]  ============================================= */
17869 typedef enum {                                  /*!< CTIMER_CTRL5_CTLINK5                                                      */
17870   CTIMER_CTRL5_CTLINK5_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A5/B5 timers as two independent 16-bit
17871                                                      timers (default).                                                         */
17872   CTIMER_CTRL5_CTLINK5_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A5/B5 timers into a single 32-bit timer.               */
17873 } CTIMER_CTRL5_CTLINK5_Enum;
17874 
17875 /* ============================================  CTIMER CTRL5 TMRB5POL [28..28]  ============================================= */
17876 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5POL                                                     */
17877   CTIMER_CTRL5_TMRB5POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB5 pin is the same as the
17878                                                      timer output.                                                             */
17879   CTIMER_CTRL5_TMRB5POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB5 pin is the inverse of
17880                                                      the timer output.                                                         */
17881 } CTIMER_CTRL5_TMRB5POL_Enum;
17882 
17883 /* ============================================  CTIMER CTRL5 TMRB5CLR [27..27]  ============================================= */
17884 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5CLR                                                     */
17885   CTIMER_CTRL5_TMRB5CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B5 to run                                       */
17886   CTIMER_CTRL5_TMRB5CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B5 at 0x0000.                                 */
17887 } CTIMER_CTRL5_TMRB5CLR_Enum;
17888 
17889 /* ============================================  CTIMER CTRL5 TMRB5IE1 [26..26]  ============================================= */
17890 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5IE1                                                     */
17891   CTIMER_CTRL5_TMRB5IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B5 from generating an interrupt
17892                                                      based on COMPR1.                                                          */
17893   CTIMER_CTRL5_TMRB5IE1_EN             = 1,     /*!< EN : Enable counter/timer B5 to generate an interrupt based
17894                                                      on COMPR1.                                                                */
17895 } CTIMER_CTRL5_TMRB5IE1_Enum;
17896 
17897 /* ============================================  CTIMER CTRL5 TMRB5IE0 [25..25]  ============================================= */
17898 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5IE0                                                     */
17899   CTIMER_CTRL5_TMRB5IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B5 from generating an interrupt
17900                                                      based on COMPR0.                                                          */
17901   CTIMER_CTRL5_TMRB5IE0_EN             = 1,     /*!< EN : Enable counter/timer B5 to generate an interrupt based
17902                                                      on COMPR0                                                                 */
17903 } CTIMER_CTRL5_TMRB5IE0_Enum;
17904 
17905 /* =============================================  CTIMER CTRL5 TMRB5FN [22..24]  ============================================= */
17906 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5FN                                                      */
17907   CTIMER_CTRL5_TMRB5FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17908                                                      to CMPR0B5, stop.                                                         */
17909   CTIMER_CTRL5_TMRB5FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17910                                                      pulses). Count to CMPR0B5, restart.                                       */
17911   CTIMER_CTRL5_TMRB5FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B5, assert,
17912                                                      count to CMPR1B5, deassert, stop.                                         */
17913   CTIMER_CTRL5_TMRB5FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B5, assert, count
17914                                                      to CMPR1B5, deassert, restart.                                            */
17915   CTIMER_CTRL5_TMRB5FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
17916   CTIMER_CTRL5_TMRB5FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
17917   CTIMER_CTRL5_TMRB5FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
17918   CTIMER_CTRL5_TMRB5FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
17919 } CTIMER_CTRL5_TMRB5FN_Enum;
17920 
17921 /* ============================================  CTIMER CTRL5 TMRB5CLK [17..21]  ============================================= */
17922 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5CLK                                                     */
17923   CTIMER_CTRL5_TMRB5CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
17924   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
17925   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
17926   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
17927   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
17928   CTIMER_CTRL5_TMRB5CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
17929   CTIMER_CTRL5_TMRB5CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
17930   CTIMER_CTRL5_TMRB5CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
17931   CTIMER_CTRL5_TMRB5CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
17932   CTIMER_CTRL5_TMRB5CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
17933   CTIMER_CTRL5_TMRB5CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
17934   CTIMER_CTRL5_TMRB5CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
17935   CTIMER_CTRL5_TMRB5CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
17936   CTIMER_CTRL5_TMRB5CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
17937   CTIMER_CTRL5_TMRB5CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
17938   CTIMER_CTRL5_TMRB5CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
17939                                                      available when MCU is in active mode)                                     */
17940   CTIMER_CTRL5_TMRB5CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
17941   CTIMER_CTRL5_TMRB5CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
17942   CTIMER_CTRL5_TMRB5CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
17943   CTIMER_CTRL5_TMRB5CLK_CTMRA5         = 20,    /*!< CTMRA5 : Clock source is CTIMERA5 OUT.                                    */
17944   CTIMER_CTRL5_TMRB5CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
17945   CTIMER_CTRL5_TMRB5CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
17946   CTIMER_CTRL5_TMRB5CLK_CTMRA6         = 23,    /*!< CTMRA6 : Clock source is CTIMERA6 OUT.                                    */
17947   CTIMER_CTRL5_TMRB5CLK_CTMRB6         = 24,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
17948   CTIMER_CTRL5_TMRB5CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
17949   CTIMER_CTRL5_TMRB5CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
17950   CTIMER_CTRL5_TMRB5CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
17951   CTIMER_CTRL5_TMRB5CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
17952   CTIMER_CTRL5_TMRB5CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
17953   CTIMER_CTRL5_TMRB5CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
17954   CTIMER_CTRL5_TMRB5CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
17955 } CTIMER_CTRL5_TMRB5CLK_Enum;
17956 
17957 /* =============================================  CTIMER CTRL5 TMRB5EN [16..16]  ============================================= */
17958 typedef enum {                                  /*!< CTIMER_CTRL5_TMRB5EN                                                      */
17959   CTIMER_CTRL5_TMRB5EN_DIS             = 0,     /*!< DIS : Counter/Timer B5 Disable.                                           */
17960   CTIMER_CTRL5_TMRB5EN_EN              = 1,     /*!< EN : Counter/Timer B5 Enable.                                             */
17961 } CTIMER_CTRL5_TMRB5EN_Enum;
17962 
17963 /* ============================================  CTIMER CTRL5 TMRA5POL [12..12]  ============================================= */
17964 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5POL                                                     */
17965   CTIMER_CTRL5_TMRA5POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA5 pin is the same as the
17966                                                      timer output.                                                             */
17967   CTIMER_CTRL5_TMRA5POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA5 pin is the inverse of
17968                                                      the timer output.                                                         */
17969 } CTIMER_CTRL5_TMRA5POL_Enum;
17970 
17971 /* ============================================  CTIMER CTRL5 TMRA5CLR [11..11]  ============================================= */
17972 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5CLR                                                     */
17973   CTIMER_CTRL5_TMRA5CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A5 to run                                       */
17974   CTIMER_CTRL5_TMRA5CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A5 at 0x0000.                                 */
17975 } CTIMER_CTRL5_TMRA5CLR_Enum;
17976 
17977 /* ============================================  CTIMER CTRL5 TMRA5IE1 [10..10]  ============================================= */
17978 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5IE1                                                     */
17979   CTIMER_CTRL5_TMRA5IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A5 from generating an interrupt
17980                                                      based on COMPR1.                                                          */
17981   CTIMER_CTRL5_TMRA5IE1_EN             = 1,     /*!< EN : Enable counter/timer A5 to generate an interrupt based
17982                                                      on COMPR1.                                                                */
17983 } CTIMER_CTRL5_TMRA5IE1_Enum;
17984 
17985 /* =============================================  CTIMER CTRL5 TMRA5IE0 [9..9]  ============================================== */
17986 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5IE0                                                     */
17987   CTIMER_CTRL5_TMRA5IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A5 from generating an interrupt
17988                                                      based on COMPR0.                                                          */
17989   CTIMER_CTRL5_TMRA5IE0_EN             = 1,     /*!< EN : Enable counter/timer A5 to generate an interrupt based
17990                                                      on COMPR0.                                                                */
17991 } CTIMER_CTRL5_TMRA5IE0_Enum;
17992 
17993 /* ==============================================  CTIMER CTRL5 TMRA5FN [6..8]  ============================================== */
17994 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5FN                                                      */
17995   CTIMER_CTRL5_TMRA5FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
17996                                                      to CMPR0A5, stop.                                                         */
17997   CTIMER_CTRL5_TMRA5FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
17998                                                      pulses). Count to CMPR0A5, restart.                                       */
17999   CTIMER_CTRL5_TMRA5FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A5, assert,
18000                                                      count to CMPR1A5, deassert, stop.                                         */
18001   CTIMER_CTRL5_TMRA5FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A5, assert, count
18002                                                      to CMPR1A5, deassert, restart.                                            */
18003   CTIMER_CTRL5_TMRA5FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18004   CTIMER_CTRL5_TMRA5FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18005   CTIMER_CTRL5_TMRA5FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18006   CTIMER_CTRL5_TMRA5FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18007 } CTIMER_CTRL5_TMRA5FN_Enum;
18008 
18009 /* =============================================  CTIMER CTRL5 TMRA5CLK [1..5]  ============================================== */
18010 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5CLK                                                     */
18011   CTIMER_CTRL5_TMRA5CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
18012   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18013   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18014   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18015   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18016   CTIMER_CTRL5_TMRA5CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18017   CTIMER_CTRL5_TMRA5CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18018   CTIMER_CTRL5_TMRA5CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18019   CTIMER_CTRL5_TMRA5CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18020   CTIMER_CTRL5_TMRA5CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18021   CTIMER_CTRL5_TMRA5CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18022   CTIMER_CTRL5_TMRA5CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18023   CTIMER_CTRL5_TMRA5CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18024   CTIMER_CTRL5_TMRA5CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18025   CTIMER_CTRL5_TMRA5CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18026   CTIMER_CTRL5_TMRA5CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18027                                                      available when MCU is in active mode)                                     */
18028   CTIMER_CTRL5_TMRA5CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18029   CTIMER_CTRL5_TMRA5CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18030   CTIMER_CTRL5_TMRA5CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18031   CTIMER_CTRL5_TMRA5CLK_CTMRB5         = 20,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18032   CTIMER_CTRL5_TMRA5CLK_CTMRA0         = 21,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
18033   CTIMER_CTRL5_TMRA5CLK_CTMRB0         = 22,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18034   CTIMER_CTRL5_TMRA5CLK_CTMRA6         = 23,    /*!< CTMRA6 : Clock source is CTIMERA6 OUT.                                    */
18035   CTIMER_CTRL5_TMRA5CLK_CTMRB6         = 24,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18036   CTIMER_CTRL5_TMRA5CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18037   CTIMER_CTRL5_TMRA5CLK_CTMRB2         = 26,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18038   CTIMER_CTRL5_TMRA5CLK_CTMRB3         = 27,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18039   CTIMER_CTRL5_TMRA5CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18040   CTIMER_CTRL5_TMRA5CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18041   CTIMER_CTRL5_TMRA5CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18042   CTIMER_CTRL5_TMRA5CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18043 } CTIMER_CTRL5_TMRA5CLK_Enum;
18044 
18045 /* ==============================================  CTIMER CTRL5 TMRA5EN [0..0]  ============================================== */
18046 typedef enum {                                  /*!< CTIMER_CTRL5_TMRA5EN                                                      */
18047   CTIMER_CTRL5_TMRA5EN_DIS             = 0,     /*!< DIS : Counter/Timer A5 Disable.                                           */
18048   CTIMER_CTRL5_TMRA5EN_EN              = 1,     /*!< EN : Counter/Timer A5 Enable.                                             */
18049 } CTIMER_CTRL5_TMRA5EN_Enum;
18050 
18051 /* =======================================================  CMPRAUXA5  ======================================================= */
18052 /* =======================================================  CMPRAUXB5  ======================================================= */
18053 /* =========================================================  AUX5  ========================================================== */
18054 /* ============================================  CTIMER AUX5 TMRB5EN23 [30..30]  ============================================= */
18055 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5EN23                                                     */
18056   CTIMER_AUX5_TMRB5EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18057   CTIMER_AUX5_TMRB5EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18058 } CTIMER_AUX5_TMRB5EN23_Enum;
18059 
18060 /* ============================================  CTIMER AUX5 TMRB5POL23 [29..29]  ============================================ */
18061 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5POL23                                                    */
18062   CTIMER_AUX5_TMRB5POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18063   CTIMER_AUX5_TMRB5POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18064 } CTIMER_AUX5_TMRB5POL23_Enum;
18065 
18066 /* ============================================  CTIMER AUX5 TMRB5TINV [28..28]  ============================================= */
18067 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5TINV                                                     */
18068   CTIMER_AUX5_TMRB5TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18069   CTIMER_AUX5_TMRB5TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18070 } CTIMER_AUX5_TMRB5TINV_Enum;
18071 
18072 /* ===========================================  CTIMER AUX5 TMRB5NOSYNC [27..27]  ============================================ */
18073 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5NOSYNC                                                   */
18074   CTIMER_AUX5_TMRB5NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18075   CTIMER_AUX5_TMRB5NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18076 } CTIMER_AUX5_TMRB5NOSYNC_Enum;
18077 
18078 /* ============================================  CTIMER AUX5 TMRB5TRIG [23..26]  ============================================= */
18079 typedef enum {                                  /*!< CTIMER_AUX5_TMRB5TRIG                                                     */
18080   CTIMER_AUX5_TMRB5TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18081   CTIMER_AUX5_TMRB5TRIG_A5OUT          = 1,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
18082   CTIMER_AUX5_TMRB5TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18083   CTIMER_AUX5_TMRB5TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18084   CTIMER_AUX5_TMRB5TRIG_A6OUT          = 4,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
18085   CTIMER_AUX5_TMRB5TRIG_B6OUT          = 5,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
18086   CTIMER_AUX5_TMRB5TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
18087   CTIMER_AUX5_TMRB5TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
18088   CTIMER_AUX5_TMRB5TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18089   CTIMER_AUX5_TMRB5TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18090   CTIMER_AUX5_TMRB5TRIG_A0OUT2         = 10,    /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2.                                 */
18091   CTIMER_AUX5_TMRB5TRIG_B0OUT2         = 11,    /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2.                                 */
18092   CTIMER_AUX5_TMRB5TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18093   CTIMER_AUX5_TMRB5TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18094   CTIMER_AUX5_TMRB5TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
18095   CTIMER_AUX5_TMRB5TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
18096 } CTIMER_AUX5_TMRB5TRIG_Enum;
18097 
18098 /* ============================================  CTIMER AUX5 TMRA5EN23 [14..14]  ============================================= */
18099 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5EN23                                                     */
18100   CTIMER_AUX5_TMRA5EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18101   CTIMER_AUX5_TMRA5EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18102 } CTIMER_AUX5_TMRA5EN23_Enum;
18103 
18104 /* ============================================  CTIMER AUX5 TMRA5POL23 [13..13]  ============================================ */
18105 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5POL23                                                    */
18106   CTIMER_AUX5_TMRA5POL23_NORMAL        = 0,     /*!< NORMAL : Upper output normal polarity                                     */
18107   CTIMER_AUX5_TMRA5POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18108 } CTIMER_AUX5_TMRA5POL23_Enum;
18109 
18110 /* ============================================  CTIMER AUX5 TMRA5TINV [12..12]  ============================================= */
18111 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5TINV                                                     */
18112   CTIMER_AUX5_TMRA5TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18113   CTIMER_AUX5_TMRA5TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18114 } CTIMER_AUX5_TMRA5TINV_Enum;
18115 
18116 /* ===========================================  CTIMER AUX5 TMRA5NOSYNC [11..11]  ============================================ */
18117 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5NOSYNC                                                   */
18118   CTIMER_AUX5_TMRA5NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18119   CTIMER_AUX5_TMRA5NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18120 } CTIMER_AUX5_TMRA5NOSYNC_Enum;
18121 
18122 /* =============================================  CTIMER AUX5 TMRA5TRIG [7..10]  ============================================= */
18123 typedef enum {                                  /*!< CTIMER_AUX5_TMRA5TRIG                                                     */
18124   CTIMER_AUX5_TMRA5TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18125   CTIMER_AUX5_TMRA5TRIG_STIMER         = 1,     /*!< STIMER : Trigger source is STimer Interrupt. Only Active When
18126                                                      CTLINK==1 and TMRB5TRIG!=0. TMRB5TRIG selects an STIMER
18127                                                      interrupt                                                                 */
18128   CTIMER_AUX5_TMRA5TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18129   CTIMER_AUX5_TMRA5TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18130   CTIMER_AUX5_TMRA5TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
18131   CTIMER_AUX5_TMRA5TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
18132   CTIMER_AUX5_TMRA5TRIG_A2OUT          = 6,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
18133   CTIMER_AUX5_TMRA5TRIG_B2OUT          = 7,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
18134   CTIMER_AUX5_TMRA5TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18135   CTIMER_AUX5_TMRA5TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18136   CTIMER_AUX5_TMRA5TRIG_A0OUT2         = 10,    /*!< A0OUT2 : Trigger source is CTIMERA0 OUT2.                                 */
18137   CTIMER_AUX5_TMRA5TRIG_B0OUT2         = 11,    /*!< B0OUT2 : Trigger source is CTIMERB0 OUT2.                                 */
18138   CTIMER_AUX5_TMRA5TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18139   CTIMER_AUX5_TMRA5TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18140   CTIMER_AUX5_TMRA5TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
18141   CTIMER_AUX5_TMRA5TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
18142 } CTIMER_AUX5_TMRA5TRIG_Enum;
18143 
18144 /* =========================================================  TMR6  ========================================================== */
18145 /* ========================================================  CMPRA6  ========================================================= */
18146 /* ========================================================  CMPRB6  ========================================================= */
18147 /* =========================================================  CTRL6  ========================================================= */
18148 /* =============================================  CTIMER CTRL6 CTLINK6 [31..31]  ============================================= */
18149 typedef enum {                                  /*!< CTIMER_CTRL6_CTLINK6                                                      */
18150   CTIMER_CTRL6_CTLINK6_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A6/B6 timers as two independent 16-bit
18151                                                      timers (default).                                                         */
18152   CTIMER_CTRL6_CTLINK6_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A6/B6 timers into a single 32-bit timer.               */
18153 } CTIMER_CTRL6_CTLINK6_Enum;
18154 
18155 /* ============================================  CTIMER CTRL6 TMRB6POL [28..28]  ============================================= */
18156 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6POL                                                     */
18157   CTIMER_CTRL6_TMRB6POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB6 pin is the same as the
18158                                                      timer output.                                                             */
18159   CTIMER_CTRL6_TMRB6POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB6 pin is the inverse of
18160                                                      the timer output.                                                         */
18161 } CTIMER_CTRL6_TMRB6POL_Enum;
18162 
18163 /* ============================================  CTIMER CTRL6 TMRB6CLR [27..27]  ============================================= */
18164 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6CLR                                                     */
18165   CTIMER_CTRL6_TMRB6CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B6 to run                                       */
18166   CTIMER_CTRL6_TMRB6CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B6 at 0x0000.                                 */
18167 } CTIMER_CTRL6_TMRB6CLR_Enum;
18168 
18169 /* ============================================  CTIMER CTRL6 TMRB6IE1 [26..26]  ============================================= */
18170 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6IE1                                                     */
18171   CTIMER_CTRL6_TMRB6IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B6 from generating an interrupt
18172                                                      based on COMPR1.                                                          */
18173   CTIMER_CTRL6_TMRB6IE1_EN             = 1,     /*!< EN : Enable counter/timer B6 to generate an interrupt based
18174                                                      on COMPR1.                                                                */
18175 } CTIMER_CTRL6_TMRB6IE1_Enum;
18176 
18177 /* ============================================  CTIMER CTRL6 TMRB6IE0 [25..25]  ============================================= */
18178 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6IE0                                                     */
18179   CTIMER_CTRL6_TMRB6IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B6 from generating an interrupt
18180                                                      based on COMPR0.                                                          */
18181   CTIMER_CTRL6_TMRB6IE0_EN             = 1,     /*!< EN : Enable counter/timer B6 to generate an interrupt based
18182                                                      on COMPR0                                                                 */
18183 } CTIMER_CTRL6_TMRB6IE0_Enum;
18184 
18185 /* =============================================  CTIMER CTRL6 TMRB6FN [22..24]  ============================================= */
18186 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6FN                                                      */
18187   CTIMER_CTRL6_TMRB6FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18188                                                      to CMPR0B6, stop.                                                         */
18189   CTIMER_CTRL6_TMRB6FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18190                                                      pulses). Count to CMPR0B6, restart.                                       */
18191   CTIMER_CTRL6_TMRB6FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B6, assert,
18192                                                      count to CMPR1B6, deassert, stop.                                         */
18193   CTIMER_CTRL6_TMRB6FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B6, assert, count
18194                                                      to CMPR1B6, deassert, restart.                                            */
18195   CTIMER_CTRL6_TMRB6FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18196   CTIMER_CTRL6_TMRB6FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18197   CTIMER_CTRL6_TMRB6FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18198   CTIMER_CTRL6_TMRB6FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18199 } CTIMER_CTRL6_TMRB6FN_Enum;
18200 
18201 /* ============================================  CTIMER CTRL6 TMRB6CLK [17..21]  ============================================= */
18202 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6CLK                                                     */
18203   CTIMER_CTRL6_TMRB6CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
18204   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18205   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18206   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18207   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18208   CTIMER_CTRL6_TMRB6CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18209   CTIMER_CTRL6_TMRB6CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18210   CTIMER_CTRL6_TMRB6CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18211   CTIMER_CTRL6_TMRB6CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18212   CTIMER_CTRL6_TMRB6CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18213   CTIMER_CTRL6_TMRB6CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18214   CTIMER_CTRL6_TMRB6CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18215   CTIMER_CTRL6_TMRB6CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18216   CTIMER_CTRL6_TMRB6CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18217   CTIMER_CTRL6_TMRB6CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18218   CTIMER_CTRL6_TMRB6CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18219                                                      available when MCU is in active mode)                                     */
18220   CTIMER_CTRL6_TMRB6CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18221   CTIMER_CTRL6_TMRB6CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18222   CTIMER_CTRL6_TMRB6CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18223   CTIMER_CTRL6_TMRB6CLK_CTMRA6         = 20,    /*!< CTMRA6 : Clock source is CTIMERA6 OUT.                                    */
18224   CTIMER_CTRL6_TMRB6CLK_CTMRA3         = 21,    /*!< CTMRA3 : Clock source is CTIMERA3 OUT.                                    */
18225   CTIMER_CTRL6_TMRB6CLK_CTMRB3         = 22,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18226   CTIMER_CTRL6_TMRB6CLK_CTMRA7         = 23,    /*!< CTMRA7 : Clock source is CTIMERA7 OUT.                                    */
18227   CTIMER_CTRL6_TMRB6CLK_CTMRB7         = 24,    /*!< CTMRB7 : Clock source is CTIMERB7 OUT.                                    */
18228   CTIMER_CTRL6_TMRB6CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18229   CTIMER_CTRL6_TMRB6CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18230   CTIMER_CTRL6_TMRB6CLK_CTMRB2         = 27,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18231   CTIMER_CTRL6_TMRB6CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18232   CTIMER_CTRL6_TMRB6CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18233   CTIMER_CTRL6_TMRB6CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18234   CTIMER_CTRL6_TMRB6CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18235 } CTIMER_CTRL6_TMRB6CLK_Enum;
18236 
18237 /* =============================================  CTIMER CTRL6 TMRB6EN [16..16]  ============================================= */
18238 typedef enum {                                  /*!< CTIMER_CTRL6_TMRB6EN                                                      */
18239   CTIMER_CTRL6_TMRB6EN_DIS             = 0,     /*!< DIS : Counter/Timer B6 Disable.                                           */
18240   CTIMER_CTRL6_TMRB6EN_EN              = 1,     /*!< EN : Counter/Timer B6 Enable.                                             */
18241 } CTIMER_CTRL6_TMRB6EN_Enum;
18242 
18243 /* ============================================  CTIMER CTRL6 TMRA6POL [12..12]  ============================================= */
18244 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6POL                                                     */
18245   CTIMER_CTRL6_TMRA6POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA6 pin is the same as the
18246                                                      timer output.                                                             */
18247   CTIMER_CTRL6_TMRA6POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA6 pin is the inverse of
18248                                                      the timer output.                                                         */
18249 } CTIMER_CTRL6_TMRA6POL_Enum;
18250 
18251 /* ============================================  CTIMER CTRL6 TMRA6CLR [11..11]  ============================================= */
18252 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6CLR                                                     */
18253   CTIMER_CTRL6_TMRA6CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A6 to run                                       */
18254   CTIMER_CTRL6_TMRA6CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A6 at 0x0000.                                 */
18255 } CTIMER_CTRL6_TMRA6CLR_Enum;
18256 
18257 /* ============================================  CTIMER CTRL6 TMRA6IE1 [10..10]  ============================================= */
18258 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6IE1                                                     */
18259   CTIMER_CTRL6_TMRA6IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A6 from generating an interrupt
18260                                                      based on COMPR1.                                                          */
18261   CTIMER_CTRL6_TMRA6IE1_EN             = 1,     /*!< EN : Enable counter/timer A6 to generate an interrupt based
18262                                                      on COMPR1.                                                                */
18263 } CTIMER_CTRL6_TMRA6IE1_Enum;
18264 
18265 /* =============================================  CTIMER CTRL6 TMRA6IE0 [9..9]  ============================================== */
18266 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6IE0                                                     */
18267   CTIMER_CTRL6_TMRA6IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A6 from generating an interrupt
18268                                                      based on COMPR0.                                                          */
18269   CTIMER_CTRL6_TMRA6IE0_EN             = 1,     /*!< EN : Enable counter/timer A6 to generate an interrupt based
18270                                                      on COMPR0.                                                                */
18271 } CTIMER_CTRL6_TMRA6IE0_Enum;
18272 
18273 /* ==============================================  CTIMER CTRL6 TMRA6FN [6..8]  ============================================== */
18274 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6FN                                                      */
18275   CTIMER_CTRL6_TMRA6FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18276                                                      to CMPR0A6, stop.                                                         */
18277   CTIMER_CTRL6_TMRA6FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18278                                                      pulses). Count to CMPR0A6, restart.                                       */
18279   CTIMER_CTRL6_TMRA6FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A6, assert,
18280                                                      count to CMPR1A6, deassert, stop.                                         */
18281   CTIMER_CTRL6_TMRA6FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A6, assert, count
18282                                                      to CMPR1A6, deassert, restart.                                            */
18283   CTIMER_CTRL6_TMRA6FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18284   CTIMER_CTRL6_TMRA6FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18285   CTIMER_CTRL6_TMRA6FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18286   CTIMER_CTRL6_TMRA6FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18287 } CTIMER_CTRL6_TMRA6FN_Enum;
18288 
18289 /* =============================================  CTIMER CTRL6 TMRA6CLK [1..5]  ============================================== */
18290 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6CLK                                                     */
18291   CTIMER_CTRL6_TMRA6CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
18292   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18293   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18294   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18295   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18296   CTIMER_CTRL6_TMRA6CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18297   CTIMER_CTRL6_TMRA6CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18298   CTIMER_CTRL6_TMRA6CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18299   CTIMER_CTRL6_TMRA6CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18300   CTIMER_CTRL6_TMRA6CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18301   CTIMER_CTRL6_TMRA6CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18302   CTIMER_CTRL6_TMRA6CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18303   CTIMER_CTRL6_TMRA6CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18304   CTIMER_CTRL6_TMRA6CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18305   CTIMER_CTRL6_TMRA6CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18306   CTIMER_CTRL6_TMRA6CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18307                                                      available when MCU is in active mode)                                     */
18308   CTIMER_CTRL6_TMRA6CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18309   CTIMER_CTRL6_TMRA6CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18310   CTIMER_CTRL6_TMRA6CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18311   CTIMER_CTRL6_TMRA6CLK_CTMRB6         = 20,    /*!< CTMRB6 : Clock source is CTIMERB6 OUT.                                    */
18312   CTIMER_CTRL6_TMRA6CLK_CTMRA3         = 21,    /*!< CTMRA3 : Clock source is CTIMERA3 OUT.                                    */
18313   CTIMER_CTRL6_TMRA6CLK_CTMRB3         = 22,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18314   CTIMER_CTRL6_TMRA6CLK_CTMRA7         = 23,    /*!< CTMRA7 : Clock source is CTIMERA7 OUT.                                    */
18315   CTIMER_CTRL6_TMRA6CLK_CTMRB7         = 24,    /*!< CTMRB7 : Clock source is CTIMERB7 OUT.                                    */
18316   CTIMER_CTRL6_TMRA6CLK_CTMRB0         = 25,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18317   CTIMER_CTRL6_TMRA6CLK_CTMRB1         = 26,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18318   CTIMER_CTRL6_TMRA6CLK_CTMRB2         = 27,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18319   CTIMER_CTRL6_TMRA6CLK_CTMRB4         = 28,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18320   CTIMER_CTRL6_TMRA6CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18321   CTIMER_CTRL6_TMRA6CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18322   CTIMER_CTRL6_TMRA6CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18323 } CTIMER_CTRL6_TMRA6CLK_Enum;
18324 
18325 /* ==============================================  CTIMER CTRL6 TMRA6EN [0..0]  ============================================== */
18326 typedef enum {                                  /*!< CTIMER_CTRL6_TMRA6EN                                                      */
18327   CTIMER_CTRL6_TMRA6EN_DIS             = 0,     /*!< DIS : Counter/Timer A6 Disable.                                           */
18328   CTIMER_CTRL6_TMRA6EN_EN              = 1,     /*!< EN : Counter/Timer A6 Enable.                                             */
18329 } CTIMER_CTRL6_TMRA6EN_Enum;
18330 
18331 /* =======================================================  CMPRAUXA6  ======================================================= */
18332 /* =======================================================  CMPRAUXB6  ======================================================= */
18333 /* =========================================================  AUX6  ========================================================== */
18334 /* ============================================  CTIMER AUX6 TMRB6EN23 [30..30]  ============================================= */
18335 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6EN23                                                     */
18336   CTIMER_AUX6_TMRB6EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18337   CTIMER_AUX6_TMRB6EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18338 } CTIMER_AUX6_TMRB6EN23_Enum;
18339 
18340 /* ============================================  CTIMER AUX6 TMRB6POL23 [29..29]  ============================================ */
18341 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6POL23                                                    */
18342   CTIMER_AUX6_TMRB6POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18343   CTIMER_AUX6_TMRB6POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18344 } CTIMER_AUX6_TMRB6POL23_Enum;
18345 
18346 /* ============================================  CTIMER AUX6 TMRB6TINV [28..28]  ============================================= */
18347 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6TINV                                                     */
18348   CTIMER_AUX6_TMRB6TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18349   CTIMER_AUX6_TMRB6TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18350 } CTIMER_AUX6_TMRB6TINV_Enum;
18351 
18352 /* ===========================================  CTIMER AUX6 TMRB6NOSYNC [27..27]  ============================================ */
18353 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6NOSYNC                                                   */
18354   CTIMER_AUX6_TMRB6NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18355   CTIMER_AUX6_TMRB6NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18356 } CTIMER_AUX6_TMRB6NOSYNC_Enum;
18357 
18358 /* ============================================  CTIMER AUX6 TMRB6TRIG [23..26]  ============================================= */
18359 typedef enum {                                  /*!< CTIMER_AUX6_TMRB6TRIG                                                     */
18360   CTIMER_AUX6_TMRB6TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18361   CTIMER_AUX6_TMRB6TRIG_A6OUT          = 1,     /*!< A6OUT : Trigger source is CTIMERA6 OUT.                                   */
18362   CTIMER_AUX6_TMRB6TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18363   CTIMER_AUX6_TMRB6TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18364   CTIMER_AUX6_TMRB6TRIG_A4OUT          = 4,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
18365   CTIMER_AUX6_TMRB6TRIG_B4OUT          = 5,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
18366   CTIMER_AUX6_TMRB6TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
18367   CTIMER_AUX6_TMRB6TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
18368   CTIMER_AUX6_TMRB6TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18369   CTIMER_AUX6_TMRB6TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18370   CTIMER_AUX6_TMRB6TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
18371   CTIMER_AUX6_TMRB6TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2.                                 */
18372   CTIMER_AUX6_TMRB6TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18373   CTIMER_AUX6_TMRB6TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18374   CTIMER_AUX6_TMRB6TRIG_B0OUT2DUAL     = 14,    /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge.                  */
18375   CTIMER_AUX6_TMRB6TRIG_A0OUT2DUAL     = 15,    /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge.                  */
18376 } CTIMER_AUX6_TMRB6TRIG_Enum;
18377 
18378 /* ============================================  CTIMER AUX6 TMRA6EN23 [14..14]  ============================================= */
18379 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6EN23                                                     */
18380   CTIMER_AUX6_TMRA6EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18381   CTIMER_AUX6_TMRA6EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18382 } CTIMER_AUX6_TMRA6EN23_Enum;
18383 
18384 /* ============================================  CTIMER AUX6 TMRA6POL23 [13..13]  ============================================ */
18385 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6POL23                                                    */
18386   CTIMER_AUX6_TMRA6POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18387   CTIMER_AUX6_TMRA6POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18388 } CTIMER_AUX6_TMRA6POL23_Enum;
18389 
18390 /* ============================================  CTIMER AUX6 TMRA6TINV [12..12]  ============================================= */
18391 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6TINV                                                     */
18392   CTIMER_AUX6_TMRA6TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18393   CTIMER_AUX6_TMRA6TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18394 } CTIMER_AUX6_TMRA6TINV_Enum;
18395 
18396 /* ===========================================  CTIMER AUX6 TMRA6NOSYNC [11..11]  ============================================ */
18397 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6NOSYNC                                                   */
18398   CTIMER_AUX6_TMRA6NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18399   CTIMER_AUX6_TMRA6NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18400 } CTIMER_AUX6_TMRA6NOSYNC_Enum;
18401 
18402 /* =============================================  CTIMER AUX6 TMRA6TRIG [7..10]  ============================================= */
18403 typedef enum {                                  /*!< CTIMER_AUX6_TMRA6TRIG                                                     */
18404   CTIMER_AUX6_TMRA6TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18405   CTIMER_AUX6_TMRA6TRIG_B6OUT          = 1,     /*!< B6OUT : Trigger source is CTIMERB6 OUT.                                   */
18406   CTIMER_AUX6_TMRA6TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18407   CTIMER_AUX6_TMRA6TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18408   CTIMER_AUX6_TMRA6TRIG_A5OUT          = 4,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
18409   CTIMER_AUX6_TMRA6TRIG_B5OUT          = 5,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
18410   CTIMER_AUX6_TMRA6TRIG_A1OUT          = 6,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
18411   CTIMER_AUX6_TMRA6TRIG_B1OUT          = 7,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
18412   CTIMER_AUX6_TMRA6TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18413   CTIMER_AUX6_TMRA6TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18414   CTIMER_AUX6_TMRA6TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
18415   CTIMER_AUX6_TMRA6TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERBb OUT2.                                 */
18416   CTIMER_AUX6_TMRA6TRIG_A5OUT2DUAL     = 12,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
18417   CTIMER_AUX6_TMRA6TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18418   CTIMER_AUX6_TMRA6TRIG_B0OUT2DUAL     = 14,    /*!< B0OUT2DUAL : Trigger source is CTIMERB0 OUT2, dual edge.                  */
18419   CTIMER_AUX6_TMRA6TRIG_A0OUT2DUAL     = 15,    /*!< A0OUT2DUAL : Trigger source is CTIMERA0 OUT2, dual edge.                  */
18420 } CTIMER_AUX6_TMRA6TRIG_Enum;
18421 
18422 /* =========================================================  TMR7  ========================================================== */
18423 /* ========================================================  CMPRA7  ========================================================= */
18424 /* ========================================================  CMPRB7  ========================================================= */
18425 /* =========================================================  CTRL7  ========================================================= */
18426 /* =============================================  CTIMER CTRL7 CTLINK7 [31..31]  ============================================= */
18427 typedef enum {                                  /*!< CTIMER_CTRL7_CTLINK7                                                      */
18428   CTIMER_CTRL7_CTLINK7_TWO_16BIT_TIMERS = 0,    /*!< TWO_16BIT_TIMERS : Use A7/B7 timers as two independent 16-bit
18429                                                      timers (default).                                                         */
18430   CTIMER_CTRL7_CTLINK7_32BIT_TIMER     = 1,     /*!< 32BIT_TIMER : Link A7/B7 timers into a single 32-bit timer.               */
18431 } CTIMER_CTRL7_CTLINK7_Enum;
18432 
18433 /* ============================================  CTIMER CTRL7 TMRB7POL [28..28]  ============================================= */
18434 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7POL                                                     */
18435   CTIMER_CTRL7_TMRB7POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINB7 pin is the same as the
18436                                                      timer output.                                                             */
18437   CTIMER_CTRL7_TMRB7POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINB7 pin is the inverse of
18438                                                      the timer output.                                                         */
18439 } CTIMER_CTRL7_TMRB7POL_Enum;
18440 
18441 /* ============================================  CTIMER CTRL7 TMRB7CLR [27..27]  ============================================= */
18442 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7CLR                                                     */
18443   CTIMER_CTRL7_TMRB7CLR_RUN            = 0,     /*!< RUN : Allow counter/timer B7 to run                                       */
18444   CTIMER_CTRL7_TMRB7CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer B7 at 0x0000.                                 */
18445 } CTIMER_CTRL7_TMRB7CLR_Enum;
18446 
18447 /* ============================================  CTIMER CTRL7 TMRB7IE1 [26..26]  ============================================= */
18448 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7IE1                                                     */
18449   CTIMER_CTRL7_TMRB7IE1_DIS            = 0,     /*!< DIS : Disable counter/timer B7 from generating an interrupt
18450                                                      based on COMPR1.                                                          */
18451   CTIMER_CTRL7_TMRB7IE1_EN             = 1,     /*!< EN : Enable counter/timer B7 to generate an interrupt based
18452                                                      on COMPR1.                                                                */
18453 } CTIMER_CTRL7_TMRB7IE1_Enum;
18454 
18455 /* ============================================  CTIMER CTRL7 TMRB7IE0 [25..25]  ============================================= */
18456 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7IE0                                                     */
18457   CTIMER_CTRL7_TMRB7IE0_DIS            = 0,     /*!< DIS : Disable counter/timer B7 from generating an interrupt
18458                                                      based on COMPR0.                                                          */
18459   CTIMER_CTRL7_TMRB7IE0_EN             = 1,     /*!< EN : Enable counter/timer B7 to generate an interrupt based
18460                                                      on COMPR0                                                                 */
18461 } CTIMER_CTRL7_TMRB7IE0_Enum;
18462 
18463 /* =============================================  CTIMER CTRL7 TMRB7FN [22..24]  ============================================= */
18464 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7FN                                                      */
18465   CTIMER_CTRL7_TMRB7FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18466                                                      to CMPR0B7, stop.                                                         */
18467   CTIMER_CTRL7_TMRB7FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18468                                                      pulses). Count to CMPR0B7, restart.                                       */
18469   CTIMER_CTRL7_TMRB7FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0B7, assert,
18470                                                      count to CMPR1B7, deassert, stop.                                         */
18471   CTIMER_CTRL7_TMRB7FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0B7, assert, count
18472                                                      to CMPR1B7, deassert, restart.                                            */
18473   CTIMER_CTRL7_TMRB7FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18474   CTIMER_CTRL7_TMRB7FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18475   CTIMER_CTRL7_TMRB7FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18476   CTIMER_CTRL7_TMRB7FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18477 } CTIMER_CTRL7_TMRB7FN_Enum;
18478 
18479 /* ============================================  CTIMER CTRL7 TMRB7CLK [17..21]  ============================================= */
18480 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7CLK                                                     */
18481   CTIMER_CTRL7_TMRB7CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINB.                                         */
18482   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18483   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18484   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18485   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18486   CTIMER_CTRL7_TMRB7CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18487   CTIMER_CTRL7_TMRB7CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18488   CTIMER_CTRL7_TMRB7CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18489   CTIMER_CTRL7_TMRB7CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18490   CTIMER_CTRL7_TMRB7CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18491   CTIMER_CTRL7_TMRB7CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18492   CTIMER_CTRL7_TMRB7CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18493   CTIMER_CTRL7_TMRB7CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18494   CTIMER_CTRL7_TMRB7CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18495   CTIMER_CTRL7_TMRB7CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18496   CTIMER_CTRL7_TMRB7CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18497                                                      available when MCU is in active mode)                                     */
18498   CTIMER_CTRL7_TMRB7CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18499   CTIMER_CTRL7_TMRB7CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18500   CTIMER_CTRL7_TMRB7CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18501   CTIMER_CTRL7_TMRB7CLK_CTMRA7         = 20,    /*!< CTMRA7 : Clock source is CTIMERA7 OUT.                                    */
18502   CTIMER_CTRL7_TMRB7CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18503   CTIMER_CTRL7_TMRB7CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18504   CTIMER_CTRL7_TMRB7CLK_CTMRA0         = 23,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
18505   CTIMER_CTRL7_TMRB7CLK_CTMRB0         = 24,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18506   CTIMER_CTRL7_TMRB7CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18507   CTIMER_CTRL7_TMRB7CLK_CTMRB3         = 26,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18508   CTIMER_CTRL7_TMRB7CLK_CTMRB4         = 27,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18509   CTIMER_CTRL7_TMRB7CLK_CTMRB5         = 28,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18510   CTIMER_CTRL7_TMRB7CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18511   CTIMER_CTRL7_TMRB7CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18512   CTIMER_CTRL7_TMRB7CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18513 } CTIMER_CTRL7_TMRB7CLK_Enum;
18514 
18515 /* =============================================  CTIMER CTRL7 TMRB7EN [16..16]  ============================================= */
18516 typedef enum {                                  /*!< CTIMER_CTRL7_TMRB7EN                                                      */
18517   CTIMER_CTRL7_TMRB7EN_DIS             = 0,     /*!< DIS : Counter/Timer B7 Disable.                                           */
18518   CTIMER_CTRL7_TMRB7EN_EN              = 1,     /*!< EN : Counter/Timer B7 Enable.                                             */
18519 } CTIMER_CTRL7_TMRB7EN_Enum;
18520 
18521 /* ============================================  CTIMER CTRL7 TMRA7POL [12..12]  ============================================= */
18522 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7POL                                                     */
18523   CTIMER_CTRL7_TMRA7POL_NORMAL         = 0,     /*!< NORMAL : The polarity of the TMRPINA7 pin is the same as the
18524                                                      timer output.                                                             */
18525   CTIMER_CTRL7_TMRA7POL_INVERTED       = 1,     /*!< INVERTED : The polarity of the TMRPINA7 pin is the inverse of
18526                                                      the timer output.                                                         */
18527 } CTIMER_CTRL7_TMRA7POL_Enum;
18528 
18529 /* ============================================  CTIMER CTRL7 TMRA7CLR [11..11]  ============================================= */
18530 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7CLR                                                     */
18531   CTIMER_CTRL7_TMRA7CLR_RUN            = 0,     /*!< RUN : Allow counter/timer A7 to run                                       */
18532   CTIMER_CTRL7_TMRA7CLR_CLEAR          = 1,     /*!< CLEAR : Holds counter/timer A7 at 0x0000.                                 */
18533 } CTIMER_CTRL7_TMRA7CLR_Enum;
18534 
18535 /* ============================================  CTIMER CTRL7 TMRA7IE1 [10..10]  ============================================= */
18536 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7IE1                                                     */
18537   CTIMER_CTRL7_TMRA7IE1_DIS            = 0,     /*!< DIS : Disable counter/timer A7 from generating an interrupt
18538                                                      based on COMPR1.                                                          */
18539   CTIMER_CTRL7_TMRA7IE1_EN             = 1,     /*!< EN : Enable counter/timer A7 to generate an interrupt based
18540                                                      on COMPR1.                                                                */
18541 } CTIMER_CTRL7_TMRA7IE1_Enum;
18542 
18543 /* =============================================  CTIMER CTRL7 TMRA7IE0 [9..9]  ============================================== */
18544 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7IE0                                                     */
18545   CTIMER_CTRL7_TMRA7IE0_DIS            = 0,     /*!< DIS : Disable counter/timer A7 from generating an interrupt
18546                                                      based on COMPR0.                                                          */
18547   CTIMER_CTRL7_TMRA7IE0_EN             = 1,     /*!< EN : Enable counter/timer A7 to generate an interrupt based
18548                                                      on COMPR0.                                                                */
18549 } CTIMER_CTRL7_TMRA7IE0_Enum;
18550 
18551 /* ==============================================  CTIMER CTRL7 TMRA7FN [6..8]  ============================================== */
18552 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7FN                                                      */
18553   CTIMER_CTRL7_TMRA7FN_SINGLECOUNT     = 0,     /*!< SINGLECOUNT : Single count (output toggles and sticks). Count
18554                                                      to CMPR0A7, stop.                                                         */
18555   CTIMER_CTRL7_TMRA7FN_REPEATEDCOUNT   = 1,     /*!< REPEATEDCOUNT : Repeated count (periodic 1-clock-cycle-wide
18556                                                      pulses). Count to CMPR0A7, restart.                                       */
18557   CTIMER_CTRL7_TMRA7FN_PULSE_ONCE      = 2,     /*!< PULSE_ONCE : Pulse once (aka one-shot). Count to CMPR0A7, assert,
18558                                                      count to CMPR1A7, deassert, stop.                                         */
18559   CTIMER_CTRL7_TMRA7FN_PULSE_CONT      = 3,     /*!< PULSE_CONT : Pulse continuously. Count to CMPR0A7, assert, count
18560                                                      to CMPR1A7, deassert, restart.                                            */
18561   CTIMER_CTRL7_TMRA7FN_SINGLEPATTERN   = 4,     /*!< SINGLEPATTERN : Single pattern.                                           */
18562   CTIMER_CTRL7_TMRA7FN_REPEATPATTERN   = 5,     /*!< REPEATPATTERN : Repeated pattern.                                         */
18563   CTIMER_CTRL7_TMRA7FN_CONTINUOUS      = 6,     /*!< CONTINUOUS : Continuous run (aka Free Run). Count continuously.           */
18564   CTIMER_CTRL7_TMRA7FN_ALTPWN          = 7,     /*!< ALTPWN : Alternate PWM                                                    */
18565 } CTIMER_CTRL7_TMRA7FN_Enum;
18566 
18567 /* =============================================  CTIMER CTRL7 TMRA7CLK [1..5]  ============================================== */
18568 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7CLK                                                     */
18569   CTIMER_CTRL7_TMRA7CLK_TMRPIN         = 0,     /*!< TMRPIN : Clock source is TMRPINA.                                         */
18570   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4      = 1,     /*!< HFRC_DIV4 : Clock source is the HFRC / 4                                  */
18571   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV16     = 2,     /*!< HFRC_DIV16 : Clock source is HFRC / 16                                    */
18572   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV256    = 3,     /*!< HFRC_DIV256 : Clock source is HFRC / 256                                  */
18573   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV1024   = 4,     /*!< HFRC_DIV1024 : Clock source is HFRC / 1024                                */
18574   CTIMER_CTRL7_TMRA7CLK_HFRC_DIV4K     = 5,     /*!< HFRC_DIV4K : Clock source is HFRC / 4096                                  */
18575   CTIMER_CTRL7_TMRA7CLK_XT             = 6,     /*!< XT : Clock source is the XT (uncalibrated).                               */
18576   CTIMER_CTRL7_TMRA7CLK_XT_DIV2        = 7,     /*!< XT_DIV2 : Clock source is XT / 2                                          */
18577   CTIMER_CTRL7_TMRA7CLK_XT_DIV16       = 8,     /*!< XT_DIV16 : Clock source is XT / 16                                        */
18578   CTIMER_CTRL7_TMRA7CLK_XT_DIV128      = 9,     /*!< XT_DIV128 : Clock source is XT / 128                                      */
18579   CTIMER_CTRL7_TMRA7CLK_LFRC_DIV2      = 10,    /*!< LFRC_DIV2 : Clock source is LFRC / 2                                      */
18580   CTIMER_CTRL7_TMRA7CLK_LFRC_DIV32     = 11,    /*!< LFRC_DIV32 : Clock source is LFRC / 32                                    */
18581   CTIMER_CTRL7_TMRA7CLK_LFRC_DIV1K     = 12,    /*!< LFRC_DIV1K : Clock source is LFRC / 1024                                  */
18582   CTIMER_CTRL7_TMRA7CLK_LFRC           = 13,    /*!< LFRC : Clock source is LFRC                                               */
18583   CTIMER_CTRL7_TMRA7CLK_RTC_100HZ      = 14,    /*!< RTC_100HZ : Clock source is 100 Hz from the current RTC oscillator.       */
18584   CTIMER_CTRL7_TMRA7CLK_HCLK_DIV4      = 15,    /*!< HCLK_DIV4 : Clock source is HCLK / 4 (note: this clock is only
18585                                                      available when MCU is in active mode)                                     */
18586   CTIMER_CTRL7_TMRA7CLK_XT_DIV4        = 16,    /*!< XT_DIV4 : Clock source is XT / 4                                          */
18587   CTIMER_CTRL7_TMRA7CLK_XT_DIV8        = 17,    /*!< XT_DIV8 : Clock source is XT / 8                                          */
18588   CTIMER_CTRL7_TMRA7CLK_XT_DIV32       = 18,    /*!< XT_DIV32 : Clock source is XT / 32                                        */
18589   CTIMER_CTRL7_TMRA7CLK_CTMRB7         = 20,    /*!< CTMRB7 : Clock source is CTIMERB7 OUT.                                    */
18590   CTIMER_CTRL7_TMRA7CLK_CTMRA2         = 21,    /*!< CTMRA2 : Clock source is CTIMERA2 OUT.                                    */
18591   CTIMER_CTRL7_TMRA7CLK_CTMRB2         = 22,    /*!< CTMRB2 : Clock source is CTIMERB2 OUT.                                    */
18592   CTIMER_CTRL7_TMRA7CLK_CTMRA0         = 23,    /*!< CTMRA0 : Clock source is CTIMERA0 OUT.                                    */
18593   CTIMER_CTRL7_TMRA7CLK_CTMRB0         = 24,    /*!< CTMRB0 : Clock source is CTIMERB0 OUT.                                    */
18594   CTIMER_CTRL7_TMRA7CLK_CTMRB1         = 25,    /*!< CTMRB1 : Clock source is CTIMERB1 OUT.                                    */
18595   CTIMER_CTRL7_TMRA7CLK_CTMRB3         = 26,    /*!< CTMRB3 : Clock source is CTIMERB3 OUT.                                    */
18596   CTIMER_CTRL7_TMRA7CLK_CTMRB4         = 27,    /*!< CTMRB4 : Clock source is CTIMERB4 OUT.                                    */
18597   CTIMER_CTRL7_TMRA7CLK_CTMRB5         = 28,    /*!< CTMRB5 : Clock source is CTIMERB5 OUT.                                    */
18598   CTIMER_CTRL7_TMRA7CLK_BUCKBLE        = 29,    /*!< BUCKBLE : Clock source is BLE buck converter TON pulses.                  */
18599   CTIMER_CTRL7_TMRA7CLK_BUCKB          = 30,    /*!< BUCKB : Clock source is Memory buck converter TON pulses.                 */
18600   CTIMER_CTRL7_TMRA7CLK_BUCKA          = 31,    /*!< BUCKA : Clock source is CPU buck converter TON pulses.                    */
18601 } CTIMER_CTRL7_TMRA7CLK_Enum;
18602 
18603 /* ==============================================  CTIMER CTRL7 TMRA7EN [0..0]  ============================================== */
18604 typedef enum {                                  /*!< CTIMER_CTRL7_TMRA7EN                                                      */
18605   CTIMER_CTRL7_TMRA7EN_DIS             = 0,     /*!< DIS : Counter/Timer A7 Disable.                                           */
18606   CTIMER_CTRL7_TMRA7EN_EN              = 1,     /*!< EN : Counter/Timer A7 Enable.                                             */
18607 } CTIMER_CTRL7_TMRA7EN_Enum;
18608 
18609 /* =======================================================  CMPRAUXA7  ======================================================= */
18610 /* =======================================================  CMPRAUXB7  ======================================================= */
18611 /* =========================================================  AUX7  ========================================================== */
18612 /* ============================================  CTIMER AUX7 TMRB7EN23 [30..30]  ============================================= */
18613 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7EN23                                                     */
18614   CTIMER_AUX7_TMRB7EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18615   CTIMER_AUX7_TMRB7EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18616 } CTIMER_AUX7_TMRB7EN23_Enum;
18617 
18618 /* ============================================  CTIMER AUX7 TMRB7POL23 [29..29]  ============================================ */
18619 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7POL23                                                    */
18620   CTIMER_AUX7_TMRB7POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18621   CTIMER_AUX7_TMRB7POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18622 } CTIMER_AUX7_TMRB7POL23_Enum;
18623 
18624 /* ============================================  CTIMER AUX7 TMRB7TINV [28..28]  ============================================= */
18625 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7TINV                                                     */
18626   CTIMER_AUX7_TMRB7TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18627   CTIMER_AUX7_TMRB7TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18628 } CTIMER_AUX7_TMRB7TINV_Enum;
18629 
18630 /* ===========================================  CTIMER AUX7 TMRB7NOSYNC [27..27]  ============================================ */
18631 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7NOSYNC                                                   */
18632   CTIMER_AUX7_TMRB7NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18633   CTIMER_AUX7_TMRB7NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18634 } CTIMER_AUX7_TMRB7NOSYNC_Enum;
18635 
18636 /* ============================================  CTIMER AUX7 TMRB7TRIG [23..26]  ============================================= */
18637 typedef enum {                                  /*!< CTIMER_AUX7_TMRB7TRIG                                                     */
18638   CTIMER_AUX7_TMRB7TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18639   CTIMER_AUX7_TMRB7TRIG_A7OUT          = 1,     /*!< A7OUT : Trigger source is CTIMERA7 OUT.                                   */
18640   CTIMER_AUX7_TMRB7TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18641   CTIMER_AUX7_TMRB7TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18642   CTIMER_AUX7_TMRB7TRIG_A5OUT          = 4,     /*!< A5OUT : Trigger source is CTIMERA5 OUT.                                   */
18643   CTIMER_AUX7_TMRB7TRIG_B5OUT          = 5,     /*!< B5OUT : Trigger source is CTIMERB5 OUT.                                   */
18644   CTIMER_AUX7_TMRB7TRIG_A2OUT          = 6,     /*!< A2OUT : Trigger source is CTIMERA2 OUT.                                   */
18645   CTIMER_AUX7_TMRB7TRIG_B2OUT          = 7,     /*!< B2OUT : Trigger source is CTIMERB2 OUT.                                   */
18646   CTIMER_AUX7_TMRB7TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18647   CTIMER_AUX7_TMRB7TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18648   CTIMER_AUX7_TMRB7TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
18649   CTIMER_AUX7_TMRB7TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2.                                 */
18650   CTIMER_AUX7_TMRB7TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18651   CTIMER_AUX7_TMRB7TRIG_A7OUT2DUAL     = 13,    /*!< A7OUT2DUAL : Trigger source is CTIMERA7 OUT2, dual edge.                  */
18652   CTIMER_AUX7_TMRB7TRIG_B1OUT2DUAL     = 14,    /*!< B1OUT2DUAL : Trigger source is CTIMERB1 OUT2, dual edge.                  */
18653   CTIMER_AUX7_TMRB7TRIG_A1OUT2DUAL     = 15,    /*!< A1OUT2DUAL : Trigger source is CTIMERA1 OUT2, dual edge.                  */
18654 } CTIMER_AUX7_TMRB7TRIG_Enum;
18655 
18656 /* ============================================  CTIMER AUX7 TMRA7EN23 [14..14]  ============================================= */
18657 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7EN23                                                     */
18658   CTIMER_AUX7_TMRA7EN23_DIS            = 1,     /*!< DIS : Disable enhanced functions.                                         */
18659   CTIMER_AUX7_TMRA7EN23_EN             = 0,     /*!< EN : Enable enhanced functions.                                           */
18660 } CTIMER_AUX7_TMRA7EN23_Enum;
18661 
18662 /* ============================================  CTIMER AUX7 TMRA7POL23 [13..13]  ============================================ */
18663 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7POL23                                                    */
18664   CTIMER_AUX7_TMRA7POL23_NORM          = 0,     /*!< NORM : Upper output normal polarity                                       */
18665   CTIMER_AUX7_TMRA7POL23_INV           = 1,     /*!< INV : Upper output inverted polarity.                                     */
18666 } CTIMER_AUX7_TMRA7POL23_Enum;
18667 
18668 /* ============================================  CTIMER AUX7 TMRA7TINV [12..12]  ============================================= */
18669 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7TINV                                                     */
18670   CTIMER_AUX7_TMRA7TINV_DIS            = 0,     /*!< DIS : Disable invert on trigger                                           */
18671   CTIMER_AUX7_TMRA7TINV_EN             = 1,     /*!< EN : Enable invert on trigger                                             */
18672 } CTIMER_AUX7_TMRA7TINV_Enum;
18673 
18674 /* ===========================================  CTIMER AUX7 TMRA7NOSYNC [11..11]  ============================================ */
18675 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7NOSYNC                                                   */
18676   CTIMER_AUX7_TMRA7NOSYNC_DIS          = 0,     /*!< DIS : Synchronization on source clock                                     */
18677   CTIMER_AUX7_TMRA7NOSYNC_NOSYNC       = 1,     /*!< NOSYNC : No synchronization on source clock                               */
18678 } CTIMER_AUX7_TMRA7NOSYNC_Enum;
18679 
18680 /* =============================================  CTIMER AUX7 TMRA7TRIG [7..10]  ============================================= */
18681 typedef enum {                                  /*!< CTIMER_AUX7_TMRA7TRIG                                                     */
18682   CTIMER_AUX7_TMRA7TRIG_DIS            = 0,     /*!< DIS : Trigger source is disabled.                                         */
18683   CTIMER_AUX7_TMRA7TRIG_B7OUT          = 1,     /*!< B7OUT : Trigger source is CTIMERB7 OUT.                                   */
18684   CTIMER_AUX7_TMRA7TRIG_B3OUT          = 2,     /*!< B3OUT : Trigger source is CTIMERB3 OUT.                                   */
18685   CTIMER_AUX7_TMRA7TRIG_A3OUT          = 3,     /*!< A3OUT : Trigger source is CTIMERA3 OUT.                                   */
18686   CTIMER_AUX7_TMRA7TRIG_A1OUT          = 4,     /*!< A1OUT : Trigger source is CTIMERA1 OUT.                                   */
18687   CTIMER_AUX7_TMRA7TRIG_B1OUT          = 5,     /*!< B1OUT : Trigger source is CTIMERB1 OUT.                                   */
18688   CTIMER_AUX7_TMRA7TRIG_A4OUT          = 6,     /*!< A4OUT : Trigger source is CTIMERA4 OUT.                                   */
18689   CTIMER_AUX7_TMRA7TRIG_B4OUT          = 7,     /*!< B4OUT : Trigger source is CTIMERB4 OUT.                                   */
18690   CTIMER_AUX7_TMRA7TRIG_B3OUT2         = 8,     /*!< B3OUT2 : Trigger source is CTIMERB3 OUT2.                                 */
18691   CTIMER_AUX7_TMRA7TRIG_A3OUT2         = 9,     /*!< A3OUT2 : Trigger source is CTIMERA3 OUT2.                                 */
18692   CTIMER_AUX7_TMRA7TRIG_A2OUT2         = 10,    /*!< A2OUT2 : Trigger source is CTIMERA2 OUT2.                                 */
18693   CTIMER_AUX7_TMRA7TRIG_B2OUT2         = 11,    /*!< B2OUT2 : Trigger source is CTIMERB2 OUT2.                                 */
18694   CTIMER_AUX7_TMRA7TRIG_A6OUT2DUAL     = 12,    /*!< A6OUT2DUAL : Trigger source is CTIMERA6 OUT2, dual edge.                  */
18695   CTIMER_AUX7_TMRA7TRIG_A5OUT2DUAL     = 13,    /*!< A5OUT2DUAL : Trigger source is CTIMERA5 OUT2, dual edge.                  */
18696   CTIMER_AUX7_TMRA7TRIG_B4OUT2DUAL     = 14,    /*!< B4OUT2DUAL : Trigger source is CTIMERB4 OUT2, dual edge.                  */
18697   CTIMER_AUX7_TMRA7TRIG_A4OUT2DUAL     = 15,    /*!< A4OUT2DUAL : Trigger source is CTIMERA4 OUT2, dual edge.                  */
18698 } CTIMER_AUX7_TMRA7TRIG_Enum;
18699 
18700 /* ========================================================  GLOBEN  ========================================================= */
18701 /* ==============================================  CTIMER GLOBEN ENB7 [15..15]  ============================================== */
18702 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB7                                                        */
18703   CTIMER_GLOBEN_ENB7_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18704   CTIMER_GLOBEN_ENB7_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18705 } CTIMER_GLOBEN_ENB7_Enum;
18706 
18707 /* ==============================================  CTIMER GLOBEN ENA7 [14..14]  ============================================== */
18708 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA7                                                        */
18709   CTIMER_GLOBEN_ENA7_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18710   CTIMER_GLOBEN_ENA7_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18711 } CTIMER_GLOBEN_ENA7_Enum;
18712 
18713 /* ==============================================  CTIMER GLOBEN ENB6 [13..13]  ============================================== */
18714 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB6                                                        */
18715   CTIMER_GLOBEN_ENB6_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18716   CTIMER_GLOBEN_ENB6_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18717 } CTIMER_GLOBEN_ENB6_Enum;
18718 
18719 /* ==============================================  CTIMER GLOBEN ENA6 [12..12]  ============================================== */
18720 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA6                                                        */
18721   CTIMER_GLOBEN_ENA6_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18722   CTIMER_GLOBEN_ENA6_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18723 } CTIMER_GLOBEN_ENA6_Enum;
18724 
18725 /* ==============================================  CTIMER GLOBEN ENB5 [11..11]  ============================================== */
18726 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB5                                                        */
18727   CTIMER_GLOBEN_ENB5_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18728   CTIMER_GLOBEN_ENB5_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18729 } CTIMER_GLOBEN_ENB5_Enum;
18730 
18731 /* ==============================================  CTIMER GLOBEN ENA5 [10..10]  ============================================== */
18732 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA5                                                        */
18733   CTIMER_GLOBEN_ENA5_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18734   CTIMER_GLOBEN_ENA5_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18735 } CTIMER_GLOBEN_ENA5_Enum;
18736 
18737 /* ===============================================  CTIMER GLOBEN ENB4 [9..9]  =============================================== */
18738 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB4                                                        */
18739   CTIMER_GLOBEN_ENB4_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18740   CTIMER_GLOBEN_ENB4_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18741 } CTIMER_GLOBEN_ENB4_Enum;
18742 
18743 /* ===============================================  CTIMER GLOBEN ENA4 [8..8]  =============================================== */
18744 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA4                                                        */
18745   CTIMER_GLOBEN_ENA4_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18746   CTIMER_GLOBEN_ENA4_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18747 } CTIMER_GLOBEN_ENA4_Enum;
18748 
18749 /* ===============================================  CTIMER GLOBEN ENB3 [7..7]  =============================================== */
18750 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB3                                                        */
18751   CTIMER_GLOBEN_ENB3_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18752   CTIMER_GLOBEN_ENB3_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18753 } CTIMER_GLOBEN_ENB3_Enum;
18754 
18755 /* ===============================================  CTIMER GLOBEN ENA3 [6..6]  =============================================== */
18756 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA3                                                        */
18757   CTIMER_GLOBEN_ENA3_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18758   CTIMER_GLOBEN_ENA3_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18759 } CTIMER_GLOBEN_ENA3_Enum;
18760 
18761 /* ===============================================  CTIMER GLOBEN ENB2 [5..5]  =============================================== */
18762 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB2                                                        */
18763   CTIMER_GLOBEN_ENB2_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18764   CTIMER_GLOBEN_ENB2_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18765 } CTIMER_GLOBEN_ENB2_Enum;
18766 
18767 /* ===============================================  CTIMER GLOBEN ENA2 [4..4]  =============================================== */
18768 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA2                                                        */
18769   CTIMER_GLOBEN_ENA2_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18770   CTIMER_GLOBEN_ENA2_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18771 } CTIMER_GLOBEN_ENA2_Enum;
18772 
18773 /* ===============================================  CTIMER GLOBEN ENB1 [3..3]  =============================================== */
18774 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB1                                                        */
18775   CTIMER_GLOBEN_ENB1_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18776   CTIMER_GLOBEN_ENB1_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18777 } CTIMER_GLOBEN_ENB1_Enum;
18778 
18779 /* ===============================================  CTIMER GLOBEN ENA1 [2..2]  =============================================== */
18780 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA1                                                        */
18781   CTIMER_GLOBEN_ENA1_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18782   CTIMER_GLOBEN_ENA1_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18783 } CTIMER_GLOBEN_ENA1_Enum;
18784 
18785 /* ===============================================  CTIMER GLOBEN ENB0 [1..1]  =============================================== */
18786 typedef enum {                                  /*!< CTIMER_GLOBEN_ENB0                                                        */
18787   CTIMER_GLOBEN_ENB0_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18788   CTIMER_GLOBEN_ENB0_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18789 } CTIMER_GLOBEN_ENB0_Enum;
18790 
18791 /* ===============================================  CTIMER GLOBEN ENA0 [0..0]  =============================================== */
18792 typedef enum {                                  /*!< CTIMER_GLOBEN_ENA0                                                        */
18793   CTIMER_GLOBEN_ENA0_LCO               = 1,     /*!< LCO : Use local enable.                                                   */
18794   CTIMER_GLOBEN_ENA0_DIS               = 0,     /*!< DIS : Disable CTIMER.                                                     */
18795 } CTIMER_GLOBEN_ENA0_Enum;
18796 
18797 /* ========================================================  OUTCFG0  ======================================================== */
18798 /* =============================================  CTIMER OUTCFG0 CFG9 [28..30]  ============================================== */
18799 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG9                                                       */
18800   CTIMER_OUTCFG0_CFG9_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18801   CTIMER_OUTCFG0_CFG9_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18802   CTIMER_OUTCFG0_CFG9_B0OUT            = 5,     /*!< B0OUT : Output is B0OUT.                                                  */
18803   CTIMER_OUTCFG0_CFG9_A4OUT            = 4,     /*!< A4OUT : Output is A4OUT.                                                  */
18804   CTIMER_OUTCFG0_CFG9_A2OUT            = 3,     /*!< A2OUT : Output is A2OUT.                                                  */
18805   CTIMER_OUTCFG0_CFG9_A2OUT2           = 2,     /*!< A2OUT2 : Output is A2OUT2                                                 */
18806   CTIMER_OUTCFG0_CFG9_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18807   CTIMER_OUTCFG0_CFG9_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18808 } CTIMER_OUTCFG0_CFG9_Enum;
18809 
18810 /* =============================================  CTIMER OUTCFG0 CFG8 [25..27]  ============================================== */
18811 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG8                                                       */
18812   CTIMER_OUTCFG0_CFG8_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18813   CTIMER_OUTCFG0_CFG8_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18814   CTIMER_OUTCFG0_CFG8_B6OUT            = 5,     /*!< B6OUT : Output is B6OUT.                                                  */
18815   CTIMER_OUTCFG0_CFG8_A4OUT2           = 4,     /*!< A4OUT2 : Output is A4OUT2.                                                */
18816   CTIMER_OUTCFG0_CFG8_A3OUT2           = 3,     /*!< A3OUT2 : Output is A3OUT.                                                 */
18817   CTIMER_OUTCFG0_CFG8_A2OUT            = 2,     /*!< A2OUT : Output is A2OUT                                                   */
18818   CTIMER_OUTCFG0_CFG8_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18819   CTIMER_OUTCFG0_CFG8_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18820 } CTIMER_OUTCFG0_CFG8_Enum;
18821 
18822 /* =============================================  CTIMER OUTCFG0 CFG7 [22..24]  ============================================== */
18823 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG7                                                       */
18824   CTIMER_OUTCFG0_CFG7_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18825   CTIMER_OUTCFG0_CFG7_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18826   CTIMER_OUTCFG0_CFG7_A7OUT            = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
18827   CTIMER_OUTCFG0_CFG7_B5OUT            = 4,     /*!< B5OUT : Output is B5OUT.                                                  */
18828   CTIMER_OUTCFG0_CFG7_B1OUT            = 3,     /*!< B1OUT : Output is B1OUT.                                                  */
18829   CTIMER_OUTCFG0_CFG7_B1OUT2           = 2,     /*!< B1OUT2 : Output is B1OUT2                                                 */
18830   CTIMER_OUTCFG0_CFG7_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18831   CTIMER_OUTCFG0_CFG7_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18832 } CTIMER_OUTCFG0_CFG7_Enum;
18833 
18834 /* =============================================  CTIMER OUTCFG0 CFG6 [19..21]  ============================================== */
18835 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG6                                                       */
18836   CTIMER_OUTCFG0_CFG6_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18837   CTIMER_OUTCFG0_CFG6_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18838   CTIMER_OUTCFG0_CFG6_B7OUT            = 5,     /*!< B7OUT : Output is B7OUT.                                                  */
18839   CTIMER_OUTCFG0_CFG6_B5OUT2           = 4,     /*!< B5OUT2 : Output is B5OUT2.                                                */
18840   CTIMER_OUTCFG0_CFG6_A1OUT            = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
18841   CTIMER_OUTCFG0_CFG6_B1OUT            = 2,     /*!< B1OUT : Output is B1OUT                                                   */
18842   CTIMER_OUTCFG0_CFG6_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18843   CTIMER_OUTCFG0_CFG6_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18844 } CTIMER_OUTCFG0_CFG6_Enum;
18845 
18846 /* =============================================  CTIMER OUTCFG0 CFG5 [16..18]  ============================================== */
18847 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG5                                                       */
18848   CTIMER_OUTCFG0_CFG5_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18849   CTIMER_OUTCFG0_CFG5_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18850   CTIMER_OUTCFG0_CFG5_A7OUT            = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
18851   CTIMER_OUTCFG0_CFG5_B6OUT            = 4,     /*!< B6OUT : Output is A5OUT.                                                  */
18852   CTIMER_OUTCFG0_CFG5_A1OUT            = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
18853   CTIMER_OUTCFG0_CFG5_A1OUT2           = 2,     /*!< A1OUT2 : Output is A1OUT2                                                 */
18854   CTIMER_OUTCFG0_CFG5_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18855   CTIMER_OUTCFG0_CFG5_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18856 } CTIMER_OUTCFG0_CFG5_Enum;
18857 
18858 /* =============================================  CTIMER OUTCFG0 CFG4 [12..14]  ============================================== */
18859 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG4                                                       */
18860   CTIMER_OUTCFG0_CFG4_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18861   CTIMER_OUTCFG0_CFG4_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18862   CTIMER_OUTCFG0_CFG4_B5OUT            = 5,     /*!< B5OUT : Output is B5OUT.                                                  */
18863   CTIMER_OUTCFG0_CFG4_A5OUT2           = 4,     /*!< A5OUT2 : Output is A5OUT2.                                                */
18864   CTIMER_OUTCFG0_CFG4_A2OUT2           = 3,     /*!< A2OUT2 : Output is A2OUT2.                                                */
18865   CTIMER_OUTCFG0_CFG4_A1OUT            = 2,     /*!< A1OUT : Output is A1OUT                                                   */
18866   CTIMER_OUTCFG0_CFG4_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18867   CTIMER_OUTCFG0_CFG4_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18868 } CTIMER_OUTCFG0_CFG4_Enum;
18869 
18870 /* ==============================================  CTIMER OUTCFG0 CFG3 [9..11]  ============================================== */
18871 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG3                                                       */
18872   CTIMER_OUTCFG0_CFG3_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18873   CTIMER_OUTCFG0_CFG3_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18874   CTIMER_OUTCFG0_CFG3_A6OUT            = 5,     /*!< A6OUT : Output is A6OUT.                                                  */
18875   CTIMER_OUTCFG0_CFG3_A1OUT            = 4,     /*!< A1OUT : Output is A1OUT.                                                  */
18876   CTIMER_OUTCFG0_CFG3_B0OUT            = 3,     /*!< B0OUT : Output is B0OUT.                                                  */
18877   CTIMER_OUTCFG0_CFG3_B0OUT2           = 2,     /*!< B0OUT2 : Output is B0OUT2                                                 */
18878   CTIMER_OUTCFG0_CFG3_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18879   CTIMER_OUTCFG0_CFG3_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18880 } CTIMER_OUTCFG0_CFG3_Enum;
18881 
18882 /* ==============================================  CTIMER OUTCFG0 CFG2 [6..8]  =============================================== */
18883 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG2                                                       */
18884   CTIMER_OUTCFG0_CFG2_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18885   CTIMER_OUTCFG0_CFG2_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18886   CTIMER_OUTCFG0_CFG2_A7OUT            = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
18887   CTIMER_OUTCFG0_CFG2_B6OUT2           = 4,     /*!< B6OUT2 : Output is B6OUT2.                                                */
18888   CTIMER_OUTCFG0_CFG2_B1OUT2           = 3,     /*!< B1OUT2 : Output is B1OUT2.                                                */
18889   CTIMER_OUTCFG0_CFG2_B0OUT            = 2,     /*!< B0OUT : Output is B0OUT                                                   */
18890   CTIMER_OUTCFG0_CFG2_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18891   CTIMER_OUTCFG0_CFG2_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18892 } CTIMER_OUTCFG0_CFG2_Enum;
18893 
18894 /* ==============================================  CTIMER OUTCFG0 CFG1 [3..5]  =============================================== */
18895 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG1                                                       */
18896   CTIMER_OUTCFG0_CFG1_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18897   CTIMER_OUTCFG0_CFG1_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18898   CTIMER_OUTCFG0_CFG1_B7OUT2           = 5,     /*!< B7OUT2 : Output is B7OUT2.                                                */
18899   CTIMER_OUTCFG0_CFG1_A5OUT            = 4,     /*!< A5OUT : Output is A5OUT.                                                  */
18900   CTIMER_OUTCFG0_CFG1_A0OUT            = 3,     /*!< A0OUT : Output is A0OUT.                                                  */
18901   CTIMER_OUTCFG0_CFG1_A0OUT2           = 2,     /*!< A0OUT2 : Output is A0OUT2                                                 */
18902   CTIMER_OUTCFG0_CFG1_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18903   CTIMER_OUTCFG0_CFG1_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18904 } CTIMER_OUTCFG0_CFG1_Enum;
18905 
18906 /* ==============================================  CTIMER OUTCFG0 CFG0 [0..2]  =============================================== */
18907 typedef enum {                                  /*!< CTIMER_OUTCFG0_CFG0                                                       */
18908   CTIMER_OUTCFG0_CFG0_A7OUT2           = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18909   CTIMER_OUTCFG0_CFG0_A6OUT2           = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18910   CTIMER_OUTCFG0_CFG0_A6OUT            = 5,     /*!< A6OUT : Output is A6OUT.                                                  */
18911   CTIMER_OUTCFG0_CFG0_A5OUT2           = 4,     /*!< A5OUT2 : Output is A5OUT2.                                                */
18912   CTIMER_OUTCFG0_CFG0_B2OUT2           = 3,     /*!< B2OUT2 : Output is B2OUT2.                                                */
18913   CTIMER_OUTCFG0_CFG0_A0OUT            = 2,     /*!< A0OUT : Output is A0OUT                                                   */
18914   CTIMER_OUTCFG0_CFG0_ONE              = 1,     /*!< ONE : Force output to 1.                                                  */
18915   CTIMER_OUTCFG0_CFG0_ZERO             = 0,     /*!< ZERO : Force output to 0                                                  */
18916 } CTIMER_OUTCFG0_CFG0_Enum;
18917 
18918 /* ========================================================  OUTCFG1  ======================================================== */
18919 /* =============================================  CTIMER OUTCFG1 CFG19 [28..30]  ============================================= */
18920 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG19                                                      */
18921   CTIMER_OUTCFG1_CFG19_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18922   CTIMER_OUTCFG1_CFG19_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18923   CTIMER_OUTCFG1_CFG19_B1OUT2          = 5,     /*!< B1OUT2 : Output is B1OUT2.                                                */
18924   CTIMER_OUTCFG1_CFG19_B4OUT           = 4,     /*!< B4OUT : Output is B4OUT.                                                  */
18925   CTIMER_OUTCFG1_CFG19_A2OUT           = 3,     /*!< A2OUT : Output is A2OUT.                                                  */
18926   CTIMER_OUTCFG1_CFG19_B4OUT2          = 2,     /*!< B4OUT2 : Output is B4OUT2                                                 */
18927   CTIMER_OUTCFG1_CFG19_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
18928   CTIMER_OUTCFG1_CFG19_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
18929 } CTIMER_OUTCFG1_CFG19_Enum;
18930 
18931 /* =============================================  CTIMER OUTCFG1 CFG18 [25..27]  ============================================= */
18932 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG18                                                      */
18933   CTIMER_OUTCFG1_CFG18_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18934   CTIMER_OUTCFG1_CFG18_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18935   CTIMER_OUTCFG1_CFG18_A3OUT2          = 5,     /*!< A3OUT2 : Output is A3OUT2.                                                */
18936   CTIMER_OUTCFG1_CFG18_A0OUT           = 4,     /*!< A0OUT : Output is A0OUT.                                                  */
18937   CTIMER_OUTCFG1_CFG18_B0OUT           = 3,     /*!< B0OUT : Output is B0OUT.                                                  */
18938   CTIMER_OUTCFG1_CFG18_B4OUT           = 2,     /*!< B4OUT : Output is B4OUT                                                   */
18939   CTIMER_OUTCFG1_CFG18_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
18940   CTIMER_OUTCFG1_CFG18_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
18941 } CTIMER_OUTCFG1_CFG18_Enum;
18942 
18943 /* =============================================  CTIMER OUTCFG1 CFG17 [22..24]  ============================================= */
18944 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG17                                                      */
18945   CTIMER_OUTCFG1_CFG17_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18946   CTIMER_OUTCFG1_CFG17_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18947   CTIMER_OUTCFG1_CFG17_A1OUT2          = 5,     /*!< A1OUT2 : Output is A1OUT2.                                                */
18948   CTIMER_OUTCFG1_CFG17_A4OUT           = 4,     /*!< A4OUT : Output is A4OUT.                                                  */
18949   CTIMER_OUTCFG1_CFG17_B7OUT           = 3,     /*!< B7OUT : Output is B7OUT.                                                  */
18950   CTIMER_OUTCFG1_CFG17_A4OUT2          = 2,     /*!< A4OUT2 : Output is A4OUT2                                                 */
18951   CTIMER_OUTCFG1_CFG17_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
18952   CTIMER_OUTCFG1_CFG17_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
18953 } CTIMER_OUTCFG1_CFG17_Enum;
18954 
18955 /* =============================================  CTIMER OUTCFG1 CFG16 [19..21]  ============================================= */
18956 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG16                                                      */
18957   CTIMER_OUTCFG1_CFG16_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18958   CTIMER_OUTCFG1_CFG16_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18959   CTIMER_OUTCFG1_CFG16_B3OUT2          = 5,     /*!< B3OUT2 : Output is B3OUT2.                                                */
18960   CTIMER_OUTCFG1_CFG16_A0OUT2          = 4,     /*!< A0OUT2 : Output is A0OUT2.                                                */
18961   CTIMER_OUTCFG1_CFG16_A0OUT           = 3,     /*!< A0OUT : Output is A0OUT.                                                  */
18962   CTIMER_OUTCFG1_CFG16_A4OUT           = 2,     /*!< A4OUT : Output is A4OUT                                                   */
18963   CTIMER_OUTCFG1_CFG16_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
18964   CTIMER_OUTCFG1_CFG16_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
18965 } CTIMER_OUTCFG1_CFG16_Enum;
18966 
18967 /* =============================================  CTIMER OUTCFG1 CFG15 [16..18]  ============================================= */
18968 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG15                                                      */
18969   CTIMER_OUTCFG1_CFG15_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18970   CTIMER_OUTCFG1_CFG15_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18971   CTIMER_OUTCFG1_CFG15_A4OUT2          = 5,     /*!< A4OUT2 : Output is A4OUT2.                                                */
18972   CTIMER_OUTCFG1_CFG15_A7OUT           = 4,     /*!< A7OUT : Output is A7OUT.                                                  */
18973   CTIMER_OUTCFG1_CFG15_B3OUT           = 3,     /*!< B3OUT : Output is B3OUT.                                                  */
18974   CTIMER_OUTCFG1_CFG15_B3OUT2          = 2,     /*!< B3OUT2 : Output is B3OUT2                                                 */
18975   CTIMER_OUTCFG1_CFG15_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
18976   CTIMER_OUTCFG1_CFG15_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
18977 } CTIMER_OUTCFG1_CFG15_Enum;
18978 
18979 /* =============================================  CTIMER OUTCFG1 CFG14 [12..14]  ============================================= */
18980 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG14                                                      */
18981   CTIMER_OUTCFG1_CFG14_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18982   CTIMER_OUTCFG1_CFG14_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18983   CTIMER_OUTCFG1_CFG14_A7OUT           = 5,     /*!< A7OUT : Output is A7OUT.                                                  */
18984   CTIMER_OUTCFG1_CFG14_B7OUT2          = 4,     /*!< B7OUT2 : Output is B7OUT2.                                                */
18985   CTIMER_OUTCFG1_CFG14_B1OUT           = 3,     /*!< B1OUT : Output is B1OUT.                                                  */
18986   CTIMER_OUTCFG1_CFG14_B3OUT           = 2,     /*!< B3OUT : Output is B3OUT                                                   */
18987   CTIMER_OUTCFG1_CFG14_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
18988   CTIMER_OUTCFG1_CFG14_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
18989 } CTIMER_OUTCFG1_CFG14_Enum;
18990 
18991 /* =============================================  CTIMER OUTCFG1 CFG13 [9..11]  ============================================== */
18992 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG13                                                      */
18993   CTIMER_OUTCFG1_CFG13_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
18994   CTIMER_OUTCFG1_CFG13_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
18995   CTIMER_OUTCFG1_CFG13_B4OUT2          = 5,     /*!< B4OUT2 : Output is B4OUT2.                                                */
18996   CTIMER_OUTCFG1_CFG13_A6OUT           = 4,     /*!< A6OUT : Output is A6OUT.                                                  */
18997   CTIMER_OUTCFG1_CFG13_A3OUT           = 3,     /*!< A3OUT : Output is A3OUT.                                                  */
18998   CTIMER_OUTCFG1_CFG13_A3OUT2          = 2,     /*!< A3OUT2 : Output is A3OUT2                                                 */
18999   CTIMER_OUTCFG1_CFG13_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19000   CTIMER_OUTCFG1_CFG13_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19001 } CTIMER_OUTCFG1_CFG13_Enum;
19002 
19003 /* ==============================================  CTIMER OUTCFG1 CFG12 [6..8]  ============================================== */
19004 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG12                                                      */
19005   CTIMER_OUTCFG1_CFG12_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19006   CTIMER_OUTCFG1_CFG12_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19007   CTIMER_OUTCFG1_CFG12_B6OUT2          = 5,     /*!< B6OUT2 : Output is B6OUT2.                                                */
19008   CTIMER_OUTCFG1_CFG12_B0OUT2          = 4,     /*!< B0OUT2 : Output is B0OUT2.                                                */
19009   CTIMER_OUTCFG1_CFG12_B1OUT           = 3,     /*!< B1OUT : Output is B1OUT.                                                  */
19010   CTIMER_OUTCFG1_CFG12_A3OUT           = 2,     /*!< A3OUT : Output is A3OUT                                                   */
19011   CTIMER_OUTCFG1_CFG12_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19012   CTIMER_OUTCFG1_CFG12_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19013 } CTIMER_OUTCFG1_CFG12_Enum;
19014 
19015 /* ==============================================  CTIMER OUTCFG1 CFG11 [3..5]  ============================================== */
19016 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG11                                                      */
19017   CTIMER_OUTCFG1_CFG11_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19018   CTIMER_OUTCFG1_CFG11_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19019   CTIMER_OUTCFG1_CFG11_B5OUT2          = 5,     /*!< B5OUT2 : Output is B5OUT2.                                                */
19020   CTIMER_OUTCFG1_CFG11_B4OUT           = 4,     /*!< B4OUT : Output is B4OUT.                                                  */
19021   CTIMER_OUTCFG1_CFG11_B2OUT           = 3,     /*!< B2OUT : Output is B2OUT.                                                  */
19022   CTIMER_OUTCFG1_CFG11_B2OUT2          = 2,     /*!< B2OUT2 : Output is B2OUT2                                                 */
19023   CTIMER_OUTCFG1_CFG11_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19024   CTIMER_OUTCFG1_CFG11_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19025 } CTIMER_OUTCFG1_CFG11_Enum;
19026 
19027 /* ==============================================  CTIMER OUTCFG1 CFG10 [0..2]  ============================================== */
19028 typedef enum {                                  /*!< CTIMER_OUTCFG1_CFG10                                                      */
19029   CTIMER_OUTCFG1_CFG10_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19030   CTIMER_OUTCFG1_CFG10_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19031   CTIMER_OUTCFG1_CFG10_A6OUT           = 5,     /*!< A6OUT : Output is A6OUT.                                                  */
19032   CTIMER_OUTCFG1_CFG10_B4OUT2          = 4,     /*!< B4OUT2 : Output is B4OUT2.                                                */
19033   CTIMER_OUTCFG1_CFG10_B3OUT2          = 3,     /*!< B3OUT2 : Output is B3OUT2.                                                */
19034   CTIMER_OUTCFG1_CFG10_B2OUT           = 2,     /*!< B2OUT : Output is B2OUT                                                   */
19035   CTIMER_OUTCFG1_CFG10_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19036   CTIMER_OUTCFG1_CFG10_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19037 } CTIMER_OUTCFG1_CFG10_Enum;
19038 
19039 /* ========================================================  OUTCFG2  ======================================================== */
19040 /* =============================================  CTIMER OUTCFG2 CFG29 [28..30]  ============================================= */
19041 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG29                                                      */
19042   CTIMER_OUTCFG2_CFG29_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19043   CTIMER_OUTCFG2_CFG29_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19044   CTIMER_OUTCFG2_CFG29_A3OUT2          = 5,     /*!< A3OUT2 : Output is A3OUT2.                                                */
19045   CTIMER_OUTCFG2_CFG29_A7OUT           = 4,     /*!< A7OUT : Output is A7OUT.                                                  */
19046   CTIMER_OUTCFG2_CFG29_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
19047   CTIMER_OUTCFG2_CFG29_B5OUT2          = 2,     /*!< B5OUT2 : Output is B5OUT2                                                 */
19048   CTIMER_OUTCFG2_CFG29_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19049   CTIMER_OUTCFG2_CFG29_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19050 } CTIMER_OUTCFG2_CFG29_Enum;
19051 
19052 /* =============================================  CTIMER OUTCFG2 CFG28 [25..27]  ============================================= */
19053 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG28                                                      */
19054   CTIMER_OUTCFG2_CFG28_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19055   CTIMER_OUTCFG2_CFG28_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19056   CTIMER_OUTCFG2_CFG28_B0OUT2          = 5,     /*!< B0OUT2 : Output is B0OUT2.                                                */
19057   CTIMER_OUTCFG2_CFG28_A5OUT2          = 4,     /*!< A5OUT2 : Output is A5OUT2.                                                */
19058   CTIMER_OUTCFG2_CFG28_A3OUT           = 3,     /*!< A3OUT : Output is A3OUT.                                                  */
19059   CTIMER_OUTCFG2_CFG28_A7OUT           = 2,     /*!< A7OUT : Output is A7OUT                                                   */
19060   CTIMER_OUTCFG2_CFG28_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19061   CTIMER_OUTCFG2_CFG28_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19062 } CTIMER_OUTCFG2_CFG28_Enum;
19063 
19064 /* =============================================  CTIMER OUTCFG2 CFG27 [22..24]  ============================================= */
19065 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG27                                                      */
19066   CTIMER_OUTCFG2_CFG27_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19067   CTIMER_OUTCFG2_CFG27_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19068   CTIMER_OUTCFG2_CFG27_B2OUT2          = 5,     /*!< B2OUT2 : Output is B2OUT2.                                                */
19069   CTIMER_OUTCFG2_CFG27_B6OUT           = 4,     /*!< B6OUT : Output is B6OUT.                                                  */
19070   CTIMER_OUTCFG2_CFG27_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
19071   CTIMER_OUTCFG2_CFG27_B6OUT2          = 2,     /*!< B6OUT2 : Output is B6OUT2                                                 */
19072   CTIMER_OUTCFG2_CFG27_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19073   CTIMER_OUTCFG2_CFG27_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19074 } CTIMER_OUTCFG2_CFG27_Enum;
19075 
19076 /* =============================================  CTIMER OUTCFG2 CFG26 [19..21]  ============================================= */
19077 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG26                                                      */
19078   CTIMER_OUTCFG2_CFG26_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19079   CTIMER_OUTCFG2_CFG26_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19080   CTIMER_OUTCFG2_CFG26_A1OUT2          = 5,     /*!< A1OUT2 : Output is A1OUT2.                                                */
19081   CTIMER_OUTCFG2_CFG26_A5OUT           = 4,     /*!< A5OUT : Output is A5OUT.                                                  */
19082   CTIMER_OUTCFG2_CFG26_B2OUT           = 3,     /*!< B2OUT : Output is B2OUT.                                                  */
19083   CTIMER_OUTCFG2_CFG26_B6OUT           = 2,     /*!< B6OUT : Output is B6OUT                                                   */
19084   CTIMER_OUTCFG2_CFG26_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19085   CTIMER_OUTCFG2_CFG26_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19086 } CTIMER_OUTCFG2_CFG26_Enum;
19087 
19088 /* =============================================  CTIMER OUTCFG2 CFG25 [16..18]  ============================================= */
19089 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG25                                                      */
19090   CTIMER_OUTCFG2_CFG25_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19091   CTIMER_OUTCFG2_CFG25_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19092   CTIMER_OUTCFG2_CFG25_A2OUT2          = 5,     /*!< A2OUT2 : Output is A2OUT2.                                                */
19093   CTIMER_OUTCFG2_CFG25_A6OUT           = 4,     /*!< A6OUT : Output is A6OUT.                                                  */
19094   CTIMER_OUTCFG2_CFG25_B2OUT           = 3,     /*!< B2OUT : Output is B2OUT.                                                  */
19095   CTIMER_OUTCFG2_CFG25_B4OUT2          = 2,     /*!< B4OUT2 : Output is B4OUT2                                                 */
19096   CTIMER_OUTCFG2_CFG25_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19097   CTIMER_OUTCFG2_CFG25_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19098 } CTIMER_OUTCFG2_CFG25_Enum;
19099 
19100 /* =============================================  CTIMER OUTCFG2 CFG24 [12..14]  ============================================= */
19101 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG24                                                      */
19102   CTIMER_OUTCFG2_CFG24_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19103   CTIMER_OUTCFG2_CFG24_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19104   CTIMER_OUTCFG2_CFG24_B1OUT2          = 5,     /*!< B1OUT2 : Output is B1OUT2.                                                */
19105   CTIMER_OUTCFG2_CFG24_A1OUT           = 4,     /*!< A1OUT : Output is A1OUT.                                                  */
19106   CTIMER_OUTCFG2_CFG24_A2OUT           = 3,     /*!< A2OUT : Output is A2OUT.                                                  */
19107   CTIMER_OUTCFG2_CFG24_A6OUT           = 2,     /*!< A6OUT : Output is A6OUT                                                   */
19108   CTIMER_OUTCFG2_CFG24_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19109   CTIMER_OUTCFG2_CFG24_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19110 } CTIMER_OUTCFG2_CFG24_Enum;
19111 
19112 /* =============================================  CTIMER OUTCFG2 CFG23 [9..11]  ============================================== */
19113 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG23                                                      */
19114   CTIMER_OUTCFG2_CFG23_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19115   CTIMER_OUTCFG2_CFG23_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19116   CTIMER_OUTCFG2_CFG23_B0OUT2          = 5,     /*!< B0OUT2 : Output is B0OUT2.                                                */
19117   CTIMER_OUTCFG2_CFG23_A5OUT           = 4,     /*!< A5OUT : Output is A5OUT.                                                  */
19118   CTIMER_OUTCFG2_CFG23_A7OUT           = 3,     /*!< A7OUT : Output is A7OUT.                                                  */
19119   CTIMER_OUTCFG2_CFG23_B5OUT2          = 2,     /*!< B5OUT2 : Output is B5OUT2                                                 */
19120   CTIMER_OUTCFG2_CFG23_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19121   CTIMER_OUTCFG2_CFG23_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19122 } CTIMER_OUTCFG2_CFG23_Enum;
19123 
19124 /* ==============================================  CTIMER OUTCFG2 CFG22 [6..8]  ============================================== */
19125 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG22                                                      */
19126   CTIMER_OUTCFG2_CFG22_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19127   CTIMER_OUTCFG2_CFG22_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19128   CTIMER_OUTCFG2_CFG22_A2OUT2          = 5,     /*!< A2OUT2 : Output is A2OUT2.                                                */
19129   CTIMER_OUTCFG2_CFG22_A1OUT           = 4,     /*!< A1OUT : Output is A1OUT.                                                  */
19130   CTIMER_OUTCFG2_CFG22_A6OUT           = 3,     /*!< A6OUT : Output is A6OUT.                                                  */
19131   CTIMER_OUTCFG2_CFG22_B5OUT           = 2,     /*!< B5OUT : Output is B5OUT                                                   */
19132   CTIMER_OUTCFG2_CFG22_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19133   CTIMER_OUTCFG2_CFG22_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19134 } CTIMER_OUTCFG2_CFG22_Enum;
19135 
19136 /* ==============================================  CTIMER OUTCFG2 CFG21 [3..5]  ============================================== */
19137 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG21                                                      */
19138   CTIMER_OUTCFG2_CFG21_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19139   CTIMER_OUTCFG2_CFG21_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19140   CTIMER_OUTCFG2_CFG21_A0OUT2          = 5,     /*!< A0OUT2 : Output is A0OUT2.                                                */
19141   CTIMER_OUTCFG2_CFG21_B5OUT           = 4,     /*!< B5OUT : Output is B5OUT.                                                  */
19142   CTIMER_OUTCFG2_CFG21_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
19143   CTIMER_OUTCFG2_CFG21_A5OUT2          = 2,     /*!< A5OUT2 : Output is A5OUT2                                                 */
19144   CTIMER_OUTCFG2_CFG21_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19145   CTIMER_OUTCFG2_CFG21_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19146 } CTIMER_OUTCFG2_CFG21_Enum;
19147 
19148 /* ==============================================  CTIMER OUTCFG2 CFG20 [0..2]  ============================================== */
19149 typedef enum {                                  /*!< CTIMER_OUTCFG2_CFG20                                                      */
19150   CTIMER_OUTCFG2_CFG20_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19151   CTIMER_OUTCFG2_CFG20_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19152   CTIMER_OUTCFG2_CFG20_B2OUT2          = 5,     /*!< B2OUT2 : Output is B2OUT2.                                                */
19153   CTIMER_OUTCFG2_CFG20_A1OUT2          = 4,     /*!< A1OUT2 : Output is A1OUT2.                                                */
19154   CTIMER_OUTCFG2_CFG20_A1OUT           = 3,     /*!< A1OUT : Output is A1OUT.                                                  */
19155   CTIMER_OUTCFG2_CFG20_A5OUT           = 2,     /*!< A5OUT : Output is A5OUT                                                   */
19156   CTIMER_OUTCFG2_CFG20_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19157   CTIMER_OUTCFG2_CFG20_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19158 } CTIMER_OUTCFG2_CFG20_Enum;
19159 
19160 /* ========================================================  OUTCFG3  ======================================================== */
19161 /* ==============================================  CTIMER OUTCFG3 CFG31 [3..5]  ============================================== */
19162 typedef enum {                                  /*!< CTIMER_OUTCFG3_CFG31                                                      */
19163   CTIMER_OUTCFG3_CFG31_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19164   CTIMER_OUTCFG3_CFG31_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19165   CTIMER_OUTCFG3_CFG31_B3OUT2          = 5,     /*!< B3OUT2 : Output is B3OUT2.                                                */
19166   CTIMER_OUTCFG3_CFG31_B7OUT           = 4,     /*!< B7OUT : Output is B7OUT.                                                  */
19167   CTIMER_OUTCFG3_CFG31_A6OUT           = 3,     /*!< A6OUT : Output is A6OUT.                                                  */
19168   CTIMER_OUTCFG3_CFG31_B7OUT2          = 2,     /*!< B7OUT2 : Output is B7OUT2                                                 */
19169   CTIMER_OUTCFG3_CFG31_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19170   CTIMER_OUTCFG3_CFG31_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19171 } CTIMER_OUTCFG3_CFG31_Enum;
19172 
19173 /* ==============================================  CTIMER OUTCFG3 CFG30 [0..2]  ============================================== */
19174 typedef enum {                                  /*!< CTIMER_OUTCFG3_CFG30                                                      */
19175   CTIMER_OUTCFG3_CFG30_A7OUT2          = 7,     /*!< A7OUT2 : Output is A7OUT2.                                                */
19176   CTIMER_OUTCFG3_CFG30_A6OUT2          = 6,     /*!< A6OUT2 : Output is A6OUT2.                                                */
19177   CTIMER_OUTCFG3_CFG30_A0OUT2          = 5,     /*!< A0OUT2 : Output is A0OUT2.                                                */
19178   CTIMER_OUTCFG3_CFG30_A4OUT2          = 4,     /*!< A4OUT2 : Output is A4OUT2.                                                */
19179   CTIMER_OUTCFG3_CFG30_B3OUT           = 3,     /*!< B3OUT : Output is B3OUT.                                                  */
19180   CTIMER_OUTCFG3_CFG30_B7OUT           = 2,     /*!< B7OUT : Output is B7OUT                                                   */
19181   CTIMER_OUTCFG3_CFG30_ONE             = 1,     /*!< ONE : Force output to 1.                                                  */
19182   CTIMER_OUTCFG3_CFG30_ZERO            = 0,     /*!< ZERO : Force output to 0                                                  */
19183 } CTIMER_OUTCFG3_CFG30_Enum;
19184 
19185 /* =========================================================  INCFG  ========================================================= */
19186 /* ==============================================  CTIMER INCFG CFGB7 [15..15]  ============================================== */
19187 typedef enum {                                  /*!< CTIMER_INCFG_CFGB7                                                        */
19188   CTIMER_INCFG_CFGB7_CT31              = 1,     /*!< CT31 : Input is CT31                                                      */
19189   CTIMER_INCFG_CFGB7_CT30              = 0,     /*!< CT30 : Input is CT30                                                      */
19190 } CTIMER_INCFG_CFGB7_Enum;
19191 
19192 /* ==============================================  CTIMER INCFG CFGA7 [14..14]  ============================================== */
19193 typedef enum {                                  /*!< CTIMER_INCFG_CFGA7                                                        */
19194   CTIMER_INCFG_CFGA7_CT29              = 1,     /*!< CT29 : Input is CT29                                                      */
19195   CTIMER_INCFG_CFGA7_CT28              = 0,     /*!< CT28 : Input is CT28                                                      */
19196 } CTIMER_INCFG_CFGA7_Enum;
19197 
19198 /* ==============================================  CTIMER INCFG CFGB6 [13..13]  ============================================== */
19199 typedef enum {                                  /*!< CTIMER_INCFG_CFGB6                                                        */
19200   CTIMER_INCFG_CFGB6_CT27              = 1,     /*!< CT27 : Input is CT27                                                      */
19201   CTIMER_INCFG_CFGB6_CT26              = 0,     /*!< CT26 : Input is CT26                                                      */
19202 } CTIMER_INCFG_CFGB6_Enum;
19203 
19204 /* ==============================================  CTIMER INCFG CFGA6 [12..12]  ============================================== */
19205 typedef enum {                                  /*!< CTIMER_INCFG_CFGA6                                                        */
19206   CTIMER_INCFG_CFGA6_CT25              = 1,     /*!< CT25 : Input is CT25                                                      */
19207   CTIMER_INCFG_CFGA6_CT24              = 0,     /*!< CT24 : Input is CT24                                                      */
19208 } CTIMER_INCFG_CFGA6_Enum;
19209 
19210 /* ==============================================  CTIMER INCFG CFGB5 [11..11]  ============================================== */
19211 typedef enum {                                  /*!< CTIMER_INCFG_CFGB5                                                        */
19212   CTIMER_INCFG_CFGB5_CT23              = 1,     /*!< CT23 : Input is CT23                                                      */
19213   CTIMER_INCFG_CFGB5_CT22              = 0,     /*!< CT22 : Input is CT22                                                      */
19214 } CTIMER_INCFG_CFGB5_Enum;
19215 
19216 /* ==============================================  CTIMER INCFG CFGA5 [10..10]  ============================================== */
19217 typedef enum {                                  /*!< CTIMER_INCFG_CFGA5                                                        */
19218   CTIMER_INCFG_CFGA5_CT21              = 1,     /*!< CT21 : Input is CT21                                                      */
19219   CTIMER_INCFG_CFGA5_CT20              = 0,     /*!< CT20 : Input is CT20                                                      */
19220 } CTIMER_INCFG_CFGA5_Enum;
19221 
19222 /* ===============================================  CTIMER INCFG CFGB4 [9..9]  =============================================== */
19223 typedef enum {                                  /*!< CTIMER_INCFG_CFGB4                                                        */
19224   CTIMER_INCFG_CFGB4_CT19              = 1,     /*!< CT19 : Input is CT19                                                      */
19225   CTIMER_INCFG_CFGB4_CT18              = 0,     /*!< CT18 : Input is CT18                                                      */
19226 } CTIMER_INCFG_CFGB4_Enum;
19227 
19228 /* ===============================================  CTIMER INCFG CFGA4 [8..8]  =============================================== */
19229 typedef enum {                                  /*!< CTIMER_INCFG_CFGA4                                                        */
19230   CTIMER_INCFG_CFGA4_CT17              = 1,     /*!< CT17 : Input is CT17                                                      */
19231   CTIMER_INCFG_CFGA4_CT16              = 0,     /*!< CT16 : Input is CT16                                                      */
19232 } CTIMER_INCFG_CFGA4_Enum;
19233 
19234 /* ===============================================  CTIMER INCFG CFGB3 [7..7]  =============================================== */
19235 typedef enum {                                  /*!< CTIMER_INCFG_CFGB3                                                        */
19236   CTIMER_INCFG_CFGB3_CT15              = 1,     /*!< CT15 : Input is CT15                                                      */
19237   CTIMER_INCFG_CFGB3_CT14              = 0,     /*!< CT14 : Input is CT14                                                      */
19238 } CTIMER_INCFG_CFGB3_Enum;
19239 
19240 /* ===============================================  CTIMER INCFG CFGA3 [6..6]  =============================================== */
19241 typedef enum {                                  /*!< CTIMER_INCFG_CFGA3                                                        */
19242   CTIMER_INCFG_CFGA3_CT13              = 1,     /*!< CT13 : Input is CT13                                                      */
19243   CTIMER_INCFG_CFGA3_CT12              = 0,     /*!< CT12 : Input is CT12                                                      */
19244 } CTIMER_INCFG_CFGA3_Enum;
19245 
19246 /* ===============================================  CTIMER INCFG CFGB2 [5..5]  =============================================== */
19247 typedef enum {                                  /*!< CTIMER_INCFG_CFGB2                                                        */
19248   CTIMER_INCFG_CFGB2_CT11              = 1,     /*!< CT11 : Input is CT11                                                      */
19249   CTIMER_INCFG_CFGB2_CT10              = 0,     /*!< CT10 : Input is CT10                                                      */
19250 } CTIMER_INCFG_CFGB2_Enum;
19251 
19252 /* ===============================================  CTIMER INCFG CFGA2 [4..4]  =============================================== */
19253 typedef enum {                                  /*!< CTIMER_INCFG_CFGA2                                                        */
19254   CTIMER_INCFG_CFGA2_CT9               = 1,     /*!< CT9 : Input is CT9                                                        */
19255   CTIMER_INCFG_CFGA2_CT8               = 0,     /*!< CT8 : Input is CT8                                                        */
19256 } CTIMER_INCFG_CFGA2_Enum;
19257 
19258 /* ===============================================  CTIMER INCFG CFGB1 [3..3]  =============================================== */
19259 typedef enum {                                  /*!< CTIMER_INCFG_CFGB1                                                        */
19260   CTIMER_INCFG_CFGB1_CT7               = 1,     /*!< CT7 : Input is CT7                                                        */
19261   CTIMER_INCFG_CFGB1_CT6               = 0,     /*!< CT6 : Input is CT6                                                        */
19262 } CTIMER_INCFG_CFGB1_Enum;
19263 
19264 /* ===============================================  CTIMER INCFG CFGA1 [2..2]  =============================================== */
19265 typedef enum {                                  /*!< CTIMER_INCFG_CFGA1                                                        */
19266   CTIMER_INCFG_CFGA1_CT5               = 1,     /*!< CT5 : Input is CT5                                                        */
19267   CTIMER_INCFG_CFGA1_CT4               = 0,     /*!< CT4 : Input is CT4                                                        */
19268 } CTIMER_INCFG_CFGA1_Enum;
19269 
19270 /* ===============================================  CTIMER INCFG CFGB0 [1..1]  =============================================== */
19271 typedef enum {                                  /*!< CTIMER_INCFG_CFGB0                                                        */
19272   CTIMER_INCFG_CFGB0_CT3               = 1,     /*!< CT3 : Input is CT3                                                        */
19273   CTIMER_INCFG_CFGB0_CT2               = 0,     /*!< CT2 : Input is CT2                                                        */
19274 } CTIMER_INCFG_CFGB0_Enum;
19275 
19276 /* ===============================================  CTIMER INCFG CFGA0 [0..0]  =============================================== */
19277 typedef enum {                                  /*!< CTIMER_INCFG_CFGA0                                                        */
19278   CTIMER_INCFG_CFGA0_CT1               = 1,     /*!< CT1 : Input is CT1                                                        */
19279   CTIMER_INCFG_CFGA0_CT0               = 0,     /*!< CT0 : Input is CT0                                                        */
19280 } CTIMER_INCFG_CFGA0_Enum;
19281 
19282 /* =========================================================  STCFG  ========================================================= */
19283 /* =============================================  CTIMER STCFG FREEZE [31..31]  ============================================== */
19284 typedef enum {                                  /*!< CTIMER_STCFG_FREEZE                                                       */
19285   CTIMER_STCFG_FREEZE_THAW             = 0,     /*!< THAW : Let the COUNTER register run on its input clock.                   */
19286   CTIMER_STCFG_FREEZE_FREEZE           = 1,     /*!< FREEZE : Stop the COUNTER register for loading.                           */
19287 } CTIMER_STCFG_FREEZE_Enum;
19288 
19289 /* ==============================================  CTIMER STCFG CLEAR [30..30]  ============================================== */
19290 typedef enum {                                  /*!< CTIMER_STCFG_CLEAR                                                        */
19291   CTIMER_STCFG_CLEAR_RUN               = 0,     /*!< RUN : Let the COUNTER register run on its input clock.                    */
19292   CTIMER_STCFG_CLEAR_CLEAR             = 1,     /*!< CLEAR : Stop the COUNTER register for loading.                            */
19293 } CTIMER_STCFG_CLEAR_Enum;
19294 
19295 /* ==========================================  CTIMER STCFG COMPARE_H_EN [15..15]  =========================================== */
19296 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_H_EN                                                 */
19297   CTIMER_STCFG_COMPARE_H_EN_DISABLE    = 0,     /*!< DISABLE : Compare H disabled.                                             */
19298   CTIMER_STCFG_COMPARE_H_EN_ENABLE     = 1,     /*!< ENABLE : Compare H enabled.                                               */
19299 } CTIMER_STCFG_COMPARE_H_EN_Enum;
19300 
19301 /* ==========================================  CTIMER STCFG COMPARE_G_EN [14..14]  =========================================== */
19302 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_G_EN                                                 */
19303   CTIMER_STCFG_COMPARE_G_EN_DISABLE    = 0,     /*!< DISABLE : Compare G disabled.                                             */
19304   CTIMER_STCFG_COMPARE_G_EN_ENABLE     = 1,     /*!< ENABLE : Compare G enabled.                                               */
19305 } CTIMER_STCFG_COMPARE_G_EN_Enum;
19306 
19307 /* ==========================================  CTIMER STCFG COMPARE_F_EN [13..13]  =========================================== */
19308 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_F_EN                                                 */
19309   CTIMER_STCFG_COMPARE_F_EN_DISABLE    = 0,     /*!< DISABLE : Compare F disabled.                                             */
19310   CTIMER_STCFG_COMPARE_F_EN_ENABLE     = 1,     /*!< ENABLE : Compare F enabled.                                               */
19311 } CTIMER_STCFG_COMPARE_F_EN_Enum;
19312 
19313 /* ==========================================  CTIMER STCFG COMPARE_E_EN [12..12]  =========================================== */
19314 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_E_EN                                                 */
19315   CTIMER_STCFG_COMPARE_E_EN_DISABLE    = 0,     /*!< DISABLE : Compare E disabled.                                             */
19316   CTIMER_STCFG_COMPARE_E_EN_ENABLE     = 1,     /*!< ENABLE : Compare E enabled.                                               */
19317 } CTIMER_STCFG_COMPARE_E_EN_Enum;
19318 
19319 /* ==========================================  CTIMER STCFG COMPARE_D_EN [11..11]  =========================================== */
19320 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_D_EN                                                 */
19321   CTIMER_STCFG_COMPARE_D_EN_DISABLE    = 0,     /*!< DISABLE : Compare D disabled.                                             */
19322   CTIMER_STCFG_COMPARE_D_EN_ENABLE     = 1,     /*!< ENABLE : Compare D enabled.                                               */
19323 } CTIMER_STCFG_COMPARE_D_EN_Enum;
19324 
19325 /* ==========================================  CTIMER STCFG COMPARE_C_EN [10..10]  =========================================== */
19326 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_C_EN                                                 */
19327   CTIMER_STCFG_COMPARE_C_EN_DISABLE    = 0,     /*!< DISABLE : Compare C disabled.                                             */
19328   CTIMER_STCFG_COMPARE_C_EN_ENABLE     = 1,     /*!< ENABLE : Compare C enabled.                                               */
19329 } CTIMER_STCFG_COMPARE_C_EN_Enum;
19330 
19331 /* ===========================================  CTIMER STCFG COMPARE_B_EN [9..9]  ============================================ */
19332 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_B_EN                                                 */
19333   CTIMER_STCFG_COMPARE_B_EN_DISABLE    = 0,     /*!< DISABLE : Compare B disabled.                                             */
19334   CTIMER_STCFG_COMPARE_B_EN_ENABLE     = 1,     /*!< ENABLE : Compare B enabled.                                               */
19335 } CTIMER_STCFG_COMPARE_B_EN_Enum;
19336 
19337 /* ===========================================  CTIMER STCFG COMPARE_A_EN [8..8]  ============================================ */
19338 typedef enum {                                  /*!< CTIMER_STCFG_COMPARE_A_EN                                                 */
19339   CTIMER_STCFG_COMPARE_A_EN_DISABLE    = 0,     /*!< DISABLE : Compare A disabled.                                             */
19340   CTIMER_STCFG_COMPARE_A_EN_ENABLE     = 1,     /*!< ENABLE : Compare A enabled.                                               */
19341 } CTIMER_STCFG_COMPARE_A_EN_Enum;
19342 
19343 /* ==============================================  CTIMER STCFG CLKSEL [0..3]  =============================================== */
19344 typedef enum {                                  /*!< CTIMER_STCFG_CLKSEL                                                       */
19345   CTIMER_STCFG_CLKSEL_NOCLK            = 0,     /*!< NOCLK : No clock enabled.                                                 */
19346   CTIMER_STCFG_CLKSEL_HFRC_DIV16       = 1,     /*!< HFRC_DIV16 : 3MHz from the HFRC clock divider.                            */
19347   CTIMER_STCFG_CLKSEL_HFRC_DIV256      = 2,     /*!< HFRC_DIV256 : 187.5KHz from the HFRC clock divider.                       */
19348   CTIMER_STCFG_CLKSEL_XTAL_DIV1        = 3,     /*!< XTAL_DIV1 : 32768Hz from the crystal oscillator.                          */
19349   CTIMER_STCFG_CLKSEL_XTAL_DIV2        = 4,     /*!< XTAL_DIV2 : 16384Hz from the crystal oscillator.                          */
19350   CTIMER_STCFG_CLKSEL_XTAL_DIV32       = 5,     /*!< XTAL_DIV32 : 1024Hz from the crystal oscillator.                          */
19351   CTIMER_STCFG_CLKSEL_LFRC_DIV1        = 6,     /*!< LFRC_DIV1 : Approximately 1KHz from the LFRC oscillator (uncalibrated).   */
19352   CTIMER_STCFG_CLKSEL_CTIMER0A         = 7,     /*!< CTIMER0A : Use CTIMER 0 section A as a prescaler for the clock
19353                                                      source.                                                                   */
19354   CTIMER_STCFG_CLKSEL_CTIMER0B         = 8,     /*!< CTIMER0B : Use CTIMER 0 section B (or A and B linked together)
19355                                                      as a prescaler for the clock source.                                      */
19356 } CTIMER_STCFG_CLKSEL_Enum;
19357 
19358 /* =========================================================  STTMR  ========================================================= */
19359 /* ====================================================  CAPTURECONTROL  ===================================================== */
19360 /* =========================================  CTIMER CAPTURECONTROL CAPTURE3 [3..3]  ========================================= */
19361 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE3                                            */
19362   CTIMER_CAPTURECONTROL_CAPTURE3_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
19363   CTIMER_CAPTURECONTROL_CAPTURE3_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
19364 } CTIMER_CAPTURECONTROL_CAPTURE3_Enum;
19365 
19366 /* =========================================  CTIMER CAPTURECONTROL CAPTURE2 [2..2]  ========================================= */
19367 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE2                                            */
19368   CTIMER_CAPTURECONTROL_CAPTURE2_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
19369   CTIMER_CAPTURECONTROL_CAPTURE2_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
19370 } CTIMER_CAPTURECONTROL_CAPTURE2_Enum;
19371 
19372 /* =========================================  CTIMER CAPTURECONTROL CAPTURE1 [1..1]  ========================================= */
19373 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE1                                            */
19374   CTIMER_CAPTURECONTROL_CAPTURE1_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
19375   CTIMER_CAPTURECONTROL_CAPTURE1_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
19376 } CTIMER_CAPTURECONTROL_CAPTURE1_Enum;
19377 
19378 /* =========================================  CTIMER CAPTURECONTROL CAPTURE0 [0..0]  ========================================= */
19379 typedef enum {                                  /*!< CTIMER_CAPTURECONTROL_CAPTURE0                                            */
19380   CTIMER_CAPTURECONTROL_CAPTURE0_DISABLE = 0,   /*!< DISABLE : Capture function disabled.                                      */
19381   CTIMER_CAPTURECONTROL_CAPTURE0_ENABLE = 1,    /*!< ENABLE : Capture function enabled.                                        */
19382 } CTIMER_CAPTURECONTROL_CAPTURE0_Enum;
19383 
19384 /* ========================================================  SCMPR0  ========================================================= */
19385 /* ========================================================  SCMPR1  ========================================================= */
19386 /* ========================================================  SCMPR2  ========================================================= */
19387 /* ========================================================  SCMPR3  ========================================================= */
19388 /* ========================================================  SCMPR4  ========================================================= */
19389 /* ========================================================  SCMPR5  ========================================================= */
19390 /* ========================================================  SCMPR6  ========================================================= */
19391 /* ========================================================  SCMPR7  ========================================================= */
19392 /* ========================================================  SCAPT0  ========================================================= */
19393 /* ========================================================  SCAPT1  ========================================================= */
19394 /* ========================================================  SCAPT2  ========================================================= */
19395 /* ========================================================  SCAPT3  ========================================================= */
19396 /* =========================================================  SNVR0  ========================================================= */
19397 /* =========================================================  SNVR1  ========================================================= */
19398 /* =========================================================  SNVR2  ========================================================= */
19399 /* =========================================================  SNVR3  ========================================================= */
19400 /* =========================================================  INTEN  ========================================================= */
19401 /* ========================================================  INTSTAT  ======================================================== */
19402 /* ========================================================  INTCLR  ========================================================= */
19403 /* ========================================================  INTSET  ========================================================= */
19404 /* =======================================================  STMINTEN  ======================================================== */
19405 /* ===========================================  CTIMER STMINTEN CAPTURED [12..12]  =========================================== */
19406 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTURED                                                  */
19407   CTIMER_STMINTEN_CAPTURED_CAPD_INT    = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
19408 } CTIMER_STMINTEN_CAPTURED_Enum;
19409 
19410 /* ===========================================  CTIMER STMINTEN CAPTUREC [11..11]  =========================================== */
19411 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTUREC                                                  */
19412   CTIMER_STMINTEN_CAPTUREC_CAPC_INT    = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
19413 } CTIMER_STMINTEN_CAPTUREC_Enum;
19414 
19415 /* ===========================================  CTIMER STMINTEN CAPTUREB [10..10]  =========================================== */
19416 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTUREB                                                  */
19417   CTIMER_STMINTEN_CAPTUREB_CAPB_INT    = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
19418 } CTIMER_STMINTEN_CAPTUREB_Enum;
19419 
19420 /* ============================================  CTIMER STMINTEN CAPTUREA [9..9]  ============================================ */
19421 typedef enum {                                  /*!< CTIMER_STMINTEN_CAPTUREA                                                  */
19422   CTIMER_STMINTEN_CAPTUREA_CAPA_INT    = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
19423 } CTIMER_STMINTEN_CAPTUREA_Enum;
19424 
19425 /* ============================================  CTIMER STMINTEN OVERFLOW [8..8]  ============================================ */
19426 typedef enum {                                  /*!< CTIMER_STMINTEN_OVERFLOW                                                  */
19427   CTIMER_STMINTEN_OVERFLOW_OFLOW_INT   = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
19428 } CTIMER_STMINTEN_OVERFLOW_Enum;
19429 
19430 /* ============================================  CTIMER STMINTEN COMPAREH [7..7]  ============================================ */
19431 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREH                                                  */
19432   CTIMER_STMINTEN_COMPAREH_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19433 } CTIMER_STMINTEN_COMPAREH_Enum;
19434 
19435 /* ============================================  CTIMER STMINTEN COMPAREG [6..6]  ============================================ */
19436 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREG                                                  */
19437   CTIMER_STMINTEN_COMPAREG_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19438 } CTIMER_STMINTEN_COMPAREG_Enum;
19439 
19440 /* ============================================  CTIMER STMINTEN COMPAREF [5..5]  ============================================ */
19441 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREF                                                  */
19442   CTIMER_STMINTEN_COMPAREF_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19443 } CTIMER_STMINTEN_COMPAREF_Enum;
19444 
19445 /* ============================================  CTIMER STMINTEN COMPAREE [4..4]  ============================================ */
19446 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREE                                                  */
19447   CTIMER_STMINTEN_COMPAREE_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19448 } CTIMER_STMINTEN_COMPAREE_Enum;
19449 
19450 /* ============================================  CTIMER STMINTEN COMPARED [3..3]  ============================================ */
19451 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPARED                                                  */
19452   CTIMER_STMINTEN_COMPARED_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19453 } CTIMER_STMINTEN_COMPARED_Enum;
19454 
19455 /* ============================================  CTIMER STMINTEN COMPAREC [2..2]  ============================================ */
19456 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREC                                                  */
19457   CTIMER_STMINTEN_COMPAREC_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19458 } CTIMER_STMINTEN_COMPAREC_Enum;
19459 
19460 /* ============================================  CTIMER STMINTEN COMPAREB [1..1]  ============================================ */
19461 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREB                                                  */
19462   CTIMER_STMINTEN_COMPAREB_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19463 } CTIMER_STMINTEN_COMPAREB_Enum;
19464 
19465 /* ============================================  CTIMER STMINTEN COMPAREA [0..0]  ============================================ */
19466 typedef enum {                                  /*!< CTIMER_STMINTEN_COMPAREA                                                  */
19467   CTIMER_STMINTEN_COMPAREA_COMPARED    = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19468 } CTIMER_STMINTEN_COMPAREA_Enum;
19469 
19470 /* ======================================================  STMINTSTAT  ======================================================= */
19471 /* ==========================================  CTIMER STMINTSTAT CAPTURED [12..12]  ========================================== */
19472 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTURED                                                */
19473   CTIMER_STMINTSTAT_CAPTURED_CAPD_INT  = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
19474 } CTIMER_STMINTSTAT_CAPTURED_Enum;
19475 
19476 /* ==========================================  CTIMER STMINTSTAT CAPTUREC [11..11]  ========================================== */
19477 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTUREC                                                */
19478   CTIMER_STMINTSTAT_CAPTUREC_CAPC_INT  = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
19479 } CTIMER_STMINTSTAT_CAPTUREC_Enum;
19480 
19481 /* ==========================================  CTIMER STMINTSTAT CAPTUREB [10..10]  ========================================== */
19482 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTUREB                                                */
19483   CTIMER_STMINTSTAT_CAPTUREB_CAPB_INT  = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
19484 } CTIMER_STMINTSTAT_CAPTUREB_Enum;
19485 
19486 /* ===========================================  CTIMER STMINTSTAT CAPTUREA [9..9]  =========================================== */
19487 typedef enum {                                  /*!< CTIMER_STMINTSTAT_CAPTUREA                                                */
19488   CTIMER_STMINTSTAT_CAPTUREA_CAPA_INT  = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
19489 } CTIMER_STMINTSTAT_CAPTUREA_Enum;
19490 
19491 /* ===========================================  CTIMER STMINTSTAT OVERFLOW [8..8]  =========================================== */
19492 typedef enum {                                  /*!< CTIMER_STMINTSTAT_OVERFLOW                                                */
19493   CTIMER_STMINTSTAT_OVERFLOW_OFLOW_INT = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
19494 } CTIMER_STMINTSTAT_OVERFLOW_Enum;
19495 
19496 /* ===========================================  CTIMER STMINTSTAT COMPAREH [7..7]  =========================================== */
19497 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREH                                                */
19498   CTIMER_STMINTSTAT_COMPAREH_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19499 } CTIMER_STMINTSTAT_COMPAREH_Enum;
19500 
19501 /* ===========================================  CTIMER STMINTSTAT COMPAREG [6..6]  =========================================== */
19502 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREG                                                */
19503   CTIMER_STMINTSTAT_COMPAREG_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19504 } CTIMER_STMINTSTAT_COMPAREG_Enum;
19505 
19506 /* ===========================================  CTIMER STMINTSTAT COMPAREF [5..5]  =========================================== */
19507 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREF                                                */
19508   CTIMER_STMINTSTAT_COMPAREF_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19509 } CTIMER_STMINTSTAT_COMPAREF_Enum;
19510 
19511 /* ===========================================  CTIMER STMINTSTAT COMPAREE [4..4]  =========================================== */
19512 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREE                                                */
19513   CTIMER_STMINTSTAT_COMPAREE_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19514 } CTIMER_STMINTSTAT_COMPAREE_Enum;
19515 
19516 /* ===========================================  CTIMER STMINTSTAT COMPARED [3..3]  =========================================== */
19517 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPARED                                                */
19518   CTIMER_STMINTSTAT_COMPARED_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19519 } CTIMER_STMINTSTAT_COMPARED_Enum;
19520 
19521 /* ===========================================  CTIMER STMINTSTAT COMPAREC [2..2]  =========================================== */
19522 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREC                                                */
19523   CTIMER_STMINTSTAT_COMPAREC_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19524 } CTIMER_STMINTSTAT_COMPAREC_Enum;
19525 
19526 /* ===========================================  CTIMER STMINTSTAT COMPAREB [1..1]  =========================================== */
19527 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREB                                                */
19528   CTIMER_STMINTSTAT_COMPAREB_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19529 } CTIMER_STMINTSTAT_COMPAREB_Enum;
19530 
19531 /* ===========================================  CTIMER STMINTSTAT COMPAREA [0..0]  =========================================== */
19532 typedef enum {                                  /*!< CTIMER_STMINTSTAT_COMPAREA                                                */
19533   CTIMER_STMINTSTAT_COMPAREA_COMPARED  = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19534 } CTIMER_STMINTSTAT_COMPAREA_Enum;
19535 
19536 /* =======================================================  STMINTCLR  ======================================================= */
19537 /* ==========================================  CTIMER STMINTCLR CAPTURED [12..12]  =========================================== */
19538 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTURED                                                 */
19539   CTIMER_STMINTCLR_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
19540 } CTIMER_STMINTCLR_CAPTURED_Enum;
19541 
19542 /* ==========================================  CTIMER STMINTCLR CAPTUREC [11..11]  =========================================== */
19543 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTUREC                                                 */
19544   CTIMER_STMINTCLR_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
19545 } CTIMER_STMINTCLR_CAPTUREC_Enum;
19546 
19547 /* ==========================================  CTIMER STMINTCLR CAPTUREB [10..10]  =========================================== */
19548 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTUREB                                                 */
19549   CTIMER_STMINTCLR_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
19550 } CTIMER_STMINTCLR_CAPTUREB_Enum;
19551 
19552 /* ===========================================  CTIMER STMINTCLR CAPTUREA [9..9]  ============================================ */
19553 typedef enum {                                  /*!< CTIMER_STMINTCLR_CAPTUREA                                                 */
19554   CTIMER_STMINTCLR_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
19555 } CTIMER_STMINTCLR_CAPTUREA_Enum;
19556 
19557 /* ===========================================  CTIMER STMINTCLR OVERFLOW [8..8]  ============================================ */
19558 typedef enum {                                  /*!< CTIMER_STMINTCLR_OVERFLOW                                                 */
19559   CTIMER_STMINTCLR_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
19560 } CTIMER_STMINTCLR_OVERFLOW_Enum;
19561 
19562 /* ===========================================  CTIMER STMINTCLR COMPAREH [7..7]  ============================================ */
19563 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREH                                                 */
19564   CTIMER_STMINTCLR_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19565 } CTIMER_STMINTCLR_COMPAREH_Enum;
19566 
19567 /* ===========================================  CTIMER STMINTCLR COMPAREG [6..6]  ============================================ */
19568 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREG                                                 */
19569   CTIMER_STMINTCLR_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19570 } CTIMER_STMINTCLR_COMPAREG_Enum;
19571 
19572 /* ===========================================  CTIMER STMINTCLR COMPAREF [5..5]  ============================================ */
19573 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREF                                                 */
19574   CTIMER_STMINTCLR_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19575 } CTIMER_STMINTCLR_COMPAREF_Enum;
19576 
19577 /* ===========================================  CTIMER STMINTCLR COMPAREE [4..4]  ============================================ */
19578 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREE                                                 */
19579   CTIMER_STMINTCLR_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19580 } CTIMER_STMINTCLR_COMPAREE_Enum;
19581 
19582 /* ===========================================  CTIMER STMINTCLR COMPARED [3..3]  ============================================ */
19583 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPARED                                                 */
19584   CTIMER_STMINTCLR_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19585 } CTIMER_STMINTCLR_COMPARED_Enum;
19586 
19587 /* ===========================================  CTIMER STMINTCLR COMPAREC [2..2]  ============================================ */
19588 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREC                                                 */
19589   CTIMER_STMINTCLR_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19590 } CTIMER_STMINTCLR_COMPAREC_Enum;
19591 
19592 /* ===========================================  CTIMER STMINTCLR COMPAREB [1..1]  ============================================ */
19593 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREB                                                 */
19594   CTIMER_STMINTCLR_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19595 } CTIMER_STMINTCLR_COMPAREB_Enum;
19596 
19597 /* ===========================================  CTIMER STMINTCLR COMPAREA [0..0]  ============================================ */
19598 typedef enum {                                  /*!< CTIMER_STMINTCLR_COMPAREA                                                 */
19599   CTIMER_STMINTCLR_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19600 } CTIMER_STMINTCLR_COMPAREA_Enum;
19601 
19602 /* =======================================================  STMINTSET  ======================================================= */
19603 /* ==========================================  CTIMER STMINTSET CAPTURED [12..12]  =========================================== */
19604 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTURED                                                 */
19605   CTIMER_STMINTSET_CAPTURED_CAPD_INT   = 1,     /*!< CAPD_INT : Capture D interrupt status bit was set.                        */
19606 } CTIMER_STMINTSET_CAPTURED_Enum;
19607 
19608 /* ==========================================  CTIMER STMINTSET CAPTUREC [11..11]  =========================================== */
19609 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTUREC                                                 */
19610   CTIMER_STMINTSET_CAPTUREC_CAPC_INT   = 1,     /*!< CAPC_INT : CAPTURE C interrupt status bit was set.                        */
19611 } CTIMER_STMINTSET_CAPTUREC_Enum;
19612 
19613 /* ==========================================  CTIMER STMINTSET CAPTUREB [10..10]  =========================================== */
19614 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTUREB                                                 */
19615   CTIMER_STMINTSET_CAPTUREB_CAPB_INT   = 1,     /*!< CAPB_INT : CAPTURE B interrupt status bit was set.                        */
19616 } CTIMER_STMINTSET_CAPTUREB_Enum;
19617 
19618 /* ===========================================  CTIMER STMINTSET CAPTUREA [9..9]  ============================================ */
19619 typedef enum {                                  /*!< CTIMER_STMINTSET_CAPTUREA                                                 */
19620   CTIMER_STMINTSET_CAPTUREA_CAPA_INT   = 1,     /*!< CAPA_INT : CAPTURE A interrupt status bit was set.                        */
19621 } CTIMER_STMINTSET_CAPTUREA_Enum;
19622 
19623 /* ===========================================  CTIMER STMINTSET OVERFLOW [8..8]  ============================================ */
19624 typedef enum {                                  /*!< CTIMER_STMINTSET_OVERFLOW                                                 */
19625   CTIMER_STMINTSET_OVERFLOW_OFLOW_INT  = 1,     /*!< OFLOW_INT : Overflow interrupt status bit was set.                        */
19626 } CTIMER_STMINTSET_OVERFLOW_Enum;
19627 
19628 /* ===========================================  CTIMER STMINTSET COMPAREH [7..7]  ============================================ */
19629 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREH                                                 */
19630   CTIMER_STMINTSET_COMPAREH_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19631 } CTIMER_STMINTSET_COMPAREH_Enum;
19632 
19633 /* ===========================================  CTIMER STMINTSET COMPAREG [6..6]  ============================================ */
19634 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREG                                                 */
19635   CTIMER_STMINTSET_COMPAREG_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19636 } CTIMER_STMINTSET_COMPAREG_Enum;
19637 
19638 /* ===========================================  CTIMER STMINTSET COMPAREF [5..5]  ============================================ */
19639 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREF                                                 */
19640   CTIMER_STMINTSET_COMPAREF_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19641 } CTIMER_STMINTSET_COMPAREF_Enum;
19642 
19643 /* ===========================================  CTIMER STMINTSET COMPAREE [4..4]  ============================================ */
19644 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREE                                                 */
19645   CTIMER_STMINTSET_COMPAREE_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19646 } CTIMER_STMINTSET_COMPAREE_Enum;
19647 
19648 /* ===========================================  CTIMER STMINTSET COMPARED [3..3]  ============================================ */
19649 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPARED                                                 */
19650   CTIMER_STMINTSET_COMPARED_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19651 } CTIMER_STMINTSET_COMPARED_Enum;
19652 
19653 /* ===========================================  CTIMER STMINTSET COMPAREC [2..2]  ============================================ */
19654 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREC                                                 */
19655   CTIMER_STMINTSET_COMPAREC_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19656 } CTIMER_STMINTSET_COMPAREC_Enum;
19657 
19658 /* ===========================================  CTIMER STMINTSET COMPAREB [1..1]  ============================================ */
19659 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREB                                                 */
19660   CTIMER_STMINTSET_COMPAREB_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19661 } CTIMER_STMINTSET_COMPAREB_Enum;
19662 
19663 /* ===========================================  CTIMER STMINTSET COMPAREA [0..0]  ============================================ */
19664 typedef enum {                                  /*!< CTIMER_STMINTSET_COMPAREA                                                 */
19665   CTIMER_STMINTSET_COMPAREA_COMPARED   = 1,     /*!< COMPARED : COUNTER greater than or equal to COMPARE register.             */
19666 } CTIMER_STMINTSET_COMPAREA_Enum;
19667 
19668 
19669 
19670 /* =========================================================================================================================== */
19671 /* ================                                           GPIO                                            ================ */
19672 /* =========================================================================================================================== */
19673 
19674 /* ========================================================  PADREGA  ======================================================== */
19675 /* ============================================  GPIO PADREGA PAD3PWRUP [30..30]  ============================================ */
19676 typedef enum {                                  /*!< GPIO_PADREGA_PAD3PWRUP                                                    */
19677   GPIO_PADREGA_PAD3PWRUP_DIS           = 0,     /*!< DIS : Power switch disabled                                               */
19678   GPIO_PADREGA_PAD3PWRUP_EN            = 1,     /*!< EN : Power switch enabled (switched to VDD)                               */
19679 } GPIO_PADREGA_PAD3PWRUP_Enum;
19680 
19681 /* ===========================================  GPIO PADREGA PAD3FNCSEL [27..29]  ============================================ */
19682 typedef enum {                                  /*!< GPIO_PADREGA_PAD3FNCSEL                                                   */
19683   GPIO_PADREGA_PAD3FNCSEL_UA0RTS       = 0,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
19684   GPIO_PADREGA_PAD3FNCSEL_SLnCE        = 1,     /*!< SLnCE : Configure as the IOSLAVE SPI nCE signal                           */
19685   GPIO_PADREGA_PAD3FNCSEL_NCE3         = 2,     /*!< NCE3 : IOM/MSPI nCE group 3                                               */
19686   GPIO_PADREGA_PAD3FNCSEL_GPIO3        = 3,     /*!< GPIO3 : Configure as GPIO3                                                */
19687   GPIO_PADREGA_PAD3FNCSEL_MSPI7        = 5,     /*!< MSPI7 : MSPI data connection 7                                            */
19688   GPIO_PADREGA_PAD3FNCSEL_TRIG1        = 6,     /*!< TRIG1 : Configure as the ADC Trigger 1 signal                             */
19689   GPIO_PADREGA_PAD3FNCSEL_I2S_WCLK     = 7,     /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input                      */
19690 } GPIO_PADREGA_PAD3FNCSEL_Enum;
19691 
19692 /* ============================================  GPIO PADREGA PAD3STRNG [26..26]  ============================================ */
19693 typedef enum {                                  /*!< GPIO_PADREGA_PAD3STRNG                                                    */
19694   GPIO_PADREGA_PAD3STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19695   GPIO_PADREGA_PAD3STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19696 } GPIO_PADREGA_PAD3STRNG_Enum;
19697 
19698 /* ============================================  GPIO PADREGA PAD3INPEN [25..25]  ============================================ */
19699 typedef enum {                                  /*!< GPIO_PADREGA_PAD3INPEN                                                    */
19700   GPIO_PADREGA_PAD3INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19701   GPIO_PADREGA_PAD3INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19702 } GPIO_PADREGA_PAD3INPEN_Enum;
19703 
19704 /* ============================================  GPIO PADREGA PAD3PULL [24..24]  ============================================= */
19705 typedef enum {                                  /*!< GPIO_PADREGA_PAD3PULL                                                     */
19706   GPIO_PADREGA_PAD3PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19707   GPIO_PADREGA_PAD3PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19708 } GPIO_PADREGA_PAD3PULL_Enum;
19709 
19710 /* ===========================================  GPIO PADREGA PAD2FNCSEL [19..21]  ============================================ */
19711 typedef enum {                                  /*!< GPIO_PADREGA_PAD2FNCSEL                                                   */
19712   GPIO_PADREGA_PAD2FNCSEL_UART1RX      = 0,     /*!< UART1RX : Configure as the UART1 RX input.                                */
19713   GPIO_PADREGA_PAD2FNCSEL_SLMISO       = 1,     /*!< SLMISO : Configure as the IOSLAVE SPI MISO signal.                        */
19714   GPIO_PADREGA_PAD2FNCSEL_UART0RX      = 2,     /*!< UART0RX : Configure as the UART0 RX input.                                */
19715   GPIO_PADREGA_PAD2FNCSEL_GPIO2        = 3,     /*!< GPIO2 : Configure as GPIO2.                                               */
19716   GPIO_PADREGA_PAD2FNCSEL_MSPI6        = 5,     /*!< MSPI6 : MSPI data connection 6.                                           */
19717   GPIO_PADREGA_PAD2FNCSEL_NCE2         = 7,     /*!< NCE2 : IOM/MSPI nCE group 2                                               */
19718 } GPIO_PADREGA_PAD2FNCSEL_Enum;
19719 
19720 /* ============================================  GPIO PADREGA PAD2STRNG [18..18]  ============================================ */
19721 typedef enum {                                  /*!< GPIO_PADREGA_PAD2STRNG                                                    */
19722   GPIO_PADREGA_PAD2STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19723   GPIO_PADREGA_PAD2STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19724 } GPIO_PADREGA_PAD2STRNG_Enum;
19725 
19726 /* ============================================  GPIO PADREGA PAD2INPEN [17..17]  ============================================ */
19727 typedef enum {                                  /*!< GPIO_PADREGA_PAD2INPEN                                                    */
19728   GPIO_PADREGA_PAD2INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19729   GPIO_PADREGA_PAD2INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19730 } GPIO_PADREGA_PAD2INPEN_Enum;
19731 
19732 /* ============================================  GPIO PADREGA PAD2PULL [16..16]  ============================================= */
19733 typedef enum {                                  /*!< GPIO_PADREGA_PAD2PULL                                                     */
19734   GPIO_PADREGA_PAD2PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19735   GPIO_PADREGA_PAD2PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19736 } GPIO_PADREGA_PAD2PULL_Enum;
19737 
19738 /* ============================================  GPIO PADREGA PAD1RSEL [14..15]  ============================================= */
19739 typedef enum {                                  /*!< GPIO_PADREGA_PAD1RSEL                                                     */
19740   GPIO_PADREGA_PAD1RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
19741   GPIO_PADREGA_PAD1RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
19742   GPIO_PADREGA_PAD1RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
19743   GPIO_PADREGA_PAD1RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
19744 } GPIO_PADREGA_PAD1RSEL_Enum;
19745 
19746 /* ===========================================  GPIO PADREGA PAD1FNCSEL [11..13]  ============================================ */
19747 typedef enum {                                  /*!< GPIO_PADREGA_PAD1FNCSEL                                                   */
19748   GPIO_PADREGA_PAD1FNCSEL_SLSDAWIR3    = 0,     /*!< SLSDAWIR3 : Configure as the IOSLAVE I2C SDA or SPI WIR3 signal           */
19749   GPIO_PADREGA_PAD1FNCSEL_SLMOSI       = 1,     /*!< SLMOSI : Configure as the IOSLAVE SPI MOSI signal                         */
19750   GPIO_PADREGA_PAD1FNCSEL_UART0TX      = 2,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
19751   GPIO_PADREGA_PAD1FNCSEL_GPIO1        = 3,     /*!< GPIO1 : Configure as GPIO1                                                */
19752   GPIO_PADREGA_PAD1FNCSEL_MSPI5        = 5,     /*!< MSPI5 : MSPI data connection 5                                            */
19753   GPIO_PADREGA_PAD1FNCSEL_NCE1         = 7,     /*!< NCE1 : IOM/MSPI nCE group 1                                               */
19754 } GPIO_PADREGA_PAD1FNCSEL_Enum;
19755 
19756 /* ============================================  GPIO PADREGA PAD1STRNG [10..10]  ============================================ */
19757 typedef enum {                                  /*!< GPIO_PADREGA_PAD1STRNG                                                    */
19758   GPIO_PADREGA_PAD1STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19759   GPIO_PADREGA_PAD1STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19760 } GPIO_PADREGA_PAD1STRNG_Enum;
19761 
19762 /* =============================================  GPIO PADREGA PAD1INPEN [9..9]  ============================================= */
19763 typedef enum {                                  /*!< GPIO_PADREGA_PAD1INPEN                                                    */
19764   GPIO_PADREGA_PAD1INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19765   GPIO_PADREGA_PAD1INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19766 } GPIO_PADREGA_PAD1INPEN_Enum;
19767 
19768 /* =============================================  GPIO PADREGA PAD1PULL [8..8]  ============================================== */
19769 typedef enum {                                  /*!< GPIO_PADREGA_PAD1PULL                                                     */
19770   GPIO_PADREGA_PAD1PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19771   GPIO_PADREGA_PAD1PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19772 } GPIO_PADREGA_PAD1PULL_Enum;
19773 
19774 /* =============================================  GPIO PADREGA PAD0RSEL [6..7]  ============================================== */
19775 typedef enum {                                  /*!< GPIO_PADREGA_PAD0RSEL                                                     */
19776   GPIO_PADREGA_PAD0RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
19777   GPIO_PADREGA_PAD0RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
19778   GPIO_PADREGA_PAD0RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
19779   GPIO_PADREGA_PAD0RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
19780 } GPIO_PADREGA_PAD0RSEL_Enum;
19781 
19782 /* ============================================  GPIO PADREGA PAD0FNCSEL [3..5]  ============================================= */
19783 typedef enum {                                  /*!< GPIO_PADREGA_PAD0FNCSEL                                                   */
19784   GPIO_PADREGA_PAD0FNCSEL_SLSCL        = 0,     /*!< SLSCL : Configure as the IOSLAVE I2C SCL signal                           */
19785   GPIO_PADREGA_PAD0FNCSEL_SLSCK        = 1,     /*!< SLSCK : Configure as the IOSLAVE SPI SCK signal                           */
19786   GPIO_PADREGA_PAD0FNCSEL_CLKOUT       = 2,     /*!< CLKOUT : Configure as the CLKOUT signal                                   */
19787   GPIO_PADREGA_PAD0FNCSEL_GPIO0        = 3,     /*!< GPIO0 : Configure as GPIO0                                                */
19788   GPIO_PADREGA_PAD0FNCSEL_MSPI4        = 5,     /*!< MSPI4 : MSPI data connection 4                                            */
19789   GPIO_PADREGA_PAD0FNCSEL_NCE0         = 7,     /*!< NCE0 : IOM/MSPI nCE group 0                                               */
19790 } GPIO_PADREGA_PAD0FNCSEL_Enum;
19791 
19792 /* =============================================  GPIO PADREGA PAD0STRNG [2..2]  ============================================= */
19793 typedef enum {                                  /*!< GPIO_PADREGA_PAD0STRNG                                                    */
19794   GPIO_PADREGA_PAD0STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19795   GPIO_PADREGA_PAD0STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19796 } GPIO_PADREGA_PAD0STRNG_Enum;
19797 
19798 /* =============================================  GPIO PADREGA PAD0INPEN [1..1]  ============================================= */
19799 typedef enum {                                  /*!< GPIO_PADREGA_PAD0INPEN                                                    */
19800   GPIO_PADREGA_PAD0INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19801   GPIO_PADREGA_PAD0INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19802 } GPIO_PADREGA_PAD0INPEN_Enum;
19803 
19804 /* =============================================  GPIO PADREGA PAD0PULL [0..0]  ============================================== */
19805 typedef enum {                                  /*!< GPIO_PADREGA_PAD0PULL                                                     */
19806   GPIO_PADREGA_PAD0PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19807   GPIO_PADREGA_PAD0PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19808 } GPIO_PADREGA_PAD0PULL_Enum;
19809 
19810 /* ========================================================  PADREGB  ======================================================== */
19811 /* ===========================================  GPIO PADREGB PAD7FNCSEL [27..29]  ============================================ */
19812 typedef enum {                                  /*!< GPIO_PADREGB_PAD7FNCSEL                                                   */
19813   GPIO_PADREGB_PAD7FNCSEL_NCE7         = 0,     /*!< NCE7 : IOM/MSPI nCE group 7                                               */
19814   GPIO_PADREGB_PAD7FNCSEL_M0MOSI       = 1,     /*!< M0MOSI : Configure as the IOMSTR0 SPI MOSI signal                         */
19815   GPIO_PADREGB_PAD7FNCSEL_CLKOUT       = 2,     /*!< CLKOUT : Configure as the CLKOUT signal                                   */
19816   GPIO_PADREGB_PAD7FNCSEL_GPIO7        = 3,     /*!< GPIO7 : Configure as GPIO7                                                */
19817   GPIO_PADREGB_PAD7FNCSEL_TRIG0        = 4,     /*!< TRIG0 : Configure as the ADC Trigger 0 signal                             */
19818   GPIO_PADREGB_PAD7FNCSEL_UART0TX      = 5,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
19819   GPIO_PADREGB_PAD7FNCSEL_CT19         = 7,     /*!< CT19 : CTIMER connection 19                                               */
19820 } GPIO_PADREGB_PAD7FNCSEL_Enum;
19821 
19822 /* ============================================  GPIO PADREGB PAD7STRNG [26..26]  ============================================ */
19823 typedef enum {                                  /*!< GPIO_PADREGB_PAD7STRNG                                                    */
19824   GPIO_PADREGB_PAD7STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19825   GPIO_PADREGB_PAD7STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19826 } GPIO_PADREGB_PAD7STRNG_Enum;
19827 
19828 /* ============================================  GPIO PADREGB PAD7INPEN [25..25]  ============================================ */
19829 typedef enum {                                  /*!< GPIO_PADREGB_PAD7INPEN                                                    */
19830   GPIO_PADREGB_PAD7INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19831   GPIO_PADREGB_PAD7INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19832 } GPIO_PADREGB_PAD7INPEN_Enum;
19833 
19834 /* ============================================  GPIO PADREGB PAD7PULL [24..24]  ============================================= */
19835 typedef enum {                                  /*!< GPIO_PADREGB_PAD7PULL                                                     */
19836   GPIO_PADREGB_PAD7PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19837   GPIO_PADREGB_PAD7PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19838 } GPIO_PADREGB_PAD7PULL_Enum;
19839 
19840 /* ============================================  GPIO PADREGB PAD6RSEL [22..23]  ============================================= */
19841 typedef enum {                                  /*!< GPIO_PADREGB_PAD6RSEL                                                     */
19842   GPIO_PADREGB_PAD6RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
19843   GPIO_PADREGB_PAD6RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
19844   GPIO_PADREGB_PAD6RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
19845   GPIO_PADREGB_PAD6RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
19846 } GPIO_PADREGB_PAD6RSEL_Enum;
19847 
19848 /* ===========================================  GPIO PADREGB PAD6FNCSEL [19..21]  ============================================ */
19849 typedef enum {                                  /*!< GPIO_PADREGB_PAD6FNCSEL                                                   */
19850   GPIO_PADREGB_PAD6FNCSEL_M0SDAWIR3    = 0,     /*!< M0SDAWIR3 : Configure as the IOMSTR0 I2C SDA or SPI WIR3 signal           */
19851   GPIO_PADREGB_PAD6FNCSEL_M0MISO       = 1,     /*!< M0MISO : Configure as the IOMSTR0 SPI MISO signal                         */
19852   GPIO_PADREGB_PAD6FNCSEL_UA0CTS       = 2,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
19853   GPIO_PADREGB_PAD6FNCSEL_GPIO6        = 3,     /*!< GPIO6 : Configure as GPIO6                                                */
19854   GPIO_PADREGB_PAD6FNCSEL_CT10         = 5,     /*!< CT10 : CTIMER connection 10                                               */
19855   GPIO_PADREGB_PAD6FNCSEL_I2S_DAT      = 7,     /*!< I2S_DAT : Configure as the PDM I2S Data output signal                     */
19856 } GPIO_PADREGB_PAD6FNCSEL_Enum;
19857 
19858 /* ============================================  GPIO PADREGB PAD6STRNG [18..18]  ============================================ */
19859 typedef enum {                                  /*!< GPIO_PADREGB_PAD6STRNG                                                    */
19860   GPIO_PADREGB_PAD6STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19861   GPIO_PADREGB_PAD6STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19862 } GPIO_PADREGB_PAD6STRNG_Enum;
19863 
19864 /* ============================================  GPIO PADREGB PAD6INPEN [17..17]  ============================================ */
19865 typedef enum {                                  /*!< GPIO_PADREGB_PAD6INPEN                                                    */
19866   GPIO_PADREGB_PAD6INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19867   GPIO_PADREGB_PAD6INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19868 } GPIO_PADREGB_PAD6INPEN_Enum;
19869 
19870 /* ============================================  GPIO PADREGB PAD6PULL [16..16]  ============================================= */
19871 typedef enum {                                  /*!< GPIO_PADREGB_PAD6PULL                                                     */
19872   GPIO_PADREGB_PAD6PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19873   GPIO_PADREGB_PAD6PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19874 } GPIO_PADREGB_PAD6PULL_Enum;
19875 
19876 /* ============================================  GPIO PADREGB PAD5RSEL [14..15]  ============================================= */
19877 typedef enum {                                  /*!< GPIO_PADREGB_PAD5RSEL                                                     */
19878   GPIO_PADREGB_PAD5RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
19879   GPIO_PADREGB_PAD5RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
19880   GPIO_PADREGB_PAD5RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
19881   GPIO_PADREGB_PAD5RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
19882 } GPIO_PADREGB_PAD5RSEL_Enum;
19883 
19884 /* ===========================================  GPIO PADREGB PAD5FNCSEL [11..13]  ============================================ */
19885 typedef enum {                                  /*!< GPIO_PADREGB_PAD5FNCSEL                                                   */
19886   GPIO_PADREGB_PAD5FNCSEL_M0SCL        = 0,     /*!< M0SCL : Configure as the IOMSTR0 I2C SCL signal                           */
19887   GPIO_PADREGB_PAD5FNCSEL_M0SCK        = 1,     /*!< M0SCK : Configure as the IOMSTR0 SPI SCK signal                           */
19888   GPIO_PADREGB_PAD5FNCSEL_UA0RTS       = 2,     /*!< UA0RTS : Configure as the UART0 RTS signal output                         */
19889   GPIO_PADREGB_PAD5FNCSEL_GPIO5        = 3,     /*!< GPIO5 : Configure as GPIO5                                                */
19890   GPIO_PADREGB_PAD5FNCSEL_EXTHFA       = 5,     /*!< EXTHFA : Configure as the External HFA input clock                        */
19891   GPIO_PADREGB_PAD5FNCSEL_CT8          = 7,     /*!< CT8 : CTIMER connection 8                                                 */
19892 } GPIO_PADREGB_PAD5FNCSEL_Enum;
19893 
19894 /* ============================================  GPIO PADREGB PAD5STRNG [10..10]  ============================================ */
19895 typedef enum {                                  /*!< GPIO_PADREGB_PAD5STRNG                                                    */
19896   GPIO_PADREGB_PAD5STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19897   GPIO_PADREGB_PAD5STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19898 } GPIO_PADREGB_PAD5STRNG_Enum;
19899 
19900 /* =============================================  GPIO PADREGB PAD5INPEN [9..9]  ============================================= */
19901 typedef enum {                                  /*!< GPIO_PADREGB_PAD5INPEN                                                    */
19902   GPIO_PADREGB_PAD5INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19903   GPIO_PADREGB_PAD5INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19904 } GPIO_PADREGB_PAD5INPEN_Enum;
19905 
19906 /* =============================================  GPIO PADREGB PAD5PULL [8..8]  ============================================== */
19907 typedef enum {                                  /*!< GPIO_PADREGB_PAD5PULL                                                     */
19908   GPIO_PADREGB_PAD5PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19909   GPIO_PADREGB_PAD5PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19910 } GPIO_PADREGB_PAD5PULL_Enum;
19911 
19912 /* ============================================  GPIO PADREGB PAD4FNCSEL [3..5]  ============================================= */
19913 typedef enum {                                  /*!< GPIO_PADREGB_PAD4FNCSEL                                                   */
19914   GPIO_PADREGB_PAD4FNCSEL_UA0CTS       = 0,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
19915   GPIO_PADREGB_PAD4FNCSEL_SLINT        = 1,     /*!< SLINT : Configure as the IOSLAVE interrupt out signal                     */
19916   GPIO_PADREGB_PAD4FNCSEL_NCE4         = 2,     /*!< NCE4 : IOM/SPI nCE group 4                                                */
19917   GPIO_PADREGB_PAD4FNCSEL_GPIO4        = 3,     /*!< GPIO4 : Configure as GPIO4                                                */
19918   GPIO_PADREGB_PAD4FNCSEL_UART1RX      = 5,     /*!< UART1RX : Configure as the UART1 RX input                                 */
19919   GPIO_PADREGB_PAD4FNCSEL_CT17         = 6,     /*!< CT17 : CTIMER connection 17                                               */
19920   GPIO_PADREGB_PAD4FNCSEL_MSPI2        = 7,     /*!< MSPI2 : MSPI data connection 2                                            */
19921 } GPIO_PADREGB_PAD4FNCSEL_Enum;
19922 
19923 /* =============================================  GPIO PADREGB PAD4STRNG [2..2]  ============================================= */
19924 typedef enum {                                  /*!< GPIO_PADREGB_PAD4STRNG                                                    */
19925   GPIO_PADREGB_PAD4STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
19926   GPIO_PADREGB_PAD4STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
19927 } GPIO_PADREGB_PAD4STRNG_Enum;
19928 
19929 /* =============================================  GPIO PADREGB PAD4INPEN [1..1]  ============================================= */
19930 typedef enum {                                  /*!< GPIO_PADREGB_PAD4INPEN                                                    */
19931   GPIO_PADREGB_PAD4INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
19932   GPIO_PADREGB_PAD4INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
19933 } GPIO_PADREGB_PAD4INPEN_Enum;
19934 
19935 /* =============================================  GPIO PADREGB PAD4PULL [0..0]  ============================================== */
19936 typedef enum {                                  /*!< GPIO_PADREGB_PAD4PULL                                                     */
19937   GPIO_PADREGB_PAD4PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
19938   GPIO_PADREGB_PAD4PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
19939 } GPIO_PADREGB_PAD4PULL_Enum;
19940 
19941 /* ========================================================  PADREGC  ======================================================== */
19942 /* ===========================================  GPIO PADREGC PAD11FNCSEL [27..29]  =========================================== */
19943 typedef enum {                                  /*!< GPIO_PADREGC_PAD11FNCSEL                                                  */
19944   GPIO_PADREGC_PAD11FNCSEL_ADCSE2      = 0,     /*!< ADCSE2 : Configure as the analog input for ADC single ended
19945                                                      input 2                                                                   */
19946   GPIO_PADREGC_PAD11FNCSEL_NCE11       = 1,     /*!< NCE11 : IOM/MSPI nCE group 11                                             */
19947   GPIO_PADREGC_PAD11FNCSEL_CT31        = 2,     /*!< CT31 : CTIMER connection 31                                               */
19948   GPIO_PADREGC_PAD11FNCSEL_GPIO11      = 3,     /*!< GPIO11 : Configure as GPIO11                                              */
19949   GPIO_PADREGC_PAD11FNCSEL_SLINT       = 4,     /*!< SLINT : Configure as the IOSLAVE interrupt out signal                     */
19950   GPIO_PADREGC_PAD11FNCSEL_UA1CTS      = 5,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
19951   GPIO_PADREGC_PAD11FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
19952   GPIO_PADREGC_PAD11FNCSEL_PDM_DATA    = 7,     /*!< PDM_DATA : Configure as the PDM Data input signal                         */
19953 } GPIO_PADREGC_PAD11FNCSEL_Enum;
19954 
19955 /* ===========================================  GPIO PADREGC PAD11STRNG [26..26]  ============================================ */
19956 typedef enum {                                  /*!< GPIO_PADREGC_PAD11STRNG                                                   */
19957   GPIO_PADREGC_PAD11STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
19958   GPIO_PADREGC_PAD11STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
19959 } GPIO_PADREGC_PAD11STRNG_Enum;
19960 
19961 /* ===========================================  GPIO PADREGC PAD11INPEN [25..25]  ============================================ */
19962 typedef enum {                                  /*!< GPIO_PADREGC_PAD11INPEN                                                   */
19963   GPIO_PADREGC_PAD11INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
19964   GPIO_PADREGC_PAD11INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
19965 } GPIO_PADREGC_PAD11INPEN_Enum;
19966 
19967 /* ============================================  GPIO PADREGC PAD11PULL [24..24]  ============================================ */
19968 typedef enum {                                  /*!< GPIO_PADREGC_PAD11PULL                                                    */
19969   GPIO_PADREGC_PAD11PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
19970   GPIO_PADREGC_PAD11PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
19971 } GPIO_PADREGC_PAD11PULL_Enum;
19972 
19973 /* ===========================================  GPIO PADREGC PAD10FNCSEL [19..21]  =========================================== */
19974 typedef enum {                                  /*!< GPIO_PADREGC_PAD10FNCSEL                                                  */
19975   GPIO_PADREGC_PAD10FNCSEL_UART1TX     = 0,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
19976   GPIO_PADREGC_PAD10FNCSEL_M1MOSI      = 1,     /*!< M1MOSI : Configure as the IOMSTR1 SPI MOSI signal                         */
19977   GPIO_PADREGC_PAD10FNCSEL_NCE10       = 2,     /*!< NCE10 : IOM/MSPI nCE group 10                                             */
19978   GPIO_PADREGC_PAD10FNCSEL_GPIO10      = 3,     /*!< GPIO10 : Configure as GPIO10                                              */
19979   GPIO_PADREGC_PAD10FNCSEL_PDMCLK      = 4,     /*!< PDMCLK : PDM serial clock out                                             */
19980   GPIO_PADREGC_PAD10FNCSEL_UA1RTS      = 5,     /*!< UA1RTS : Configure as the UART1 RTS output signal                         */
19981 } GPIO_PADREGC_PAD10FNCSEL_Enum;
19982 
19983 /* ===========================================  GPIO PADREGC PAD10STRNG [18..18]  ============================================ */
19984 typedef enum {                                  /*!< GPIO_PADREGC_PAD10STRNG                                                   */
19985   GPIO_PADREGC_PAD10STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
19986   GPIO_PADREGC_PAD10STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
19987 } GPIO_PADREGC_PAD10STRNG_Enum;
19988 
19989 /* ===========================================  GPIO PADREGC PAD10INPEN [17..17]  ============================================ */
19990 typedef enum {                                  /*!< GPIO_PADREGC_PAD10INPEN                                                   */
19991   GPIO_PADREGC_PAD10INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
19992   GPIO_PADREGC_PAD10INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
19993 } GPIO_PADREGC_PAD10INPEN_Enum;
19994 
19995 /* ============================================  GPIO PADREGC PAD10PULL [16..16]  ============================================ */
19996 typedef enum {                                  /*!< GPIO_PADREGC_PAD10PULL                                                    */
19997   GPIO_PADREGC_PAD10PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
19998   GPIO_PADREGC_PAD10PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
19999 } GPIO_PADREGC_PAD10PULL_Enum;
20000 
20001 /* ============================================  GPIO PADREGC PAD9RSEL [14..15]  ============================================= */
20002 typedef enum {                                  /*!< GPIO_PADREGC_PAD9RSEL                                                     */
20003   GPIO_PADREGC_PAD9RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20004   GPIO_PADREGC_PAD9RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20005   GPIO_PADREGC_PAD9RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20006   GPIO_PADREGC_PAD9RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20007 } GPIO_PADREGC_PAD9RSEL_Enum;
20008 
20009 /* ===========================================  GPIO PADREGC PAD9FNCSEL [11..13]  ============================================ */
20010 typedef enum {                                  /*!< GPIO_PADREGC_PAD9FNCSEL                                                   */
20011   GPIO_PADREGC_PAD9FNCSEL_M1SDAWIR3    = 0,     /*!< M1SDAWIR3 : Configure as the IOMSTR1 I2C SDA or SPI WIR3 signal           */
20012   GPIO_PADREGC_PAD9FNCSEL_M1MISO       = 1,     /*!< M1MISO : Configure as the IOMSTR1 SPI MISO signal                         */
20013   GPIO_PADREGC_PAD9FNCSEL_NCE9         = 2,     /*!< NCE9 : IOM/MSPI nCE group 9                                               */
20014   GPIO_PADREGC_PAD9FNCSEL_GPIO9        = 3,     /*!< GPIO9 : Configure as GPIO9                                                */
20015   GPIO_PADREGC_PAD9FNCSEL_SCCIO        = 4,     /*!< SCCIO : SCARD data I/O connection                                         */
20016   GPIO_PADREGC_PAD9FNCSEL_UART1RX      = 6,     /*!< UART1RX : Configure as UART1 RX input signal                              */
20017 } GPIO_PADREGC_PAD9FNCSEL_Enum;
20018 
20019 /* ============================================  GPIO PADREGC PAD9STRNG [10..10]  ============================================ */
20020 typedef enum {                                  /*!< GPIO_PADREGC_PAD9STRNG                                                    */
20021   GPIO_PADREGC_PAD9STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
20022   GPIO_PADREGC_PAD9STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
20023 } GPIO_PADREGC_PAD9STRNG_Enum;
20024 
20025 /* =============================================  GPIO PADREGC PAD9INPEN [9..9]  ============================================= */
20026 typedef enum {                                  /*!< GPIO_PADREGC_PAD9INPEN                                                    */
20027   GPIO_PADREGC_PAD9INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
20028   GPIO_PADREGC_PAD9INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
20029 } GPIO_PADREGC_PAD9INPEN_Enum;
20030 
20031 /* =============================================  GPIO PADREGC PAD9PULL [8..8]  ============================================== */
20032 typedef enum {                                  /*!< GPIO_PADREGC_PAD9PULL                                                     */
20033   GPIO_PADREGC_PAD9PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
20034   GPIO_PADREGC_PAD9PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
20035 } GPIO_PADREGC_PAD9PULL_Enum;
20036 
20037 /* =============================================  GPIO PADREGC PAD8RSEL [6..7]  ============================================== */
20038 typedef enum {                                  /*!< GPIO_PADREGC_PAD8RSEL                                                     */
20039   GPIO_PADREGC_PAD8RSEL_PULL1_5K       = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20040   GPIO_PADREGC_PAD8RSEL_PULL6K         = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20041   GPIO_PADREGC_PAD8RSEL_PULL12K        = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20042   GPIO_PADREGC_PAD8RSEL_PULL24K        = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20043 } GPIO_PADREGC_PAD8RSEL_Enum;
20044 
20045 /* ============================================  GPIO PADREGC PAD8FNCSEL [3..5]  ============================================= */
20046 typedef enum {                                  /*!< GPIO_PADREGC_PAD8FNCSEL                                                   */
20047   GPIO_PADREGC_PAD8FNCSEL_M1SCL        = 0,     /*!< M1SCL : Configure as the IOMSTR1 I2C SCL signal                           */
20048   GPIO_PADREGC_PAD8FNCSEL_M1SCK        = 1,     /*!< M1SCK : Configure as the IOMSTR1 SPI SCK signal                           */
20049   GPIO_PADREGC_PAD8FNCSEL_NCE8         = 2,     /*!< NCE8 : IOM/MSPI nCE group 8                                               */
20050   GPIO_PADREGC_PAD8FNCSEL_GPIO8        = 3,     /*!< GPIO8 : Configure as GPIO8                                                */
20051   GPIO_PADREGC_PAD8FNCSEL_SCCLK        = 4,     /*!< SCCLK : SCARD serial clock output                                         */
20052   GPIO_PADREGC_PAD8FNCSEL_UART1TX      = 6,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
20053 } GPIO_PADREGC_PAD8FNCSEL_Enum;
20054 
20055 /* =============================================  GPIO PADREGC PAD8STRNG [2..2]  ============================================= */
20056 typedef enum {                                  /*!< GPIO_PADREGC_PAD8STRNG                                                    */
20057   GPIO_PADREGC_PAD8STRNG_LOW           = 0,     /*!< LOW : Low drive strength                                                  */
20058   GPIO_PADREGC_PAD8STRNG_HIGH          = 1,     /*!< HIGH : High drive strength                                                */
20059 } GPIO_PADREGC_PAD8STRNG_Enum;
20060 
20061 /* =============================================  GPIO PADREGC PAD8INPEN [1..1]  ============================================= */
20062 typedef enum {                                  /*!< GPIO_PADREGC_PAD8INPEN                                                    */
20063   GPIO_PADREGC_PAD8INPEN_DIS           = 0,     /*!< DIS : Pad input disabled                                                  */
20064   GPIO_PADREGC_PAD8INPEN_EN            = 1,     /*!< EN : Pad input enabled                                                    */
20065 } GPIO_PADREGC_PAD8INPEN_Enum;
20066 
20067 /* =============================================  GPIO PADREGC PAD8PULL [0..0]  ============================================== */
20068 typedef enum {                                  /*!< GPIO_PADREGC_PAD8PULL                                                     */
20069   GPIO_PADREGC_PAD8PULL_DIS            = 0,     /*!< DIS : Pullup disabled                                                     */
20070   GPIO_PADREGC_PAD8PULL_EN             = 1,     /*!< EN : Pullup enabled                                                       */
20071 } GPIO_PADREGC_PAD8PULL_Enum;
20072 
20073 /* ========================================================  PADREGD  ======================================================== */
20074 /* ===========================================  GPIO PADREGD PAD15FNCSEL [27..29]  =========================================== */
20075 typedef enum {                                  /*!< GPIO_PADREGD_PAD15FNCSEL                                                  */
20076   GPIO_PADREGD_PAD15FNCSEL_ADCD1N      = 0,     /*!< ADCD1N : Configure as the analog ADC differential pair 1 N input
20077                                                      signal                                                                    */
20078   GPIO_PADREGD_PAD15FNCSEL_NCE15       = 1,     /*!< NCE15 : IOM/MSPI nCE group 15                                             */
20079   GPIO_PADREGD_PAD15FNCSEL_UART1RX     = 2,     /*!< UART1RX : Configure as the UART1 RX signal                                */
20080   GPIO_PADREGD_PAD15FNCSEL_GPIO15      = 3,     /*!< GPIO15 : Configure as GPIO15                                              */
20081   GPIO_PADREGD_PAD15FNCSEL_PDMDATA     = 4,     /*!< PDMDATA : PDM serial data input                                           */
20082   GPIO_PADREGD_PAD15FNCSEL_EXTXT       = 5,     /*!< EXTXT : Configure as the external XTAL oscillator input                   */
20083   GPIO_PADREGD_PAD15FNCSEL_SWDIO       = 6,     /*!< SWDIO : Configure as an alternate port for the SWDIO I/O signal           */
20084   GPIO_PADREGD_PAD15FNCSEL_SWO         = 7,     /*!< SWO : Configure as an SWO (Serial Wire Trace output)                      */
20085 } GPIO_PADREGD_PAD15FNCSEL_Enum;
20086 
20087 /* ===========================================  GPIO PADREGD PAD15STRNG [26..26]  ============================================ */
20088 typedef enum {                                  /*!< GPIO_PADREGD_PAD15STRNG                                                   */
20089   GPIO_PADREGD_PAD15STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20090   GPIO_PADREGD_PAD15STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20091 } GPIO_PADREGD_PAD15STRNG_Enum;
20092 
20093 /* ===========================================  GPIO PADREGD PAD15INPEN [25..25]  ============================================ */
20094 typedef enum {                                  /*!< GPIO_PADREGD_PAD15INPEN                                                   */
20095   GPIO_PADREGD_PAD15INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20096   GPIO_PADREGD_PAD15INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20097 } GPIO_PADREGD_PAD15INPEN_Enum;
20098 
20099 /* ============================================  GPIO PADREGD PAD15PULL [24..24]  ============================================ */
20100 typedef enum {                                  /*!< GPIO_PADREGD_PAD15PULL                                                    */
20101   GPIO_PADREGD_PAD15PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20102   GPIO_PADREGD_PAD15PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20103 } GPIO_PADREGD_PAD15PULL_Enum;
20104 
20105 /* ===========================================  GPIO PADREGD PAD14FNCSEL [19..21]  =========================================== */
20106 typedef enum {                                  /*!< GPIO_PADREGD_PAD14FNCSEL                                                  */
20107   GPIO_PADREGD_PAD14FNCSEL_ADCD1P      = 0,     /*!< ADCD1P : Configure as the analog ADC differential pair 1 P input
20108                                                      signal                                                                    */
20109   GPIO_PADREGD_PAD14FNCSEL_NCE14       = 1,     /*!< NCE14 : IOM/MSPI nCE group 14                                             */
20110   GPIO_PADREGD_PAD14FNCSEL_UART1TX     = 2,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
20111   GPIO_PADREGD_PAD14FNCSEL_GPIO14      = 3,     /*!< GPIO14 : Configure as GPIO14                                              */
20112   GPIO_PADREGD_PAD14FNCSEL_PDMCLK      = 4,     /*!< PDMCLK : PDM serial clock output                                          */
20113   GPIO_PADREGD_PAD14FNCSEL_EXTHFS      = 5,     /*!< EXTHFS : Configure as the External HFRC oscillator input select           */
20114   GPIO_PADREGD_PAD14FNCSEL_SWDCK       = 6,     /*!< SWDCK : Configure as the alternate input for the SWDCK input
20115                                                      signal                                                                    */
20116   GPIO_PADREGD_PAD14FNCSEL_32kHzXT     = 7,     /*!< 32kHzXT : Configure as the 32kHz crystal output signal                    */
20117 } GPIO_PADREGD_PAD14FNCSEL_Enum;
20118 
20119 /* ===========================================  GPIO PADREGD PAD14STRNG [18..18]  ============================================ */
20120 typedef enum {                                  /*!< GPIO_PADREGD_PAD14STRNG                                                   */
20121   GPIO_PADREGD_PAD14STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20122   GPIO_PADREGD_PAD14STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20123 } GPIO_PADREGD_PAD14STRNG_Enum;
20124 
20125 /* ===========================================  GPIO PADREGD PAD14INPEN [17..17]  ============================================ */
20126 typedef enum {                                  /*!< GPIO_PADREGD_PAD14INPEN                                                   */
20127   GPIO_PADREGD_PAD14INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20128   GPIO_PADREGD_PAD14INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20129 } GPIO_PADREGD_PAD14INPEN_Enum;
20130 
20131 /* ============================================  GPIO PADREGD PAD14PULL [16..16]  ============================================ */
20132 typedef enum {                                  /*!< GPIO_PADREGD_PAD14PULL                                                    */
20133   GPIO_PADREGD_PAD14PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20134   GPIO_PADREGD_PAD14PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20135 } GPIO_PADREGD_PAD14PULL_Enum;
20136 
20137 /* ===========================================  GPIO PADREGD PAD13FNCSEL [11..13]  =========================================== */
20138 typedef enum {                                  /*!< GPIO_PADREGD_PAD13FNCSEL                                                  */
20139   GPIO_PADREGD_PAD13FNCSEL_ADCD0PSE8   = 0,     /*!< ADCD0PSE8 : Configure as the ADC Differential pair 0 P, or Single
20140                                                      Ended input 8 analog input signal. Determination of the
20141                                                      D0P vs SE8 usage is done when the particular channel is
20142                                                      selected within the ADC module                                            */
20143   GPIO_PADREGD_PAD13FNCSEL_NCE13       = 1,     /*!< NCE13 : IOM/MSPI nCE group 13                                             */
20144   GPIO_PADREGD_PAD13FNCSEL_CT2         = 2,     /*!< CT2 : CTIMER connection 2                                                 */
20145   GPIO_PADREGD_PAD13FNCSEL_GPIO13      = 3,     /*!< GPIO13 : Configure as GPIO13                                              */
20146   GPIO_PADREGD_PAD13FNCSEL_I2SBCLK     = 4,     /*!< I2SBCLK : I2C interface bit clock                                         */
20147   GPIO_PADREGD_PAD13FNCSEL_EXTHFB      = 5,     /*!< EXTHFB : Configure as the external HFRC oscillator input                  */
20148   GPIO_PADREGD_PAD13FNCSEL_UA0RTS      = 6,     /*!< UA0RTS : Configure as the UART0 RTS signal output                         */
20149   GPIO_PADREGD_PAD13FNCSEL_UART1RX     = 7,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
20150 } GPIO_PADREGD_PAD13FNCSEL_Enum;
20151 
20152 /* ===========================================  GPIO PADREGD PAD13STRNG [10..10]  ============================================ */
20153 typedef enum {                                  /*!< GPIO_PADREGD_PAD13STRNG                                                   */
20154   GPIO_PADREGD_PAD13STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20155   GPIO_PADREGD_PAD13STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20156 } GPIO_PADREGD_PAD13STRNG_Enum;
20157 
20158 /* ============================================  GPIO PADREGD PAD13INPEN [9..9]  ============================================= */
20159 typedef enum {                                  /*!< GPIO_PADREGD_PAD13INPEN                                                   */
20160   GPIO_PADREGD_PAD13INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20161   GPIO_PADREGD_PAD13INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20162 } GPIO_PADREGD_PAD13INPEN_Enum;
20163 
20164 /* =============================================  GPIO PADREGD PAD13PULL [8..8]  ============================================= */
20165 typedef enum {                                  /*!< GPIO_PADREGD_PAD13PULL                                                    */
20166   GPIO_PADREGD_PAD13PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20167   GPIO_PADREGD_PAD13PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20168 } GPIO_PADREGD_PAD13PULL_Enum;
20169 
20170 /* ============================================  GPIO PADREGD PAD12FNCSEL [3..5]  ============================================ */
20171 typedef enum {                                  /*!< GPIO_PADREGD_PAD12FNCSEL                                                  */
20172   GPIO_PADREGD_PAD12FNCSEL_ADCD0NSE9   = 0,     /*!< ADCD0NSE9 : Configure as the ADC Differential pair 0 N, or Single
20173                                                      Ended input 9 analog input signal. Determination of the
20174                                                      D0N vs SE9 usage is done when the particular channel is
20175                                                      selected within the ADC module                                            */
20176   GPIO_PADREGD_PAD12FNCSEL_NCE12       = 1,     /*!< NCE12 : IOM/MSPI nCE group 12                                             */
20177   GPIO_PADREGD_PAD12FNCSEL_CT0         = 2,     /*!< CT0 : CTIMER connection 0                                                 */
20178   GPIO_PADREGD_PAD12FNCSEL_GPIO12      = 3,     /*!< GPIO12 : Configure as GPIO12                                              */
20179   GPIO_PADREGD_PAD12FNCSEL_PDMCLK      = 5,     /*!< PDMCLK : PDM serial clock output                                          */
20180   GPIO_PADREGD_PAD12FNCSEL_UA0CTS      = 6,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
20181   GPIO_PADREGD_PAD12FNCSEL_UART1TX     = 7,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
20182 } GPIO_PADREGD_PAD12FNCSEL_Enum;
20183 
20184 /* ============================================  GPIO PADREGD PAD12STRNG [2..2]  ============================================= */
20185 typedef enum {                                  /*!< GPIO_PADREGD_PAD12STRNG                                                   */
20186   GPIO_PADREGD_PAD12STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20187   GPIO_PADREGD_PAD12STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20188 } GPIO_PADREGD_PAD12STRNG_Enum;
20189 
20190 /* ============================================  GPIO PADREGD PAD12INPEN [1..1]  ============================================= */
20191 typedef enum {                                  /*!< GPIO_PADREGD_PAD12INPEN                                                   */
20192   GPIO_PADREGD_PAD12INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20193   GPIO_PADREGD_PAD12INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20194 } GPIO_PADREGD_PAD12INPEN_Enum;
20195 
20196 /* =============================================  GPIO PADREGD PAD12PULL [0..0]  ============================================= */
20197 typedef enum {                                  /*!< GPIO_PADREGD_PAD12PULL                                                    */
20198   GPIO_PADREGD_PAD12PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20199   GPIO_PADREGD_PAD12PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20200 } GPIO_PADREGD_PAD12PULL_Enum;
20201 
20202 /* ========================================================  PADREGE  ======================================================== */
20203 /* ===========================================  GPIO PADREGE PAD19FNCSEL [27..29]  =========================================== */
20204 typedef enum {                                  /*!< GPIO_PADREGE_PAD19FNCSEL                                                  */
20205   GPIO_PADREGE_PAD19FNCSEL_CMPRF0      = 0,     /*!< CMPRF0 : Configure as the analog comparator reference 0 signal            */
20206   GPIO_PADREGE_PAD19FNCSEL_NCE19       = 1,     /*!< NCE19 : IOM/MSPI nCE group 19                                             */
20207   GPIO_PADREGE_PAD19FNCSEL_CT6         = 2,     /*!< CT6 : CTIMER conenction 6                                                 */
20208   GPIO_PADREGE_PAD19FNCSEL_GPIO19      = 3,     /*!< GPIO19 : Configure as GPIO19                                              */
20209   GPIO_PADREGE_PAD19FNCSEL_SCCLK       = 4,     /*!< SCCLK : SCARD serial clock                                                */
20210   GPIO_PADREGE_PAD19FNCSEL_ANATEST1    = 5,     /*!< ANATEST1 : Configure as the ANATEST1 I/O signal                           */
20211   GPIO_PADREGE_PAD19FNCSEL_UART1RX     = 6,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
20212   GPIO_PADREGE_PAD19FNCSEL_I2SBCLK     = 7,     /*!< I2SBCLK : Configure as the PDM I2S bit clock input signal                 */
20213 } GPIO_PADREGE_PAD19FNCSEL_Enum;
20214 
20215 /* ===========================================  GPIO PADREGE PAD19STRNG [26..26]  ============================================ */
20216 typedef enum {                                  /*!< GPIO_PADREGE_PAD19STRNG                                                   */
20217   GPIO_PADREGE_PAD19STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20218   GPIO_PADREGE_PAD19STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20219 } GPIO_PADREGE_PAD19STRNG_Enum;
20220 
20221 /* ===========================================  GPIO PADREGE PAD19INPEN [25..25]  ============================================ */
20222 typedef enum {                                  /*!< GPIO_PADREGE_PAD19INPEN                                                   */
20223   GPIO_PADREGE_PAD19INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20224   GPIO_PADREGE_PAD19INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20225 } GPIO_PADREGE_PAD19INPEN_Enum;
20226 
20227 /* ============================================  GPIO PADREGE PAD19PULL [24..24]  ============================================ */
20228 typedef enum {                                  /*!< GPIO_PADREGE_PAD19PULL                                                    */
20229   GPIO_PADREGE_PAD19PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20230   GPIO_PADREGE_PAD19PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20231 } GPIO_PADREGE_PAD19PULL_Enum;
20232 
20233 /* ===========================================  GPIO PADREGE PAD18FNCSEL [19..21]  =========================================== */
20234 typedef enum {                                  /*!< GPIO_PADREGE_PAD18FNCSEL                                                  */
20235   GPIO_PADREGE_PAD18FNCSEL_CMPIN1      = 0,     /*!< CMPIN1 : Configure as the analog comparator input 1 signal                */
20236   GPIO_PADREGE_PAD18FNCSEL_NCE18       = 1,     /*!< NCE18 : IOM/MSPI nCE group 18                                             */
20237   GPIO_PADREGE_PAD18FNCSEL_CT4         = 2,     /*!< CT4 : CTIMER connection 4                                                 */
20238   GPIO_PADREGE_PAD18FNCSEL_GPIO18      = 3,     /*!< GPIO18 : Configure as GPIO18                                              */
20239   GPIO_PADREGE_PAD18FNCSEL_UA0RTS      = 4,     /*!< UA0RTS : Configure as UART0 RTS output signal                             */
20240   GPIO_PADREGE_PAD18FNCSEL_ANATEST2    = 5,     /*!< ANATEST2 : Configure as ANATEST2 I/O signal                               */
20241   GPIO_PADREGE_PAD18FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as UART1 TX output signal                             */
20242   GPIO_PADREGE_PAD18FNCSEL_SCCIO       = 7,     /*!< SCCIO : SCARD data input/output connection                                */
20243 } GPIO_PADREGE_PAD18FNCSEL_Enum;
20244 
20245 /* ===========================================  GPIO PADREGE PAD18STRNG [18..18]  ============================================ */
20246 typedef enum {                                  /*!< GPIO_PADREGE_PAD18STRNG                                                   */
20247   GPIO_PADREGE_PAD18STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20248   GPIO_PADREGE_PAD18STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20249 } GPIO_PADREGE_PAD18STRNG_Enum;
20250 
20251 /* ===========================================  GPIO PADREGE PAD18INPEN [17..17]  ============================================ */
20252 typedef enum {                                  /*!< GPIO_PADREGE_PAD18INPEN                                                   */
20253   GPIO_PADREGE_PAD18INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20254   GPIO_PADREGE_PAD18INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20255 } GPIO_PADREGE_PAD18INPEN_Enum;
20256 
20257 /* ============================================  GPIO PADREGE PAD18PULL [16..16]  ============================================ */
20258 typedef enum {                                  /*!< GPIO_PADREGE_PAD18PULL                                                    */
20259   GPIO_PADREGE_PAD18PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20260   GPIO_PADREGE_PAD18PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20261 } GPIO_PADREGE_PAD18PULL_Enum;
20262 
20263 /* ===========================================  GPIO PADREGE PAD17FNCSEL [11..13]  =========================================== */
20264 typedef enum {                                  /*!< GPIO_PADREGE_PAD17FNCSEL                                                  */
20265   GPIO_PADREGE_PAD17FNCSEL_CMPRF1      = 0,     /*!< CMPRF1 : Configure as the analog comparator reference signal
20266                                                      1 input signal                                                            */
20267   GPIO_PADREGE_PAD17FNCSEL_NCE17       = 1,     /*!< NCE17 : IOM/MSPI nCE group 17                                             */
20268   GPIO_PADREGE_PAD17FNCSEL_TRIG1       = 2,     /*!< TRIG1 : Configure as the ADC Trigger 1 signal                             */
20269   GPIO_PADREGE_PAD17FNCSEL_GPIO17      = 3,     /*!< GPIO17 : Configure as GPIO17                                              */
20270   GPIO_PADREGE_PAD17FNCSEL_SCCCLK      = 4,     /*!< SCCCLK : SCARD serial clock output                                        */
20271   GPIO_PADREGE_PAD17FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as UART0 RX input signal                              */
20272   GPIO_PADREGE_PAD17FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as UART1 CTS input signal                              */
20273 } GPIO_PADREGE_PAD17FNCSEL_Enum;
20274 
20275 /* ===========================================  GPIO PADREGE PAD17STRNG [10..10]  ============================================ */
20276 typedef enum {                                  /*!< GPIO_PADREGE_PAD17STRNG                                                   */
20277   GPIO_PADREGE_PAD17STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20278   GPIO_PADREGE_PAD17STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20279 } GPIO_PADREGE_PAD17STRNG_Enum;
20280 
20281 /* ============================================  GPIO PADREGE PAD17INPEN [9..9]  ============================================= */
20282 typedef enum {                                  /*!< GPIO_PADREGE_PAD17INPEN                                                   */
20283   GPIO_PADREGE_PAD17INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20284   GPIO_PADREGE_PAD17INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20285 } GPIO_PADREGE_PAD17INPEN_Enum;
20286 
20287 /* =============================================  GPIO PADREGE PAD17PULL [8..8]  ============================================= */
20288 typedef enum {                                  /*!< GPIO_PADREGE_PAD17PULL                                                    */
20289   GPIO_PADREGE_PAD17PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20290   GPIO_PADREGE_PAD17PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20291 } GPIO_PADREGE_PAD17PULL_Enum;
20292 
20293 /* ============================================  GPIO PADREGE PAD16FNCSEL [3..5]  ============================================ */
20294 typedef enum {                                  /*!< GPIO_PADREGE_PAD16FNCSEL                                                  */
20295   GPIO_PADREGE_PAD16FNCSEL_ADCSE0      = 0,     /*!< ADCSE0 : Configure as the analog ADC single ended port 0 input
20296                                                      signal                                                                    */
20297   GPIO_PADREGE_PAD16FNCSEL_NCE16       = 1,     /*!< NCE16 : IOM/MSPI nCE group 16                                             */
20298   GPIO_PADREGE_PAD16FNCSEL_TRIG0       = 2,     /*!< TRIG0 : Configure as the ADC Trigger 0 signal                             */
20299   GPIO_PADREGE_PAD16FNCSEL_GPIO16      = 3,     /*!< GPIO16 : Configure as GPIO16                                              */
20300   GPIO_PADREGE_PAD16FNCSEL_SCCRST      = 4,     /*!< SCCRST : SCARD reset output                                               */
20301   GPIO_PADREGE_PAD16FNCSEL_CMPIN0      = 5,     /*!< CMPIN0 : Configure as comparator input 0 signal                           */
20302   GPIO_PADREGE_PAD16FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as UART0 TX output signal                             */
20303   GPIO_PADREGE_PAD16FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
20304 } GPIO_PADREGE_PAD16FNCSEL_Enum;
20305 
20306 /* ============================================  GPIO PADREGE PAD16STRNG [2..2]  ============================================= */
20307 typedef enum {                                  /*!< GPIO_PADREGE_PAD16STRNG                                                   */
20308   GPIO_PADREGE_PAD16STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20309   GPIO_PADREGE_PAD16STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20310 } GPIO_PADREGE_PAD16STRNG_Enum;
20311 
20312 /* ============================================  GPIO PADREGE PAD16INPEN [1..1]  ============================================= */
20313 typedef enum {                                  /*!< GPIO_PADREGE_PAD16INPEN                                                   */
20314   GPIO_PADREGE_PAD16INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20315   GPIO_PADREGE_PAD16INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20316 } GPIO_PADREGE_PAD16INPEN_Enum;
20317 
20318 /* =============================================  GPIO PADREGE PAD16PULL [0..0]  ============================================= */
20319 typedef enum {                                  /*!< GPIO_PADREGE_PAD16PULL                                                    */
20320   GPIO_PADREGE_PAD16PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20321   GPIO_PADREGE_PAD16PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20322 } GPIO_PADREGE_PAD16PULL_Enum;
20323 
20324 /* ========================================================  PADREGF  ======================================================== */
20325 /* ===========================================  GPIO PADREGF PAD23FNCSEL [27..29]  =========================================== */
20326 typedef enum {                                  /*!< GPIO_PADREGF_PAD23FNCSEL                                                  */
20327   GPIO_PADREGF_PAD23FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as the UART0 RX signal                                */
20328   GPIO_PADREGF_PAD23FNCSEL_NCE23       = 1,     /*!< NCE23 : IOM/MSPI nCE group 23                                             */
20329   GPIO_PADREGF_PAD23FNCSEL_CT14        = 2,     /*!< CT14 : CTIMER connection 14                                               */
20330   GPIO_PADREGF_PAD23FNCSEL_GPIO23      = 3,     /*!< GPIO23 : Configure as GPIO23                                              */
20331   GPIO_PADREGF_PAD23FNCSEL_I2SWCLK     = 4,     /*!< I2SWCLK : I2S word clock input                                            */
20332   GPIO_PADREGF_PAD23FNCSEL_CMPOUT      = 5,     /*!< CMPOUT : Configure as voltage comparator output                           */
20333   GPIO_PADREGF_PAD23FNCSEL_MSPI3       = 6,     /*!< MSPI3 : MSPI data connection 3                                            */
20334   GPIO_PADREGF_PAD23FNCSEL_EXTXT       = 7,     /*!< EXTXT : External XTAL oscillator input                                    */
20335 } GPIO_PADREGF_PAD23FNCSEL_Enum;
20336 
20337 /* ===========================================  GPIO PADREGF PAD23STRNG [26..26]  ============================================ */
20338 typedef enum {                                  /*!< GPIO_PADREGF_PAD23STRNG                                                   */
20339   GPIO_PADREGF_PAD23STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20340   GPIO_PADREGF_PAD23STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20341 } GPIO_PADREGF_PAD23STRNG_Enum;
20342 
20343 /* ===========================================  GPIO PADREGF PAD23INPEN [25..25]  ============================================ */
20344 typedef enum {                                  /*!< GPIO_PADREGF_PAD23INPEN                                                   */
20345   GPIO_PADREGF_PAD23INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20346   GPIO_PADREGF_PAD23INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20347 } GPIO_PADREGF_PAD23INPEN_Enum;
20348 
20349 /* ============================================  GPIO PADREGF PAD23PULL [24..24]  ============================================ */
20350 typedef enum {                                  /*!< GPIO_PADREGF_PAD23PULL                                                    */
20351   GPIO_PADREGF_PAD23PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20352   GPIO_PADREGF_PAD23PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20353 } GPIO_PADREGF_PAD23PULL_Enum;
20354 
20355 /* ===========================================  GPIO PADREGF PAD22FNCSEL [19..21]  =========================================== */
20356 typedef enum {                                  /*!< GPIO_PADREGF_PAD22FNCSEL                                                  */
20357   GPIO_PADREGF_PAD22FNCSEL_UART0TX     = 0,     /*!< UART0TX : Configure as the UART0 TX signal                                */
20358   GPIO_PADREGF_PAD22FNCSEL_NCE22       = 1,     /*!< NCE22 : IOM/MSPI nCE group 22                                             */
20359   GPIO_PADREGF_PAD22FNCSEL_CT12        = 2,     /*!< CT12 : CTIMER connection 12                                               */
20360   GPIO_PADREGF_PAD22FNCSEL_GPIO22      = 3,     /*!< GPIO22 : Configure as GPIO22                                              */
20361   GPIO_PADREGF_PAD22FNCSEL_PDM_CLK     = 4,     /*!< PDM_CLK : Configure as the PDM CLK output                                 */
20362   GPIO_PADREGF_PAD22FNCSEL_EXTLF       = 5,     /*!< EXTLF : External LFRC input                                               */
20363   GPIO_PADREGF_PAD22FNCSEL_MSPI0       = 6,     /*!< MSPI0 : MSPI data connection 0                                            */
20364   GPIO_PADREGF_PAD22FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial trace data output signal                    */
20365 } GPIO_PADREGF_PAD22FNCSEL_Enum;
20366 
20367 /* ===========================================  GPIO PADREGF PAD22STRNG [18..18]  ============================================ */
20368 typedef enum {                                  /*!< GPIO_PADREGF_PAD22STRNG                                                   */
20369   GPIO_PADREGF_PAD22STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20370   GPIO_PADREGF_PAD22STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20371 } GPIO_PADREGF_PAD22STRNG_Enum;
20372 
20373 /* ===========================================  GPIO PADREGF PAD22INPEN [17..17]  ============================================ */
20374 typedef enum {                                  /*!< GPIO_PADREGF_PAD22INPEN                                                   */
20375   GPIO_PADREGF_PAD22INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20376   GPIO_PADREGF_PAD22INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20377 } GPIO_PADREGF_PAD22INPEN_Enum;
20378 
20379 /* ============================================  GPIO PADREGF PAD22PULL [16..16]  ============================================ */
20380 typedef enum {                                  /*!< GPIO_PADREGF_PAD22PULL                                                    */
20381   GPIO_PADREGF_PAD22PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20382   GPIO_PADREGF_PAD22PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20383 } GPIO_PADREGF_PAD22PULL_Enum;
20384 
20385 /* ===========================================  GPIO PADREGF PAD21FNCSEL [11..13]  =========================================== */
20386 typedef enum {                                  /*!< GPIO_PADREGF_PAD21FNCSEL                                                  */
20387   GPIO_PADREGF_PAD21FNCSEL_SWDIO       = 0,     /*!< SWDIO : Configure as the serial wire debug data signal                    */
20388   GPIO_PADREGF_PAD21FNCSEL_NCE21       = 1,     /*!< NCE21 : IOM/MSPI nCE group 21                                             */
20389   GPIO_PADREGF_PAD21FNCSEL_GPIO21      = 3,     /*!< GPIO21 : Configure as GPIO21                                              */
20390   GPIO_PADREGF_PAD21FNCSEL_UART0RX     = 4,     /*!< UART0RX : Configure as UART0 RX input signal                              */
20391   GPIO_PADREGF_PAD21FNCSEL_UART1RX     = 5,     /*!< UART1RX : Configure as UART1 RX input signal                              */
20392   GPIO_PADREGF_PAD21FNCSEL_I2SBCLK     = 6,     /*!< I2SBCLK : I2S byte clock input                                            */
20393   GPIO_PADREGF_PAD21FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as UART1 CTS input signal                              */
20394 } GPIO_PADREGF_PAD21FNCSEL_Enum;
20395 
20396 /* ===========================================  GPIO PADREGF PAD21STRNG [10..10]  ============================================ */
20397 typedef enum {                                  /*!< GPIO_PADREGF_PAD21STRNG                                                   */
20398   GPIO_PADREGF_PAD21STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20399   GPIO_PADREGF_PAD21STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20400 } GPIO_PADREGF_PAD21STRNG_Enum;
20401 
20402 /* ============================================  GPIO PADREGF PAD21INPEN [9..9]  ============================================= */
20403 typedef enum {                                  /*!< GPIO_PADREGF_PAD21INPEN                                                   */
20404   GPIO_PADREGF_PAD21INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20405   GPIO_PADREGF_PAD21INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20406 } GPIO_PADREGF_PAD21INPEN_Enum;
20407 
20408 /* =============================================  GPIO PADREGF PAD21PULL [8..8]  ============================================= */
20409 typedef enum {                                  /*!< GPIO_PADREGF_PAD21PULL                                                    */
20410   GPIO_PADREGF_PAD21PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20411   GPIO_PADREGF_PAD21PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20412 } GPIO_PADREGF_PAD21PULL_Enum;
20413 
20414 /* ============================================  GPIO PADREGF PAD20FNCSEL [3..5]  ============================================ */
20415 typedef enum {                                  /*!< GPIO_PADREGF_PAD20FNCSEL                                                  */
20416   GPIO_PADREGF_PAD20FNCSEL_SWDCK       = 0,     /*!< SWDCK : Configure as the serial wire debug clock signal                   */
20417   GPIO_PADREGF_PAD20FNCSEL_NCE20       = 1,     /*!< NCE20 : IOM/MSPI nCE group 20                                             */
20418   GPIO_PADREGF_PAD20FNCSEL_GPIO20      = 3,     /*!< GPIO20 : Configure as GPIO20                                              */
20419   GPIO_PADREGF_PAD20FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as UART0 TX output signal                             */
20420   GPIO_PADREGF_PAD20FNCSEL_UART1TX     = 5,     /*!< UART1TX : Configure as UART1 TX output signal                             */
20421   GPIO_PADREGF_PAD20FNCSEL_I2SBCLK     = 6,     /*!< I2SBCLK : I2S byte clock input                                            */
20422   GPIO_PADREGF_PAD20FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
20423 } GPIO_PADREGF_PAD20FNCSEL_Enum;
20424 
20425 /* ============================================  GPIO PADREGF PAD20STRNG [2..2]  ============================================= */
20426 typedef enum {                                  /*!< GPIO_PADREGF_PAD20STRNG                                                   */
20427   GPIO_PADREGF_PAD20STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20428   GPIO_PADREGF_PAD20STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20429 } GPIO_PADREGF_PAD20STRNG_Enum;
20430 
20431 /* ============================================  GPIO PADREGF PAD20INPEN [1..1]  ============================================= */
20432 typedef enum {                                  /*!< GPIO_PADREGF_PAD20INPEN                                                   */
20433   GPIO_PADREGF_PAD20INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20434   GPIO_PADREGF_PAD20INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20435 } GPIO_PADREGF_PAD20INPEN_Enum;
20436 
20437 /* =============================================  GPIO PADREGF PAD20PULL [0..0]  ============================================= */
20438 typedef enum {                                  /*!< GPIO_PADREGF_PAD20PULL                                                    */
20439   GPIO_PADREGF_PAD20PULL_DIS           = 0,     /*!< DIS : Pulldown disabled                                                   */
20440   GPIO_PADREGF_PAD20PULL_EN            = 1,     /*!< EN : Pulldown enabled                                                     */
20441 } GPIO_PADREGF_PAD20PULL_Enum;
20442 
20443 /* ========================================================  PADREGG  ======================================================== */
20444 /* ============================================  GPIO PADREGG PAD27RSEL [30..31]  ============================================ */
20445 typedef enum {                                  /*!< GPIO_PADREGG_PAD27RSEL                                                    */
20446   GPIO_PADREGG_PAD27RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20447   GPIO_PADREGG_PAD27RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20448   GPIO_PADREGG_PAD27RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20449   GPIO_PADREGG_PAD27RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20450 } GPIO_PADREGG_PAD27RSEL_Enum;
20451 
20452 /* ===========================================  GPIO PADREGG PAD27FNCSEL [27..29]  =========================================== */
20453 typedef enum {                                  /*!< GPIO_PADREGG_PAD27FNCSEL                                                  */
20454   GPIO_PADREGG_PAD27FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as UART0 RX input signal                              */
20455   GPIO_PADREGG_PAD27FNCSEL_NCE27       = 1,     /*!< NCE27 : IOM/MSPI nCE group 27                                             */
20456   GPIO_PADREGG_PAD27FNCSEL_CT5         = 2,     /*!< CT5 : CTIMER connection 5                                                 */
20457   GPIO_PADREGG_PAD27FNCSEL_GPIO27      = 3,     /*!< GPIO27 : Configure as GPIO27                                              */
20458   GPIO_PADREGG_PAD27FNCSEL_M2SCL       = 4,     /*!< M2SCL : Configure as I2C clock I/O signal from IOMSTR2                    */
20459   GPIO_PADREGG_PAD27FNCSEL_M2SCK       = 5,     /*!< M2SCK : Configure as SPI clock output signal from IOMSTR2                 */
20460 } GPIO_PADREGG_PAD27FNCSEL_Enum;
20461 
20462 /* ===========================================  GPIO PADREGG PAD27STRNG [26..26]  ============================================ */
20463 typedef enum {                                  /*!< GPIO_PADREGG_PAD27STRNG                                                   */
20464   GPIO_PADREGG_PAD27STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20465   GPIO_PADREGG_PAD27STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20466 } GPIO_PADREGG_PAD27STRNG_Enum;
20467 
20468 /* ===========================================  GPIO PADREGG PAD27INPEN [25..25]  ============================================ */
20469 typedef enum {                                  /*!< GPIO_PADREGG_PAD27INPEN                                                   */
20470   GPIO_PADREGG_PAD27INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20471   GPIO_PADREGG_PAD27INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20472 } GPIO_PADREGG_PAD27INPEN_Enum;
20473 
20474 /* ============================================  GPIO PADREGG PAD27PULL [24..24]  ============================================ */
20475 typedef enum {                                  /*!< GPIO_PADREGG_PAD27PULL                                                    */
20476   GPIO_PADREGG_PAD27PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20477   GPIO_PADREGG_PAD27PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20478 } GPIO_PADREGG_PAD27PULL_Enum;
20479 
20480 /* ===========================================  GPIO PADREGG PAD26FNCSEL [19..21]  =========================================== */
20481 typedef enum {                                  /*!< GPIO_PADREGG_PAD26FNCSEL                                                  */
20482   GPIO_PADREGG_PAD26FNCSEL_EXTHF       = 0,     /*!< EXTHF : Configure as the external HFRC oscillator input                   */
20483   GPIO_PADREGG_PAD26FNCSEL_NCE26       = 1,     /*!< NCE26 : IOM/MSPI nCE group 26                                             */
20484   GPIO_PADREGG_PAD26FNCSEL_CT3         = 2,     /*!< CT3 : CTIMER connection 3                                                 */
20485   GPIO_PADREGG_PAD26FNCSEL_GPIO26      = 3,     /*!< GPIO26 : Configure as GPIO26                                              */
20486   GPIO_PADREGG_PAD26FNCSEL_SCCRST      = 4,     /*!< SCCRST : SCARD reset output                                               */
20487   GPIO_PADREGG_PAD26FNCSEL_MSPI1       = 5,     /*!< MSPI1 : MSPI data connection 1                                            */
20488   GPIO_PADREGG_PAD26FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as UART0 TX output signal                             */
20489   GPIO_PADREGG_PAD26FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as UART1 CTS input signal                              */
20490 } GPIO_PADREGG_PAD26FNCSEL_Enum;
20491 
20492 /* ===========================================  GPIO PADREGG PAD26STRNG [18..18]  ============================================ */
20493 typedef enum {                                  /*!< GPIO_PADREGG_PAD26STRNG                                                   */
20494   GPIO_PADREGG_PAD26STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20495   GPIO_PADREGG_PAD26STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20496 } GPIO_PADREGG_PAD26STRNG_Enum;
20497 
20498 /* ===========================================  GPIO PADREGG PAD26INPEN [17..17]  ============================================ */
20499 typedef enum {                                  /*!< GPIO_PADREGG_PAD26INPEN                                                   */
20500   GPIO_PADREGG_PAD26INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20501   GPIO_PADREGG_PAD26INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20502 } GPIO_PADREGG_PAD26INPEN_Enum;
20503 
20504 /* ============================================  GPIO PADREGG PAD26PULL [16..16]  ============================================ */
20505 typedef enum {                                  /*!< GPIO_PADREGG_PAD26PULL                                                    */
20506   GPIO_PADREGG_PAD26PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20507   GPIO_PADREGG_PAD26PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20508 } GPIO_PADREGG_PAD26PULL_Enum;
20509 
20510 /* ============================================  GPIO PADREGG PAD25RSEL [14..15]  ============================================ */
20511 typedef enum {                                  /*!< GPIO_PADREGG_PAD25RSEL                                                    */
20512   GPIO_PADREGG_PAD25RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20513   GPIO_PADREGG_PAD25RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20514   GPIO_PADREGG_PAD25RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20515   GPIO_PADREGG_PAD25RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20516 } GPIO_PADREGG_PAD25RSEL_Enum;
20517 
20518 /* ===========================================  GPIO PADREGG PAD25FNCSEL [11..13]  =========================================== */
20519 typedef enum {                                  /*!< GPIO_PADREGG_PAD25FNCSEL                                                  */
20520   GPIO_PADREGG_PAD25FNCSEL_UART1RX     = 0,     /*!< UART1RX : Configure as UART1 RX input signal                              */
20521   GPIO_PADREGG_PAD25FNCSEL_NCE25       = 1,     /*!< NCE25 : IOM/MSPI nCE group 25                                             */
20522   GPIO_PADREGG_PAD25FNCSEL_CT1         = 2,     /*!< CT1 : CTIMER connection 1                                                 */
20523   GPIO_PADREGG_PAD25FNCSEL_GPIO25      = 3,     /*!< GPIO25 : Configure as GPIO25                                              */
20524   GPIO_PADREGG_PAD25FNCSEL_M2SDAWIR3   = 4,     /*!< M2SDAWIR3 : Configure as the IOMSTR2 I2C SDA or SPI WIR3 signal           */
20525   GPIO_PADREGG_PAD25FNCSEL_M2MISO      = 5,     /*!< M2MISO : Configure as the IOMSTR2 SPI MISO input signal                   */
20526 } GPIO_PADREGG_PAD25FNCSEL_Enum;
20527 
20528 /* ===========================================  GPIO PADREGG PAD25STRNG [10..10]  ============================================ */
20529 typedef enum {                                  /*!< GPIO_PADREGG_PAD25STRNG                                                   */
20530   GPIO_PADREGG_PAD25STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20531   GPIO_PADREGG_PAD25STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20532 } GPIO_PADREGG_PAD25STRNG_Enum;
20533 
20534 /* ============================================  GPIO PADREGG PAD25INPEN [9..9]  ============================================= */
20535 typedef enum {                                  /*!< GPIO_PADREGG_PAD25INPEN                                                   */
20536   GPIO_PADREGG_PAD25INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20537   GPIO_PADREGG_PAD25INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20538 } GPIO_PADREGG_PAD25INPEN_Enum;
20539 
20540 /* =============================================  GPIO PADREGG PAD25PULL [8..8]  ============================================= */
20541 typedef enum {                                  /*!< GPIO_PADREGG_PAD25PULL                                                    */
20542   GPIO_PADREGG_PAD25PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20543   GPIO_PADREGG_PAD25PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20544 } GPIO_PADREGG_PAD25PULL_Enum;
20545 
20546 /* ============================================  GPIO PADREGG PAD24FNCSEL [3..5]  ============================================ */
20547 typedef enum {                                  /*!< GPIO_PADREGG_PAD24FNCSEL                                                  */
20548   GPIO_PADREGG_PAD24FNCSEL_UART1TX     = 0,     /*!< UART1TX : Configure as UART1 TX output signal                             */
20549   GPIO_PADREGG_PAD24FNCSEL_NCE24       = 1,     /*!< NCE24 : IOM/MSPI nCE group 24                                             */
20550   GPIO_PADREGG_PAD24FNCSEL_MSPI8       = 2,     /*!< MSPI8 : MSPI data connection 8                                            */
20551   GPIO_PADREGG_PAD24FNCSEL_GPIO24      = 3,     /*!< GPIO24 : Configure as GPIO24                                              */
20552   GPIO_PADREGG_PAD24FNCSEL_UA0CTS      = 4,     /*!< UA0CTS : Configure as UART0 CTS input signal                              */
20553   GPIO_PADREGG_PAD24FNCSEL_CT21        = 5,     /*!< CT21 : CTIMER connection 21                                               */
20554   GPIO_PADREGG_PAD24FNCSEL_32kHzXT     = 6,     /*!< 32kHzXT : Configure as the 32kHz crystal output signal                    */
20555   GPIO_PADREGG_PAD24FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial trace data output signal                    */
20556 } GPIO_PADREGG_PAD24FNCSEL_Enum;
20557 
20558 /* ============================================  GPIO PADREGG PAD24STRNG [2..2]  ============================================= */
20559 typedef enum {                                  /*!< GPIO_PADREGG_PAD24STRNG                                                   */
20560   GPIO_PADREGG_PAD24STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20561   GPIO_PADREGG_PAD24STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20562 } GPIO_PADREGG_PAD24STRNG_Enum;
20563 
20564 /* ============================================  GPIO PADREGG PAD24INPEN [1..1]  ============================================= */
20565 typedef enum {                                  /*!< GPIO_PADREGG_PAD24INPEN                                                   */
20566   GPIO_PADREGG_PAD24INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20567   GPIO_PADREGG_PAD24INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20568 } GPIO_PADREGG_PAD24INPEN_Enum;
20569 
20570 /* =============================================  GPIO PADREGG PAD24PULL [0..0]  ============================================= */
20571 typedef enum {                                  /*!< GPIO_PADREGG_PAD24PULL                                                    */
20572   GPIO_PADREGG_PAD24PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20573   GPIO_PADREGG_PAD24PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20574 } GPIO_PADREGG_PAD24PULL_Enum;
20575 
20576 /* ========================================================  PADREGH  ======================================================== */
20577 /* ===========================================  GPIO PADREGH PAD31FNCSEL [27..29]  =========================================== */
20578 typedef enum {                                  /*!< GPIO_PADREGH_PAD31FNCSEL                                                  */
20579   GPIO_PADREGH_PAD31FNCSEL_ADCSE3      = 0,     /*!< ADCSE3 : Configure as the analog input for ADC single ended
20580                                                      input 3                                                                   */
20581   GPIO_PADREGH_PAD31FNCSEL_NCE31       = 1,     /*!< NCE31 : IOM/MSPI nCE group 31                                             */
20582   GPIO_PADREGH_PAD31FNCSEL_CT13        = 2,     /*!< CT13 : CTIMER connection 13                                               */
20583   GPIO_PADREGH_PAD31FNCSEL_GPIO31      = 3,     /*!< GPIO31 : Configure as GPIO31                                              */
20584   GPIO_PADREGH_PAD31FNCSEL_UART0RX     = 4,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
20585   GPIO_PADREGH_PAD31FNCSEL_SCCCLK      = 5,     /*!< SCCCLK : SCARD serial clock output                                        */
20586   GPIO_PADREGH_PAD31FNCSEL_UA1RTS      = 7,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
20587 } GPIO_PADREGH_PAD31FNCSEL_Enum;
20588 
20589 /* ===========================================  GPIO PADREGH PAD31STRNG [26..26]  ============================================ */
20590 typedef enum {                                  /*!< GPIO_PADREGH_PAD31STRNG                                                   */
20591   GPIO_PADREGH_PAD31STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20592   GPIO_PADREGH_PAD31STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20593 } GPIO_PADREGH_PAD31STRNG_Enum;
20594 
20595 /* ===========================================  GPIO PADREGH PAD31INPEN [25..25]  ============================================ */
20596 typedef enum {                                  /*!< GPIO_PADREGH_PAD31INPEN                                                   */
20597   GPIO_PADREGH_PAD31INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20598   GPIO_PADREGH_PAD31INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20599 } GPIO_PADREGH_PAD31INPEN_Enum;
20600 
20601 /* ============================================  GPIO PADREGH PAD31PULL [24..24]  ============================================ */
20602 typedef enum {                                  /*!< GPIO_PADREGH_PAD31PULL                                                    */
20603   GPIO_PADREGH_PAD31PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20604   GPIO_PADREGH_PAD31PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20605 } GPIO_PADREGH_PAD31PULL_Enum;
20606 
20607 /* ===========================================  GPIO PADREGH PAD30FNCSEL [19..21]  =========================================== */
20608 typedef enum {                                  /*!< GPIO_PADREGH_PAD30FNCSEL                                                  */
20609   GPIO_PADREGH_PAD30FNCSEL_ANATEST1    = 0,     /*!< ANATEST1 : Configure as the ANATEST1 I/O signal                           */
20610   GPIO_PADREGH_PAD30FNCSEL_NCE30       = 1,     /*!< NCE30 : IOM/MSPI nCE group 30                                             */
20611   GPIO_PADREGH_PAD30FNCSEL_CT11        = 2,     /*!< CT11 : CTIMER connection 11                                               */
20612   GPIO_PADREGH_PAD30FNCSEL_GPIO30      = 3,     /*!< GPIO30 : Configure as GPIO30                                              */
20613   GPIO_PADREGH_PAD30FNCSEL_UART0TX     = 4,     /*!< UART0TX : Configure as UART0 TX output signal                             */
20614   GPIO_PADREGH_PAD30FNCSEL_UA1RTS      = 5,     /*!< UA1RTS : Configure as UART1 RTS output signal                             */
20615   GPIO_PADREGH_PAD30FNCSEL_I2S_DAT     = 7,     /*!< I2S_DAT : Configure as the PDM I2S Data output signal                     */
20616 } GPIO_PADREGH_PAD30FNCSEL_Enum;
20617 
20618 /* ===========================================  GPIO PADREGH PAD30STRNG [18..18]  ============================================ */
20619 typedef enum {                                  /*!< GPIO_PADREGH_PAD30STRNG                                                   */
20620   GPIO_PADREGH_PAD30STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20621   GPIO_PADREGH_PAD30STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20622 } GPIO_PADREGH_PAD30STRNG_Enum;
20623 
20624 /* ===========================================  GPIO PADREGH PAD30INPEN [17..17]  ============================================ */
20625 typedef enum {                                  /*!< GPIO_PADREGH_PAD30INPEN                                                   */
20626   GPIO_PADREGH_PAD30INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20627   GPIO_PADREGH_PAD30INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20628 } GPIO_PADREGH_PAD30INPEN_Enum;
20629 
20630 /* ============================================  GPIO PADREGH PAD30PULL [16..16]  ============================================ */
20631 typedef enum {                                  /*!< GPIO_PADREGH_PAD30PULL                                                    */
20632   GPIO_PADREGH_PAD30PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20633   GPIO_PADREGH_PAD30PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20634 } GPIO_PADREGH_PAD30PULL_Enum;
20635 
20636 /* ===========================================  GPIO PADREGH PAD29FNCSEL [11..13]  =========================================== */
20637 typedef enum {                                  /*!< GPIO_PADREGH_PAD29FNCSEL                                                  */
20638   GPIO_PADREGH_PAD29FNCSEL_ADCSE1      = 0,     /*!< ADCSE1 : Configure as the analog input for ADC single ended
20639                                                      input 1                                                                   */
20640   GPIO_PADREGH_PAD29FNCSEL_NCE29       = 1,     /*!< NCE29 : IOM/MSPI nCE group 29                                             */
20641   GPIO_PADREGH_PAD29FNCSEL_CT9         = 2,     /*!< CT9 : CTIMER connection 9                                                 */
20642   GPIO_PADREGH_PAD29FNCSEL_GPIO29      = 3,     /*!< GPIO29 : Configure as GPIO29                                              */
20643   GPIO_PADREGH_PAD29FNCSEL_UA0CTS      = 4,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
20644   GPIO_PADREGH_PAD29FNCSEL_UA1CTS      = 5,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
20645   GPIO_PADREGH_PAD29FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
20646   GPIO_PADREGH_PAD29FNCSEL_PDM_DATA    = 7,     /*!< PDM_DATA : Configure as PDM DATA input                                    */
20647 } GPIO_PADREGH_PAD29FNCSEL_Enum;
20648 
20649 /* ===========================================  GPIO PADREGH PAD29STRNG [10..10]  ============================================ */
20650 typedef enum {                                  /*!< GPIO_PADREGH_PAD29STRNG                                                   */
20651   GPIO_PADREGH_PAD29STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20652   GPIO_PADREGH_PAD29STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20653 } GPIO_PADREGH_PAD29STRNG_Enum;
20654 
20655 /* ============================================  GPIO PADREGH PAD29INPEN [9..9]  ============================================= */
20656 typedef enum {                                  /*!< GPIO_PADREGH_PAD29INPEN                                                   */
20657   GPIO_PADREGH_PAD29INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20658   GPIO_PADREGH_PAD29INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20659 } GPIO_PADREGH_PAD29INPEN_Enum;
20660 
20661 /* =============================================  GPIO PADREGH PAD29PULL [8..8]  ============================================= */
20662 typedef enum {                                  /*!< GPIO_PADREGH_PAD29PULL                                                    */
20663   GPIO_PADREGH_PAD29PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20664   GPIO_PADREGH_PAD29PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20665 } GPIO_PADREGH_PAD29PULL_Enum;
20666 
20667 /* ============================================  GPIO PADREGH PAD28FNCSEL [3..5]  ============================================ */
20668 typedef enum {                                  /*!< GPIO_PADREGH_PAD28FNCSEL                                                  */
20669   GPIO_PADREGH_PAD28FNCSEL_I2S_WCLK    = 0,     /*!< I2S_WCLK : Configure as the PDM I2S Word Clock input                      */
20670   GPIO_PADREGH_PAD28FNCSEL_NCE28       = 1,     /*!< NCE28 : IOM/MSPI nCE group 28                                             */
20671   GPIO_PADREGH_PAD28FNCSEL_CT7         = 2,     /*!< CT7 : CTIMER connection 7                                                 */
20672   GPIO_PADREGH_PAD28FNCSEL_GPIO28      = 3,     /*!< GPIO28 : Configure as GPIO28                                              */
20673   GPIO_PADREGH_PAD28FNCSEL_M2MOSI      = 5,     /*!< M2MOSI : Configure as the IOMSTR2 SPI MOSI output signal                  */
20674   GPIO_PADREGH_PAD28FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
20675 } GPIO_PADREGH_PAD28FNCSEL_Enum;
20676 
20677 /* ============================================  GPIO PADREGH PAD28STRNG [2..2]  ============================================= */
20678 typedef enum {                                  /*!< GPIO_PADREGH_PAD28STRNG                                                   */
20679   GPIO_PADREGH_PAD28STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20680   GPIO_PADREGH_PAD28STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20681 } GPIO_PADREGH_PAD28STRNG_Enum;
20682 
20683 /* ============================================  GPIO PADREGH PAD28INPEN [1..1]  ============================================= */
20684 typedef enum {                                  /*!< GPIO_PADREGH_PAD28INPEN                                                   */
20685   GPIO_PADREGH_PAD28INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20686   GPIO_PADREGH_PAD28INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20687 } GPIO_PADREGH_PAD28INPEN_Enum;
20688 
20689 /* =============================================  GPIO PADREGH PAD28PULL [0..0]  ============================================= */
20690 typedef enum {                                  /*!< GPIO_PADREGH_PAD28PULL                                                    */
20691   GPIO_PADREGH_PAD28PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20692   GPIO_PADREGH_PAD28PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20693 } GPIO_PADREGH_PAD28PULL_Enum;
20694 
20695 /* ========================================================  PADREGI  ======================================================== */
20696 /* ===========================================  GPIO PADREGI PAD35FNCSEL [27..29]  =========================================== */
20697 typedef enum {                                  /*!< GPIO_PADREGI_PAD35FNCSEL                                                  */
20698   GPIO_PADREGI_PAD35FNCSEL_ADCSE7      = 0,     /*!< ADCSE7 : Configure as the analog input for ADC single ended
20699                                                      input 7                                                                   */
20700   GPIO_PADREGI_PAD35FNCSEL_NCE35       = 1,     /*!< NCE35 : IOM/MSPI nCE group 35                                             */
20701   GPIO_PADREGI_PAD35FNCSEL_UART1TX     = 2,     /*!< UART1TX : Configure as the UART1 TX signal                                */
20702   GPIO_PADREGI_PAD35FNCSEL_GPIO35      = 3,     /*!< GPIO35 : Configure as GPIO35                                              */
20703   GPIO_PADREGI_PAD35FNCSEL_I2SDAT      = 4,     /*!< I2SDAT : I2S serial data output                                           */
20704   GPIO_PADREGI_PAD35FNCSEL_CT27        = 5,     /*!< CT27 : CTIMER connection 27                                               */
20705   GPIO_PADREGI_PAD35FNCSEL_UA0RTS      = 6,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
20706 } GPIO_PADREGI_PAD35FNCSEL_Enum;
20707 
20708 /* ===========================================  GPIO PADREGI PAD35STRNG [26..26]  ============================================ */
20709 typedef enum {                                  /*!< GPIO_PADREGI_PAD35STRNG                                                   */
20710   GPIO_PADREGI_PAD35STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20711   GPIO_PADREGI_PAD35STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20712 } GPIO_PADREGI_PAD35STRNG_Enum;
20713 
20714 /* ===========================================  GPIO PADREGI PAD35INPEN [25..25]  ============================================ */
20715 typedef enum {                                  /*!< GPIO_PADREGI_PAD35INPEN                                                   */
20716   GPIO_PADREGI_PAD35INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20717   GPIO_PADREGI_PAD35INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20718 } GPIO_PADREGI_PAD35INPEN_Enum;
20719 
20720 /* ============================================  GPIO PADREGI PAD35PULL [24..24]  ============================================ */
20721 typedef enum {                                  /*!< GPIO_PADREGI_PAD35PULL                                                    */
20722   GPIO_PADREGI_PAD35PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20723   GPIO_PADREGI_PAD35PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20724 } GPIO_PADREGI_PAD35PULL_Enum;
20725 
20726 /* ===========================================  GPIO PADREGI PAD34FNCSEL [19..21]  =========================================== */
20727 typedef enum {                                  /*!< GPIO_PADREGI_PAD34FNCSEL                                                  */
20728   GPIO_PADREGI_PAD34FNCSEL_ADCSE6      = 0,     /*!< ADCSE6 : Configure as the analog input for ADC single ended
20729                                                      input 6                                                                   */
20730   GPIO_PADREGI_PAD34FNCSEL_NCE34       = 1,     /*!< NCE34 : IOM/MSPI nCE group 34                                             */
20731   GPIO_PADREGI_PAD34FNCSEL_UA1RTS      = 2,     /*!< UA1RTS : Configure as the UART1 RTS output                                */
20732   GPIO_PADREGI_PAD34FNCSEL_GPIO34      = 3,     /*!< GPIO34 : Configure as GPIO34                                              */
20733   GPIO_PADREGI_PAD34FNCSEL_CMPRF2      = 4,     /*!< CMPRF2 : Configure as the analog comparator reference 2 signal            */
20734   GPIO_PADREGI_PAD34FNCSEL_UA0RTS      = 5,     /*!< UA0RTS : Configure as the UART0 RTS output                                */
20735   GPIO_PADREGI_PAD34FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the UART0 RX input                                 */
20736   GPIO_PADREGI_PAD34FNCSEL_PDMDATA     = 7,     /*!< PDMDATA : PDM serial data input                                           */
20737 } GPIO_PADREGI_PAD34FNCSEL_Enum;
20738 
20739 /* ===========================================  GPIO PADREGI PAD34STRNG [18..18]  ============================================ */
20740 typedef enum {                                  /*!< GPIO_PADREGI_PAD34STRNG                                                   */
20741   GPIO_PADREGI_PAD34STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20742   GPIO_PADREGI_PAD34STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20743 } GPIO_PADREGI_PAD34STRNG_Enum;
20744 
20745 /* ===========================================  GPIO PADREGI PAD34INPEN [17..17]  ============================================ */
20746 typedef enum {                                  /*!< GPIO_PADREGI_PAD34INPEN                                                   */
20747   GPIO_PADREGI_PAD34INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20748   GPIO_PADREGI_PAD34INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20749 } GPIO_PADREGI_PAD34INPEN_Enum;
20750 
20751 /* ============================================  GPIO PADREGI PAD34PULL [16..16]  ============================================ */
20752 typedef enum {                                  /*!< GPIO_PADREGI_PAD34PULL                                                    */
20753   GPIO_PADREGI_PAD34PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20754   GPIO_PADREGI_PAD34PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20755 } GPIO_PADREGI_PAD34PULL_Enum;
20756 
20757 /* ===========================================  GPIO PADREGI PAD33FNCSEL [11..13]  =========================================== */
20758 typedef enum {                                  /*!< GPIO_PADREGI_PAD33FNCSEL                                                  */
20759   GPIO_PADREGI_PAD33FNCSEL_ADCSE5      = 0,     /*!< ADCSE5 : Configure as the analog ADC single ended port 5 input
20760                                                      signal                                                                    */
20761   GPIO_PADREGI_PAD33FNCSEL_NCE33       = 1,     /*!< NCE33 : IOM/MSPI nCE group 33                                             */
20762   GPIO_PADREGI_PAD33FNCSEL_32kHzXT     = 2,     /*!< 32kHzXT : Configure as the 32kHz crystal output signal                    */
20763   GPIO_PADREGI_PAD33FNCSEL_GPIO33      = 3,     /*!< GPIO33 : Configure as GPIO33                                              */
20764   GPIO_PADREGI_PAD33FNCSEL_UA0CTS      = 5,     /*!< UA0CTS : Configure as the UART0 CTS input                                 */
20765   GPIO_PADREGI_PAD33FNCSEL_CT23        = 6,     /*!< CT23 : CTIMER connection 23                                               */
20766   GPIO_PADREGI_PAD33FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial trace data output signal                    */
20767 } GPIO_PADREGI_PAD33FNCSEL_Enum;
20768 
20769 /* ===========================================  GPIO PADREGI PAD33STRNG [10..10]  ============================================ */
20770 typedef enum {                                  /*!< GPIO_PADREGI_PAD33STRNG                                                   */
20771   GPIO_PADREGI_PAD33STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20772   GPIO_PADREGI_PAD33STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20773 } GPIO_PADREGI_PAD33STRNG_Enum;
20774 
20775 /* ============================================  GPIO PADREGI PAD33INPEN [9..9]  ============================================= */
20776 typedef enum {                                  /*!< GPIO_PADREGI_PAD33INPEN                                                   */
20777   GPIO_PADREGI_PAD33INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20778   GPIO_PADREGI_PAD33INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20779 } GPIO_PADREGI_PAD33INPEN_Enum;
20780 
20781 /* =============================================  GPIO PADREGI PAD33PULL [8..8]  ============================================= */
20782 typedef enum {                                  /*!< GPIO_PADREGI_PAD33PULL                                                    */
20783   GPIO_PADREGI_PAD33PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20784   GPIO_PADREGI_PAD33PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20785 } GPIO_PADREGI_PAD33PULL_Enum;
20786 
20787 /* ============================================  GPIO PADREGI PAD32FNCSEL [3..5]  ============================================ */
20788 typedef enum {                                  /*!< GPIO_PADREGI_PAD32FNCSEL                                                  */
20789   GPIO_PADREGI_PAD32FNCSEL_ADCSE4      = 0,     /*!< ADCSE4 : Configure as the analog input for ADC single ended
20790                                                      input 4                                                                   */
20791   GPIO_PADREGI_PAD32FNCSEL_NCE32       = 1,     /*!< NCE32 : IOM/MSPI nCE group 32                                             */
20792   GPIO_PADREGI_PAD32FNCSEL_CT15        = 2,     /*!< CT15 : CTIMER connection 15                                               */
20793   GPIO_PADREGI_PAD32FNCSEL_GPIO32      = 3,     /*!< GPIO32 : Configure as GPIO32                                              */
20794   GPIO_PADREGI_PAD32FNCSEL_SCCIO       = 4,     /*!< SCCIO : SCARD serial data input/output                                    */
20795   GPIO_PADREGI_PAD32FNCSEL_EXTLF       = 5,     /*!< EXTLF : External input to the LFRC oscillator                             */
20796   GPIO_PADREGI_PAD32FNCSEL_UA1CTS      = 7,     /*!< UA1CTS : Configure as the UART1 CTS input                                 */
20797 } GPIO_PADREGI_PAD32FNCSEL_Enum;
20798 
20799 /* ============================================  GPIO PADREGI PAD32STRNG [2..2]  ============================================= */
20800 typedef enum {                                  /*!< GPIO_PADREGI_PAD32STRNG                                                   */
20801   GPIO_PADREGI_PAD32STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20802   GPIO_PADREGI_PAD32STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20803 } GPIO_PADREGI_PAD32STRNG_Enum;
20804 
20805 /* ============================================  GPIO PADREGI PAD32INPEN [1..1]  ============================================= */
20806 typedef enum {                                  /*!< GPIO_PADREGI_PAD32INPEN                                                   */
20807   GPIO_PADREGI_PAD32INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20808   GPIO_PADREGI_PAD32INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20809 } GPIO_PADREGI_PAD32INPEN_Enum;
20810 
20811 /* =============================================  GPIO PADREGI PAD32PULL [0..0]  ============================================= */
20812 typedef enum {                                  /*!< GPIO_PADREGI_PAD32PULL                                                    */
20813   GPIO_PADREGI_PAD32PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20814   GPIO_PADREGI_PAD32PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20815 } GPIO_PADREGI_PAD32PULL_Enum;
20816 
20817 /* ========================================================  PADREGJ  ======================================================== */
20818 /* ============================================  GPIO PADREGJ PAD39RSEL [30..31]  ============================================ */
20819 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39RSEL                                                    */
20820   GPIO_PADREGJ_PAD39RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20821   GPIO_PADREGJ_PAD39RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20822   GPIO_PADREGJ_PAD39RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20823   GPIO_PADREGJ_PAD39RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20824 } GPIO_PADREGJ_PAD39RSEL_Enum;
20825 
20826 /* ===========================================  GPIO PADREGJ PAD39FNCSEL [27..29]  =========================================== */
20827 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39FNCSEL                                                  */
20828   GPIO_PADREGJ_PAD39FNCSEL_UART0TX     = 0,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
20829   GPIO_PADREGJ_PAD39FNCSEL_UART1TX     = 1,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
20830   GPIO_PADREGJ_PAD39FNCSEL_CT25        = 2,     /*!< CT25 : CTIMER connection 25                                               */
20831   GPIO_PADREGJ_PAD39FNCSEL_GPIO39      = 3,     /*!< GPIO39 : Configure as GPIO39                                              */
20832   GPIO_PADREGJ_PAD39FNCSEL_M4SCL       = 4,     /*!< M4SCL : Configure as the IOMSTR4 I2C SCL signal                           */
20833   GPIO_PADREGJ_PAD39FNCSEL_M4SCK       = 5,     /*!< M4SCK : Configure as the IOMSTR4 SPI SCK signal                           */
20834 } GPIO_PADREGJ_PAD39FNCSEL_Enum;
20835 
20836 /* ===========================================  GPIO PADREGJ PAD39STRNG [26..26]  ============================================ */
20837 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39STRNG                                                   */
20838   GPIO_PADREGJ_PAD39STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20839   GPIO_PADREGJ_PAD39STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20840 } GPIO_PADREGJ_PAD39STRNG_Enum;
20841 
20842 /* ===========================================  GPIO PADREGJ PAD39INPEN [25..25]  ============================================ */
20843 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39INPEN                                                   */
20844   GPIO_PADREGJ_PAD39INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20845   GPIO_PADREGJ_PAD39INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20846 } GPIO_PADREGJ_PAD39INPEN_Enum;
20847 
20848 /* ============================================  GPIO PADREGJ PAD39PULL [24..24]  ============================================ */
20849 typedef enum {                                  /*!< GPIO_PADREGJ_PAD39PULL                                                    */
20850   GPIO_PADREGJ_PAD39PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20851   GPIO_PADREGJ_PAD39PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20852 } GPIO_PADREGJ_PAD39PULL_Enum;
20853 
20854 /* ===========================================  GPIO PADREGJ PAD38FNCSEL [19..21]  =========================================== */
20855 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38FNCSEL                                                  */
20856   GPIO_PADREGJ_PAD38FNCSEL_TRIG3       = 0,     /*!< TRIG3 : Configure as the ADC Trigger 3 signal                             */
20857   GPIO_PADREGJ_PAD38FNCSEL_NCE38       = 1,     /*!< NCE38 : IOM/MSPI nCE group 38                                             */
20858   GPIO_PADREGJ_PAD38FNCSEL_UA0CTS      = 2,     /*!< UA0CTS : Configure as the UART0 CTS signal                                */
20859   GPIO_PADREGJ_PAD38FNCSEL_GPIO38      = 3,     /*!< GPIO38 : Configure as GPIO38                                              */
20860   GPIO_PADREGJ_PAD38FNCSEL_M3MOSI      = 5,     /*!< M3MOSI : Configure as the IOMSTR3 SPI MOSI output signal                  */
20861   GPIO_PADREGJ_PAD38FNCSEL_UART1RX     = 6,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
20862 } GPIO_PADREGJ_PAD38FNCSEL_Enum;
20863 
20864 /* ===========================================  GPIO PADREGJ PAD38STRNG [18..18]  ============================================ */
20865 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38STRNG                                                   */
20866   GPIO_PADREGJ_PAD38STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20867   GPIO_PADREGJ_PAD38STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20868 } GPIO_PADREGJ_PAD38STRNG_Enum;
20869 
20870 /* ===========================================  GPIO PADREGJ PAD38INPEN [17..17]  ============================================ */
20871 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38INPEN                                                   */
20872   GPIO_PADREGJ_PAD38INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20873   GPIO_PADREGJ_PAD38INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20874 } GPIO_PADREGJ_PAD38INPEN_Enum;
20875 
20876 /* ============================================  GPIO PADREGJ PAD38PULL [16..16]  ============================================ */
20877 typedef enum {                                  /*!< GPIO_PADREGJ_PAD38PULL                                                    */
20878   GPIO_PADREGJ_PAD38PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20879   GPIO_PADREGJ_PAD38PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20880 } GPIO_PADREGJ_PAD38PULL_Enum;
20881 
20882 /* ===========================================  GPIO PADREGJ PAD37PWRDN [15..15]  ============================================ */
20883 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37PWRDN                                                   */
20884   GPIO_PADREGJ_PAD37PWRDN_DIS          = 0,     /*!< DIS : Power switch disabled                                               */
20885   GPIO_PADREGJ_PAD37PWRDN_EN           = 1,     /*!< EN : Power switch enabled (switch to GND)                                 */
20886 } GPIO_PADREGJ_PAD37PWRDN_Enum;
20887 
20888 /* ===========================================  GPIO PADREGJ PAD37FNCSEL [11..13]  =========================================== */
20889 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37FNCSEL                                                  */
20890   GPIO_PADREGJ_PAD37FNCSEL_TRIG2       = 0,     /*!< TRIG2 : Configure as the ADC Trigger 2 signal                             */
20891   GPIO_PADREGJ_PAD37FNCSEL_NCE37       = 1,     /*!< NCE37 : IOM/MSPI nCE group 37                                             */
20892   GPIO_PADREGJ_PAD37FNCSEL_UA0RTS      = 2,     /*!< UA0RTS : Configure as the UART0 RTS output signal                         */
20893   GPIO_PADREGJ_PAD37FNCSEL_GPIO37      = 3,     /*!< GPIO37 : Configure as GPIO37                                              */
20894   GPIO_PADREGJ_PAD37FNCSEL_SCCIO       = 4,     /*!< SCCIO : SCARD serial data input/output                                    */
20895   GPIO_PADREGJ_PAD37FNCSEL_UART1TX     = 5,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
20896   GPIO_PADREGJ_PAD37FNCSEL_PDMCLK      = 6,     /*!< PDMCLK : Configure as the PDM CLK output signal                           */
20897   GPIO_PADREGJ_PAD37FNCSEL_CT29        = 7,     /*!< CT29 : CTIMER connection 29                                               */
20898 } GPIO_PADREGJ_PAD37FNCSEL_Enum;
20899 
20900 /* ===========================================  GPIO PADREGJ PAD37STRNG [10..10]  ============================================ */
20901 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37STRNG                                                   */
20902   GPIO_PADREGJ_PAD37STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20903   GPIO_PADREGJ_PAD37STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20904 } GPIO_PADREGJ_PAD37STRNG_Enum;
20905 
20906 /* ============================================  GPIO PADREGJ PAD37INPEN [9..9]  ============================================= */
20907 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37INPEN                                                   */
20908   GPIO_PADREGJ_PAD37INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20909   GPIO_PADREGJ_PAD37INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20910 } GPIO_PADREGJ_PAD37INPEN_Enum;
20911 
20912 /* =============================================  GPIO PADREGJ PAD37PULL [8..8]  ============================================= */
20913 typedef enum {                                  /*!< GPIO_PADREGJ_PAD37PULL                                                    */
20914   GPIO_PADREGJ_PAD37PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20915   GPIO_PADREGJ_PAD37PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20916 } GPIO_PADREGJ_PAD37PULL_Enum;
20917 
20918 /* ============================================  GPIO PADREGJ PAD36PWRUP [6..6]  ============================================= */
20919 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36PWRUP                                                   */
20920   GPIO_PADREGJ_PAD36PWRUP_DIS          = 0,     /*!< DIS : Power switch disabled                                               */
20921   GPIO_PADREGJ_PAD36PWRUP_EN           = 1,     /*!< EN : Power switch enabled (switched to VDD)                               */
20922 } GPIO_PADREGJ_PAD36PWRUP_Enum;
20923 
20924 /* ============================================  GPIO PADREGJ PAD36FNCSEL [3..5]  ============================================ */
20925 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36FNCSEL                                                  */
20926   GPIO_PADREGJ_PAD36FNCSEL_TRIG1       = 0,     /*!< TRIG1 : Configure as the ADC Trigger 1 signal                             */
20927   GPIO_PADREGJ_PAD36FNCSEL_NCE36       = 1,     /*!< NCE36 : IOM/MSPI nCE group 36                                             */
20928   GPIO_PADREGJ_PAD36FNCSEL_UART1RX     = 2,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
20929   GPIO_PADREGJ_PAD36FNCSEL_GPIO36      = 3,     /*!< GPIO36 : Configure as GPIO36                                              */
20930   GPIO_PADREGJ_PAD36FNCSEL_32kHzXT     = 4,     /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal            */
20931   GPIO_PADREGJ_PAD36FNCSEL_UA1CTS      = 5,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
20932   GPIO_PADREGJ_PAD36FNCSEL_UA0CTS      = 6,     /*!< UA0CTS : Configure as the UART0 CTS input signal                          */
20933   GPIO_PADREGJ_PAD36FNCSEL_PDMDATA     = 7,     /*!< PDMDATA : PDM serial data input                                           */
20934 } GPIO_PADREGJ_PAD36FNCSEL_Enum;
20935 
20936 /* ============================================  GPIO PADREGJ PAD36STRNG [2..2]  ============================================= */
20937 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36STRNG                                                   */
20938   GPIO_PADREGJ_PAD36STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20939   GPIO_PADREGJ_PAD36STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20940 } GPIO_PADREGJ_PAD36STRNG_Enum;
20941 
20942 /* ============================================  GPIO PADREGJ PAD36INPEN [1..1]  ============================================= */
20943 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36INPEN                                                   */
20944   GPIO_PADREGJ_PAD36INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20945   GPIO_PADREGJ_PAD36INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20946 } GPIO_PADREGJ_PAD36INPEN_Enum;
20947 
20948 /* =============================================  GPIO PADREGJ PAD36PULL [0..0]  ============================================= */
20949 typedef enum {                                  /*!< GPIO_PADREGJ_PAD36PULL                                                    */
20950   GPIO_PADREGJ_PAD36PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20951   GPIO_PADREGJ_PAD36PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20952 } GPIO_PADREGJ_PAD36PULL_Enum;
20953 
20954 /* ========================================================  PADREGK  ======================================================== */
20955 /* ============================================  GPIO PADREGK PAD43RSEL [30..31]  ============================================ */
20956 typedef enum {                                  /*!< GPIO_PADREGK_PAD43RSEL                                                    */
20957   GPIO_PADREGK_PAD43RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20958   GPIO_PADREGK_PAD43RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20959   GPIO_PADREGK_PAD43RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20960   GPIO_PADREGK_PAD43RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20961 } GPIO_PADREGK_PAD43RSEL_Enum;
20962 
20963 /* ===========================================  GPIO PADREGK PAD43FNCSEL [27..29]  =========================================== */
20964 typedef enum {                                  /*!< GPIO_PADREGK_PAD43FNCSEL                                                  */
20965   GPIO_PADREGK_PAD43FNCSEL_UART1RX     = 0,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
20966   GPIO_PADREGK_PAD43FNCSEL_NCE43       = 1,     /*!< NCE43 : IOM/MSPI nCE group 43                                             */
20967   GPIO_PADREGK_PAD43FNCSEL_CT18        = 2,     /*!< CT18 : CTIMER connection 18                                               */
20968   GPIO_PADREGK_PAD43FNCSEL_GPIO43      = 3,     /*!< GPIO43 : Configure as GPIO43                                              */
20969   GPIO_PADREGK_PAD43FNCSEL_M3SDAWIR3   = 4,     /*!< M3SDAWIR3 : Configure as the IOMSTR3 I2C SDA or SPI WIR3 signal           */
20970   GPIO_PADREGK_PAD43FNCSEL_M3MISO      = 5,     /*!< M3MISO : Configure as the IOMSTR3 SPI MISO signal                         */
20971 } GPIO_PADREGK_PAD43FNCSEL_Enum;
20972 
20973 /* ===========================================  GPIO PADREGK PAD43STRNG [26..26]  ============================================ */
20974 typedef enum {                                  /*!< GPIO_PADREGK_PAD43STRNG                                                   */
20975   GPIO_PADREGK_PAD43STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
20976   GPIO_PADREGK_PAD43STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
20977 } GPIO_PADREGK_PAD43STRNG_Enum;
20978 
20979 /* ===========================================  GPIO PADREGK PAD43INPEN [25..25]  ============================================ */
20980 typedef enum {                                  /*!< GPIO_PADREGK_PAD43INPEN                                                   */
20981   GPIO_PADREGK_PAD43INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
20982   GPIO_PADREGK_PAD43INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
20983 } GPIO_PADREGK_PAD43INPEN_Enum;
20984 
20985 /* ============================================  GPIO PADREGK PAD43PULL [24..24]  ============================================ */
20986 typedef enum {                                  /*!< GPIO_PADREGK_PAD43PULL                                                    */
20987   GPIO_PADREGK_PAD43PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
20988   GPIO_PADREGK_PAD43PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
20989 } GPIO_PADREGK_PAD43PULL_Enum;
20990 
20991 /* ============================================  GPIO PADREGK PAD42RSEL [22..23]  ============================================ */
20992 typedef enum {                                  /*!< GPIO_PADREGK_PAD42RSEL                                                    */
20993   GPIO_PADREGK_PAD42RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
20994   GPIO_PADREGK_PAD42RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
20995   GPIO_PADREGK_PAD42RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
20996   GPIO_PADREGK_PAD42RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
20997 } GPIO_PADREGK_PAD42RSEL_Enum;
20998 
20999 /* ===========================================  GPIO PADREGK PAD42FNCSEL [19..21]  =========================================== */
21000 typedef enum {                                  /*!< GPIO_PADREGK_PAD42FNCSEL                                                  */
21001   GPIO_PADREGK_PAD42FNCSEL_UART1TX     = 0,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
21002   GPIO_PADREGK_PAD42FNCSEL_NCE42       = 1,     /*!< NCE42 : IOM/MSPI nCE group 42                                             */
21003   GPIO_PADREGK_PAD42FNCSEL_CT16        = 2,     /*!< CT16 : CTIMER connection 16                                               */
21004   GPIO_PADREGK_PAD42FNCSEL_GPIO42      = 3,     /*!< GPIO42 : Configure as GPIO42                                              */
21005   GPIO_PADREGK_PAD42FNCSEL_M3SCL       = 4,     /*!< M3SCL : Configure as the IOMSTR3 I2C SCL clock I/O signal                 */
21006   GPIO_PADREGK_PAD42FNCSEL_M3SCK       = 5,     /*!< M3SCK : Configure as the IOMSTR3 SPI SCK output                           */
21007 } GPIO_PADREGK_PAD42FNCSEL_Enum;
21008 
21009 /* ===========================================  GPIO PADREGK PAD42STRNG [18..18]  ============================================ */
21010 typedef enum {                                  /*!< GPIO_PADREGK_PAD42STRNG                                                   */
21011   GPIO_PADREGK_PAD42STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21012   GPIO_PADREGK_PAD42STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21013 } GPIO_PADREGK_PAD42STRNG_Enum;
21014 
21015 /* ===========================================  GPIO PADREGK PAD42INPEN [17..17]  ============================================ */
21016 typedef enum {                                  /*!< GPIO_PADREGK_PAD42INPEN                                                   */
21017   GPIO_PADREGK_PAD42INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21018   GPIO_PADREGK_PAD42INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21019 } GPIO_PADREGK_PAD42INPEN_Enum;
21020 
21021 /* ============================================  GPIO PADREGK PAD42PULL [16..16]  ============================================ */
21022 typedef enum {                                  /*!< GPIO_PADREGK_PAD42PULL                                                    */
21023   GPIO_PADREGK_PAD42PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21024   GPIO_PADREGK_PAD42PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21025 } GPIO_PADREGK_PAD42PULL_Enum;
21026 
21027 /* ===========================================  GPIO PADREGK PAD41PWRDN [15..15]  ============================================ */
21028 typedef enum {                                  /*!< GPIO_PADREGK_PAD41PWRDN                                                   */
21029   GPIO_PADREGK_PAD41PWRDN_DIS          = 0,     /*!< DIS : Power switch disabled                                               */
21030   GPIO_PADREGK_PAD41PWRDN_EN           = 1,     /*!< EN : Power switch enabled (Switch pad to VSS)                             */
21031 } GPIO_PADREGK_PAD41PWRDN_Enum;
21032 
21033 /* ===========================================  GPIO PADREGK PAD41FNCSEL [11..13]  =========================================== */
21034 typedef enum {                                  /*!< GPIO_PADREGK_PAD41FNCSEL                                                  */
21035   GPIO_PADREGK_PAD41FNCSEL_NCE41       = 0,     /*!< NCE41 : IOM/MSPI nCE group 41                                             */
21036   GPIO_PADREGK_PAD41FNCSEL_SWO         = 2,     /*!< SWO : Configure as the serial wire debug SWO signal                       */
21037   GPIO_PADREGK_PAD41FNCSEL_GPIO41      = 3,     /*!< GPIO41 : Configure as GPIO41                                              */
21038   GPIO_PADREGK_PAD41FNCSEL_I2SWCLK     = 4,     /*!< I2SWCLK : I2S word clock input                                            */
21039   GPIO_PADREGK_PAD41FNCSEL_UA1RTS      = 5,     /*!< UA1RTS : Configure as the UART1 RTS output signal                         */
21040   GPIO_PADREGK_PAD41FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
21041   GPIO_PADREGK_PAD41FNCSEL_UA0RTS      = 7,     /*!< UA0RTS : Configure as the UART0 RTS output signal                         */
21042 } GPIO_PADREGK_PAD41FNCSEL_Enum;
21043 
21044 /* ===========================================  GPIO PADREGK PAD41STRNG [10..10]  ============================================ */
21045 typedef enum {                                  /*!< GPIO_PADREGK_PAD41STRNG                                                   */
21046   GPIO_PADREGK_PAD41STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21047   GPIO_PADREGK_PAD41STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21048 } GPIO_PADREGK_PAD41STRNG_Enum;
21049 
21050 /* ============================================  GPIO PADREGK PAD41INPEN [9..9]  ============================================= */
21051 typedef enum {                                  /*!< GPIO_PADREGK_PAD41INPEN                                                   */
21052   GPIO_PADREGK_PAD41INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21053   GPIO_PADREGK_PAD41INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21054 } GPIO_PADREGK_PAD41INPEN_Enum;
21055 
21056 /* =============================================  GPIO PADREGK PAD41PULL [8..8]  ============================================= */
21057 typedef enum {                                  /*!< GPIO_PADREGK_PAD41PULL                                                    */
21058   GPIO_PADREGK_PAD41PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21059   GPIO_PADREGK_PAD41PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21060 } GPIO_PADREGK_PAD41PULL_Enum;
21061 
21062 /* =============================================  GPIO PADREGK PAD40RSEL [6..7]  ============================================= */
21063 typedef enum {                                  /*!< GPIO_PADREGK_PAD40RSEL                                                    */
21064   GPIO_PADREGK_PAD40RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21065   GPIO_PADREGK_PAD40RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21066   GPIO_PADREGK_PAD40RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21067   GPIO_PADREGK_PAD40RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21068 } GPIO_PADREGK_PAD40RSEL_Enum;
21069 
21070 /* ============================================  GPIO PADREGK PAD40FNCSEL [3..5]  ============================================ */
21071 typedef enum {                                  /*!< GPIO_PADREGK_PAD40FNCSEL                                                  */
21072   GPIO_PADREGK_PAD40FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
21073   GPIO_PADREGK_PAD40FNCSEL_UART1RX     = 1,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
21074   GPIO_PADREGK_PAD40FNCSEL_TRIG0       = 2,     /*!< TRIG0 : Configure as the ADC Trigger 0 signal                             */
21075   GPIO_PADREGK_PAD40FNCSEL_GPIO40      = 3,     /*!< GPIO40 : Configure as GPIO40                                              */
21076   GPIO_PADREGK_PAD40FNCSEL_M4SDAWIR3   = 4,     /*!< M4SDAWIR3 : Configure as the IOMSTR4 I2C SDA or SPI WIR3 signal           */
21077   GPIO_PADREGK_PAD40FNCSEL_M4MISO      = 5,     /*!< M4MISO : Configure as the IOMSTR4 SPI MISO input signal                   */
21078 } GPIO_PADREGK_PAD40FNCSEL_Enum;
21079 
21080 /* ============================================  GPIO PADREGK PAD40STRNG [2..2]  ============================================= */
21081 typedef enum {                                  /*!< GPIO_PADREGK_PAD40STRNG                                                   */
21082   GPIO_PADREGK_PAD40STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21083   GPIO_PADREGK_PAD40STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21084 } GPIO_PADREGK_PAD40STRNG_Enum;
21085 
21086 /* ============================================  GPIO PADREGK PAD40INPEN [1..1]  ============================================= */
21087 typedef enum {                                  /*!< GPIO_PADREGK_PAD40INPEN                                                   */
21088   GPIO_PADREGK_PAD40INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21089   GPIO_PADREGK_PAD40INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21090 } GPIO_PADREGK_PAD40INPEN_Enum;
21091 
21092 /* =============================================  GPIO PADREGK PAD40PULL [0..0]  ============================================= */
21093 typedef enum {                                  /*!< GPIO_PADREGK_PAD40PULL                                                    */
21094   GPIO_PADREGK_PAD40PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21095   GPIO_PADREGK_PAD40PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21096 } GPIO_PADREGK_PAD40PULL_Enum;
21097 
21098 /* ========================================================  PADREGL  ======================================================== */
21099 /* ===========================================  GPIO PADREGL PAD47FNCSEL [27..29]  =========================================== */
21100 typedef enum {                                  /*!< GPIO_PADREGL_PAD47FNCSEL                                                  */
21101   GPIO_PADREGL_PAD47FNCSEL_32kHzXT     = 0,     /*!< 32kHzXT : Configure as the 32kHz output clock from the crystal            */
21102   GPIO_PADREGL_PAD47FNCSEL_NCE47       = 1,     /*!< NCE47 : IOM/MSPI nCE group 47                                             */
21103   GPIO_PADREGL_PAD47FNCSEL_CT26        = 2,     /*!< CT26 : CTIMER connection 26                                               */
21104   GPIO_PADREGL_PAD47FNCSEL_GPIO47      = 3,     /*!< GPIO47 : Configure as GPIO47                                              */
21105   GPIO_PADREGL_PAD47FNCSEL_M5MOSI      = 5,     /*!< M5MOSI : Configure as the IOMSTR5 SPI MOSI output signal                  */
21106   GPIO_PADREGL_PAD47FNCSEL_UART1RX     = 6,     /*!< UART1RX : Configure as the UART1 RX input signal                          */
21107 } GPIO_PADREGL_PAD47FNCSEL_Enum;
21108 
21109 /* ===========================================  GPIO PADREGL PAD47STRNG [26..26]  ============================================ */
21110 typedef enum {                                  /*!< GPIO_PADREGL_PAD47STRNG                                                   */
21111   GPIO_PADREGL_PAD47STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21112   GPIO_PADREGL_PAD47STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21113 } GPIO_PADREGL_PAD47STRNG_Enum;
21114 
21115 /* ===========================================  GPIO PADREGL PAD47INPEN [25..25]  ============================================ */
21116 typedef enum {                                  /*!< GPIO_PADREGL_PAD47INPEN                                                   */
21117   GPIO_PADREGL_PAD47INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21118   GPIO_PADREGL_PAD47INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21119 } GPIO_PADREGL_PAD47INPEN_Enum;
21120 
21121 /* ============================================  GPIO PADREGL PAD47PULL [24..24]  ============================================ */
21122 typedef enum {                                  /*!< GPIO_PADREGL_PAD47PULL                                                    */
21123   GPIO_PADREGL_PAD47PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21124   GPIO_PADREGL_PAD47PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21125 } GPIO_PADREGL_PAD47PULL_Enum;
21126 
21127 /* ===========================================  GPIO PADREGL PAD46FNCSEL [19..21]  =========================================== */
21128 typedef enum {                                  /*!< GPIO_PADREGL_PAD46FNCSEL                                                  */
21129   GPIO_PADREGL_PAD46FNCSEL_32khz_XT    = 0,     /*!< 32khz_XT : Configure as the 32kHz output clock from the crystal           */
21130   GPIO_PADREGL_PAD46FNCSEL_NCE46       = 1,     /*!< NCE46 : IOM/MSPI nCE group 46                                             */
21131   GPIO_PADREGL_PAD46FNCSEL_CT24        = 2,     /*!< CT24 : CTIMER connection 24                                               */
21132   GPIO_PADREGL_PAD46FNCSEL_GPIO46      = 3,     /*!< GPIO46 : Configure as GPIO46                                              */
21133   GPIO_PADREGL_PAD46FNCSEL_SCCRST      = 4,     /*!< SCCRST : SCARD reset output                                               */
21134   GPIO_PADREGL_PAD46FNCSEL_PDMCLK      = 5,     /*!< PDMCLK : PDM serial clock output                                          */
21135   GPIO_PADREGL_PAD46FNCSEL_UART1TX     = 6,     /*!< UART1TX : Configure as the UART1 TX output signal                         */
21136   GPIO_PADREGL_PAD46FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial wire debug SWO signal                       */
21137 } GPIO_PADREGL_PAD46FNCSEL_Enum;
21138 
21139 /* ===========================================  GPIO PADREGL PAD46STRNG [18..18]  ============================================ */
21140 typedef enum {                                  /*!< GPIO_PADREGL_PAD46STRNG                                                   */
21141   GPIO_PADREGL_PAD46STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21142   GPIO_PADREGL_PAD46STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21143 } GPIO_PADREGL_PAD46STRNG_Enum;
21144 
21145 /* ===========================================  GPIO PADREGL PAD46INPEN [17..17]  ============================================ */
21146 typedef enum {                                  /*!< GPIO_PADREGL_PAD46INPEN                                                   */
21147   GPIO_PADREGL_PAD46INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21148   GPIO_PADREGL_PAD46INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21149 } GPIO_PADREGL_PAD46INPEN_Enum;
21150 
21151 /* ============================================  GPIO PADREGL PAD46PULL [16..16]  ============================================ */
21152 typedef enum {                                  /*!< GPIO_PADREGL_PAD46PULL                                                    */
21153   GPIO_PADREGL_PAD46PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21154   GPIO_PADREGL_PAD46PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21155 } GPIO_PADREGL_PAD46PULL_Enum;
21156 
21157 /* ===========================================  GPIO PADREGL PAD45FNCSEL [11..13]  =========================================== */
21158 typedef enum {                                  /*!< GPIO_PADREGL_PAD45FNCSEL                                                  */
21159   GPIO_PADREGL_PAD45FNCSEL_UA1CTS      = 0,     /*!< UA1CTS : Configure as the UART1 CTS input signal                          */
21160   GPIO_PADREGL_PAD45FNCSEL_NCE45       = 1,     /*!< NCE45 : IOM/MSPI nCE group 45                                             */
21161   GPIO_PADREGL_PAD45FNCSEL_CT22        = 2,     /*!< CT22 : CTIMER connection 22                                               */
21162   GPIO_PADREGL_PAD45FNCSEL_GPIO45      = 3,     /*!< GPIO45 : Configure as GPIO45                                              */
21163   GPIO_PADREGL_PAD45FNCSEL_I2SDAT      = 4,     /*!< I2SDAT : I2S serial data output                                           */
21164   GPIO_PADREGL_PAD45FNCSEL_PDMDATA     = 5,     /*!< PDMDATA : PDM serial data input                                           */
21165   GPIO_PADREGL_PAD45FNCSEL_UART0RX     = 6,     /*!< UART0RX : Configure as the SPI channel 5 nCE signal from IOMSTR5          */
21166   GPIO_PADREGL_PAD45FNCSEL_SWO         = 7,     /*!< SWO : Configure as the serial wire debug SWO signal                       */
21167 } GPIO_PADREGL_PAD45FNCSEL_Enum;
21168 
21169 /* ===========================================  GPIO PADREGL PAD45STRNG [10..10]  ============================================ */
21170 typedef enum {                                  /*!< GPIO_PADREGL_PAD45STRNG                                                   */
21171   GPIO_PADREGL_PAD45STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21172   GPIO_PADREGL_PAD45STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21173 } GPIO_PADREGL_PAD45STRNG_Enum;
21174 
21175 /* ============================================  GPIO PADREGL PAD45INPEN [9..9]  ============================================= */
21176 typedef enum {                                  /*!< GPIO_PADREGL_PAD45INPEN                                                   */
21177   GPIO_PADREGL_PAD45INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21178   GPIO_PADREGL_PAD45INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21179 } GPIO_PADREGL_PAD45INPEN_Enum;
21180 
21181 /* =============================================  GPIO PADREGL PAD45PULL [8..8]  ============================================= */
21182 typedef enum {                                  /*!< GPIO_PADREGL_PAD45PULL                                                    */
21183   GPIO_PADREGL_PAD45PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21184   GPIO_PADREGL_PAD45PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21185 } GPIO_PADREGL_PAD45PULL_Enum;
21186 
21187 /* ============================================  GPIO PADREGL PAD44FNCSEL [3..5]  ============================================ */
21188 typedef enum {                                  /*!< GPIO_PADREGL_PAD44FNCSEL                                                  */
21189   GPIO_PADREGL_PAD44FNCSEL_UA1RTS      = 0,     /*!< UA1RTS : Configure as the UART1 RTS output signal                         */
21190   GPIO_PADREGL_PAD44FNCSEL_NCE44       = 1,     /*!< NCE44 : IOM/MSPI nCE group 44                                             */
21191   GPIO_PADREGL_PAD44FNCSEL_CT20        = 2,     /*!< CT20 : CTIMER connection 20                                               */
21192   GPIO_PADREGL_PAD44FNCSEL_GPIO44      = 3,     /*!< GPIO44 : Configure as GPIO44                                              */
21193   GPIO_PADREGL_PAD44FNCSEL_M4MOSI      = 5,     /*!< M4MOSI : Configure as the IOMSTR4 SPI MOSI signal                         */
21194   GPIO_PADREGL_PAD44FNCSEL_UART0TX     = 6,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
21195 } GPIO_PADREGL_PAD44FNCSEL_Enum;
21196 
21197 /* ============================================  GPIO PADREGL PAD44STRNG [2..2]  ============================================= */
21198 typedef enum {                                  /*!< GPIO_PADREGL_PAD44STRNG                                                   */
21199   GPIO_PADREGL_PAD44STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21200   GPIO_PADREGL_PAD44STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21201 } GPIO_PADREGL_PAD44STRNG_Enum;
21202 
21203 /* ============================================  GPIO PADREGL PAD44INPEN [1..1]  ============================================= */
21204 typedef enum {                                  /*!< GPIO_PADREGL_PAD44INPEN                                                   */
21205   GPIO_PADREGL_PAD44INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21206   GPIO_PADREGL_PAD44INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21207 } GPIO_PADREGL_PAD44INPEN_Enum;
21208 
21209 /* =============================================  GPIO PADREGL PAD44PULL [0..0]  ============================================= */
21210 typedef enum {                                  /*!< GPIO_PADREGL_PAD44PULL                                                    */
21211   GPIO_PADREGL_PAD44PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21212   GPIO_PADREGL_PAD44PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21213 } GPIO_PADREGL_PAD44PULL_Enum;
21214 
21215 /* ========================================================  PADREGM  ======================================================== */
21216 /* ============================================  GPIO PADREGM PAD49RSEL [14..15]  ============================================ */
21217 typedef enum {                                  /*!< GPIO_PADREGM_PAD49RSEL                                                    */
21218   GPIO_PADREGM_PAD49RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21219   GPIO_PADREGM_PAD49RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21220   GPIO_PADREGM_PAD49RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21221   GPIO_PADREGM_PAD49RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21222 } GPIO_PADREGM_PAD49RSEL_Enum;
21223 
21224 /* ===========================================  GPIO PADREGM PAD49FNCSEL [11..13]  =========================================== */
21225 typedef enum {                                  /*!< GPIO_PADREGM_PAD49FNCSEL                                                  */
21226   GPIO_PADREGM_PAD49FNCSEL_UART0RX     = 0,     /*!< UART0RX : Configure as the UART0 RX input signal                          */
21227   GPIO_PADREGM_PAD49FNCSEL_NCE49       = 1,     /*!< NCE49 : IOM/MSPPI nCE group 49                                            */
21228   GPIO_PADREGM_PAD49FNCSEL_CT30        = 2,     /*!< CT30 : CTIMER connection 30                                               */
21229   GPIO_PADREGM_PAD49FNCSEL_GPIO49      = 3,     /*!< GPIO49 : Configure as GPIO49                                              */
21230   GPIO_PADREGM_PAD49FNCSEL_M5SDAWIR3   = 4,     /*!< M5SDAWIR3 : Configure as the IOMSTR5 I2C SDA or SPI WIR3 signal           */
21231   GPIO_PADREGM_PAD49FNCSEL_M5MISO      = 5,     /*!< M5MISO : Configure as the IOMSTR5 SPI MISO input signal                   */
21232 } GPIO_PADREGM_PAD49FNCSEL_Enum;
21233 
21234 /* ===========================================  GPIO PADREGM PAD49STRNG [10..10]  ============================================ */
21235 typedef enum {                                  /*!< GPIO_PADREGM_PAD49STRNG                                                   */
21236   GPIO_PADREGM_PAD49STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21237   GPIO_PADREGM_PAD49STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21238 } GPIO_PADREGM_PAD49STRNG_Enum;
21239 
21240 /* ============================================  GPIO PADREGM PAD49INPEN [9..9]  ============================================= */
21241 typedef enum {                                  /*!< GPIO_PADREGM_PAD49INPEN                                                   */
21242   GPIO_PADREGM_PAD49INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21243   GPIO_PADREGM_PAD49INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21244 } GPIO_PADREGM_PAD49INPEN_Enum;
21245 
21246 /* =============================================  GPIO PADREGM PAD49PULL [8..8]  ============================================= */
21247 typedef enum {                                  /*!< GPIO_PADREGM_PAD49PULL                                                    */
21248   GPIO_PADREGM_PAD49PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21249   GPIO_PADREGM_PAD49PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21250 } GPIO_PADREGM_PAD49PULL_Enum;
21251 
21252 /* =============================================  GPIO PADREGM PAD48RSEL [6..7]  ============================================= */
21253 typedef enum {                                  /*!< GPIO_PADREGM_PAD48RSEL                                                    */
21254   GPIO_PADREGM_PAD48RSEL_PULL1_5K      = 0,     /*!< PULL1_5K : Pullup is ~1.5 KOhms                                           */
21255   GPIO_PADREGM_PAD48RSEL_PULL6K        = 1,     /*!< PULL6K : Pullup is ~6 KOhms                                               */
21256   GPIO_PADREGM_PAD48RSEL_PULL12K       = 2,     /*!< PULL12K : Pullup is ~12 KOhms                                             */
21257   GPIO_PADREGM_PAD48RSEL_PULL24K       = 3,     /*!< PULL24K : Pullup is ~24 KOhms                                             */
21258 } GPIO_PADREGM_PAD48RSEL_Enum;
21259 
21260 /* ============================================  GPIO PADREGM PAD48FNCSEL [3..5]  ============================================ */
21261 typedef enum {                                  /*!< GPIO_PADREGM_PAD48FNCSEL                                                  */
21262   GPIO_PADREGM_PAD48FNCSEL_UART0TX     = 0,     /*!< UART0TX : Configure as the UART0 TX output signal                         */
21263   GPIO_PADREGM_PAD48FNCSEL_NCE48       = 1,     /*!< NCE48 : IOM/MSPI nCE group 48                                             */
21264   GPIO_PADREGM_PAD48FNCSEL_CT28        = 2,     /*!< CT28 : CTIMER connection 28                                               */
21265   GPIO_PADREGM_PAD48FNCSEL_GPIO48      = 3,     /*!< GPIO48 : Configure as GPIO48                                              */
21266   GPIO_PADREGM_PAD48FNCSEL_M5SCL       = 4,     /*!< M5SCL : Configure as the IOMSTR5 I2C SCL clock I/O signal                 */
21267   GPIO_PADREGM_PAD48FNCSEL_M5SCK       = 5,     /*!< M5SCK : Configure as the IOMSTR5 SPI SCK output                           */
21268 } GPIO_PADREGM_PAD48FNCSEL_Enum;
21269 
21270 /* ============================================  GPIO PADREGM PAD48STRNG [2..2]  ============================================= */
21271 typedef enum {                                  /*!< GPIO_PADREGM_PAD48STRNG                                                   */
21272   GPIO_PADREGM_PAD48STRNG_LOW          = 0,     /*!< LOW : Low drive strength                                                  */
21273   GPIO_PADREGM_PAD48STRNG_HIGH         = 1,     /*!< HIGH : High drive strength                                                */
21274 } GPIO_PADREGM_PAD48STRNG_Enum;
21275 
21276 /* ============================================  GPIO PADREGM PAD48INPEN [1..1]  ============================================= */
21277 typedef enum {                                  /*!< GPIO_PADREGM_PAD48INPEN                                                   */
21278   GPIO_PADREGM_PAD48INPEN_DIS          = 0,     /*!< DIS : Pad input disabled                                                  */
21279   GPIO_PADREGM_PAD48INPEN_EN           = 1,     /*!< EN : Pad input enabled                                                    */
21280 } GPIO_PADREGM_PAD48INPEN_Enum;
21281 
21282 /* =============================================  GPIO PADREGM PAD48PULL [0..0]  ============================================= */
21283 typedef enum {                                  /*!< GPIO_PADREGM_PAD48PULL                                                    */
21284   GPIO_PADREGM_PAD48PULL_DIS           = 0,     /*!< DIS : Pullup disabled                                                     */
21285   GPIO_PADREGM_PAD48PULL_EN            = 1,     /*!< EN : Pullup enabled                                                       */
21286 } GPIO_PADREGM_PAD48PULL_Enum;
21287 
21288 /* =========================================================  CFGA  ========================================================== */
21289 /* =============================================  GPIO CFGA GPIO7INTD [31..31]  ============================================== */
21290 typedef enum {                                  /*!< GPIO_CFGA_GPIO7INTD                                                       */
21291   GPIO_CFGA_GPIO7INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low                           */
21292   GPIO_CFGA_GPIO7INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high                         */
21293 } GPIO_CFGA_GPIO7INTD_Enum;
21294 
21295 /* ============================================  GPIO CFGA GPIO7OUTCFG [29..30]  ============================================= */
21296 typedef enum {                                  /*!< GPIO_CFGA_GPIO7OUTCFG                                                     */
21297   GPIO_CFGA_GPIO7OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21298   GPIO_CFGA_GPIO7OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21299   GPIO_CFGA_GPIO7OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21300   GPIO_CFGA_GPIO7OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21301 } GPIO_CFGA_GPIO7OUTCFG_Enum;
21302 
21303 /* =============================================  GPIO CFGA GPIO7INCFG [28..28]  ============================================= */
21304 typedef enum {                                  /*!< GPIO_CFGA_GPIO7INCFG                                                      */
21305   GPIO_CFGA_GPIO7INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21306   GPIO_CFGA_GPIO7INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21307 } GPIO_CFGA_GPIO7INCFG_Enum;
21308 
21309 /* =============================================  GPIO CFGA GPIO6INTD [27..27]  ============================================== */
21310 typedef enum {                                  /*!< GPIO_CFGA_GPIO6INTD                                                       */
21311   GPIO_CFGA_GPIO6INTD_INTDIS           = 0,     /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition                      */
21312   GPIO_CFGA_GPIO6INTD_INTBOTH          = 1,     /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
21313                                                      to low GPIO transition                                                    */
21314 } GPIO_CFGA_GPIO6INTD_Enum;
21315 
21316 /* ============================================  GPIO CFGA GPIO6OUTCFG [25..26]  ============================================= */
21317 typedef enum {                                  /*!< GPIO_CFGA_GPIO6OUTCFG                                                     */
21318   GPIO_CFGA_GPIO6OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21319   GPIO_CFGA_GPIO6OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21320   GPIO_CFGA_GPIO6OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21321   GPIO_CFGA_GPIO6OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21322 } GPIO_CFGA_GPIO6OUTCFG_Enum;
21323 
21324 /* =============================================  GPIO CFGA GPIO6INCFG [24..24]  ============================================= */
21325 typedef enum {                                  /*!< GPIO_CFGA_GPIO6INCFG                                                      */
21326   GPIO_CFGA_GPIO6INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21327   GPIO_CFGA_GPIO6INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21328 } GPIO_CFGA_GPIO6INCFG_Enum;
21329 
21330 /* =============================================  GPIO CFGA GPIO5INTD [23..23]  ============================================== */
21331 typedef enum {                                  /*!< GPIO_CFGA_GPIO5INTD                                                       */
21332   GPIO_CFGA_GPIO5INTD_INTDIS           = 0,     /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition                      */
21333   GPIO_CFGA_GPIO5INTD_INTBOTH          = 1,     /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
21334                                                      to low GPIO transition                                                    */
21335 } GPIO_CFGA_GPIO5INTD_Enum;
21336 
21337 /* ============================================  GPIO CFGA GPIO5OUTCFG [21..22]  ============================================= */
21338 typedef enum {                                  /*!< GPIO_CFGA_GPIO5OUTCFG                                                     */
21339   GPIO_CFGA_GPIO5OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21340   GPIO_CFGA_GPIO5OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21341   GPIO_CFGA_GPIO5OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21342   GPIO_CFGA_GPIO5OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21343 } GPIO_CFGA_GPIO5OUTCFG_Enum;
21344 
21345 /* =============================================  GPIO CFGA GPIO5INCFG [20..20]  ============================================= */
21346 typedef enum {                                  /*!< GPIO_CFGA_GPIO5INCFG                                                      */
21347   GPIO_CFGA_GPIO5INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21348   GPIO_CFGA_GPIO5INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21349 } GPIO_CFGA_GPIO5INCFG_Enum;
21350 
21351 /* =============================================  GPIO CFGA GPIO4INTD [19..19]  ============================================== */
21352 typedef enum {                                  /*!< GPIO_CFGA_GPIO4INTD                                                       */
21353   GPIO_CFGA_GPIO4INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low                           */
21354   GPIO_CFGA_GPIO4INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high                         */
21355 } GPIO_CFGA_GPIO4INTD_Enum;
21356 
21357 /* ============================================  GPIO CFGA GPIO4OUTCFG [17..18]  ============================================= */
21358 typedef enum {                                  /*!< GPIO_CFGA_GPIO4OUTCFG                                                     */
21359   GPIO_CFGA_GPIO4OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21360   GPIO_CFGA_GPIO4OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21361   GPIO_CFGA_GPIO4OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21362   GPIO_CFGA_GPIO4OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21363 } GPIO_CFGA_GPIO4OUTCFG_Enum;
21364 
21365 /* =============================================  GPIO CFGA GPIO4INCFG [16..16]  ============================================= */
21366 typedef enum {                                  /*!< GPIO_CFGA_GPIO4INCFG                                                      */
21367   GPIO_CFGA_GPIO4INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21368   GPIO_CFGA_GPIO4INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21369 } GPIO_CFGA_GPIO4INCFG_Enum;
21370 
21371 /* =============================================  GPIO CFGA GPIO3INTD [15..15]  ============================================== */
21372 typedef enum {                                  /*!< GPIO_CFGA_GPIO3INTD                                                       */
21373   GPIO_CFGA_GPIO3INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low                           */
21374   GPIO_CFGA_GPIO3INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high                         */
21375 } GPIO_CFGA_GPIO3INTD_Enum;
21376 
21377 /* ============================================  GPIO CFGA GPIO3OUTCFG [13..14]  ============================================= */
21378 typedef enum {                                  /*!< GPIO_CFGA_GPIO3OUTCFG                                                     */
21379   GPIO_CFGA_GPIO3OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21380   GPIO_CFGA_GPIO3OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21381   GPIO_CFGA_GPIO3OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21382   GPIO_CFGA_GPIO3OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21383 } GPIO_CFGA_GPIO3OUTCFG_Enum;
21384 
21385 /* =============================================  GPIO CFGA GPIO3INCFG [12..12]  ============================================= */
21386 typedef enum {                                  /*!< GPIO_CFGA_GPIO3INCFG                                                      */
21387   GPIO_CFGA_GPIO3INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21388   GPIO_CFGA_GPIO3INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21389 } GPIO_CFGA_GPIO3INCFG_Enum;
21390 
21391 /* =============================================  GPIO CFGA GPIO2INTD [11..11]  ============================================== */
21392 typedef enum {                                  /*!< GPIO_CFGA_GPIO2INTD                                                       */
21393   GPIO_CFGA_GPIO2INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low                           */
21394   GPIO_CFGA_GPIO2INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high                         */
21395 } GPIO_CFGA_GPIO2INTD_Enum;
21396 
21397 /* =============================================  GPIO CFGA GPIO2OUTCFG [9..10]  ============================================= */
21398 typedef enum {                                  /*!< GPIO_CFGA_GPIO2OUTCFG                                                     */
21399   GPIO_CFGA_GPIO2OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21400   GPIO_CFGA_GPIO2OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21401   GPIO_CFGA_GPIO2OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21402   GPIO_CFGA_GPIO2OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21403 } GPIO_CFGA_GPIO2OUTCFG_Enum;
21404 
21405 /* ==============================================  GPIO CFGA GPIO2INCFG [8..8]  ============================================== */
21406 typedef enum {                                  /*!< GPIO_CFGA_GPIO2INCFG                                                      */
21407   GPIO_CFGA_GPIO2INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21408   GPIO_CFGA_GPIO2INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21409 } GPIO_CFGA_GPIO2INCFG_Enum;
21410 
21411 /* ==============================================  GPIO CFGA GPIO1INTD [7..7]  =============================================== */
21412 typedef enum {                                  /*!< GPIO_CFGA_GPIO1INTD                                                       */
21413   GPIO_CFGA_GPIO1INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low                           */
21414   GPIO_CFGA_GPIO1INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high                         */
21415 } GPIO_CFGA_GPIO1INTD_Enum;
21416 
21417 /* =============================================  GPIO CFGA GPIO1OUTCFG [5..6]  ============================================== */
21418 typedef enum {                                  /*!< GPIO_CFGA_GPIO1OUTCFG                                                     */
21419   GPIO_CFGA_GPIO1OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21420   GPIO_CFGA_GPIO1OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21421   GPIO_CFGA_GPIO1OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21422   GPIO_CFGA_GPIO1OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21423 } GPIO_CFGA_GPIO1OUTCFG_Enum;
21424 
21425 /* ==============================================  GPIO CFGA GPIO1INCFG [4..4]  ============================================== */
21426 typedef enum {                                  /*!< GPIO_CFGA_GPIO1INCFG                                                      */
21427   GPIO_CFGA_GPIO1INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21428   GPIO_CFGA_GPIO1INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21429 } GPIO_CFGA_GPIO1INCFG_Enum;
21430 
21431 /* ==============================================  GPIO CFGA GPIO0INTD [3..3]  =============================================== */
21432 typedef enum {                                  /*!< GPIO_CFGA_GPIO0INTD                                                       */
21433   GPIO_CFGA_GPIO0INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x7 - nCE polarity active low                           */
21434   GPIO_CFGA_GPIO0INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x7 - nCE polarity active high                         */
21435 } GPIO_CFGA_GPIO0INTD_Enum;
21436 
21437 /* =============================================  GPIO CFGA GPIO0OUTCFG [1..2]  ============================================== */
21438 typedef enum {                                  /*!< GPIO_CFGA_GPIO0OUTCFG                                                     */
21439   GPIO_CFGA_GPIO0OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21440   GPIO_CFGA_GPIO0OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21441   GPIO_CFGA_GPIO0OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21442   GPIO_CFGA_GPIO0OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21443 } GPIO_CFGA_GPIO0OUTCFG_Enum;
21444 
21445 /* ==============================================  GPIO CFGA GPIO0INCFG [0..0]  ============================================== */
21446 typedef enum {                                  /*!< GPIO_CFGA_GPIO0INCFG                                                      */
21447   GPIO_CFGA_GPIO0INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21448   GPIO_CFGA_GPIO0INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21449 } GPIO_CFGA_GPIO0INCFG_Enum;
21450 
21451 /* =========================================================  CFGB  ========================================================== */
21452 /* =============================================  GPIO CFGB GPIO15INTD [31..31]  ============================================= */
21453 typedef enum {                                  /*!< GPIO_CFGB_GPIO15INTD                                                      */
21454   GPIO_CFGB_GPIO15INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21455   GPIO_CFGB_GPIO15INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21456 } GPIO_CFGB_GPIO15INTD_Enum;
21457 
21458 /* ============================================  GPIO CFGB GPIO15OUTCFG [29..30]  ============================================ */
21459 typedef enum {                                  /*!< GPIO_CFGB_GPIO15OUTCFG                                                    */
21460   GPIO_CFGB_GPIO15OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21461   GPIO_CFGB_GPIO15OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21462   GPIO_CFGB_GPIO15OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21463   GPIO_CFGB_GPIO15OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21464 } GPIO_CFGB_GPIO15OUTCFG_Enum;
21465 
21466 /* ============================================  GPIO CFGB GPIO15INCFG [28..28]  ============================================= */
21467 typedef enum {                                  /*!< GPIO_CFGB_GPIO15INCFG                                                     */
21468   GPIO_CFGB_GPIO15INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21469   GPIO_CFGB_GPIO15INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21470 } GPIO_CFGB_GPIO15INCFG_Enum;
21471 
21472 /* =============================================  GPIO CFGB GPIO14INTD [27..27]  ============================================= */
21473 typedef enum {                                  /*!< GPIO_CFGB_GPIO14INTD                                                      */
21474   GPIO_CFGB_GPIO14INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21475   GPIO_CFGB_GPIO14INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21476 } GPIO_CFGB_GPIO14INTD_Enum;
21477 
21478 /* ============================================  GPIO CFGB GPIO14OUTCFG [25..26]  ============================================ */
21479 typedef enum {                                  /*!< GPIO_CFGB_GPIO14OUTCFG                                                    */
21480   GPIO_CFGB_GPIO14OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21481   GPIO_CFGB_GPIO14OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21482   GPIO_CFGB_GPIO14OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21483   GPIO_CFGB_GPIO14OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21484 } GPIO_CFGB_GPIO14OUTCFG_Enum;
21485 
21486 /* ============================================  GPIO CFGB GPIO14INCFG [24..24]  ============================================= */
21487 typedef enum {                                  /*!< GPIO_CFGB_GPIO14INCFG                                                     */
21488   GPIO_CFGB_GPIO14INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21489   GPIO_CFGB_GPIO14INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21490 } GPIO_CFGB_GPIO14INCFG_Enum;
21491 
21492 /* =============================================  GPIO CFGB GPIO13INTD [23..23]  ============================================= */
21493 typedef enum {                                  /*!< GPIO_CFGB_GPIO13INTD                                                      */
21494   GPIO_CFGB_GPIO13INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21495   GPIO_CFGB_GPIO13INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21496 } GPIO_CFGB_GPIO13INTD_Enum;
21497 
21498 /* ============================================  GPIO CFGB GPIO13OUTCFG [21..22]  ============================================ */
21499 typedef enum {                                  /*!< GPIO_CFGB_GPIO13OUTCFG                                                    */
21500   GPIO_CFGB_GPIO13OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21501   GPIO_CFGB_GPIO13OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21502   GPIO_CFGB_GPIO13OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21503   GPIO_CFGB_GPIO13OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21504 } GPIO_CFGB_GPIO13OUTCFG_Enum;
21505 
21506 /* ============================================  GPIO CFGB GPIO13INCFG [20..20]  ============================================= */
21507 typedef enum {                                  /*!< GPIO_CFGB_GPIO13INCFG                                                     */
21508   GPIO_CFGB_GPIO13INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21509   GPIO_CFGB_GPIO13INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21510 } GPIO_CFGB_GPIO13INCFG_Enum;
21511 
21512 /* =============================================  GPIO CFGB GPIO12INTD [19..19]  ============================================= */
21513 typedef enum {                                  /*!< GPIO_CFGB_GPIO12INTD                                                      */
21514   GPIO_CFGB_GPIO12INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21515   GPIO_CFGB_GPIO12INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21516 } GPIO_CFGB_GPIO12INTD_Enum;
21517 
21518 /* ============================================  GPIO CFGB GPIO12OUTCFG [17..18]  ============================================ */
21519 typedef enum {                                  /*!< GPIO_CFGB_GPIO12OUTCFG                                                    */
21520   GPIO_CFGB_GPIO12OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21521   GPIO_CFGB_GPIO12OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21522   GPIO_CFGB_GPIO12OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21523   GPIO_CFGB_GPIO12OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21524 } GPIO_CFGB_GPIO12OUTCFG_Enum;
21525 
21526 /* ============================================  GPIO CFGB GPIO12INCFG [16..16]  ============================================= */
21527 typedef enum {                                  /*!< GPIO_CFGB_GPIO12INCFG                                                     */
21528   GPIO_CFGB_GPIO12INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21529   GPIO_CFGB_GPIO12INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21530 } GPIO_CFGB_GPIO12INCFG_Enum;
21531 
21532 /* =============================================  GPIO CFGB GPIO11INTD [15..15]  ============================================= */
21533 typedef enum {                                  /*!< GPIO_CFGB_GPIO11INTD                                                      */
21534   GPIO_CFGB_GPIO11INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21535   GPIO_CFGB_GPIO11INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21536 } GPIO_CFGB_GPIO11INTD_Enum;
21537 
21538 /* ============================================  GPIO CFGB GPIO11OUTCFG [13..14]  ============================================ */
21539 typedef enum {                                  /*!< GPIO_CFGB_GPIO11OUTCFG                                                    */
21540   GPIO_CFGB_GPIO11OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21541   GPIO_CFGB_GPIO11OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21542   GPIO_CFGB_GPIO11OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21543   GPIO_CFGB_GPIO11OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21544 } GPIO_CFGB_GPIO11OUTCFG_Enum;
21545 
21546 /* ============================================  GPIO CFGB GPIO11INCFG [12..12]  ============================================= */
21547 typedef enum {                                  /*!< GPIO_CFGB_GPIO11INCFG                                                     */
21548   GPIO_CFGB_GPIO11INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21549   GPIO_CFGB_GPIO11INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21550 } GPIO_CFGB_GPIO11INCFG_Enum;
21551 
21552 /* =============================================  GPIO CFGB GPIO10INTD [11..11]  ============================================= */
21553 typedef enum {                                  /*!< GPIO_CFGB_GPIO10INTD                                                      */
21554   GPIO_CFGB_GPIO10INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low                           */
21555   GPIO_CFGB_GPIO10INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high                         */
21556 } GPIO_CFGB_GPIO10INTD_Enum;
21557 
21558 /* ============================================  GPIO CFGB GPIO10OUTCFG [9..10]  ============================================= */
21559 typedef enum {                                  /*!< GPIO_CFGB_GPIO10OUTCFG                                                    */
21560   GPIO_CFGB_GPIO10OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21561   GPIO_CFGB_GPIO10OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21562   GPIO_CFGB_GPIO10OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21563   GPIO_CFGB_GPIO10OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21564 } GPIO_CFGB_GPIO10OUTCFG_Enum;
21565 
21566 /* =============================================  GPIO CFGB GPIO10INCFG [8..8]  ============================================== */
21567 typedef enum {                                  /*!< GPIO_CFGB_GPIO10INCFG                                                     */
21568   GPIO_CFGB_GPIO10INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21569   GPIO_CFGB_GPIO10INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21570 } GPIO_CFGB_GPIO10INCFG_Enum;
21571 
21572 /* ==============================================  GPIO CFGB GPIO9INTD [7..7]  =============================================== */
21573 typedef enum {                                  /*!< GPIO_CFGB_GPIO9INTD                                                       */
21574   GPIO_CFGB_GPIO9INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low                           */
21575   GPIO_CFGB_GPIO9INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high                         */
21576 } GPIO_CFGB_GPIO9INTD_Enum;
21577 
21578 /* =============================================  GPIO CFGB GPIO9OUTCFG [5..6]  ============================================== */
21579 typedef enum {                                  /*!< GPIO_CFGB_GPIO9OUTCFG                                                     */
21580   GPIO_CFGB_GPIO9OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21581   GPIO_CFGB_GPIO9OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21582   GPIO_CFGB_GPIO9OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21583   GPIO_CFGB_GPIO9OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21584 } GPIO_CFGB_GPIO9OUTCFG_Enum;
21585 
21586 /* ==============================================  GPIO CFGB GPIO9INCFG [4..4]  ============================================== */
21587 typedef enum {                                  /*!< GPIO_CFGB_GPIO9INCFG                                                      */
21588   GPIO_CFGB_GPIO9INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21589   GPIO_CFGB_GPIO9INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21590 } GPIO_CFGB_GPIO9INCFG_Enum;
21591 
21592 /* ==============================================  GPIO CFGB GPIO8INTD [3..3]  =============================================== */
21593 typedef enum {                                  /*!< GPIO_CFGB_GPIO8INTD                                                       */
21594   GPIO_CFGB_GPIO8INTD_nCELOW           = 0,     /*!< nCELOW : FNCSEL = 0x2 - nCE polarity active low                           */
21595   GPIO_CFGB_GPIO8INTD_nCEHIGH          = 1,     /*!< nCEHIGH : FNCSEL = 0x2 - nCE polarity active high                         */
21596 } GPIO_CFGB_GPIO8INTD_Enum;
21597 
21598 /* =============================================  GPIO CFGB GPIO8OUTCFG [1..2]  ============================================== */
21599 typedef enum {                                  /*!< GPIO_CFGB_GPIO8OUTCFG                                                     */
21600   GPIO_CFGB_GPIO8OUTCFG_DIS            = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21601   GPIO_CFGB_GPIO8OUTCFG_PUSHPULL       = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21602   GPIO_CFGB_GPIO8OUTCFG_OD             = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21603   GPIO_CFGB_GPIO8OUTCFG_TS             = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21604 } GPIO_CFGB_GPIO8OUTCFG_Enum;
21605 
21606 /* ==============================================  GPIO CFGB GPIO8INCFG [0..0]  ============================================== */
21607 typedef enum {                                  /*!< GPIO_CFGB_GPIO8INCFG                                                      */
21608   GPIO_CFGB_GPIO8INCFG_READ            = 0,     /*!< READ : Read the GPIO pin data                                             */
21609   GPIO_CFGB_GPIO8INCFG_RDZERO          = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21610 } GPIO_CFGB_GPIO8INCFG_Enum;
21611 
21612 /* =========================================================  CFGC  ========================================================== */
21613 /* =============================================  GPIO CFGC GPIO23INTD [31..31]  ============================================= */
21614 typedef enum {                                  /*!< GPIO_CFGC_GPIO23INTD                                                      */
21615   GPIO_CFGC_GPIO23INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21616   GPIO_CFGC_GPIO23INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21617 } GPIO_CFGC_GPIO23INTD_Enum;
21618 
21619 /* ============================================  GPIO CFGC GPIO23OUTCFG [29..30]  ============================================ */
21620 typedef enum {                                  /*!< GPIO_CFGC_GPIO23OUTCFG                                                    */
21621   GPIO_CFGC_GPIO23OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21622   GPIO_CFGC_GPIO23OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21623   GPIO_CFGC_GPIO23OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21624   GPIO_CFGC_GPIO23OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21625 } GPIO_CFGC_GPIO23OUTCFG_Enum;
21626 
21627 /* ============================================  GPIO CFGC GPIO23INCFG [28..28]  ============================================= */
21628 typedef enum {                                  /*!< GPIO_CFGC_GPIO23INCFG                                                     */
21629   GPIO_CFGC_GPIO23INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21630   GPIO_CFGC_GPIO23INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21631 } GPIO_CFGC_GPIO23INCFG_Enum;
21632 
21633 /* =============================================  GPIO CFGC GPIO22INTD [27..27]  ============================================= */
21634 typedef enum {                                  /*!< GPIO_CFGC_GPIO22INTD                                                      */
21635   GPIO_CFGC_GPIO22INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21636   GPIO_CFGC_GPIO22INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21637 } GPIO_CFGC_GPIO22INTD_Enum;
21638 
21639 /* ============================================  GPIO CFGC GPIO22OUTCFG [25..26]  ============================================ */
21640 typedef enum {                                  /*!< GPIO_CFGC_GPIO22OUTCFG                                                    */
21641   GPIO_CFGC_GPIO22OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21642   GPIO_CFGC_GPIO22OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21643   GPIO_CFGC_GPIO22OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21644   GPIO_CFGC_GPIO22OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21645 } GPIO_CFGC_GPIO22OUTCFG_Enum;
21646 
21647 /* ============================================  GPIO CFGC GPIO22INCFG [24..24]  ============================================= */
21648 typedef enum {                                  /*!< GPIO_CFGC_GPIO22INCFG                                                     */
21649   GPIO_CFGC_GPIO22INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21650   GPIO_CFGC_GPIO22INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21651 } GPIO_CFGC_GPIO22INCFG_Enum;
21652 
21653 /* =============================================  GPIO CFGC GPIO21INTD [23..23]  ============================================= */
21654 typedef enum {                                  /*!< GPIO_CFGC_GPIO21INTD                                                      */
21655   GPIO_CFGC_GPIO21INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21656   GPIO_CFGC_GPIO21INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21657 } GPIO_CFGC_GPIO21INTD_Enum;
21658 
21659 /* ============================================  GPIO CFGC GPIO21OUTCFG [21..22]  ============================================ */
21660 typedef enum {                                  /*!< GPIO_CFGC_GPIO21OUTCFG                                                    */
21661   GPIO_CFGC_GPIO21OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21662   GPIO_CFGC_GPIO21OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21663   GPIO_CFGC_GPIO21OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21664   GPIO_CFGC_GPIO21OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21665 } GPIO_CFGC_GPIO21OUTCFG_Enum;
21666 
21667 /* ============================================  GPIO CFGC GPIO21INCFG [20..20]  ============================================= */
21668 typedef enum {                                  /*!< GPIO_CFGC_GPIO21INCFG                                                     */
21669   GPIO_CFGC_GPIO21INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21670   GPIO_CFGC_GPIO21INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21671 } GPIO_CFGC_GPIO21INCFG_Enum;
21672 
21673 /* =============================================  GPIO CFGC GPIO20INTD [19..19]  ============================================= */
21674 typedef enum {                                  /*!< GPIO_CFGC_GPIO20INTD                                                      */
21675   GPIO_CFGC_GPIO20INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21676   GPIO_CFGC_GPIO20INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21677 } GPIO_CFGC_GPIO20INTD_Enum;
21678 
21679 /* ============================================  GPIO CFGC GPIO20OUTCFG [17..18]  ============================================ */
21680 typedef enum {                                  /*!< GPIO_CFGC_GPIO20OUTCFG                                                    */
21681   GPIO_CFGC_GPIO20OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21682   GPIO_CFGC_GPIO20OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21683   GPIO_CFGC_GPIO20OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21684   GPIO_CFGC_GPIO20OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21685 } GPIO_CFGC_GPIO20OUTCFG_Enum;
21686 
21687 /* ============================================  GPIO CFGC GPIO20INCFG [16..16]  ============================================= */
21688 typedef enum {                                  /*!< GPIO_CFGC_GPIO20INCFG                                                     */
21689   GPIO_CFGC_GPIO20INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21690   GPIO_CFGC_GPIO20INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21691 } GPIO_CFGC_GPIO20INCFG_Enum;
21692 
21693 /* =============================================  GPIO CFGC GPIO19INTD [15..15]  ============================================= */
21694 typedef enum {                                  /*!< GPIO_CFGC_GPIO19INTD                                                      */
21695   GPIO_CFGC_GPIO19INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21696   GPIO_CFGC_GPIO19INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21697 } GPIO_CFGC_GPIO19INTD_Enum;
21698 
21699 /* ============================================  GPIO CFGC GPIO19OUTCFG [13..14]  ============================================ */
21700 typedef enum {                                  /*!< GPIO_CFGC_GPIO19OUTCFG                                                    */
21701   GPIO_CFGC_GPIO19OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21702   GPIO_CFGC_GPIO19OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21703   GPIO_CFGC_GPIO19OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21704   GPIO_CFGC_GPIO19OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21705 } GPIO_CFGC_GPIO19OUTCFG_Enum;
21706 
21707 /* ============================================  GPIO CFGC GPIO19INCFG [12..12]  ============================================= */
21708 typedef enum {                                  /*!< GPIO_CFGC_GPIO19INCFG                                                     */
21709   GPIO_CFGC_GPIO19INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21710   GPIO_CFGC_GPIO19INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21711 } GPIO_CFGC_GPIO19INCFG_Enum;
21712 
21713 /* =============================================  GPIO CFGC GPIO18INTD [11..11]  ============================================= */
21714 typedef enum {                                  /*!< GPIO_CFGC_GPIO18INTD                                                      */
21715   GPIO_CFGC_GPIO18INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21716   GPIO_CFGC_GPIO18INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21717 } GPIO_CFGC_GPIO18INTD_Enum;
21718 
21719 /* ============================================  GPIO CFGC GPIO18OUTCFG [9..10]  ============================================= */
21720 typedef enum {                                  /*!< GPIO_CFGC_GPIO18OUTCFG                                                    */
21721   GPIO_CFGC_GPIO18OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21722   GPIO_CFGC_GPIO18OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21723   GPIO_CFGC_GPIO18OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21724   GPIO_CFGC_GPIO18OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21725 } GPIO_CFGC_GPIO18OUTCFG_Enum;
21726 
21727 /* =============================================  GPIO CFGC GPIO18INCFG [8..8]  ============================================== */
21728 typedef enum {                                  /*!< GPIO_CFGC_GPIO18INCFG                                                     */
21729   GPIO_CFGC_GPIO18INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21730   GPIO_CFGC_GPIO18INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21731 } GPIO_CFGC_GPIO18INCFG_Enum;
21732 
21733 /* ==============================================  GPIO CFGC GPIO17INTD [7..7]  ============================================== */
21734 typedef enum {                                  /*!< GPIO_CFGC_GPIO17INTD                                                      */
21735   GPIO_CFGC_GPIO17INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21736   GPIO_CFGC_GPIO17INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21737 } GPIO_CFGC_GPIO17INTD_Enum;
21738 
21739 /* =============================================  GPIO CFGC GPIO17OUTCFG [5..6]  ============================================= */
21740 typedef enum {                                  /*!< GPIO_CFGC_GPIO17OUTCFG                                                    */
21741   GPIO_CFGC_GPIO17OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21742   GPIO_CFGC_GPIO17OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21743   GPIO_CFGC_GPIO17OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21744   GPIO_CFGC_GPIO17OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21745 } GPIO_CFGC_GPIO17OUTCFG_Enum;
21746 
21747 /* =============================================  GPIO CFGC GPIO17INCFG [4..4]  ============================================== */
21748 typedef enum {                                  /*!< GPIO_CFGC_GPIO17INCFG                                                     */
21749   GPIO_CFGC_GPIO17INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21750   GPIO_CFGC_GPIO17INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21751 } GPIO_CFGC_GPIO17INCFG_Enum;
21752 
21753 /* ==============================================  GPIO CFGC GPIO16INTD [3..3]  ============================================== */
21754 typedef enum {                                  /*!< GPIO_CFGC_GPIO16INTD                                                      */
21755   GPIO_CFGC_GPIO16INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21756   GPIO_CFGC_GPIO16INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21757 } GPIO_CFGC_GPIO16INTD_Enum;
21758 
21759 /* =============================================  GPIO CFGC GPIO16OUTCFG [1..2]  ============================================= */
21760 typedef enum {                                  /*!< GPIO_CFGC_GPIO16OUTCFG                                                    */
21761   GPIO_CFGC_GPIO16OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21762   GPIO_CFGC_GPIO16OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21763   GPIO_CFGC_GPIO16OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21764   GPIO_CFGC_GPIO16OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21765 } GPIO_CFGC_GPIO16OUTCFG_Enum;
21766 
21767 /* =============================================  GPIO CFGC GPIO16INCFG [0..0]  ============================================== */
21768 typedef enum {                                  /*!< GPIO_CFGC_GPIO16INCFG                                                     */
21769   GPIO_CFGC_GPIO16INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21770   GPIO_CFGC_GPIO16INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21771 } GPIO_CFGC_GPIO16INCFG_Enum;
21772 
21773 /* =========================================================  CFGD  ========================================================== */
21774 /* =============================================  GPIO CFGD GPIO31INTD [31..31]  ============================================= */
21775 typedef enum {                                  /*!< GPIO_CFGD_GPIO31INTD                                                      */
21776   GPIO_CFGD_GPIO31INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21777   GPIO_CFGD_GPIO31INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21778 } GPIO_CFGD_GPIO31INTD_Enum;
21779 
21780 /* ============================================  GPIO CFGD GPIO31OUTCFG [29..30]  ============================================ */
21781 typedef enum {                                  /*!< GPIO_CFGD_GPIO31OUTCFG                                                    */
21782   GPIO_CFGD_GPIO31OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21783   GPIO_CFGD_GPIO31OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21784   GPIO_CFGD_GPIO31OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21785   GPIO_CFGD_GPIO31OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21786 } GPIO_CFGD_GPIO31OUTCFG_Enum;
21787 
21788 /* ============================================  GPIO CFGD GPIO31INCFG [28..28]  ============================================= */
21789 typedef enum {                                  /*!< GPIO_CFGD_GPIO31INCFG                                                     */
21790   GPIO_CFGD_GPIO31INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21791   GPIO_CFGD_GPIO31INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21792 } GPIO_CFGD_GPIO31INCFG_Enum;
21793 
21794 /* =============================================  GPIO CFGD GPIO30INTD [27..27]  ============================================= */
21795 typedef enum {                                  /*!< GPIO_CFGD_GPIO30INTD                                                      */
21796   GPIO_CFGD_GPIO30INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21797   GPIO_CFGD_GPIO30INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21798 } GPIO_CFGD_GPIO30INTD_Enum;
21799 
21800 /* ============================================  GPIO CFGD GPIO30OUTCFG [25..26]  ============================================ */
21801 typedef enum {                                  /*!< GPIO_CFGD_GPIO30OUTCFG                                                    */
21802   GPIO_CFGD_GPIO30OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21803   GPIO_CFGD_GPIO30OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21804   GPIO_CFGD_GPIO30OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21805   GPIO_CFGD_GPIO30OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21806 } GPIO_CFGD_GPIO30OUTCFG_Enum;
21807 
21808 /* ============================================  GPIO CFGD GPIO30INCFG [24..24]  ============================================= */
21809 typedef enum {                                  /*!< GPIO_CFGD_GPIO30INCFG                                                     */
21810   GPIO_CFGD_GPIO30INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21811   GPIO_CFGD_GPIO30INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21812 } GPIO_CFGD_GPIO30INCFG_Enum;
21813 
21814 /* =============================================  GPIO CFGD GPIO29INTD [23..23]  ============================================= */
21815 typedef enum {                                  /*!< GPIO_CFGD_GPIO29INTD                                                      */
21816   GPIO_CFGD_GPIO29INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21817   GPIO_CFGD_GPIO29INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21818 } GPIO_CFGD_GPIO29INTD_Enum;
21819 
21820 /* ============================================  GPIO CFGD GPIO29OUTCFG [21..22]  ============================================ */
21821 typedef enum {                                  /*!< GPIO_CFGD_GPIO29OUTCFG                                                    */
21822   GPIO_CFGD_GPIO29OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21823   GPIO_CFGD_GPIO29OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21824   GPIO_CFGD_GPIO29OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21825   GPIO_CFGD_GPIO29OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21826 } GPIO_CFGD_GPIO29OUTCFG_Enum;
21827 
21828 /* ============================================  GPIO CFGD GPIO29INCFG [20..20]  ============================================= */
21829 typedef enum {                                  /*!< GPIO_CFGD_GPIO29INCFG                                                     */
21830   GPIO_CFGD_GPIO29INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21831   GPIO_CFGD_GPIO29INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21832 } GPIO_CFGD_GPIO29INCFG_Enum;
21833 
21834 /* =============================================  GPIO CFGD GPIO28INTD [19..19]  ============================================= */
21835 typedef enum {                                  /*!< GPIO_CFGD_GPIO28INTD                                                      */
21836   GPIO_CFGD_GPIO28INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21837   GPIO_CFGD_GPIO28INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21838 } GPIO_CFGD_GPIO28INTD_Enum;
21839 
21840 /* ============================================  GPIO CFGD GPIO28OUTCFG [17..18]  ============================================ */
21841 typedef enum {                                  /*!< GPIO_CFGD_GPIO28OUTCFG                                                    */
21842   GPIO_CFGD_GPIO28OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21843   GPIO_CFGD_GPIO28OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21844   GPIO_CFGD_GPIO28OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21845   GPIO_CFGD_GPIO28OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21846 } GPIO_CFGD_GPIO28OUTCFG_Enum;
21847 
21848 /* ============================================  GPIO CFGD GPIO28INCFG [16..16]  ============================================= */
21849 typedef enum {                                  /*!< GPIO_CFGD_GPIO28INCFG                                                     */
21850   GPIO_CFGD_GPIO28INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21851   GPIO_CFGD_GPIO28INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21852 } GPIO_CFGD_GPIO28INCFG_Enum;
21853 
21854 /* =============================================  GPIO CFGD GPIO27INTD [15..15]  ============================================= */
21855 typedef enum {                                  /*!< GPIO_CFGD_GPIO27INTD                                                      */
21856   GPIO_CFGD_GPIO27INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21857   GPIO_CFGD_GPIO27INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21858 } GPIO_CFGD_GPIO27INTD_Enum;
21859 
21860 /* ============================================  GPIO CFGD GPIO27OUTCFG [13..14]  ============================================ */
21861 typedef enum {                                  /*!< GPIO_CFGD_GPIO27OUTCFG                                                    */
21862   GPIO_CFGD_GPIO27OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21863   GPIO_CFGD_GPIO27OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21864   GPIO_CFGD_GPIO27OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21865   GPIO_CFGD_GPIO27OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21866 } GPIO_CFGD_GPIO27OUTCFG_Enum;
21867 
21868 /* ============================================  GPIO CFGD GPIO27INCFG [12..12]  ============================================= */
21869 typedef enum {                                  /*!< GPIO_CFGD_GPIO27INCFG                                                     */
21870   GPIO_CFGD_GPIO27INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21871   GPIO_CFGD_GPIO27INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21872 } GPIO_CFGD_GPIO27INCFG_Enum;
21873 
21874 /* =============================================  GPIO CFGD GPIO26INTD [11..11]  ============================================= */
21875 typedef enum {                                  /*!< GPIO_CFGD_GPIO26INTD                                                      */
21876   GPIO_CFGD_GPIO26INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21877   GPIO_CFGD_GPIO26INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21878 } GPIO_CFGD_GPIO26INTD_Enum;
21879 
21880 /* ============================================  GPIO CFGD GPIO26OUTCFG [9..10]  ============================================= */
21881 typedef enum {                                  /*!< GPIO_CFGD_GPIO26OUTCFG                                                    */
21882   GPIO_CFGD_GPIO26OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21883   GPIO_CFGD_GPIO26OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21884   GPIO_CFGD_GPIO26OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21885   GPIO_CFGD_GPIO26OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21886 } GPIO_CFGD_GPIO26OUTCFG_Enum;
21887 
21888 /* =============================================  GPIO CFGD GPIO26INCFG [8..8]  ============================================== */
21889 typedef enum {                                  /*!< GPIO_CFGD_GPIO26INCFG                                                     */
21890   GPIO_CFGD_GPIO26INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21891   GPIO_CFGD_GPIO26INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21892 } GPIO_CFGD_GPIO26INCFG_Enum;
21893 
21894 /* ==============================================  GPIO CFGD GPIO25INTD [7..7]  ============================================== */
21895 typedef enum {                                  /*!< GPIO_CFGD_GPIO25INTD                                                      */
21896   GPIO_CFGD_GPIO25INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21897   GPIO_CFGD_GPIO25INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21898 } GPIO_CFGD_GPIO25INTD_Enum;
21899 
21900 /* =============================================  GPIO CFGD GPIO25OUTCFG [5..6]  ============================================= */
21901 typedef enum {                                  /*!< GPIO_CFGD_GPIO25OUTCFG                                                    */
21902   GPIO_CFGD_GPIO25OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21903   GPIO_CFGD_GPIO25OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21904   GPIO_CFGD_GPIO25OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21905   GPIO_CFGD_GPIO25OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21906 } GPIO_CFGD_GPIO25OUTCFG_Enum;
21907 
21908 /* =============================================  GPIO CFGD GPIO25INCFG [4..4]  ============================================== */
21909 typedef enum {                                  /*!< GPIO_CFGD_GPIO25INCFG                                                     */
21910   GPIO_CFGD_GPIO25INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21911   GPIO_CFGD_GPIO25INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21912 } GPIO_CFGD_GPIO25INCFG_Enum;
21913 
21914 /* ==============================================  GPIO CFGD GPIO24INTD [3..3]  ============================================== */
21915 typedef enum {                                  /*!< GPIO_CFGD_GPIO24INTD                                                      */
21916   GPIO_CFGD_GPIO24INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21917   GPIO_CFGD_GPIO24INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21918 } GPIO_CFGD_GPIO24INTD_Enum;
21919 
21920 /* =============================================  GPIO CFGD GPIO24OUTCFG [1..2]  ============================================= */
21921 typedef enum {                                  /*!< GPIO_CFGD_GPIO24OUTCFG                                                    */
21922   GPIO_CFGD_GPIO24OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21923   GPIO_CFGD_GPIO24OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21924   GPIO_CFGD_GPIO24OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21925   GPIO_CFGD_GPIO24OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21926 } GPIO_CFGD_GPIO24OUTCFG_Enum;
21927 
21928 /* =============================================  GPIO CFGD GPIO24INCFG [0..0]  ============================================== */
21929 typedef enum {                                  /*!< GPIO_CFGD_GPIO24INCFG                                                     */
21930   GPIO_CFGD_GPIO24INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21931   GPIO_CFGD_GPIO24INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21932 } GPIO_CFGD_GPIO24INCFG_Enum;
21933 
21934 /* =========================================================  CFGE  ========================================================== */
21935 /* =============================================  GPIO CFGE GPIO39INTD [31..31]  ============================================= */
21936 typedef enum {                                  /*!< GPIO_CFGE_GPIO39INTD                                                      */
21937   GPIO_CFGE_GPIO39INTD_INTDIS          = 0,     /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition                      */
21938   GPIO_CFGE_GPIO39INTD_INTBOTH         = 1,     /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
21939                                                      to low GPIO transition                                                    */
21940 } GPIO_CFGE_GPIO39INTD_Enum;
21941 
21942 /* ============================================  GPIO CFGE GPIO39OUTCFG [29..30]  ============================================ */
21943 typedef enum {                                  /*!< GPIO_CFGE_GPIO39OUTCFG                                                    */
21944   GPIO_CFGE_GPIO39OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21945   GPIO_CFGE_GPIO39OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21946   GPIO_CFGE_GPIO39OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21947   GPIO_CFGE_GPIO39OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21948 } GPIO_CFGE_GPIO39OUTCFG_Enum;
21949 
21950 /* ============================================  GPIO CFGE GPIO39INCFG [28..28]  ============================================= */
21951 typedef enum {                                  /*!< GPIO_CFGE_GPIO39INCFG                                                     */
21952   GPIO_CFGE_GPIO39INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21953   GPIO_CFGE_GPIO39INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21954 } GPIO_CFGE_GPIO39INCFG_Enum;
21955 
21956 /* =============================================  GPIO CFGE GPIO38INTD [27..27]  ============================================= */
21957 typedef enum {                                  /*!< GPIO_CFGE_GPIO38INTD                                                      */
21958   GPIO_CFGE_GPIO38INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21959   GPIO_CFGE_GPIO38INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21960 } GPIO_CFGE_GPIO38INTD_Enum;
21961 
21962 /* ============================================  GPIO CFGE GPIO38OUTCFG [25..26]  ============================================ */
21963 typedef enum {                                  /*!< GPIO_CFGE_GPIO38OUTCFG                                                    */
21964   GPIO_CFGE_GPIO38OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21965   GPIO_CFGE_GPIO38OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21966   GPIO_CFGE_GPIO38OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21967   GPIO_CFGE_GPIO38OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21968 } GPIO_CFGE_GPIO38OUTCFG_Enum;
21969 
21970 /* ============================================  GPIO CFGE GPIO38INCFG [24..24]  ============================================= */
21971 typedef enum {                                  /*!< GPIO_CFGE_GPIO38INCFG                                                     */
21972   GPIO_CFGE_GPIO38INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21973   GPIO_CFGE_GPIO38INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21974 } GPIO_CFGE_GPIO38INCFG_Enum;
21975 
21976 /* =============================================  GPIO CFGE GPIO37INTD [23..23]  ============================================= */
21977 typedef enum {                                  /*!< GPIO_CFGE_GPIO37INTD                                                      */
21978   GPIO_CFGE_GPIO37INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21979   GPIO_CFGE_GPIO37INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
21980 } GPIO_CFGE_GPIO37INTD_Enum;
21981 
21982 /* ============================================  GPIO CFGE GPIO37OUTCFG [21..22]  ============================================ */
21983 typedef enum {                                  /*!< GPIO_CFGE_GPIO37OUTCFG                                                    */
21984   GPIO_CFGE_GPIO37OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
21985   GPIO_CFGE_GPIO37OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
21986   GPIO_CFGE_GPIO37OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
21987   GPIO_CFGE_GPIO37OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
21988 } GPIO_CFGE_GPIO37OUTCFG_Enum;
21989 
21990 /* ============================================  GPIO CFGE GPIO37INCFG [20..20]  ============================================= */
21991 typedef enum {                                  /*!< GPIO_CFGE_GPIO37INCFG                                                     */
21992   GPIO_CFGE_GPIO37INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
21993   GPIO_CFGE_GPIO37INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
21994 } GPIO_CFGE_GPIO37INCFG_Enum;
21995 
21996 /* =============================================  GPIO CFGE GPIO36INTD [19..19]  ============================================= */
21997 typedef enum {                                  /*!< GPIO_CFGE_GPIO36INTD                                                      */
21998   GPIO_CFGE_GPIO36INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
21999   GPIO_CFGE_GPIO36INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22000 } GPIO_CFGE_GPIO36INTD_Enum;
22001 
22002 /* ============================================  GPIO CFGE GPIO36OUTCFG [17..18]  ============================================ */
22003 typedef enum {                                  /*!< GPIO_CFGE_GPIO36OUTCFG                                                    */
22004   GPIO_CFGE_GPIO36OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22005   GPIO_CFGE_GPIO36OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22006   GPIO_CFGE_GPIO36OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22007   GPIO_CFGE_GPIO36OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22008 } GPIO_CFGE_GPIO36OUTCFG_Enum;
22009 
22010 /* ============================================  GPIO CFGE GPIO36INCFG [16..16]  ============================================= */
22011 typedef enum {                                  /*!< GPIO_CFGE_GPIO36INCFG                                                     */
22012   GPIO_CFGE_GPIO36INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22013   GPIO_CFGE_GPIO36INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22014 } GPIO_CFGE_GPIO36INCFG_Enum;
22015 
22016 /* =============================================  GPIO CFGE GPIO35INTD [15..15]  ============================================= */
22017 typedef enum {                                  /*!< GPIO_CFGE_GPIO35INTD                                                      */
22018   GPIO_CFGE_GPIO35INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22019   GPIO_CFGE_GPIO35INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22020 } GPIO_CFGE_GPIO35INTD_Enum;
22021 
22022 /* ============================================  GPIO CFGE GPIO35OUTCFG [13..14]  ============================================ */
22023 typedef enum {                                  /*!< GPIO_CFGE_GPIO35OUTCFG                                                    */
22024   GPIO_CFGE_GPIO35OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22025   GPIO_CFGE_GPIO35OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22026   GPIO_CFGE_GPIO35OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22027   GPIO_CFGE_GPIO35OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22028 } GPIO_CFGE_GPIO35OUTCFG_Enum;
22029 
22030 /* ============================================  GPIO CFGE GPIO35INCFG [12..12]  ============================================= */
22031 typedef enum {                                  /*!< GPIO_CFGE_GPIO35INCFG                                                     */
22032   GPIO_CFGE_GPIO35INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22033   GPIO_CFGE_GPIO35INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22034 } GPIO_CFGE_GPIO35INCFG_Enum;
22035 
22036 /* =============================================  GPIO CFGE GPIO34INTD [11..11]  ============================================= */
22037 typedef enum {                                  /*!< GPIO_CFGE_GPIO34INTD                                                      */
22038   GPIO_CFGE_GPIO34INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22039   GPIO_CFGE_GPIO34INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22040 } GPIO_CFGE_GPIO34INTD_Enum;
22041 
22042 /* ============================================  GPIO CFGE GPIO34OUTCFG [9..10]  ============================================= */
22043 typedef enum {                                  /*!< GPIO_CFGE_GPIO34OUTCFG                                                    */
22044   GPIO_CFGE_GPIO34OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22045   GPIO_CFGE_GPIO34OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22046   GPIO_CFGE_GPIO34OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22047   GPIO_CFGE_GPIO34OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22048 } GPIO_CFGE_GPIO34OUTCFG_Enum;
22049 
22050 /* =============================================  GPIO CFGE GPIO34INCFG [8..8]  ============================================== */
22051 typedef enum {                                  /*!< GPIO_CFGE_GPIO34INCFG                                                     */
22052   GPIO_CFGE_GPIO34INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22053   GPIO_CFGE_GPIO34INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22054 } GPIO_CFGE_GPIO34INCFG_Enum;
22055 
22056 /* ==============================================  GPIO CFGE GPIO33INTD [7..7]  ============================================== */
22057 typedef enum {                                  /*!< GPIO_CFGE_GPIO33INTD                                                      */
22058   GPIO_CFGE_GPIO33INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22059   GPIO_CFGE_GPIO33INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22060 } GPIO_CFGE_GPIO33INTD_Enum;
22061 
22062 /* =============================================  GPIO CFGE GPIO33OUTCFG [5..6]  ============================================= */
22063 typedef enum {                                  /*!< GPIO_CFGE_GPIO33OUTCFG                                                    */
22064   GPIO_CFGE_GPIO33OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22065   GPIO_CFGE_GPIO33OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22066   GPIO_CFGE_GPIO33OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22067   GPIO_CFGE_GPIO33OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22068 } GPIO_CFGE_GPIO33OUTCFG_Enum;
22069 
22070 /* =============================================  GPIO CFGE GPIO33INCFG [4..4]  ============================================== */
22071 typedef enum {                                  /*!< GPIO_CFGE_GPIO33INCFG                                                     */
22072   GPIO_CFGE_GPIO33INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22073   GPIO_CFGE_GPIO33INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22074 } GPIO_CFGE_GPIO33INCFG_Enum;
22075 
22076 /* ==============================================  GPIO CFGE GPIO32INTD [3..3]  ============================================== */
22077 typedef enum {                                  /*!< GPIO_CFGE_GPIO32INTD                                                      */
22078   GPIO_CFGE_GPIO32INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22079   GPIO_CFGE_GPIO32INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22080 } GPIO_CFGE_GPIO32INTD_Enum;
22081 
22082 /* =============================================  GPIO CFGE GPIO32OUTCFG [1..2]  ============================================= */
22083 typedef enum {                                  /*!< GPIO_CFGE_GPIO32OUTCFG                                                    */
22084   GPIO_CFGE_GPIO32OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22085   GPIO_CFGE_GPIO32OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22086   GPIO_CFGE_GPIO32OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22087   GPIO_CFGE_GPIO32OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22088 } GPIO_CFGE_GPIO32OUTCFG_Enum;
22089 
22090 /* =============================================  GPIO CFGE GPIO32INCFG [0..0]  ============================================== */
22091 typedef enum {                                  /*!< GPIO_CFGE_GPIO32INCFG                                                     */
22092   GPIO_CFGE_GPIO32INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22093   GPIO_CFGE_GPIO32INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22094 } GPIO_CFGE_GPIO32INCFG_Enum;
22095 
22096 /* =========================================================  CFGF  ========================================================== */
22097 /* =============================================  GPIO CFGF GPIO47INTD [31..31]  ============================================= */
22098 typedef enum {                                  /*!< GPIO_CFGF_GPIO47INTD                                                      */
22099   GPIO_CFGF_GPIO47INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22100   GPIO_CFGF_GPIO47INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22101 } GPIO_CFGF_GPIO47INTD_Enum;
22102 
22103 /* ============================================  GPIO CFGF GPIO47OUTCFG [29..30]  ============================================ */
22104 typedef enum {                                  /*!< GPIO_CFGF_GPIO47OUTCFG                                                    */
22105   GPIO_CFGF_GPIO47OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22106   GPIO_CFGF_GPIO47OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22107   GPIO_CFGF_GPIO47OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22108   GPIO_CFGF_GPIO47OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22109 } GPIO_CFGF_GPIO47OUTCFG_Enum;
22110 
22111 /* ============================================  GPIO CFGF GPIO47INCFG [28..28]  ============================================= */
22112 typedef enum {                                  /*!< GPIO_CFGF_GPIO47INCFG                                                     */
22113   GPIO_CFGF_GPIO47INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22114   GPIO_CFGF_GPIO47INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22115 } GPIO_CFGF_GPIO47INCFG_Enum;
22116 
22117 /* =============================================  GPIO CFGF GPIO46INTD [27..27]  ============================================= */
22118 typedef enum {                                  /*!< GPIO_CFGF_GPIO46INTD                                                      */
22119   GPIO_CFGF_GPIO46INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22120   GPIO_CFGF_GPIO46INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22121 } GPIO_CFGF_GPIO46INTD_Enum;
22122 
22123 /* ============================================  GPIO CFGF GPIO46OUTCFG [25..26]  ============================================ */
22124 typedef enum {                                  /*!< GPIO_CFGF_GPIO46OUTCFG                                                    */
22125   GPIO_CFGF_GPIO46OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22126   GPIO_CFGF_GPIO46OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22127   GPIO_CFGF_GPIO46OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22128   GPIO_CFGF_GPIO46OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22129 } GPIO_CFGF_GPIO46OUTCFG_Enum;
22130 
22131 /* ============================================  GPIO CFGF GPIO46INCFG [24..24]  ============================================= */
22132 typedef enum {                                  /*!< GPIO_CFGF_GPIO46INCFG                                                     */
22133   GPIO_CFGF_GPIO46INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22134   GPIO_CFGF_GPIO46INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22135 } GPIO_CFGF_GPIO46INCFG_Enum;
22136 
22137 /* =============================================  GPIO CFGF GPIO45INTD [23..23]  ============================================= */
22138 typedef enum {                                  /*!< GPIO_CFGF_GPIO45INTD                                                      */
22139   GPIO_CFGF_GPIO45INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22140   GPIO_CFGF_GPIO45INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22141 } GPIO_CFGF_GPIO45INTD_Enum;
22142 
22143 /* ============================================  GPIO CFGF GPIO45OUTCFG [21..22]  ============================================ */
22144 typedef enum {                                  /*!< GPIO_CFGF_GPIO45OUTCFG                                                    */
22145   GPIO_CFGF_GPIO45OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22146   GPIO_CFGF_GPIO45OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22147   GPIO_CFGF_GPIO45OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22148   GPIO_CFGF_GPIO45OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22149 } GPIO_CFGF_GPIO45OUTCFG_Enum;
22150 
22151 /* ============================================  GPIO CFGF GPIO45INCFG [20..20]  ============================================= */
22152 typedef enum {                                  /*!< GPIO_CFGF_GPIO45INCFG                                                     */
22153   GPIO_CFGF_GPIO45INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22154   GPIO_CFGF_GPIO45INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22155 } GPIO_CFGF_GPIO45INCFG_Enum;
22156 
22157 /* =============================================  GPIO CFGF GPIO44INTD [19..19]  ============================================= */
22158 typedef enum {                                  /*!< GPIO_CFGF_GPIO44INTD                                                      */
22159   GPIO_CFGF_GPIO44INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22160   GPIO_CFGF_GPIO44INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22161 } GPIO_CFGF_GPIO44INTD_Enum;
22162 
22163 /* ============================================  GPIO CFGF GPIO44OUTCFG [17..18]  ============================================ */
22164 typedef enum {                                  /*!< GPIO_CFGF_GPIO44OUTCFG                                                    */
22165   GPIO_CFGF_GPIO44OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22166   GPIO_CFGF_GPIO44OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22167   GPIO_CFGF_GPIO44OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22168   GPIO_CFGF_GPIO44OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22169 } GPIO_CFGF_GPIO44OUTCFG_Enum;
22170 
22171 /* ============================================  GPIO CFGF GPIO44INCFG [16..16]  ============================================= */
22172 typedef enum {                                  /*!< GPIO_CFGF_GPIO44INCFG                                                     */
22173   GPIO_CFGF_GPIO44INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22174   GPIO_CFGF_GPIO44INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22175 } GPIO_CFGF_GPIO44INCFG_Enum;
22176 
22177 /* =============================================  GPIO CFGF GPIO43INTD [15..15]  ============================================= */
22178 typedef enum {                                  /*!< GPIO_CFGF_GPIO43INTD                                                      */
22179   GPIO_CFGF_GPIO43INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22180   GPIO_CFGF_GPIO43INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22181 } GPIO_CFGF_GPIO43INTD_Enum;
22182 
22183 /* ============================================  GPIO CFGF GPIO43OUTCFG [13..14]  ============================================ */
22184 typedef enum {                                  /*!< GPIO_CFGF_GPIO43OUTCFG                                                    */
22185   GPIO_CFGF_GPIO43OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22186   GPIO_CFGF_GPIO43OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22187   GPIO_CFGF_GPIO43OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22188   GPIO_CFGF_GPIO43OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22189 } GPIO_CFGF_GPIO43OUTCFG_Enum;
22190 
22191 /* ============================================  GPIO CFGF GPIO43INCFG [12..12]  ============================================= */
22192 typedef enum {                                  /*!< GPIO_CFGF_GPIO43INCFG                                                     */
22193   GPIO_CFGF_GPIO43INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22194   GPIO_CFGF_GPIO43INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22195 } GPIO_CFGF_GPIO43INCFG_Enum;
22196 
22197 /* =============================================  GPIO CFGF GPIO42INTD [11..11]  ============================================= */
22198 typedef enum {                                  /*!< GPIO_CFGF_GPIO42INTD                                                      */
22199   GPIO_CFGF_GPIO42INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22200   GPIO_CFGF_GPIO42INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22201 } GPIO_CFGF_GPIO42INTD_Enum;
22202 
22203 /* ============================================  GPIO CFGF GPIO42OUTCFG [9..10]  ============================================= */
22204 typedef enum {                                  /*!< GPIO_CFGF_GPIO42OUTCFG                                                    */
22205   GPIO_CFGF_GPIO42OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22206   GPIO_CFGF_GPIO42OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22207   GPIO_CFGF_GPIO42OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22208   GPIO_CFGF_GPIO42OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22209 } GPIO_CFGF_GPIO42OUTCFG_Enum;
22210 
22211 /* =============================================  GPIO CFGF GPIO42INCFG [8..8]  ============================================== */
22212 typedef enum {                                  /*!< GPIO_CFGF_GPIO42INCFG                                                     */
22213   GPIO_CFGF_GPIO42INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22214   GPIO_CFGF_GPIO42INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22215 } GPIO_CFGF_GPIO42INCFG_Enum;
22216 
22217 /* ==============================================  GPIO CFGF GPIO41INTD [7..7]  ============================================== */
22218 typedef enum {                                  /*!< GPIO_CFGF_GPIO41INTD                                                      */
22219   GPIO_CFGF_GPIO41INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x0 - nCE polarity active low                           */
22220   GPIO_CFGF_GPIO41INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x0 - nCE polarity active high                         */
22221 } GPIO_CFGF_GPIO41INTD_Enum;
22222 
22223 /* =============================================  GPIO CFGF GPIO41OUTCFG [5..6]  ============================================= */
22224 typedef enum {                                  /*!< GPIO_CFGF_GPIO41OUTCFG                                                    */
22225   GPIO_CFGF_GPIO41OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22226   GPIO_CFGF_GPIO41OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22227   GPIO_CFGF_GPIO41OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22228   GPIO_CFGF_GPIO41OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22229 } GPIO_CFGF_GPIO41OUTCFG_Enum;
22230 
22231 /* =============================================  GPIO CFGF GPIO41INCFG [4..4]  ============================================== */
22232 typedef enum {                                  /*!< GPIO_CFGF_GPIO41INCFG                                                     */
22233   GPIO_CFGF_GPIO41INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22234   GPIO_CFGF_GPIO41INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22235 } GPIO_CFGF_GPIO41INCFG_Enum;
22236 
22237 /* ==============================================  GPIO CFGF GPIO40INTD [3..3]  ============================================== */
22238 typedef enum {                                  /*!< GPIO_CFGF_GPIO40INTD                                                      */
22239   GPIO_CFGF_GPIO40INTD_INTDIS          = 0,     /*!< INTDIS : INCFG = 1 - No interrupt on GPIO transition                      */
22240   GPIO_CFGF_GPIO40INTD_INTBOTH         = 1,     /*!< INTBOTH : INCFG = 1 - Interrupt on either low to high or high
22241                                                      to low GPIO transition                                                    */
22242 } GPIO_CFGF_GPIO40INTD_Enum;
22243 
22244 /* =============================================  GPIO CFGF GPIO40OUTCFG [1..2]  ============================================= */
22245 typedef enum {                                  /*!< GPIO_CFGF_GPIO40OUTCFG                                                    */
22246   GPIO_CFGF_GPIO40OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22247   GPIO_CFGF_GPIO40OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22248   GPIO_CFGF_GPIO40OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22249   GPIO_CFGF_GPIO40OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22250 } GPIO_CFGF_GPIO40OUTCFG_Enum;
22251 
22252 /* =============================================  GPIO CFGF GPIO40INCFG [0..0]  ============================================== */
22253 typedef enum {                                  /*!< GPIO_CFGF_GPIO40INCFG                                                     */
22254   GPIO_CFGF_GPIO40INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22255   GPIO_CFGF_GPIO40INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22256 } GPIO_CFGF_GPIO40INCFG_Enum;
22257 
22258 /* =========================================================  CFGG  ========================================================== */
22259 /* ==============================================  GPIO CFGG GPIO49INTD [7..7]  ============================================== */
22260 typedef enum {                                  /*!< GPIO_CFGG_GPIO49INTD                                                      */
22261   GPIO_CFGG_GPIO49INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22262   GPIO_CFGG_GPIO49INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22263 } GPIO_CFGG_GPIO49INTD_Enum;
22264 
22265 /* =============================================  GPIO CFGG GPIO49OUTCFG [5..6]  ============================================= */
22266 typedef enum {                                  /*!< GPIO_CFGG_GPIO49OUTCFG                                                    */
22267   GPIO_CFGG_GPIO49OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22268   GPIO_CFGG_GPIO49OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22269   GPIO_CFGG_GPIO49OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22270   GPIO_CFGG_GPIO49OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22271 } GPIO_CFGG_GPIO49OUTCFG_Enum;
22272 
22273 /* =============================================  GPIO CFGG GPIO49INCFG [4..4]  ============================================== */
22274 typedef enum {                                  /*!< GPIO_CFGG_GPIO49INCFG                                                     */
22275   GPIO_CFGG_GPIO49INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22276   GPIO_CFGG_GPIO49INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22277 } GPIO_CFGG_GPIO49INCFG_Enum;
22278 
22279 /* ==============================================  GPIO CFGG GPIO48INTD [3..3]  ============================================== */
22280 typedef enum {                                  /*!< GPIO_CFGG_GPIO48INTD                                                      */
22281   GPIO_CFGG_GPIO48INTD_nCELOW          = 0,     /*!< nCELOW : FNCSEL = 0x1 - nCE polarity active low                           */
22282   GPIO_CFGG_GPIO48INTD_nCEHIGH         = 1,     /*!< nCEHIGH : FNCSEL = 0x1 - nCE polarity active high                         */
22283 } GPIO_CFGG_GPIO48INTD_Enum;
22284 
22285 /* =============================================  GPIO CFGG GPIO48OUTCFG [1..2]  ============================================= */
22286 typedef enum {                                  /*!< GPIO_CFGG_GPIO48OUTCFG                                                    */
22287   GPIO_CFGG_GPIO48OUTCFG_DIS           = 0,     /*!< DIS : FNCSEL = 0x3 - Output disabled                                      */
22288   GPIO_CFGG_GPIO48OUTCFG_PUSHPULL      = 1,     /*!< PUSHPULL : FNCSEL = 0x3 - Output is push-pull                             */
22289   GPIO_CFGG_GPIO48OUTCFG_OD            = 2,     /*!< OD : FNCSEL = 0x3 - Output is open drain                                  */
22290   GPIO_CFGG_GPIO48OUTCFG_TS            = 3,     /*!< TS : FNCSEL = 0x3 - Output is tri-state                                   */
22291 } GPIO_CFGG_GPIO48OUTCFG_Enum;
22292 
22293 /* =============================================  GPIO CFGG GPIO48INCFG [0..0]  ============================================== */
22294 typedef enum {                                  /*!< GPIO_CFGG_GPIO48INCFG                                                     */
22295   GPIO_CFGG_GPIO48INCFG_READ           = 0,     /*!< READ : Read the GPIO pin data                                             */
22296   GPIO_CFGG_GPIO48INCFG_RDZERO         = 1,     /*!< RDZERO : INTD = 0 - Readback will always be zero                          */
22297 } GPIO_CFGG_GPIO48INCFG_Enum;
22298 
22299 /* ========================================================  PADKEY  ========================================================= */
22300 /* ==============================================  GPIO PADKEY PADKEY [0..31]  =============================================== */
22301 typedef enum {                                  /*!< GPIO_PADKEY_PADKEY                                                        */
22302   GPIO_PADKEY_PADKEY_Key               = 115,   /*!< Key : Key value to unlock the register.                                   */
22303 } GPIO_PADKEY_PADKEY_Enum;
22304 
22305 /* ==========================================================  RDA  ========================================================== */
22306 /* ==========================================================  RDB  ========================================================== */
22307 /* ==========================================================  WTA  ========================================================== */
22308 /* ==========================================================  WTB  ========================================================== */
22309 /* =========================================================  WTSA  ========================================================== */
22310 /* =========================================================  WTSB  ========================================================== */
22311 /* =========================================================  WTCA  ========================================================== */
22312 /* =========================================================  WTCB  ========================================================== */
22313 /* ==========================================================  ENA  ========================================================== */
22314 /* ==========================================================  ENB  ========================================================== */
22315 /* =========================================================  ENSA  ========================================================== */
22316 /* =========================================================  ENSB  ========================================================== */
22317 /* =========================================================  ENCA  ========================================================== */
22318 /* =========================================================  ENCB  ========================================================== */
22319 /* ========================================================  STMRCAP  ======================================================== */
22320 /* =============================================  GPIO STMRCAP STPOL3 [30..30]  ============================================== */
22321 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL3                                                       */
22322   GPIO_STMRCAP_STPOL3_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
22323   GPIO_STMRCAP_STPOL3_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
22324 } GPIO_STMRCAP_STPOL3_Enum;
22325 
22326 /* =============================================  GPIO STMRCAP STPOL2 [22..22]  ============================================== */
22327 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL2                                                       */
22328   GPIO_STMRCAP_STPOL2_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
22329   GPIO_STMRCAP_STPOL2_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
22330 } GPIO_STMRCAP_STPOL2_Enum;
22331 
22332 /* =============================================  GPIO STMRCAP STPOL1 [14..14]  ============================================== */
22333 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL1                                                       */
22334   GPIO_STMRCAP_STPOL1_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
22335   GPIO_STMRCAP_STPOL1_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
22336 } GPIO_STMRCAP_STPOL1_Enum;
22337 
22338 /* ==============================================  GPIO STMRCAP STPOL0 [6..6]  =============================================== */
22339 typedef enum {                                  /*!< GPIO_STMRCAP_STPOL0                                                       */
22340   GPIO_STMRCAP_STPOL0_CAPLH            = 0,     /*!< CAPLH : Capture on low to high GPIO transition                            */
22341   GPIO_STMRCAP_STPOL0_CAPHL            = 1,     /*!< CAPHL : Capture on high to low GPIO transition                            */
22342 } GPIO_STMRCAP_STPOL0_Enum;
22343 
22344 /* ========================================================  IOM0IRQ  ======================================================== */
22345 /* ========================================================  IOM1IRQ  ======================================================== */
22346 /* ========================================================  IOM2IRQ  ======================================================== */
22347 /* ========================================================  IOM3IRQ  ======================================================== */
22348 /* ========================================================  IOM4IRQ  ======================================================== */
22349 /* ========================================================  IOM5IRQ  ======================================================== */
22350 /* =======================================================  BLEIFIRQ  ======================================================== */
22351 /* ========================================================  GPIOOBS  ======================================================== */
22352 /* ======================================================  ALTPADCFGA  ======================================================= */
22353 /* ===========================================  GPIO ALTPADCFGA PAD3_SR [28..28]  ============================================ */
22354 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD3_SR                                                   */
22355   GPIO_ALTPADCFGA_PAD3_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22356 } GPIO_ALTPADCFGA_PAD3_SR_Enum;
22357 
22358 /* ===========================================  GPIO ALTPADCFGA PAD2_SR [20..20]  ============================================ */
22359 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD2_SR                                                   */
22360   GPIO_ALTPADCFGA_PAD2_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22361 } GPIO_ALTPADCFGA_PAD2_SR_Enum;
22362 
22363 /* ===========================================  GPIO ALTPADCFGA PAD1_SR [12..12]  ============================================ */
22364 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD1_SR                                                   */
22365   GPIO_ALTPADCFGA_PAD1_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22366 } GPIO_ALTPADCFGA_PAD1_SR_Enum;
22367 
22368 /* ============================================  GPIO ALTPADCFGA PAD0_SR [4..4]  ============================================= */
22369 typedef enum {                                  /*!< GPIO_ALTPADCFGA_PAD0_SR                                                   */
22370   GPIO_ALTPADCFGA_PAD0_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22371 } GPIO_ALTPADCFGA_PAD0_SR_Enum;
22372 
22373 /* ======================================================  ALTPADCFGB  ======================================================= */
22374 /* ===========================================  GPIO ALTPADCFGB PAD7_SR [28..28]  ============================================ */
22375 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD7_SR                                                   */
22376   GPIO_ALTPADCFGB_PAD7_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22377 } GPIO_ALTPADCFGB_PAD7_SR_Enum;
22378 
22379 /* ===========================================  GPIO ALTPADCFGB PAD6_SR [20..20]  ============================================ */
22380 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD6_SR                                                   */
22381   GPIO_ALTPADCFGB_PAD6_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22382 } GPIO_ALTPADCFGB_PAD6_SR_Enum;
22383 
22384 /* ===========================================  GPIO ALTPADCFGB PAD5_SR [12..12]  ============================================ */
22385 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD5_SR                                                   */
22386   GPIO_ALTPADCFGB_PAD5_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22387 } GPIO_ALTPADCFGB_PAD5_SR_Enum;
22388 
22389 /* ============================================  GPIO ALTPADCFGB PAD4_SR [4..4]  ============================================= */
22390 typedef enum {                                  /*!< GPIO_ALTPADCFGB_PAD4_SR                                                   */
22391   GPIO_ALTPADCFGB_PAD4_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22392 } GPIO_ALTPADCFGB_PAD4_SR_Enum;
22393 
22394 /* ======================================================  ALTPADCFGC  ======================================================= */
22395 /* ===========================================  GPIO ALTPADCFGC PAD11_SR [28..28]  =========================================== */
22396 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD11_SR                                                  */
22397   GPIO_ALTPADCFGC_PAD11_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22398 } GPIO_ALTPADCFGC_PAD11_SR_Enum;
22399 
22400 /* ===========================================  GPIO ALTPADCFGC PAD10_SR [20..20]  =========================================== */
22401 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD10_SR                                                  */
22402   GPIO_ALTPADCFGC_PAD10_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22403 } GPIO_ALTPADCFGC_PAD10_SR_Enum;
22404 
22405 /* ===========================================  GPIO ALTPADCFGC PAD9_SR [12..12]  ============================================ */
22406 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD9_SR                                                   */
22407   GPIO_ALTPADCFGC_PAD9_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22408 } GPIO_ALTPADCFGC_PAD9_SR_Enum;
22409 
22410 /* ============================================  GPIO ALTPADCFGC PAD8_SR [4..4]  ============================================= */
22411 typedef enum {                                  /*!< GPIO_ALTPADCFGC_PAD8_SR                                                   */
22412   GPIO_ALTPADCFGC_PAD8_SR_SR_EN        = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22413 } GPIO_ALTPADCFGC_PAD8_SR_Enum;
22414 
22415 /* ======================================================  ALTPADCFGD  ======================================================= */
22416 /* ===========================================  GPIO ALTPADCFGD PAD15_SR [28..28]  =========================================== */
22417 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD15_SR                                                  */
22418   GPIO_ALTPADCFGD_PAD15_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22419 } GPIO_ALTPADCFGD_PAD15_SR_Enum;
22420 
22421 /* ===========================================  GPIO ALTPADCFGD PAD14_SR [20..20]  =========================================== */
22422 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD14_SR                                                  */
22423   GPIO_ALTPADCFGD_PAD14_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22424 } GPIO_ALTPADCFGD_PAD14_SR_Enum;
22425 
22426 /* ===========================================  GPIO ALTPADCFGD PAD13_SR [12..12]  =========================================== */
22427 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD13_SR                                                  */
22428   GPIO_ALTPADCFGD_PAD13_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22429 } GPIO_ALTPADCFGD_PAD13_SR_Enum;
22430 
22431 /* ============================================  GPIO ALTPADCFGD PAD12_SR [4..4]  ============================================ */
22432 typedef enum {                                  /*!< GPIO_ALTPADCFGD_PAD12_SR                                                  */
22433   GPIO_ALTPADCFGD_PAD12_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22434 } GPIO_ALTPADCFGD_PAD12_SR_Enum;
22435 
22436 /* ======================================================  ALTPADCFGE  ======================================================= */
22437 /* ===========================================  GPIO ALTPADCFGE PAD19_SR [28..28]  =========================================== */
22438 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD19_SR                                                  */
22439   GPIO_ALTPADCFGE_PAD19_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22440 } GPIO_ALTPADCFGE_PAD19_SR_Enum;
22441 
22442 /* ===========================================  GPIO ALTPADCFGE PAD18_SR [20..20]  =========================================== */
22443 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD18_SR                                                  */
22444   GPIO_ALTPADCFGE_PAD18_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22445 } GPIO_ALTPADCFGE_PAD18_SR_Enum;
22446 
22447 /* ===========================================  GPIO ALTPADCFGE PAD17_SR [12..12]  =========================================== */
22448 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD17_SR                                                  */
22449   GPIO_ALTPADCFGE_PAD17_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22450 } GPIO_ALTPADCFGE_PAD17_SR_Enum;
22451 
22452 /* ============================================  GPIO ALTPADCFGE PAD16_SR [4..4]  ============================================ */
22453 typedef enum {                                  /*!< GPIO_ALTPADCFGE_PAD16_SR                                                  */
22454   GPIO_ALTPADCFGE_PAD16_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22455 } GPIO_ALTPADCFGE_PAD16_SR_Enum;
22456 
22457 /* ======================================================  ALTPADCFGF  ======================================================= */
22458 /* ===========================================  GPIO ALTPADCFGF PAD23_SR [28..28]  =========================================== */
22459 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD23_SR                                                  */
22460   GPIO_ALTPADCFGF_PAD23_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22461 } GPIO_ALTPADCFGF_PAD23_SR_Enum;
22462 
22463 /* ===========================================  GPIO ALTPADCFGF PAD22_SR [20..20]  =========================================== */
22464 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD22_SR                                                  */
22465   GPIO_ALTPADCFGF_PAD22_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22466 } GPIO_ALTPADCFGF_PAD22_SR_Enum;
22467 
22468 /* ===========================================  GPIO ALTPADCFGF PAD21_SR [12..12]  =========================================== */
22469 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD21_SR                                                  */
22470   GPIO_ALTPADCFGF_PAD21_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22471 } GPIO_ALTPADCFGF_PAD21_SR_Enum;
22472 
22473 /* ============================================  GPIO ALTPADCFGF PAD20_SR [4..4]  ============================================ */
22474 typedef enum {                                  /*!< GPIO_ALTPADCFGF_PAD20_SR                                                  */
22475   GPIO_ALTPADCFGF_PAD20_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22476 } GPIO_ALTPADCFGF_PAD20_SR_Enum;
22477 
22478 /* ======================================================  ALTPADCFGG  ======================================================= */
22479 /* ===========================================  GPIO ALTPADCFGG PAD27_SR [28..28]  =========================================== */
22480 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD27_SR                                                  */
22481   GPIO_ALTPADCFGG_PAD27_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22482 } GPIO_ALTPADCFGG_PAD27_SR_Enum;
22483 
22484 /* ===========================================  GPIO ALTPADCFGG PAD26_SR [20..20]  =========================================== */
22485 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD26_SR                                                  */
22486   GPIO_ALTPADCFGG_PAD26_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22487 } GPIO_ALTPADCFGG_PAD26_SR_Enum;
22488 
22489 /* ===========================================  GPIO ALTPADCFGG PAD25_SR [12..12]  =========================================== */
22490 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD25_SR                                                  */
22491   GPIO_ALTPADCFGG_PAD25_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22492 } GPIO_ALTPADCFGG_PAD25_SR_Enum;
22493 
22494 /* ============================================  GPIO ALTPADCFGG PAD24_SR [4..4]  ============================================ */
22495 typedef enum {                                  /*!< GPIO_ALTPADCFGG_PAD24_SR                                                  */
22496   GPIO_ALTPADCFGG_PAD24_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22497 } GPIO_ALTPADCFGG_PAD24_SR_Enum;
22498 
22499 /* ======================================================  ALTPADCFGH  ======================================================= */
22500 /* ===========================================  GPIO ALTPADCFGH PAD31_SR [28..28]  =========================================== */
22501 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD31_SR                                                  */
22502   GPIO_ALTPADCFGH_PAD31_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22503 } GPIO_ALTPADCFGH_PAD31_SR_Enum;
22504 
22505 /* ===========================================  GPIO ALTPADCFGH PAD30_SR [20..20]  =========================================== */
22506 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD30_SR                                                  */
22507   GPIO_ALTPADCFGH_PAD30_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22508 } GPIO_ALTPADCFGH_PAD30_SR_Enum;
22509 
22510 /* ===========================================  GPIO ALTPADCFGH PAD29_SR [12..12]  =========================================== */
22511 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD29_SR                                                  */
22512   GPIO_ALTPADCFGH_PAD29_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22513 } GPIO_ALTPADCFGH_PAD29_SR_Enum;
22514 
22515 /* ============================================  GPIO ALTPADCFGH PAD28_SR [4..4]  ============================================ */
22516 typedef enum {                                  /*!< GPIO_ALTPADCFGH_PAD28_SR                                                  */
22517   GPIO_ALTPADCFGH_PAD28_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22518 } GPIO_ALTPADCFGH_PAD28_SR_Enum;
22519 
22520 /* ======================================================  ALTPADCFGI  ======================================================= */
22521 /* ===========================================  GPIO ALTPADCFGI PAD35_SR [28..28]  =========================================== */
22522 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD35_SR                                                  */
22523   GPIO_ALTPADCFGI_PAD35_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22524 } GPIO_ALTPADCFGI_PAD35_SR_Enum;
22525 
22526 /* ===========================================  GPIO ALTPADCFGI PAD34_SR [20..20]  =========================================== */
22527 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD34_SR                                                  */
22528   GPIO_ALTPADCFGI_PAD34_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22529 } GPIO_ALTPADCFGI_PAD34_SR_Enum;
22530 
22531 /* ===========================================  GPIO ALTPADCFGI PAD33_SR [12..12]  =========================================== */
22532 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD33_SR                                                  */
22533   GPIO_ALTPADCFGI_PAD33_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22534 } GPIO_ALTPADCFGI_PAD33_SR_Enum;
22535 
22536 /* ============================================  GPIO ALTPADCFGI PAD32_SR [4..4]  ============================================ */
22537 typedef enum {                                  /*!< GPIO_ALTPADCFGI_PAD32_SR                                                  */
22538   GPIO_ALTPADCFGI_PAD32_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22539 } GPIO_ALTPADCFGI_PAD32_SR_Enum;
22540 
22541 /* ======================================================  ALTPADCFGJ  ======================================================= */
22542 /* ===========================================  GPIO ALTPADCFGJ PAD39_SR [28..28]  =========================================== */
22543 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD39_SR                                                  */
22544   GPIO_ALTPADCFGJ_PAD39_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22545 } GPIO_ALTPADCFGJ_PAD39_SR_Enum;
22546 
22547 /* ===========================================  GPIO ALTPADCFGJ PAD38_SR [20..20]  =========================================== */
22548 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD38_SR                                                  */
22549   GPIO_ALTPADCFGJ_PAD38_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22550 } GPIO_ALTPADCFGJ_PAD38_SR_Enum;
22551 
22552 /* ===========================================  GPIO ALTPADCFGJ PAD37_SR [12..12]  =========================================== */
22553 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD37_SR                                                  */
22554   GPIO_ALTPADCFGJ_PAD37_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22555 } GPIO_ALTPADCFGJ_PAD37_SR_Enum;
22556 
22557 /* ============================================  GPIO ALTPADCFGJ PAD36_SR [4..4]  ============================================ */
22558 typedef enum {                                  /*!< GPIO_ALTPADCFGJ_PAD36_SR                                                  */
22559   GPIO_ALTPADCFGJ_PAD36_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22560 } GPIO_ALTPADCFGJ_PAD36_SR_Enum;
22561 
22562 /* ======================================================  ALTPADCFGK  ======================================================= */
22563 /* ===========================================  GPIO ALTPADCFGK PAD43_SR [28..28]  =========================================== */
22564 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD43_SR                                                  */
22565   GPIO_ALTPADCFGK_PAD43_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22566 } GPIO_ALTPADCFGK_PAD43_SR_Enum;
22567 
22568 /* ===========================================  GPIO ALTPADCFGK PAD42_SR [20..20]  =========================================== */
22569 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD42_SR                                                  */
22570   GPIO_ALTPADCFGK_PAD42_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22571 } GPIO_ALTPADCFGK_PAD42_SR_Enum;
22572 
22573 /* ===========================================  GPIO ALTPADCFGK PAD41_SR [12..12]  =========================================== */
22574 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD41_SR                                                  */
22575   GPIO_ALTPADCFGK_PAD41_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22576 } GPIO_ALTPADCFGK_PAD41_SR_Enum;
22577 
22578 /* ============================================  GPIO ALTPADCFGK PAD40_SR [4..4]  ============================================ */
22579 typedef enum {                                  /*!< GPIO_ALTPADCFGK_PAD40_SR                                                  */
22580   GPIO_ALTPADCFGK_PAD40_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22581 } GPIO_ALTPADCFGK_PAD40_SR_Enum;
22582 
22583 /* ======================================================  ALTPADCFGL  ======================================================= */
22584 /* ===========================================  GPIO ALTPADCFGL PAD47_SR [28..28]  =========================================== */
22585 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD47_SR                                                  */
22586   GPIO_ALTPADCFGL_PAD47_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22587 } GPIO_ALTPADCFGL_PAD47_SR_Enum;
22588 
22589 /* ===========================================  GPIO ALTPADCFGL PAD46_SR [20..20]  =========================================== */
22590 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD46_SR                                                  */
22591   GPIO_ALTPADCFGL_PAD46_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22592 } GPIO_ALTPADCFGL_PAD46_SR_Enum;
22593 
22594 /* ===========================================  GPIO ALTPADCFGL PAD45_SR [12..12]  =========================================== */
22595 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD45_SR                                                  */
22596   GPIO_ALTPADCFGL_PAD45_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22597 } GPIO_ALTPADCFGL_PAD45_SR_Enum;
22598 
22599 /* ============================================  GPIO ALTPADCFGL PAD44_SR [4..4]  ============================================ */
22600 typedef enum {                                  /*!< GPIO_ALTPADCFGL_PAD44_SR                                                  */
22601   GPIO_ALTPADCFGL_PAD44_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22602 } GPIO_ALTPADCFGL_PAD44_SR_Enum;
22603 
22604 /* ======================================================  ALTPADCFGM  ======================================================= */
22605 /* ===========================================  GPIO ALTPADCFGM PAD49_SR [12..12]  =========================================== */
22606 typedef enum {                                  /*!< GPIO_ALTPADCFGM_PAD49_SR                                                  */
22607   GPIO_ALTPADCFGM_PAD49_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22608 } GPIO_ALTPADCFGM_PAD49_SR_Enum;
22609 
22610 /* ============================================  GPIO ALTPADCFGM PAD48_SR [4..4]  ============================================ */
22611 typedef enum {                                  /*!< GPIO_ALTPADCFGM_PAD48_SR                                                  */
22612   GPIO_ALTPADCFGM_PAD48_SR_SR_EN       = 1,     /*!< SR_EN : Enables Slew rate control on pad                                  */
22613 } GPIO_ALTPADCFGM_PAD48_SR_Enum;
22614 
22615 /* =========================================================  SCDET  ========================================================= */
22616 /* ========================================================  CTENCFG  ======================================================== */
22617 /* ==============================================  GPIO CTENCFG EN31 [31..31]  =============================================== */
22618 typedef enum {                                  /*!< GPIO_CTENCFG_EN31                                                         */
22619   GPIO_CTENCFG_EN31_DIS                = 1,     /*!< DIS : Disable CT31 for output                                             */
22620   GPIO_CTENCFG_EN31_EN                 = 0,     /*!< EN : Enable CT31 for output                                               */
22621 } GPIO_CTENCFG_EN31_Enum;
22622 
22623 /* ==============================================  GPIO CTENCFG EN30 [30..30]  =============================================== */
22624 typedef enum {                                  /*!< GPIO_CTENCFG_EN30                                                         */
22625   GPIO_CTENCFG_EN30_DIS                = 1,     /*!< DIS : Disable CT30 for output                                             */
22626   GPIO_CTENCFG_EN30_EN                 = 0,     /*!< EN : Enable CT30 for output                                               */
22627 } GPIO_CTENCFG_EN30_Enum;
22628 
22629 /* ==============================================  GPIO CTENCFG EN29 [29..29]  =============================================== */
22630 typedef enum {                                  /*!< GPIO_CTENCFG_EN29                                                         */
22631   GPIO_CTENCFG_EN29_DIS                = 1,     /*!< DIS : Disable CT29 for output                                             */
22632   GPIO_CTENCFG_EN29_EN                 = 0,     /*!< EN : Enable CT29 for output                                               */
22633 } GPIO_CTENCFG_EN29_Enum;
22634 
22635 /* ==============================================  GPIO CTENCFG EN28 [28..28]  =============================================== */
22636 typedef enum {                                  /*!< GPIO_CTENCFG_EN28                                                         */
22637   GPIO_CTENCFG_EN28_DIS                = 1,     /*!< DIS : Disable CT28 for output                                             */
22638   GPIO_CTENCFG_EN28_EN                 = 0,     /*!< EN : Enable CT28 for output                                               */
22639 } GPIO_CTENCFG_EN28_Enum;
22640 
22641 /* ==============================================  GPIO CTENCFG EN27 [27..27]  =============================================== */
22642 typedef enum {                                  /*!< GPIO_CTENCFG_EN27                                                         */
22643   GPIO_CTENCFG_EN27_DIS                = 1,     /*!< DIS : Disable CT27 for output                                             */
22644   GPIO_CTENCFG_EN27_EN                 = 0,     /*!< EN : Enable CT27 for output                                               */
22645 } GPIO_CTENCFG_EN27_Enum;
22646 
22647 /* ==============================================  GPIO CTENCFG EN26 [26..26]  =============================================== */
22648 typedef enum {                                  /*!< GPIO_CTENCFG_EN26                                                         */
22649   GPIO_CTENCFG_EN26_DIS                = 1,     /*!< DIS : Disable CT26 for output                                             */
22650   GPIO_CTENCFG_EN26_EN                 = 0,     /*!< EN : Enable CT26 for output                                               */
22651 } GPIO_CTENCFG_EN26_Enum;
22652 
22653 /* ==============================================  GPIO CTENCFG EN25 [25..25]  =============================================== */
22654 typedef enum {                                  /*!< GPIO_CTENCFG_EN25                                                         */
22655   GPIO_CTENCFG_EN25_DIS                = 1,     /*!< DIS : Disable CT25 for output                                             */
22656   GPIO_CTENCFG_EN25_EN                 = 0,     /*!< EN : Enable CT25 for output                                               */
22657 } GPIO_CTENCFG_EN25_Enum;
22658 
22659 /* ==============================================  GPIO CTENCFG EN24 [24..24]  =============================================== */
22660 typedef enum {                                  /*!< GPIO_CTENCFG_EN24                                                         */
22661   GPIO_CTENCFG_EN24_DIS                = 1,     /*!< DIS : Disable CT24 for output                                             */
22662   GPIO_CTENCFG_EN24_EN                 = 0,     /*!< EN : Enable CT24 for output                                               */
22663 } GPIO_CTENCFG_EN24_Enum;
22664 
22665 /* ==============================================  GPIO CTENCFG EN23 [23..23]  =============================================== */
22666 typedef enum {                                  /*!< GPIO_CTENCFG_EN23                                                         */
22667   GPIO_CTENCFG_EN23_DIS                = 1,     /*!< DIS : Disable CT23 for output                                             */
22668   GPIO_CTENCFG_EN23_EN                 = 0,     /*!< EN : Enable CT23 for output                                               */
22669 } GPIO_CTENCFG_EN23_Enum;
22670 
22671 /* ==============================================  GPIO CTENCFG EN22 [22..22]  =============================================== */
22672 typedef enum {                                  /*!< GPIO_CTENCFG_EN22                                                         */
22673   GPIO_CTENCFG_EN22_DIS                = 1,     /*!< DIS : Disable CT22 for output                                             */
22674   GPIO_CTENCFG_EN22_EN                 = 0,     /*!< EN : Enable CT22 for output                                               */
22675 } GPIO_CTENCFG_EN22_Enum;
22676 
22677 /* ==============================================  GPIO CTENCFG EN21 [21..21]  =============================================== */
22678 typedef enum {                                  /*!< GPIO_CTENCFG_EN21                                                         */
22679   GPIO_CTENCFG_EN21_DIS                = 1,     /*!< DIS : Disable CT21 for output                                             */
22680   GPIO_CTENCFG_EN21_EN                 = 0,     /*!< EN : Enable CT21 for output                                               */
22681 } GPIO_CTENCFG_EN21_Enum;
22682 
22683 /* ==============================================  GPIO CTENCFG EN20 [20..20]  =============================================== */
22684 typedef enum {                                  /*!< GPIO_CTENCFG_EN20                                                         */
22685   GPIO_CTENCFG_EN20_DIS                = 1,     /*!< DIS : Disable CT20 for output                                             */
22686   GPIO_CTENCFG_EN20_EN                 = 0,     /*!< EN : Enable CT20 for output                                               */
22687 } GPIO_CTENCFG_EN20_Enum;
22688 
22689 /* ==============================================  GPIO CTENCFG EN19 [19..19]  =============================================== */
22690 typedef enum {                                  /*!< GPIO_CTENCFG_EN19                                                         */
22691   GPIO_CTENCFG_EN19_DIS                = 1,     /*!< DIS : Disable CT19 for output                                             */
22692   GPIO_CTENCFG_EN19_EN                 = 0,     /*!< EN : Enable CT19 for output                                               */
22693 } GPIO_CTENCFG_EN19_Enum;
22694 
22695 /* ==============================================  GPIO CTENCFG EN18 [18..18]  =============================================== */
22696 typedef enum {                                  /*!< GPIO_CTENCFG_EN18                                                         */
22697   GPIO_CTENCFG_EN18_DIS                = 1,     /*!< DIS : Disable CT18 for output                                             */
22698   GPIO_CTENCFG_EN18_EN                 = 0,     /*!< EN : Enable CT18 for output                                               */
22699 } GPIO_CTENCFG_EN18_Enum;
22700 
22701 /* ==============================================  GPIO CTENCFG EN17 [17..17]  =============================================== */
22702 typedef enum {                                  /*!< GPIO_CTENCFG_EN17                                                         */
22703   GPIO_CTENCFG_EN17_DIS                = 1,     /*!< DIS : Disable CT17 for output                                             */
22704   GPIO_CTENCFG_EN17_EN                 = 0,     /*!< EN : Enable CT17 for output                                               */
22705 } GPIO_CTENCFG_EN17_Enum;
22706 
22707 /* ==============================================  GPIO CTENCFG EN16 [16..16]  =============================================== */
22708 typedef enum {                                  /*!< GPIO_CTENCFG_EN16                                                         */
22709   GPIO_CTENCFG_EN16_DIS                = 1,     /*!< DIS : Disable CT16 for output                                             */
22710   GPIO_CTENCFG_EN16_EN                 = 0,     /*!< EN : Enable CT16 for output                                               */
22711 } GPIO_CTENCFG_EN16_Enum;
22712 
22713 /* ==============================================  GPIO CTENCFG EN15 [15..15]  =============================================== */
22714 typedef enum {                                  /*!< GPIO_CTENCFG_EN15                                                         */
22715   GPIO_CTENCFG_EN15_DIS                = 1,     /*!< DIS : Disable CT15 for output                                             */
22716   GPIO_CTENCFG_EN15_EN                 = 0,     /*!< EN : Enable CT15 for output                                               */
22717 } GPIO_CTENCFG_EN15_Enum;
22718 
22719 /* ==============================================  GPIO CTENCFG EN14 [14..14]  =============================================== */
22720 typedef enum {                                  /*!< GPIO_CTENCFG_EN14                                                         */
22721   GPIO_CTENCFG_EN14_DIS                = 1,     /*!< DIS : Disable CT14 for output                                             */
22722   GPIO_CTENCFG_EN14_EN                 = 0,     /*!< EN : Enable CT14 for output                                               */
22723 } GPIO_CTENCFG_EN14_Enum;
22724 
22725 /* ==============================================  GPIO CTENCFG EN13 [13..13]  =============================================== */
22726 typedef enum {                                  /*!< GPIO_CTENCFG_EN13                                                         */
22727   GPIO_CTENCFG_EN13_DIS                = 1,     /*!< DIS : Disable CT13 for output                                             */
22728   GPIO_CTENCFG_EN13_EN                 = 0,     /*!< EN : Enable CT13 for output                                               */
22729 } GPIO_CTENCFG_EN13_Enum;
22730 
22731 /* ==============================================  GPIO CTENCFG EN12 [12..12]  =============================================== */
22732 typedef enum {                                  /*!< GPIO_CTENCFG_EN12                                                         */
22733   GPIO_CTENCFG_EN12_DIS                = 1,     /*!< DIS : Disable CT12 for output                                             */
22734   GPIO_CTENCFG_EN12_EN                 = 0,     /*!< EN : Enable CT12 for output                                               */
22735 } GPIO_CTENCFG_EN12_Enum;
22736 
22737 /* ==============================================  GPIO CTENCFG EN11 [11..11]  =============================================== */
22738 typedef enum {                                  /*!< GPIO_CTENCFG_EN11                                                         */
22739   GPIO_CTENCFG_EN11_DIS                = 1,     /*!< DIS : Disable CT11 for output                                             */
22740   GPIO_CTENCFG_EN11_EN                 = 0,     /*!< EN : Enable CT11 for output                                               */
22741 } GPIO_CTENCFG_EN11_Enum;
22742 
22743 /* ==============================================  GPIO CTENCFG EN10 [10..10]  =============================================== */
22744 typedef enum {                                  /*!< GPIO_CTENCFG_EN10                                                         */
22745   GPIO_CTENCFG_EN10_DIS                = 1,     /*!< DIS : Disable CT10 for output                                             */
22746   GPIO_CTENCFG_EN10_EN                 = 0,     /*!< EN : Enable CT10 for output                                               */
22747 } GPIO_CTENCFG_EN10_Enum;
22748 
22749 /* ================================================  GPIO CTENCFG EN9 [9..9]  ================================================ */
22750 typedef enum {                                  /*!< GPIO_CTENCFG_EN9                                                          */
22751   GPIO_CTENCFG_EN9_DIS                 = 0,     /*!< DIS : Disable CT9 for output                                              */
22752 } GPIO_CTENCFG_EN9_Enum;
22753 
22754 /* ================================================  GPIO CTENCFG EN8 [8..8]  ================================================ */
22755 typedef enum {                                  /*!< GPIO_CTENCFG_EN8                                                          */
22756   GPIO_CTENCFG_EN8_DIS                 = 1,     /*!< DIS : Disable CT8 for output                                              */
22757   GPIO_CTENCFG_EN8_EN                  = 0,     /*!< EN : Enable CT8 for output                                                */
22758 } GPIO_CTENCFG_EN8_Enum;
22759 
22760 /* ================================================  GPIO CTENCFG EN7 [7..7]  ================================================ */
22761 typedef enum {                                  /*!< GPIO_CTENCFG_EN7                                                          */
22762   GPIO_CTENCFG_EN7_DIS                 = 1,     /*!< DIS : Disable CT7 for output                                              */
22763   GPIO_CTENCFG_EN7_EN                  = 0,     /*!< EN : Enable CT7 for output                                                */
22764 } GPIO_CTENCFG_EN7_Enum;
22765 
22766 /* ================================================  GPIO CTENCFG EN6 [6..6]  ================================================ */
22767 typedef enum {                                  /*!< GPIO_CTENCFG_EN6                                                          */
22768   GPIO_CTENCFG_EN6_DIS                 = 1,     /*!< DIS : Disable CT6 for output                                              */
22769   GPIO_CTENCFG_EN6_EN                  = 0,     /*!< EN : Enable CT6 for output                                                */
22770 } GPIO_CTENCFG_EN6_Enum;
22771 
22772 /* ================================================  GPIO CTENCFG EN5 [5..5]  ================================================ */
22773 typedef enum {                                  /*!< GPIO_CTENCFG_EN5                                                          */
22774   GPIO_CTENCFG_EN5_DIS                 = 1,     /*!< DIS : Disable CT5 for output                                              */
22775   GPIO_CTENCFG_EN5_EN                  = 0,     /*!< EN : Enable CT5 for output                                                */
22776 } GPIO_CTENCFG_EN5_Enum;
22777 
22778 /* ================================================  GPIO CTENCFG EN4 [4..4]  ================================================ */
22779 typedef enum {                                  /*!< GPIO_CTENCFG_EN4                                                          */
22780   GPIO_CTENCFG_EN4_DIS                 = 1,     /*!< DIS : Disable CT4 for output                                              */
22781   GPIO_CTENCFG_EN4_EN                  = 0,     /*!< EN : Enable CT4 for output                                                */
22782 } GPIO_CTENCFG_EN4_Enum;
22783 
22784 /* ================================================  GPIO CTENCFG EN3 [3..3]  ================================================ */
22785 typedef enum {                                  /*!< GPIO_CTENCFG_EN3                                                          */
22786   GPIO_CTENCFG_EN3_DIS                 = 1,     /*!< DIS : Disable CT3 for output                                              */
22787   GPIO_CTENCFG_EN3_EN                  = 0,     /*!< EN : Enable CT3 for output                                                */
22788 } GPIO_CTENCFG_EN3_Enum;
22789 
22790 /* ================================================  GPIO CTENCFG EN2 [2..2]  ================================================ */
22791 typedef enum {                                  /*!< GPIO_CTENCFG_EN2                                                          */
22792   GPIO_CTENCFG_EN2_DIS                 = 1,     /*!< DIS : Disable CT2 for output                                              */
22793   GPIO_CTENCFG_EN2_EN                  = 0,     /*!< EN : Enable CT2 for output                                                */
22794 } GPIO_CTENCFG_EN2_Enum;
22795 
22796 /* ================================================  GPIO CTENCFG EN1 [1..1]  ================================================ */
22797 typedef enum {                                  /*!< GPIO_CTENCFG_EN1                                                          */
22798   GPIO_CTENCFG_EN1_DIS                 = 1,     /*!< DIS : Disable CT1 for output                                              */
22799   GPIO_CTENCFG_EN1_EN                  = 0,     /*!< EN : Enable CT1 for output                                                */
22800 } GPIO_CTENCFG_EN1_Enum;
22801 
22802 /* ================================================  GPIO CTENCFG EN0 [0..0]  ================================================ */
22803 typedef enum {                                  /*!< GPIO_CTENCFG_EN0                                                          */
22804   GPIO_CTENCFG_EN0_DIS                 = 1,     /*!< DIS : Disable CT0 for output                                              */
22805   GPIO_CTENCFG_EN0_EN                  = 0,     /*!< EN : Enable CT0 for output                                                */
22806 } GPIO_CTENCFG_EN0_Enum;
22807 
22808 /* ========================================================  INT0EN  ========================================================= */
22809 /* =======================================================  INT0STAT  ======================================================== */
22810 /* ========================================================  INT0CLR  ======================================================== */
22811 /* ========================================================  INT0SET  ======================================================== */
22812 /* ========================================================  INT1EN  ========================================================= */
22813 /* =======================================================  INT1STAT  ======================================================== */
22814 /* ========================================================  INT1CLR  ======================================================== */
22815 /* ========================================================  INT1SET  ======================================================== */
22816 
22817 
22818 /* =========================================================================================================================== */
22819 /* ================                                           IOM0                                            ================ */
22820 /* =========================================================================================================================== */
22821 
22822 /* =========================================================  FIFO  ========================================================== */
22823 /* ========================================================  FIFOPTR  ======================================================== */
22824 /* ========================================================  FIFOTHR  ======================================================== */
22825 /* ========================================================  FIFOPOP  ======================================================== */
22826 /* =======================================================  FIFOPUSH  ======================================================== */
22827 /* =======================================================  FIFOCTRL  ======================================================== */
22828 /* ========================================================  FIFOLOC  ======================================================== */
22829 /* =========================================================  INTEN  ========================================================= */
22830 /* ========================================================  INTSTAT  ======================================================== */
22831 /* ========================================================  INTCLR  ========================================================= */
22832 /* ========================================================  INTSET  ========================================================= */
22833 /* ========================================================  CLKCFG  ========================================================= */
22834 /* ==============================================  IOM0 CLKCFG DIVEN [12..12]  =============================================== */
22835 typedef enum {                                  /*!< IOM0_CLKCFG_DIVEN                                                         */
22836   IOM0_CLKCFG_DIVEN_DIS                = 0,     /*!< DIS : Disable TOTPER division.                                            */
22837   IOM0_CLKCFG_DIVEN_EN                 = 1,     /*!< EN : Enable TOTPER division.                                              */
22838 } IOM0_CLKCFG_DIVEN_Enum;
22839 
22840 /* ===============================================  IOM0 CLKCFG DIV3 [11..11]  =============================================== */
22841 typedef enum {                                  /*!< IOM0_CLKCFG_DIV3                                                          */
22842   IOM0_CLKCFG_DIV3_DIS                 = 0,     /*!< DIS : Select divide by 1.                                                 */
22843   IOM0_CLKCFG_DIV3_EN                  = 1,     /*!< EN : Select divide by 3.                                                  */
22844 } IOM0_CLKCFG_DIV3_Enum;
22845 
22846 /* ===============================================  IOM0 CLKCFG FSEL [8..10]  ================================================ */
22847 typedef enum {                                  /*!< IOM0_CLKCFG_FSEL                                                          */
22848   IOM0_CLKCFG_FSEL_MIN_PWR             = 0,     /*!< MIN_PWR : Selects the minimum power clock. This setting should
22849                                                      be used whenever the IOM is not active.                                   */
22850   IOM0_CLKCFG_FSEL_HFRC                = 1,     /*!< HFRC : Selects the HFRC as the input clock.                               */
22851   IOM0_CLKCFG_FSEL_HFRC_DIV2           = 2,     /*!< HFRC_DIV2 : Selects the HFRC / 2 as the input clock.                      */
22852   IOM0_CLKCFG_FSEL_HFRC_DIV4           = 3,     /*!< HFRC_DIV4 : Selects the HFRC / 4 as the input clock.                      */
22853   IOM0_CLKCFG_FSEL_HFRC_DIV8           = 4,     /*!< HFRC_DIV8 : Selects the HFRC / 8 as the input clock.                      */
22854   IOM0_CLKCFG_FSEL_HFRC_DIV16          = 5,     /*!< HFRC_DIV16 : Selects the HFRC / 16 as the input clock.                    */
22855   IOM0_CLKCFG_FSEL_HFRC_DIV32          = 6,     /*!< HFRC_DIV32 : Selects the HFRC / 32 as the input clock.                    */
22856   IOM0_CLKCFG_FSEL_HFRC_DIV64          = 7,     /*!< HFRC_DIV64 : Selects the HFRC / 64 as the input clock.                    */
22857 } IOM0_CLKCFG_FSEL_Enum;
22858 
22859 /* ======================================================  SUBMODCTRL  ======================================================= */
22860 /* ===========================================  IOM0 SUBMODCTRL SMOD1TYPE [5..7]  ============================================ */
22861 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD1TYPE                                                 */
22862   IOM0_SUBMODCTRL_SMOD1TYPE_MSPI       = 0,     /*!< MSPI : SPI Master submodule                                               */
22863   IOM0_SUBMODCTRL_SMOD1TYPE_I2C_MASTER = 1,     /*!< I2C_MASTER : MI2C submodule                                               */
22864   IOM0_SUBMODCTRL_SMOD1TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
22865   IOM0_SUBMODCTRL_SMOD1TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
22866   IOM0_SUBMODCTRL_SMOD1TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
22867 } IOM0_SUBMODCTRL_SMOD1TYPE_Enum;
22868 
22869 /* ===========================================  IOM0 SUBMODCTRL SMOD0TYPE [1..3]  ============================================ */
22870 typedef enum {                                  /*!< IOM0_SUBMODCTRL_SMOD0TYPE                                                 */
22871   IOM0_SUBMODCTRL_SMOD0TYPE_SPI_MASTER = 0,     /*!< SPI_MASTER : MSPI submodule                                               */
22872   IOM0_SUBMODCTRL_SMOD0TYPE_I2C_MASTER = 1,     /*!< I2C_MASTER : I2C Master submodule                                         */
22873   IOM0_SUBMODCTRL_SMOD0TYPE_SSPI       = 2,     /*!< SSPI : SPI Slave submodule                                                */
22874   IOM0_SUBMODCTRL_SMOD0TYPE_SI2C       = 3,     /*!< SI2C : I2C Slave submodule                                                */
22875   IOM0_SUBMODCTRL_SMOD0TYPE_NA         = 7,     /*!< NA : NOT INSTALLED                                                        */
22876 } IOM0_SUBMODCTRL_SMOD0TYPE_Enum;
22877 
22878 /* ==========================================================  CMD  ========================================================== */
22879 /* ==================================================  IOM0 CMD CMD [0..4]  ================================================== */
22880 typedef enum {                                  /*!< IOM0_CMD_CMD                                                              */
22881   IOM0_CMD_CMD_WRITE                   = 1,     /*!< WRITE : Write command using count of offset bytes specified
22882                                                      in the OFFSETCNT field                                                    */
22883   IOM0_CMD_CMD_READ                    = 2,     /*!< READ : Read command using count of offset bytes specified in
22884                                                      the OFFSETCNT field                                                       */
22885   IOM0_CMD_CMD_TMW                     = 3,     /*!< TMW : SPI only. Test mode to do constant write operations. Useful
22886                                                      for debug and power measurements. Will continually send
22887                                                      data in OFFSET field                                                      */
22888   IOM0_CMD_CMD_TMR                     = 4,     /*!< TMR : SPI Only. Test mode to do constant read operations. Useful
22889                                                      for debug and power measurements. Will continually read
22890                                                      data from external input                                                  */
22891 } IOM0_CMD_CMD_Enum;
22892 
22893 /* ==========================================================  DCX  ========================================================== */
22894 /* =================================================  IOM0 DCX DCXEN [4..4]  ================================================= */
22895 typedef enum {                                  /*!< IOM0_DCX_DCXEN                                                            */
22896   IOM0_DCX_DCXEN_EN                    = 1,     /*!< EN : Enable DCX.                                                          */
22897   IOM0_DCX_DCXEN_DIS                   = 0,     /*!< DIS : Disable DCX.                                                        */
22898 } IOM0_DCX_DCXEN_Enum;
22899 
22900 /* =======================================================  OFFSETHI  ======================================================== */
22901 /* ========================================================  CMDSTAT  ======================================================== */
22902 /* ==============================================  IOM0 CMDSTAT CMDSTAT [5..7]  ============================================== */
22903 typedef enum {                                  /*!< IOM0_CMDSTAT_CMDSTAT                                                      */
22904   IOM0_CMDSTAT_CMDSTAT_ERR             = 1,     /*!< ERR : Error encountered with command                                      */
22905   IOM0_CMDSTAT_CMDSTAT_ACTIVE          = 2,     /*!< ACTIVE : Actively processing command                                      */
22906   IOM0_CMDSTAT_CMDSTAT_IDLE            = 4,     /*!< IDLE : Idle state, no active command, no error                            */
22907   IOM0_CMDSTAT_CMDSTAT_WAIT            = 6,     /*!< WAIT : Command in progress, but waiting on data from host                 */
22908 } IOM0_CMDSTAT_CMDSTAT_Enum;
22909 
22910 /* =======================================================  DMATRIGEN  ======================================================= */
22911 /* ======================================================  DMATRIGSTAT  ====================================================== */
22912 /* ========================================================  DMACFG  ========================================================= */
22913 /* ==============================================  IOM0 DMACFG DPWROFF [9..9]  =============================================== */
22914 typedef enum {                                  /*!< IOM0_DMACFG_DPWROFF                                                       */
22915   IOM0_DMACFG_DPWROFF_DIS              = 0,     /*!< DIS : Power off disabled                                                  */
22916   IOM0_DMACFG_DPWROFF_EN               = 1,     /*!< EN : Power off enabled                                                    */
22917 } IOM0_DMACFG_DPWROFF_Enum;
22918 
22919 /* ===============================================  IOM0 DMACFG DMAPRI [8..8]  =============================================== */
22920 typedef enum {                                  /*!< IOM0_DMACFG_DMAPRI                                                        */
22921   IOM0_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
22922   IOM0_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
22923 } IOM0_DMACFG_DMAPRI_Enum;
22924 
22925 /* ===============================================  IOM0 DMACFG DMADIR [1..1]  =============================================== */
22926 typedef enum {                                  /*!< IOM0_DMACFG_DMADIR                                                        */
22927   IOM0_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. To be set when
22928                                                      doing IOM read operations, i.e., reading data from external
22929                                                      devices.                                                                  */
22930   IOM0_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction. To be set when doing
22931                                                      IOM write operations, i.e., writing data to external devices.             */
22932 } IOM0_DMACFG_DMADIR_Enum;
22933 
22934 /* ===============================================  IOM0 DMACFG DMAEN [0..0]  ================================================ */
22935 typedef enum {                                  /*!< IOM0_DMACFG_DMAEN                                                         */
22936   IOM0_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
22937   IOM0_DMACFG_DMAEN_EN                 = 1,     /*!< EN : Enable DMA Function                                                  */
22938 } IOM0_DMACFG_DMAEN_Enum;
22939 
22940 /* ======================================================  DMATOTCOUNT  ====================================================== */
22941 /* ======================================================  DMATARGADDR  ====================================================== */
22942 /* ========================================================  DMASTAT  ======================================================== */
22943 /* =========================================================  CQCFG  ========================================================= */
22944 /* ================================================  IOM0 CQCFG CQPRI [1..1]  ================================================ */
22945 typedef enum {                                  /*!< IOM0_CQCFG_CQPRI                                                          */
22946   IOM0_CQCFG_CQPRI_LOW                 = 0,     /*!< LOW : Low Priority (service as best effort)                               */
22947   IOM0_CQCFG_CQPRI_HIGH                = 1,     /*!< HIGH : High Priority (service immediately)                                */
22948 } IOM0_CQCFG_CQPRI_Enum;
22949 
22950 /* ================================================  IOM0 CQCFG CQEN [0..0]  ================================================= */
22951 typedef enum {                                  /*!< IOM0_CQCFG_CQEN                                                           */
22952   IOM0_CQCFG_CQEN_DIS                  = 0,     /*!< DIS : Disable CQ Function                                                 */
22953   IOM0_CQCFG_CQEN_EN                   = 1,     /*!< EN : Enable CQ Function                                                   */
22954 } IOM0_CQCFG_CQEN_Enum;
22955 
22956 /* ========================================================  CQADDR  ========================================================= */
22957 /* ========================================================  CQSTAT  ========================================================= */
22958 /* ========================================================  CQFLAGS  ======================================================== */
22959 /* ======================================================  CQSETCLEAR  ======================================================= */
22960 /* =======================================================  CQPAUSEEN  ======================================================= */
22961 /* =============================================  IOM0 CQPAUSEEN CQPEN [0..15]  ============================================== */
22962 typedef enum {                                  /*!< IOM0_CQPAUSEEN_CQPEN                                                      */
22963   IOM0_CQPAUSEEN_CQPEN_IDXEQ           = 32768, /*!< IDXEQ : Pauses the command queue when the current index matches
22964                                                      the last index                                                            */
22965   IOM0_CQPAUSEEN_CQPEN_BLEXOREN        = 16384, /*!< BLEXOREN : Pause command queue when input BLE bit XORed with
22966                                                      SWFLAG4 is '1'                                                            */
22967   IOM0_CQPAUSEEN_CQPEN_IOMXOREN        = 8192,  /*!< IOMXOREN : Pause command queue when input IOM bit XORed with
22968                                                      SWFLAG3 is '1'                                                            */
22969   IOM0_CQPAUSEEN_CQPEN_GPIOXOREN       = 4096,  /*!< GPIOXOREN : Pause command queue when input GPIO irq_bit XORed
22970                                                      with SWFLAG2 is '1'                                                       */
22971   IOM0_CQPAUSEEN_CQPEN_MSPI1XNOREN     = 2048,  /*!< MSPI1XNOREN : Pause command queue when input MSPI1 bit XNORed
22972                                                      with SWFLAG1 is '1'                                                       */
22973   IOM0_CQPAUSEEN_CQPEN_MSPI0XNOREN     = 1024,  /*!< MSPI0XNOREN : Pause command queue when input MSPI0 bit XNORed
22974                                                      with SWFLAG0 is '1'                                                       */
22975   IOM0_CQPAUSEEN_CQPEN_MSPI1XOREN      = 512,   /*!< MSPI1XOREN : Pause command queue when input MSPI1 bit XORed
22976                                                      with SWFLAG1 is '1'                                                       */
22977   IOM0_CQPAUSEEN_CQPEN_MSPI0XOREN      = 256,   /*!< MSPI0XOREN : Pause command queue when input MSPI0 bit XORed
22978                                                      with SWFLAG0 is '1'                                                       */
22979   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN7       = 128,   /*!< SWFLAGEN7 : Pause the command queue when software flag bit 7
22980                                                      is '1'.                                                                   */
22981   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN6       = 64,    /*!< SWFLAGEN6 : Pause the command queue when software flag bit 6
22982                                                      is '1'                                                                    */
22983   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN5       = 32,    /*!< SWFLAGEN5 : Pause the command queue when software flag bit 5
22984                                                      is '1'                                                                    */
22985   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN4       = 16,    /*!< SWFLAGEN4 : Pause the command queue when software flag bit 4
22986                                                      is '1'                                                                    */
22987   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN3       = 8,     /*!< SWFLAGEN3 : Pause the command queue when software flag bit 3
22988                                                      is '1'                                                                    */
22989   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN2       = 4,     /*!< SWFLAGEN2 : Pause the command queue when software flag bit 2
22990                                                      is '1'                                                                    */
22991   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN1       = 2,     /*!< SWFLAGEN1 : Pause the command queue when software flag bit 1
22992                                                      is '1'                                                                    */
22993   IOM0_CQPAUSEEN_CQPEN_SWFLAGEN0       = 1,     /*!< SWFLAGEN0 : Pause the command queue when software flag bit 0
22994                                                      is '1'                                                                    */
22995 } IOM0_CQPAUSEEN_CQPEN_Enum;
22996 
22997 /* =======================================================  CQCURIDX  ======================================================== */
22998 /* =======================================================  CQENDIDX  ======================================================== */
22999 /* ========================================================  STATUS  ========================================================= */
23000 /* ===============================================  IOM0 STATUS IDLEST [2..2]  =============================================== */
23001 typedef enum {                                  /*!< IOM0_STATUS_IDLEST                                                        */
23002   IOM0_STATUS_IDLEST_IDLE              = 1,     /*!< IDLE : The I/O state machine is in the idle state.                        */
23003 } IOM0_STATUS_IDLEST_Enum;
23004 
23005 /* ===============================================  IOM0 STATUS CMDACT [1..1]  =============================================== */
23006 typedef enum {                                  /*!< IOM0_STATUS_CMDACT                                                        */
23007   IOM0_STATUS_CMDACT_ACTIVE            = 1,     /*!< ACTIVE : An I/O command is active. Indicates the active module
23008                                                      has an active command and is processing this. De-asserted
23009                                                      when the command is completed.                                            */
23010 } IOM0_STATUS_CMDACT_Enum;
23011 
23012 /* ================================================  IOM0 STATUS ERR [0..0]  ================================================= */
23013 typedef enum {                                  /*!< IOM0_STATUS_ERR                                                           */
23014   IOM0_STATUS_ERR_ERROR                = 1,     /*!< ERROR : Bit has been deprecated and will always return 0.                 */
23015 } IOM0_STATUS_ERR_Enum;
23016 
23017 /* ========================================================  MSPICFG  ======================================================== */
23018 /* =============================================  IOM0 MSPICFG SPILSB [23..23]  ============================================== */
23019 typedef enum {                                  /*!< IOM0_MSPICFG_SPILSB                                                       */
23020   IOM0_MSPICFG_SPILSB_MSB              = 0,     /*!< MSB : Send and receive MSB bit first                                      */
23021   IOM0_MSPICFG_SPILSB_LSB              = 1,     /*!< LSB : Send and receive LSB bit first                                      */
23022 } IOM0_MSPICFG_SPILSB_Enum;
23023 
23024 /* =============================================  IOM0 MSPICFG RDFCPOL [22..22]  ============================================= */
23025 typedef enum {                                  /*!< IOM0_MSPICFG_RDFCPOL                                                      */
23026   IOM0_MSPICFG_RDFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high creates flow control.                     */
23027   IOM0_MSPICFG_RDFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low creates flow control.                       */
23028 } IOM0_MSPICFG_RDFCPOL_Enum;
23029 
23030 /* =============================================  IOM0 MSPICFG WTFCPOL [21..21]  ============================================= */
23031 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCPOL                                                      */
23032   IOM0_MSPICFG_WTFCPOL_HIGH            = 0,     /*!< HIGH : Flow control signal high(1) creates flow control and
23033                                                      byte transfers will stop until the flow control signal
23034                                                      goes low.                                                                 */
23035   IOM0_MSPICFG_WTFCPOL_LOW             = 1,     /*!< LOW : Flow control signal low(0) creates flow control and byte
23036                                                      transfers will stop until the flow control signal goes
23037                                                      high(1).                                                                  */
23038 } IOM0_MSPICFG_WTFCPOL_Enum;
23039 
23040 /* =============================================  IOM0 MSPICFG WTFCIRQ [20..20]  ============================================= */
23041 typedef enum {                                  /*!< IOM0_MSPICFG_WTFCIRQ                                                      */
23042   IOM0_MSPICFG_WTFCIRQ_MISO            = 0,     /*!< MISO : MISO is used as the write mode flow control signal.                */
23043   IOM0_MSPICFG_WTFCIRQ_IRQ             = 1,     /*!< IRQ : IRQ is used as the write mode flow control signal.                  */
23044 } IOM0_MSPICFG_WTFCIRQ_Enum;
23045 
23046 /* =============================================  IOM0 MSPICFG MOSIINV [18..18]  ============================================= */
23047 typedef enum {                                  /*!< IOM0_MSPICFG_MOSIINV                                                      */
23048   IOM0_MSPICFG_MOSIINV_NORMAL          = 0,     /*!< NORMAL : MOSI is set to 0 in read mode and 1 in write mode.               */
23049   IOM0_MSPICFG_MOSIINV_INVERT          = 1,     /*!< INVERT : MOSI is set to 1 in read mode and 0 in write mode.               */
23050 } IOM0_MSPICFG_MOSIINV_Enum;
23051 
23052 /* ==============================================  IOM0 MSPICFG RDFC [17..17]  =============================================== */
23053 typedef enum {                                  /*!< IOM0_MSPICFG_RDFC                                                         */
23054   IOM0_MSPICFG_RDFC_DIS                = 0,     /*!< DIS : Read mode flow control disabled.                                    */
23055   IOM0_MSPICFG_RDFC_EN                 = 1,     /*!< EN : Read mode flow control enabled.                                      */
23056 } IOM0_MSPICFG_RDFC_Enum;
23057 
23058 /* ==============================================  IOM0 MSPICFG WTFC [16..16]  =============================================== */
23059 typedef enum {                                  /*!< IOM0_MSPICFG_WTFC                                                         */
23060   IOM0_MSPICFG_WTFC_DIS                = 0,     /*!< DIS : Write mode flow control disabled.                                   */
23061   IOM0_MSPICFG_WTFC_EN                 = 1,     /*!< EN : Write mode flow control enabled.                                     */
23062 } IOM0_MSPICFG_WTFC_Enum;
23063 
23064 /* ===============================================  IOM0 MSPICFG SPHA [1..1]  ================================================ */
23065 typedef enum {                                  /*!< IOM0_MSPICFG_SPHA                                                         */
23066   IOM0_MSPICFG_SPHA_SAMPLE_LEADING_EDGE = 0,    /*!< SAMPLE_LEADING_EDGE : Sample on the leading (first) clock edge.           */
23067   IOM0_MSPICFG_SPHA_SAMPLE_TRAILING_EDGE = 1,   /*!< SAMPLE_TRAILING_EDGE : Sample on the trailing (second) clock
23068                                                      edge.                                                                     */
23069 } IOM0_MSPICFG_SPHA_Enum;
23070 
23071 /* ===============================================  IOM0 MSPICFG SPOL [0..0]  ================================================ */
23072 typedef enum {                                  /*!< IOM0_MSPICFG_SPOL                                                         */
23073   IOM0_MSPICFG_SPOL_CLK_BASE_0         = 0,     /*!< CLK_BASE_0 : The base value of the clock is 0.                            */
23074   IOM0_MSPICFG_SPOL_CLK_BASE_1         = 1,     /*!< CLK_BASE_1 : The base value of the clock is 1.                            */
23075 } IOM0_MSPICFG_SPOL_Enum;
23076 
23077 /* ========================================================  MI2CCFG  ======================================================== */
23078 /* ===============================================  IOM0 MI2CCFG ARBEN [2..2]  =============================================== */
23079 typedef enum {                                  /*!< IOM0_MI2CCFG_ARBEN                                                        */
23080   IOM0_MI2CCFG_ARBEN_ARBEN             = 1,     /*!< ARBEN : Enable multi-master bus arbitration support for this
23081                                                      I2C master                                                                */
23082   IOM0_MI2CCFG_ARBEN_ARBDIS            = 0,     /*!< ARBDIS : Disable multi-master bus arbitration support for this
23083                                                      I2C master                                                                */
23084 } IOM0_MI2CCFG_ARBEN_Enum;
23085 
23086 /* ==============================================  IOM0 MI2CCFG I2CLSB [1..1]  =============================================== */
23087 typedef enum {                                  /*!< IOM0_MI2CCFG_I2CLSB                                                       */
23088   IOM0_MI2CCFG_I2CLSB_MSBFIRST         = 0,     /*!< MSBFIRST : Byte data is transmitted MSB first onto the bus/read
23089                                                      from the bus                                                              */
23090   IOM0_MI2CCFG_I2CLSB_LSBFIRST         = 1,     /*!< LSBFIRST : Byte data is transmitted LSB first onto the bus/read
23091                                                      from the bus                                                              */
23092 } IOM0_MI2CCFG_I2CLSB_Enum;
23093 
23094 /* ==============================================  IOM0 MI2CCFG ADDRSZ [0..0]  =============================================== */
23095 typedef enum {                                  /*!< IOM0_MI2CCFG_ADDRSZ                                                       */
23096   IOM0_MI2CCFG_ADDRSZ_ADDRSZ7          = 0,     /*!< ADDRSZ7 : Use 7-bit addressing for I2C master transactions                */
23097   IOM0_MI2CCFG_ADDRSZ_ADDRSZ10         = 1,     /*!< ADDRSZ10 : Use 10-bit addressing for I2C master transactions              */
23098 } IOM0_MI2CCFG_ADDRSZ_Enum;
23099 
23100 /* ========================================================  DEVCFG  ========================================================= */
23101 /* ========================================================  IOMDBG  ========================================================= */
23102 
23103 
23104 /* =========================================================================================================================== */
23105 /* ================                                          IOSLAVE                                          ================ */
23106 /* =========================================================================================================================== */
23107 
23108 /* ========================================================  FIFOPTR  ======================================================== */
23109 /* ========================================================  FIFOCFG  ======================================================== */
23110 /* ========================================================  FIFOTHR  ======================================================== */
23111 /* =========================================================  FUPD  ========================================================== */
23112 /* ========================================================  FIFOCTR  ======================================================== */
23113 /* ========================================================  FIFOINC  ======================================================== */
23114 /* ==========================================================  CFG  ========================================================== */
23115 /* ==============================================  IOSLAVE CFG IFCEN [31..31]  =============================================== */
23116 typedef enum {                                  /*!< IOSLAVE_CFG_IFCEN                                                         */
23117   IOSLAVE_CFG_IFCEN_DIS                = 0,     /*!< DIS : Disable the IOSLAVE                                                 */
23118   IOSLAVE_CFG_IFCEN_EN                 = 1,     /*!< EN : Enable the IOSLAVE                                                   */
23119 } IOSLAVE_CFG_IFCEN_Enum;
23120 
23121 /* ==============================================  IOSLAVE CFG STARTRD [4..4]  =============================================== */
23122 typedef enum {                                  /*!< IOSLAVE_CFG_STARTRD                                                       */
23123   IOSLAVE_CFG_STARTRD_LATE             = 0,     /*!< LATE : Initiate I/O RAM read late in each transferred byte.               */
23124   IOSLAVE_CFG_STARTRD_EARLY            = 1,     /*!< EARLY : Initiate I/O RAM read early in each transferred byte.             */
23125 } IOSLAVE_CFG_STARTRD_Enum;
23126 
23127 /* ================================================  IOSLAVE CFG LSB [2..2]  ================================================= */
23128 typedef enum {                                  /*!< IOSLAVE_CFG_LSB                                                           */
23129   IOSLAVE_CFG_LSB_MSB_FIRST            = 0,     /*!< MSB_FIRST : Data is assumed to be sent and received with MSB
23130                                                      first.                                                                    */
23131   IOSLAVE_CFG_LSB_LSB_FIRST            = 1,     /*!< LSB_FIRST : Data is assumed to be sent and received with LSB
23132                                                      first.                                                                    */
23133 } IOSLAVE_CFG_LSB_Enum;
23134 
23135 /* ================================================  IOSLAVE CFG SPOL [1..1]  ================================================ */
23136 typedef enum {                                  /*!< IOSLAVE_CFG_SPOL                                                          */
23137   IOSLAVE_CFG_SPOL_SPI_MODES_0_3       = 0,     /*!< SPI_MODES_0_3 : Polarity 0, handles SPI modes 0 and 3.                    */
23138   IOSLAVE_CFG_SPOL_SPI_MODES_1_2       = 1,     /*!< SPI_MODES_1_2 : Polarity 1, handles SPI modes 1 and 2.                    */
23139 } IOSLAVE_CFG_SPOL_Enum;
23140 
23141 /* ===============================================  IOSLAVE CFG IFCSEL [0..0]  =============================================== */
23142 typedef enum {                                  /*!< IOSLAVE_CFG_IFCSEL                                                        */
23143   IOSLAVE_CFG_IFCSEL_I2C               = 0,     /*!< I2C : Selects I2C interface for the IO Slave.                             */
23144   IOSLAVE_CFG_IFCSEL_SPI               = 1,     /*!< SPI : Selects SPI interface for the IO Slave.                             */
23145 } IOSLAVE_CFG_IFCSEL_Enum;
23146 
23147 /* =========================================================  PRENC  ========================================================= */
23148 /* =======================================================  IOINTCTL  ======================================================== */
23149 /* ========================================================  GENADD  ========================================================= */
23150 /* =========================================================  INTEN  ========================================================= */
23151 /* ========================================================  INTSTAT  ======================================================== */
23152 /* ========================================================  INTCLR  ========================================================= */
23153 /* ========================================================  INTSET  ========================================================= */
23154 /* ======================================================  REGACCINTEN  ====================================================== */
23155 /* =====================================================  REGACCINTSTAT  ===================================================== */
23156 /* =====================================================  REGACCINTCLR  ====================================================== */
23157 /* =====================================================  REGACCINTSET  ====================================================== */
23158 
23159 
23160 /* =========================================================================================================================== */
23161 /* ================                                          MCUCTRL                                          ================ */
23162 /* =========================================================================================================================== */
23163 
23164 /* ========================================================  CHIPPN  ========================================================= */
23165 /* ============================================  MCUCTRL CHIPPN PARTNUM [0..31]  ============================================= */
23166 typedef enum {                                  /*!< MCUCTRL_CHIPPN_PARTNUM                                                    */
23167   MCUCTRL_CHIPPN_PARTNUM_APOLLO3P      = 0x07000000,/*!< APOLLO3P : Apollo3 Blue Plus part number is 0x07xxxxxx.                */
23168   MCUCTRL_CHIPPN_PARTNUM_APOLLO3       = 0x06000000,/*!< APOLLO3 : Apollo3 Blue part number is 0x06xxxxxx.                      */
23169   MCUCTRL_CHIPPN_PARTNUM_APOLLO2       = 0x03000000,/*!< APOLLO2 : Apollo2 part number is 0x03xxxxxx.                            */
23170   MCUCTRL_CHIPPN_PARTNUM_APOLLO        = 0x01000000,/*!< APOLLO : Apollo part number is 0x01xxxxxx.                              */
23171   MCUCTRL_CHIPPN_PARTNUM_PN_M          = 0xFF000000,/*!< PN_M : Mask for the part number field.                                 */
23172   MCUCTRL_CHIPPN_PARTNUM_PN_S          = 24,    /*!< PN_S : Bit position for the part number field.                            */
23173   MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_M   = 0xF00000,/*!< FLASHSIZE_M : Mask for the FLASH_SIZE field.Values:0: 16KB1:
23174                                                      32KB2: 64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 2MB                           */
23175   MCUCTRL_CHIPPN_PARTNUM_FLASHSIZE_S   = 20,    /*!< FLASHSIZE_S : Bit position for the FLASH_SIZE field.                      */
23176   MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_M    = 0xF0000,/*!< SRAMSIZE_M : Mask for the SRAM_SIZE field.Values:0: 16KB1: 32KB2:
23177                                                      64KB3: 128KB4: 256KB5: 512KB6: 1MB7: 384KB8: 768KB                        */
23178   MCUCTRL_CHIPPN_PARTNUM_SRAMSIZE_S    = 16,    /*!< SRAMSIZE_S : Bit position for the SRAM_SIZE field.                        */
23179   MCUCTRL_CHIPPN_PARTNUM_REV_M         = 0xFF00,/*!< REV_M : Mask for the revision field. Bits [15:12] are major
23180                                                      rev, [11:8] are minor rev.Values:0: Major Rev A, Minor
23181                                                      Rev 01: Major Rev B, Minor Rev 1                                          */
23182   MCUCTRL_CHIPPN_PARTNUM_REV_S         = 8,     /*!< REV_S : Bit position for the revision field.                              */
23183   MCUCTRL_CHIPPN_PARTNUM_PKG_M         = 0xC0,  /*!< PKG_M : Mask for the package field.Values:0: SIP1: QFN2: BGA3:
23184                                                      CSP                                                                       */
23185   MCUCTRL_CHIPPN_PARTNUM_PKG_S         = 6,     /*!< PKG_S : Bit position for the package field.                               */
23186   MCUCTRL_CHIPPN_PARTNUM_PINS_M        = 0x38,  /*!< PINS_M : Mask for the pins field.Values:0: 25 pins1: 49 pins2:
23187                                                      64 pins3: 81 pins4: 104 pins                                              */
23188   MCUCTRL_CHIPPN_PARTNUM_PINS_S        = 3,     /*!< PINS_S : Bit position for the pins field.                                 */
23189   MCUCTRL_CHIPPN_PARTNUM_TEMP_S        = 1,     /*!< TEMP_S : Bit position for the temperature field.                          */
23190 } MCUCTRL_CHIPPN_PARTNUM_Enum;
23191 
23192 /* ========================================================  CHIPID0  ======================================================== */
23193 /* ============================================  MCUCTRL CHIPID0 CHIPID0 [0..31]  ============================================ */
23194 typedef enum {                                  /*!< MCUCTRL_CHIPID0_CHIPID0                                                   */
23195   MCUCTRL_CHIPID0_CHIPID0_APOLLO3      = 0,     /*!< APOLLO3 : Apollo3 Blue CHIPID0.                                           */
23196 } MCUCTRL_CHIPID0_CHIPID0_Enum;
23197 
23198 /* ========================================================  CHIPID1  ======================================================== */
23199 /* ============================================  MCUCTRL CHIPID1 CHIPID1 [0..31]  ============================================ */
23200 typedef enum {                                  /*!< MCUCTRL_CHIPID1_CHIPID1                                                   */
23201   MCUCTRL_CHIPID1_CHIPID1_APOLLO3      = 0,     /*!< APOLLO3 : Apollo3 Blue CHIPID1.                                           */
23202 } MCUCTRL_CHIPID1_CHIPID1_Enum;
23203 
23204 /* ========================================================  CHIPREV  ======================================================== */
23205 /* =============================================  MCUCTRL CHIPREV REVMAJ [4..7]  ============================================= */
23206 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMAJ                                                    */
23207   MCUCTRL_CHIPREV_REVMAJ_C             = 3,     /*!< C : Apollo3 Blue Plus                                                     */
23208   MCUCTRL_CHIPREV_REVMAJ_B             = 2,     /*!< B : Apollo3 Blue revision B                                               */
23209   MCUCTRL_CHIPREV_REVMAJ_A             = 1,     /*!< A : Apollo3 Blue revision A                                               */
23210 } MCUCTRL_CHIPREV_REVMAJ_Enum;
23211 
23212 /* =============================================  MCUCTRL CHIPREV REVMIN [0..3]  ============================================= */
23213 typedef enum {                                  /*!< MCUCTRL_CHIPREV_REVMIN                                                    */
23214   MCUCTRL_CHIPREV_REVMIN_REV1          = 2,     /*!< REV1 : Apollo3 Blue minor rev 1.                                          */
23215   MCUCTRL_CHIPREV_REVMIN_REV0          = 1,     /*!< REV0 : Apollo3 Blue minor rev 0. Minor revision value, succeeding
23216                                                      minor revisions will increment from this value.                           */
23217 } MCUCTRL_CHIPREV_REVMIN_Enum;
23218 
23219 /* =======================================================  VENDORID  ======================================================== */
23220 /* ===========================================  MCUCTRL VENDORID VENDORID [0..31]  =========================================== */
23221 typedef enum {                                  /*!< MCUCTRL_VENDORID_VENDORID                                                 */
23222   MCUCTRL_VENDORID_VENDORID_AMBIQ      = 1095582289,/*!< AMBIQ : Ambiq Vendor ID 'AMBQ'                                        */
23223 } MCUCTRL_VENDORID_VENDORID_Enum;
23224 
23225 /* ==========================================================  SKU  ========================================================== */
23226 /* =====================================================  FEATUREENABLE  ===================================================== */
23227 /* ========================================  MCUCTRL FEATUREENABLE BURSTAVAIL [6..6]  ======================================== */
23228 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BURSTAVAIL                                          */
23229   MCUCTRL_FEATUREENABLE_BURSTAVAIL_AVAIL = 1,   /*!< AVAIL : Burst functionality available                                     */
23230   MCUCTRL_FEATUREENABLE_BURSTAVAIL_NOTAVAIL = 0,/*!< NOTAVAIL : Burst functionality not available                              */
23231 } MCUCTRL_FEATUREENABLE_BURSTAVAIL_Enum;
23232 
23233 /* =========================================  MCUCTRL FEATUREENABLE BURSTREQ [4..4]  ========================================= */
23234 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BURSTREQ                                            */
23235   MCUCTRL_FEATUREENABLE_BURSTREQ_EN    = 1,     /*!< EN : Enable the Burst functionality                                       */
23236   MCUCTRL_FEATUREENABLE_BURSTREQ_DIS   = 0,     /*!< DIS : Disable the Burst functionality                                     */
23237 } MCUCTRL_FEATUREENABLE_BURSTREQ_Enum;
23238 
23239 /* =========================================  MCUCTRL FEATUREENABLE BLEAVAIL [2..2]  ========================================= */
23240 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BLEAVAIL                                            */
23241   MCUCTRL_FEATUREENABLE_BLEAVAIL_AVAIL = 1,     /*!< AVAIL : BLE functionality available                                       */
23242   MCUCTRL_FEATUREENABLE_BLEAVAIL_NOTAVAIL = 0,  /*!< NOTAVAIL : BLE functionality not available                                */
23243 } MCUCTRL_FEATUREENABLE_BLEAVAIL_Enum;
23244 
23245 /* ==========================================  MCUCTRL FEATUREENABLE BLEREQ [0..0]  ========================================== */
23246 typedef enum {                                  /*!< MCUCTRL_FEATUREENABLE_BLEREQ                                              */
23247   MCUCTRL_FEATUREENABLE_BLEREQ_EN      = 1,     /*!< EN : Enable the BLE functionality                                         */
23248   MCUCTRL_FEATUREENABLE_BLEREQ_DIS     = 0,     /*!< DIS : Disable the BLE functionality                                       */
23249 } MCUCTRL_FEATUREENABLE_BLEREQ_Enum;
23250 
23251 /* =======================================================  DEBUGGER  ======================================================== */
23252 /* ========================================================  BODCTRL  ======================================================== */
23253 /* =======================================================  ADCPWRDLY  ======================================================= */
23254 /* ========================================================  ADCCAL  ========================================================= */
23255 /* ==========================================  MCUCTRL ADCCAL ADCCALIBRATED [1..1]  ========================================== */
23256 typedef enum {                                  /*!< MCUCTRL_ADCCAL_ADCCALIBRATED                                              */
23257   MCUCTRL_ADCCAL_ADCCALIBRATED_FALSE   = 0,     /*!< FALSE : ADC is not calibrated                                             */
23258   MCUCTRL_ADCCAL_ADCCALIBRATED_TRUE    = 1,     /*!< TRUE : ADC is calibrated                                                  */
23259 } MCUCTRL_ADCCAL_ADCCALIBRATED_Enum;
23260 
23261 /* ===========================================  MCUCTRL ADCCAL CALONPWRUP [0..0]  ============================================ */
23262 typedef enum {                                  /*!< MCUCTRL_ADCCAL_CALONPWRUP                                                 */
23263   MCUCTRL_ADCCAL_CALONPWRUP_DIS        = 0,     /*!< DIS : Disable automatic calibration on initial power up                   */
23264   MCUCTRL_ADCCAL_CALONPWRUP_EN         = 1,     /*!< EN : Enable automatic calibration on initial power up                     */
23265 } MCUCTRL_ADCCAL_CALONPWRUP_Enum;
23266 
23267 /* ======================================================  ADCBATTLOAD  ====================================================== */
23268 /* ==========================================  MCUCTRL ADCBATTLOAD BATTLOAD [0..0]  ========================================== */
23269 typedef enum {                                  /*!< MCUCTRL_ADCBATTLOAD_BATTLOAD                                              */
23270   MCUCTRL_ADCBATTLOAD_BATTLOAD_DIS     = 0,     /*!< DIS : Battery load is disconnected                                        */
23271   MCUCTRL_ADCBATTLOAD_BATTLOAD_EN      = 1,     /*!< EN : Battery load is enabled                                              */
23272 } MCUCTRL_ADCBATTLOAD_BATTLOAD_Enum;
23273 
23274 /* ========================================================  ADCTRIM  ======================================================== */
23275 /* ======================================================  ADCREFCOMP  ======================================================= */
23276 /* =======================================================  XTALCTRL  ======================================================== */
23277 /* ==========================================  MCUCTRL XTALCTRL PWDBODXTAL [5..5]  =========================================== */
23278 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_PWDBODXTAL                                               */
23279   MCUCTRL_XTALCTRL_PWDBODXTAL_PWRUPBOD = 0,     /*!< PWRUPBOD : Power up XTAL on BOD.                                          */
23280   MCUCTRL_XTALCTRL_PWDBODXTAL_PWRDNBOD = 1,     /*!< PWRDNBOD : Power down XTAL on BOD.                                        */
23281 } MCUCTRL_XTALCTRL_PWDBODXTAL_Enum;
23282 
23283 /* =========================================  MCUCTRL XTALCTRL PDNBCMPRXTAL [4..4]  ========================================== */
23284 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_PDNBCMPRXTAL                                             */
23285   MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRUPCOMP = 1,  /*!< PWRUPCOMP : Power up XTAL oscillator comparator.                          */
23286   MCUCTRL_XTALCTRL_PDNBCMPRXTAL_PWRDNCOMP = 0,  /*!< PWRDNCOMP : Power down XTAL oscillator comparator.                        */
23287 } MCUCTRL_XTALCTRL_PDNBCMPRXTAL_Enum;
23288 
23289 /* =========================================  MCUCTRL XTALCTRL PDNBCOREXTAL [3..3]  ========================================== */
23290 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_PDNBCOREXTAL                                             */
23291   MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRUPCORE = 1,  /*!< PWRUPCORE : Power up XTAL oscillator core.                                */
23292   MCUCTRL_XTALCTRL_PDNBCOREXTAL_PWRDNCORE = 0,  /*!< PWRDNCORE : Power down XTAL oscillator core.                              */
23293 } MCUCTRL_XTALCTRL_PDNBCOREXTAL_Enum;
23294 
23295 /* ==========================================  MCUCTRL XTALCTRL BYPCMPRXTAL [2..2]  ========================================== */
23296 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_BYPCMPRXTAL                                              */
23297   MCUCTRL_XTALCTRL_BYPCMPRXTAL_USECOMP = 0,     /*!< USECOMP : Use the XTAL oscillator comparator.                             */
23298   MCUCTRL_XTALCTRL_BYPCMPRXTAL_BYPCOMP = 1,     /*!< BYPCOMP : Bypass the XTAL oscillator comparator.                          */
23299 } MCUCTRL_XTALCTRL_BYPCMPRXTAL_Enum;
23300 
23301 /* =========================================  MCUCTRL XTALCTRL FDBKDSBLXTAL [1..1]  ========================================== */
23302 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_FDBKDSBLXTAL                                             */
23303   MCUCTRL_XTALCTRL_FDBKDSBLXTAL_EN     = 0,     /*!< EN : Enable XTAL oscillator comparator.                                   */
23304   MCUCTRL_XTALCTRL_FDBKDSBLXTAL_DIS    = 1,     /*!< DIS : Disable XTAL oscillator comparator.                                 */
23305 } MCUCTRL_XTALCTRL_FDBKDSBLXTAL_Enum;
23306 
23307 /* ============================================  MCUCTRL XTALCTRL XTALSWE [0..0]  ============================================ */
23308 typedef enum {                                  /*!< MCUCTRL_XTALCTRL_XTALSWE                                                  */
23309   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_DIS = 0,    /*!< OVERRIDE_DIS : XTAL Software Override Disable.                            */
23310   MCUCTRL_XTALCTRL_XTALSWE_OVERRIDE_EN = 1,     /*!< OVERRIDE_EN : XTAL Software Override Enable.                              */
23311 } MCUCTRL_XTALCTRL_XTALSWE_Enum;
23312 
23313 /* ======================================================  XTALGENCTRL  ====================================================== */
23314 /* ==========================================  MCUCTRL XTALGENCTRL ACWARMUP [0..1]  ========================================== */
23315 typedef enum {                                  /*!< MCUCTRL_XTALGENCTRL_ACWARMUP                                              */
23316   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC1    = 0,     /*!< SEC1 : Warm-up period of 1-2 seconds                                      */
23317   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC2    = 1,     /*!< SEC2 : Warm-up period of 2-4 seconds                                      */
23318   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC4    = 2,     /*!< SEC4 : Warm-up period of 4-8 seconds                                      */
23319   MCUCTRL_XTALGENCTRL_ACWARMUP_SEC8    = 3,     /*!< SEC8 : Warm-up period of 8-16 seconds                                     */
23320 } MCUCTRL_XTALGENCTRL_ACWARMUP_Enum;
23321 
23322 /* =======================================================  MISCCTRL  ======================================================== */
23323 /* ======================================================  BOOTLOADER  ======================================================= */
23324 /* =======================================  MCUCTRL BOOTLOADER SECBOOTONRST [30..31]  ======================================== */
23325 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTONRST                                           */
23326   MCUCTRL_BOOTLOADER_SECBOOTONRST_DISABLED = 0, /*!< DISABLED : Secure boot disabled                                           */
23327   MCUCTRL_BOOTLOADER_SECBOOTONRST_ENABLED = 1,  /*!< ENABLED : Secure boot enabled                                             */
23328   MCUCTRL_BOOTLOADER_SECBOOTONRST_ERROR = 2,    /*!< ERROR : Error in secure boot configuration                                */
23329 } MCUCTRL_BOOTLOADER_SECBOOTONRST_Enum;
23330 
23331 /* ==========================================  MCUCTRL BOOTLOADER SECBOOT [28..29]  ========================================== */
23332 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOT                                                */
23333   MCUCTRL_BOOTLOADER_SECBOOT_DISABLED  = 0,     /*!< DISABLED : Secure boot disabled                                           */
23334   MCUCTRL_BOOTLOADER_SECBOOT_ENABLED   = 1,     /*!< ENABLED : Secure boot enabled                                             */
23335   MCUCTRL_BOOTLOADER_SECBOOT_ERROR     = 2,     /*!< ERROR : Error in secure boot configuration                                */
23336 } MCUCTRL_BOOTLOADER_SECBOOT_Enum;
23337 
23338 /* ======================================  MCUCTRL BOOTLOADER SECBOOTFEATURE [26..27]  ======================================= */
23339 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SECBOOTFEATURE                                         */
23340   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_DISABLED = 0,/*!< DISABLED : Secure boot disabled                                          */
23341   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ENABLED = 1,/*!< ENABLED : Secure boot enabled                                             */
23342   MCUCTRL_BOOTLOADER_SECBOOTFEATURE_ERROR = 2,  /*!< ERROR : Error in secure boot configuration                                */
23343 } MCUCTRL_BOOTLOADER_SECBOOTFEATURE_Enum;
23344 
23345 /* ==========================================  MCUCTRL BOOTLOADER PROTLOCK [2..2]  =========================================== */
23346 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_PROTLOCK                                               */
23347   MCUCTRL_BOOTLOADER_PROTLOCK_LOCK     = 1,     /*!< LOCK : Enable the secure boot lock                                        */
23348 } MCUCTRL_BOOTLOADER_PROTLOCK_Enum;
23349 
23350 /* ===========================================  MCUCTRL BOOTLOADER SBLOCK [1..1]  ============================================ */
23351 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_SBLOCK                                                 */
23352   MCUCTRL_BOOTLOADER_SBLOCK_LOCK       = 1,     /*!< LOCK : Enable the secure boot lock                                        */
23353 } MCUCTRL_BOOTLOADER_SBLOCK_Enum;
23354 
23355 /* ========================================  MCUCTRL BOOTLOADER BOOTLOADERLOW [0..0]  ======================================== */
23356 typedef enum {                                  /*!< MCUCTRL_BOOTLOADER_BOOTLOADERLOW                                          */
23357   MCUCTRL_BOOTLOADER_BOOTLOADERLOW_ADDR0 = 1,   /*!< ADDR0 : Bootloader code at 0x00000000.                                    */
23358 } MCUCTRL_BOOTLOADER_BOOTLOADERLOW_Enum;
23359 
23360 /* ======================================================  SHADOWVALID  ====================================================== */
23361 /* ========================================  MCUCTRL SHADOWVALID INFO0_VALID [2..2]  ========================================= */
23362 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_INFO0_VALID                                           */
23363   MCUCTRL_SHADOWVALID_INFO0_VALID_VALID = 1,    /*!< VALID : Flash INFO0 (customer) space contains valid data.                 */
23364 } MCUCTRL_SHADOWVALID_INFO0_VALID_Enum;
23365 
23366 /* ==========================================  MCUCTRL SHADOWVALID BLDSLEEP [1..1]  ========================================== */
23367 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_BLDSLEEP                                              */
23368   MCUCTRL_SHADOWVALID_BLDSLEEP_DEEPSLEEP = 1,   /*!< DEEPSLEEP : Bootloader will go to deep sleep if no flash image
23369                                                      loaded                                                                    */
23370 } MCUCTRL_SHADOWVALID_BLDSLEEP_Enum;
23371 
23372 /* ===========================================  MCUCTRL SHADOWVALID VALID [0..0]  ============================================ */
23373 typedef enum {                                  /*!< MCUCTRL_SHADOWVALID_VALID                                                 */
23374   MCUCTRL_SHADOWVALID_VALID_VALID      = 1,     /*!< VALID : Flash information space contains valid data.                      */
23375 } MCUCTRL_SHADOWVALID_VALID_Enum;
23376 
23377 /* =======================================================  SCRATCH0  ======================================================== */
23378 /* =======================================================  SCRATCH1  ======================================================== */
23379 /* ====================================================  ICODEFAULTADDR  ===================================================== */
23380 /* ====================================================  DCODEFAULTADDR  ===================================================== */
23381 /* =====================================================  SYSFAULTADDR  ====================================================== */
23382 /* ======================================================  FAULTSTATUS  ====================================================== */
23383 /* ==========================================  MCUCTRL FAULTSTATUS SYSFAULT [2..2]  ========================================== */
23384 typedef enum {                                  /*!< MCUCTRL_FAULTSTATUS_SYSFAULT                                              */
23385   MCUCTRL_FAULTSTATUS_SYSFAULT_NOFAULT = 0,     /*!< NOFAULT : No bus fault has been detected.                                 */
23386   MCUCTRL_FAULTSTATUS_SYSFAULT_FAULT   = 1,     /*!< FAULT : Bus fault detected.                                               */
23387 } MCUCTRL_FAULTSTATUS_SYSFAULT_Enum;
23388 
23389 /* =========================================  MCUCTRL FAULTSTATUS DCODEFAULT [1..1]  ========================================= */
23390 typedef enum {                                  /*!< MCUCTRL_FAULTSTATUS_DCODEFAULT                                            */
23391   MCUCTRL_FAULTSTATUS_DCODEFAULT_NOFAULT = 0,   /*!< NOFAULT : No DCODE fault has been detected.                               */
23392   MCUCTRL_FAULTSTATUS_DCODEFAULT_FAULT = 1,     /*!< FAULT : DCODE fault detected.                                             */
23393 } MCUCTRL_FAULTSTATUS_DCODEFAULT_Enum;
23394 
23395 /* =========================================  MCUCTRL FAULTSTATUS ICODEFAULT [0..0]  ========================================= */
23396 typedef enum {                                  /*!< MCUCTRL_FAULTSTATUS_ICODEFAULT                                            */
23397   MCUCTRL_FAULTSTATUS_ICODEFAULT_NOFAULT = 0,   /*!< NOFAULT : No ICODE fault has been detected.                               */
23398   MCUCTRL_FAULTSTATUS_ICODEFAULT_FAULT = 1,     /*!< FAULT : ICODE fault detected.                                             */
23399 } MCUCTRL_FAULTSTATUS_ICODEFAULT_Enum;
23400 
23401 /* ====================================================  FAULTCAPTUREEN  ===================================================== */
23402 /* =====================================  MCUCTRL FAULTCAPTUREEN FAULTCAPTUREEN [0..0]  ====================================== */
23403 typedef enum {                                  /*!< MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN                                     */
23404   MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_DIS = 0,/*!< DIS : Disable fault capture.                                              */
23405   MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_EN = 1, /*!< EN : Enable fault capture.                                                */
23406 } MCUCTRL_FAULTCAPTUREEN_FAULTCAPTUREEN_Enum;
23407 
23408 /* =========================================================  DBGR1  ========================================================= */
23409 /* =========================================================  DBGR2  ========================================================= */
23410 /* =======================================================  PMUENABLE  ======================================================= */
23411 /* ============================================  MCUCTRL PMUENABLE ENABLE [0..0]  ============================================ */
23412 typedef enum {                                  /*!< MCUCTRL_PMUENABLE_ENABLE                                                  */
23413   MCUCTRL_PMUENABLE_ENABLE_DIS         = 0,     /*!< DIS : Disable MCU power management.                                       */
23414   MCUCTRL_PMUENABLE_ENABLE_EN          = 1,     /*!< EN : Enable MCU power management.                                         */
23415 } MCUCTRL_PMUENABLE_ENABLE_Enum;
23416 
23417 /* =======================================================  TPIUCTRL  ======================================================== */
23418 /* ============================================  MCUCTRL TPIUCTRL CLKSEL [8..10]  ============================================ */
23419 typedef enum {                                  /*!< MCUCTRL_TPIUCTRL_CLKSEL                                                   */
23420   MCUCTRL_TPIUCTRL_CLKSEL_LOWPWR       = 0,     /*!< LOWPWR : Low power state.                                                 */
23421   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV2     = 1,     /*!< HFRCDIV2 : Selects HFRC divided by 2 as the source TPIU clock             */
23422   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV8     = 2,     /*!< HFRCDIV8 : Selects HFRC divided by 8 as the source TPIU clock             */
23423   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV16    = 3,     /*!< HFRCDIV16 : Selects HFRC divided by 16 as the source TPIU clock           */
23424   MCUCTRL_TPIUCTRL_CLKSEL_HFRCDIV32    = 4,     /*!< HFRCDIV32 : Selects HFRC divided by 32 as the source TPIU clock           */
23425 } MCUCTRL_TPIUCTRL_CLKSEL_Enum;
23426 
23427 /* ============================================  MCUCTRL TPIUCTRL ENABLE [0..0]  ============================================= */
23428 typedef enum {                                  /*!< MCUCTRL_TPIUCTRL_ENABLE                                                   */
23429   MCUCTRL_TPIUCTRL_ENABLE_DIS          = 0,     /*!< DIS : Disable the TPIU.                                                   */
23430   MCUCTRL_TPIUCTRL_ENABLE_EN           = 1,     /*!< EN : Enable the TPIU.                                                     */
23431 } MCUCTRL_TPIUCTRL_ENABLE_Enum;
23432 
23433 /* ======================================================  OTAPOINTER  ======================================================= */
23434 /* ======================================================  APBDMACTRL  ======================================================= */
23435 /* =========================================  MCUCTRL APBDMACTRL DECODEABORT [1..1]  ========================================= */
23436 typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DECODEABORT                                            */
23437   MCUCTRL_APBDMACTRL_DECODEABORT_DISABLE = 0,   /*!< DISABLE : Bus operations to powered down peripherals are quietly
23438                                                      discarded                                                                 */
23439   MCUCTRL_APBDMACTRL_DECODEABORT_ENABLE = 1,    /*!< ENABLE : Bus operations to powered down peripherals result in
23440                                                      a bus fault.                                                              */
23441 } MCUCTRL_APBDMACTRL_DECODEABORT_Enum;
23442 
23443 /* =========================================  MCUCTRL APBDMACTRL DMA_ENABLE [0..0]  ========================================== */
23444 typedef enum {                                  /*!< MCUCTRL_APBDMACTRL_DMA_ENABLE                                             */
23445   MCUCTRL_APBDMACTRL_DMA_ENABLE_DISABLE = 0,    /*!< DISABLE : DMA operations disabled                                         */
23446   MCUCTRL_APBDMACTRL_DMA_ENABLE_ENABLE = 1,     /*!< ENABLE : DMA operations enabled                                           */
23447 } MCUCTRL_APBDMACTRL_DMA_ENABLE_Enum;
23448 
23449 /* =======================================================  SRAMMODE  ======================================================== */
23450 /* ======================================================  KEXTCLKSEL  ======================================================= */
23451 /* =========================================  MCUCTRL KEXTCLKSEL KEXTCLKSEL [0..31]  ========================================= */
23452 typedef enum {                                  /*!< MCUCTRL_KEXTCLKSEL_KEXTCLKSEL                                             */
23453   MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Key    = 83,    /*!< Key : Key value to unlock the register.                                   */
23454 } MCUCTRL_KEXTCLKSEL_KEXTCLKSEL_Enum;
23455 
23456 /* =======================================================  SIMOBUCK1  ======================================================= */
23457 /* =======================================================  SIMOBUCK2  ======================================================= */
23458 /* =======================================================  SIMOBUCK3  ======================================================= */
23459 /* =======================================================  SIMOBUCK4  ======================================================= */
23460 /* =======================================================  BLEBUCK2  ======================================================== */
23461 /* ======================================================  FLASHWPROT0  ====================================================== */
23462 /* ======================================================  FLASHWPROT1  ====================================================== */
23463 /* ======================================================  FLASHRPROT0  ====================================================== */
23464 /* ======================================================  FLASHRPROT1  ====================================================== */
23465 /* =================================================  DMASRAMWRITEPROTECT0  ================================================== */
23466 /* =================================================  DMASRAMWRITEPROTECT1  ================================================== */
23467 /* ==================================================  DMASRAMREADPROTECT0  ================================================== */
23468 /* ==================================================  DMASRAMREADPROTECT1  ================================================== */
23469 
23470 
23471 /* =========================================================================================================================== */
23472 /* ================                                           MSPI                                            ================ */
23473 /* =========================================================================================================================== */
23474 
23475 /* =========================================================  CTRL  ========================================================== */
23476 /* ==========================================================  CFG  ========================================================== */
23477 /* ================================================  MSPI CFG CPOL [17..17]  ================================================= */
23478 typedef enum {                                  /*!< MSPI_CFG_CPOL                                                             */
23479   MSPI_CFG_CPOL_LOW                    = 0,     /*!< LOW : Clock inactive state is low.                                        */
23480   MSPI_CFG_CPOL_HIGH                   = 1,     /*!< HIGH : Clock inactive state is high.                                      */
23481 } MSPI_CFG_CPOL_Enum;
23482 
23483 /* ================================================  MSPI CFG CPHA [16..16]  ================================================= */
23484 typedef enum {                                  /*!< MSPI_CFG_CPHA                                                             */
23485   MSPI_CFG_CPHA_MIDDLE                 = 0,     /*!< MIDDLE : Clock toggles in middle of data bit.                             */
23486   MSPI_CFG_CPHA_START                  = 1,     /*!< START : Clock toggles at start of data bit.                               */
23487 } MSPI_CFG_CPHA_Enum;
23488 
23489 /* =================================================  MSPI CFG ASIZE [4..5]  ================================================= */
23490 typedef enum {                                  /*!< MSPI_CFG_ASIZE                                                            */
23491   MSPI_CFG_ASIZE_A1                    = 0,     /*!< A1 : Send one address byte                                                */
23492   MSPI_CFG_ASIZE_A2                    = 1,     /*!< A2 : Send two address bytes                                               */
23493   MSPI_CFG_ASIZE_A3                    = 2,     /*!< A3 : Send three address bytes                                             */
23494   MSPI_CFG_ASIZE_A4                    = 3,     /*!< A4 : Send four address bytes                                              */
23495 } MSPI_CFG_ASIZE_Enum;
23496 
23497 /* ================================================  MSPI CFG DEVCFG [0..3]  ================================================= */
23498 typedef enum {                                  /*!< MSPI_CFG_DEVCFG                                                           */
23499   MSPI_CFG_DEVCFG_SERIAL0              = 1,     /*!< SERIAL0 : Single bit SPI flash on chip select 0                           */
23500   MSPI_CFG_DEVCFG_SERIAL1              = 2,     /*!< SERIAL1 : Single bit SPI flash on chip select 1                           */
23501   MSPI_CFG_DEVCFG_DUAL0                = 5,     /*!< DUAL0 : Dual SPI flash on chip select 0                                   */
23502   MSPI_CFG_DEVCFG_DUAL1                = 6,     /*!< DUAL1 : Dual bit SPI flash on chip select 1                               */
23503   MSPI_CFG_DEVCFG_QUAD0                = 9,     /*!< QUAD0 : Quad SPI flash on chip select 0                                   */
23504   MSPI_CFG_DEVCFG_QUAD1                = 10,    /*!< QUAD1 : Quad SPI flash on chip select 1                                   */
23505   MSPI_CFG_DEVCFG_OCTAL0               = 13,    /*!< OCTAL0 : Octal SPI flash on chip select 0                                 */
23506   MSPI_CFG_DEVCFG_OCTAL1               = 14,    /*!< OCTAL1 : Octal SPI flash on chip select 1                                 */
23507   MSPI_CFG_DEVCFG_QUADPAIRED           = 15,    /*!< QUADPAIRED : Dual Quad SPI flash on chip selects 0/1.                     */
23508   MSPI_CFG_DEVCFG_QUADPAIRED_SERIAL    = 3,     /*!< QUADPAIRED_SERIAL : Dual Quad SPI flash on chip selects 0/1,
23509                                                      but transmit in serial mode for initialization operations                 */
23510 } MSPI_CFG_DEVCFG_Enum;
23511 
23512 /* =========================================================  ADDR  ========================================================== */
23513 /* =========================================================  INSTR  ========================================================= */
23514 /* ========================================================  TXFIFO  ========================================================= */
23515 /* ========================================================  RXFIFO  ========================================================= */
23516 /* =======================================================  TXENTRIES  ======================================================= */
23517 /* =======================================================  RXENTRIES  ======================================================= */
23518 /* =======================================================  THRESHOLD  ======================================================= */
23519 /* ========================================================  MSPICFG  ======================================================== */
23520 /* ==============================================  MSPI MSPICFG CLKDIV [8..13]  ============================================== */
23521 typedef enum {                                  /*!< MSPI_MSPICFG_CLKDIV                                                       */
23522   MSPI_MSPICFG_CLKDIV_CLK48            = 1,     /*!< CLK48 : 48 MHz MSPI clock                                                 */
23523   MSPI_MSPICFG_CLKDIV_CLK24            = 2,     /*!< CLK24 : 24 MHz MSPI clock                                                 */
23524   MSPI_MSPICFG_CLKDIV_CLK12            = 4,     /*!< CLK12 : 12 MHz MSPI clock                                                 */
23525   MSPI_MSPICFG_CLKDIV_CLK6             = 8,     /*!< CLK6 : 6 MHz MSPI clock                                                   */
23526   MSPI_MSPICFG_CLKDIV_CLK3             = 16,    /*!< CLK3 : 3 MHz MSPI clock                                                   */
23527   MSPI_MSPICFG_CLKDIV_CLK1_5           = 32,    /*!< CLK1_5 : 1.5 MHz MSPI clock                                               */
23528 } MSPI_MSPICFG_CLKDIV_Enum;
23529 
23530 /* ==============================================  MSPI MSPICFG IOMSEL [4..6]  =============================================== */
23531 typedef enum {                                  /*!< MSPI_MSPICFG_IOMSEL                                                       */
23532   MSPI_MSPICFG_IOMSEL_IOM0             = 0,     /*!< IOM0 : Select IOM0                                                        */
23533   MSPI_MSPICFG_IOMSEL_IOM1             = 1,     /*!< IOM1 : Select IOM1                                                        */
23534   MSPI_MSPICFG_IOMSEL_IOM2             = 2,     /*!< IOM2 : Select IOM2                                                        */
23535   MSPI_MSPICFG_IOMSEL_IOM3             = 3,     /*!< IOM3 : Select IOM3                                                        */
23536   MSPI_MSPICFG_IOMSEL_IOM4             = 4,     /*!< IOM4 : Select IOM4                                                        */
23537   MSPI_MSPICFG_IOMSEL_IOM5             = 5,     /*!< IOM5 : Select IOM5                                                        */
23538   MSPI_MSPICFG_IOMSEL_DISABLED         = 7,     /*!< DISABLED : No IOM selected. Signals always zero.                          */
23539 } MSPI_MSPICFG_IOMSEL_Enum;
23540 
23541 /* ===============================================  MSPI MSPICFG TXNEG [3..3]  =============================================== */
23542 typedef enum {                                  /*!< MSPI_MSPICFG_TXNEG                                                        */
23543   MSPI_MSPICFG_TXNEG_NORMAL            = 0,     /*!< NORMAL : TX launched from posedge internal clock                          */
23544   MSPI_MSPICFG_TXNEG_NEGEDGE           = 1,     /*!< NEGEDGE : TX data launched from negedge of internal clock                 */
23545 } MSPI_MSPICFG_TXNEG_Enum;
23546 
23547 /* ===============================================  MSPI MSPICFG RXNEG [2..2]  =============================================== */
23548 typedef enum {                                  /*!< MSPI_MSPICFG_RXNEG                                                        */
23549   MSPI_MSPICFG_RXNEG_NORMAL            = 0,     /*!< NORMAL : RX data sampled on posedge of internal clock                     */
23550   MSPI_MSPICFG_RXNEG_NEGEDGE           = 1,     /*!< NEGEDGE : RX data sampled on negedge of internal clock                    */
23551 } MSPI_MSPICFG_RXNEG_Enum;
23552 
23553 /* ===============================================  MSPI MSPICFG RXCAP [1..1]  =============================================== */
23554 typedef enum {                                  /*!< MSPI_MSPICFG_RXCAP                                                        */
23555   MSPI_MSPICFG_RXCAP_NORMAL            = 0,     /*!< NORMAL : RX Capture phase aligns with CPHA setting                        */
23556   MSPI_MSPICFG_RXCAP_DELAY             = 1,     /*!< DELAY : RX Capture phase is delayed from CPHA setting by one
23557                                                      clock edge                                                                */
23558 } MSPI_MSPICFG_RXCAP_Enum;
23559 
23560 /* ==============================================  MSPI MSPICFG APBCLK [0..0]  =============================================== */
23561 typedef enum {                                  /*!< MSPI_MSPICFG_APBCLK                                                       */
23562   MSPI_MSPICFG_APBCLK_DIS              = 0,     /*!< DIS : Disable continuous clock.                                           */
23563   MSPI_MSPICFG_APBCLK_EN               = 1,     /*!< EN : Enable continuous clock.                                             */
23564 } MSPI_MSPICFG_APBCLK_Enum;
23565 
23566 /* ========================================================  PADCFG  ========================================================= */
23567 /* =======================================================  PADOUTEN  ======================================================== */
23568 /* ==============================================  MSPI PADOUTEN OUTEN [0..8]  =============================================== */
23569 typedef enum {                                  /*!< MSPI_PADOUTEN_OUTEN                                                       */
23570   MSPI_PADOUTEN_OUTEN_QUAD0            = 271,   /*!< QUAD0 : Quad0 (4 data + 1 clock)                                          */
23571   MSPI_PADOUTEN_OUTEN_QUAD1            = 496,   /*!< QUAD1 : Quad1 (4 data + 1 clock)                                          */
23572   MSPI_PADOUTEN_OUTEN_OCTAL            = 511,   /*!< OCTAL : Octal (8 data + 1 clock)                                          */
23573   MSPI_PADOUTEN_OUTEN_SERIAL0          = 259,   /*!< SERIAL0 : Serial (2 data + 1 clock)                                       */
23574   MSPI_PADOUTEN_OUTEN_SERIAL1          = 304,   /*!< SERIAL1 : Serial (2 data + 1 clock)                                       */
23575 } MSPI_PADOUTEN_OUTEN_Enum;
23576 
23577 /* =========================================================  FLASH  ========================================================= */
23578 /* ==============================================  MSPI FLASH XIPMIXED [8..10]  ============================================== */
23579 typedef enum {                                  /*!< MSPI_FLASH_XIPMIXED                                                       */
23580   MSPI_FLASH_XIPMIXED_NORMAL           = 0,     /*!< NORMAL : Transfers all proceed using the settings in DEVCFG
23581                                                      register (everything in the same data rate)                               */
23582   MSPI_FLASH_XIPMIXED_D2               = 1,     /*!< D2 : Data operations proceed in dual data rate                            */
23583   MSPI_FLASH_XIPMIXED_AD2              = 3,     /*!< AD2 : Address and Data operations proceed in dual data rate               */
23584   MSPI_FLASH_XIPMIXED_D4               = 5,     /*!< D4 : Data operations proceed in quad data rate                            */
23585   MSPI_FLASH_XIPMIXED_AD4              = 7,     /*!< AD4 : Address and Data operations proceed in quad data rate               */
23586 } MSPI_FLASH_XIPMIXED_Enum;
23587 
23588 /* ===============================================  MSPI FLASH XIPACK [2..3]  ================================================ */
23589 typedef enum {                                  /*!< MSPI_FLASH_XIPACK                                                         */
23590   MSPI_FLASH_XIPACK_NOACK              = 0,     /*!< NOACK : No acknowledgment sent. Data IOs are tri-stated the
23591                                                      first turnaround cycle                                                    */
23592   MSPI_FLASH_XIPACK_ACK                = 2,     /*!< ACK : Positive acknowledgment sent. Data IOs are driven to 0
23593                                                      the first turnaround cycle to acknowledge XIP mode                        */
23594   MSPI_FLASH_XIPACK_TERMINATE          = 3,     /*!< TERMINATE : Negative acknowledgment sent. Data IOs are driven
23595                                                      to 1 the first turnaround cycle to terminate XIP mode.
23596                                                      XIPSENDI should be re-enabled for the next transfer                       */
23597 } MSPI_FLASH_XIPACK_Enum;
23598 
23599 /* ======================================================  SCRAMBLING  ======================================================= */
23600 /* =========================================================  INTEN  ========================================================= */
23601 /* ========================================================  INTSTAT  ======================================================== */
23602 /* ========================================================  INTCLR  ========================================================= */
23603 /* ========================================================  INTSET  ========================================================= */
23604 /* ========================================================  DMACFG  ========================================================= */
23605 /* ===============================================  MSPI DMACFG DMAPRI [3..4]  =============================================== */
23606 typedef enum {                                  /*!< MSPI_DMACFG_DMAPRI                                                        */
23607   MSPI_DMACFG_DMAPRI_LOW               = 0,     /*!< LOW : Low Priority (service as best effort)                               */
23608   MSPI_DMACFG_DMAPRI_HIGH              = 1,     /*!< HIGH : High Priority (service immediately)                                */
23609   MSPI_DMACFG_DMAPRI_AUTO              = 2,     /*!< AUTO : Auto Priority (priority raised once TX FIFO empties or
23610                                                      RX FIFO fills)                                                            */
23611 } MSPI_DMACFG_DMAPRI_Enum;
23612 
23613 /* ===============================================  MSPI DMACFG DMADIR [2..2]  =============================================== */
23614 typedef enum {                                  /*!< MSPI_DMACFG_DMADIR                                                        */
23615   MSPI_DMACFG_DMADIR_P2M               = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction                             */
23616   MSPI_DMACFG_DMADIR_M2P               = 1,     /*!< M2P : Memory to Peripheral transaction                                    */
23617 } MSPI_DMACFG_DMADIR_Enum;
23618 
23619 /* ===============================================  MSPI DMACFG DMAEN [0..1]  ================================================ */
23620 typedef enum {                                  /*!< MSPI_DMACFG_DMAEN                                                         */
23621   MSPI_DMACFG_DMAEN_DIS                = 0,     /*!< DIS : Disable DMA Function                                                */
23622   MSPI_DMACFG_DMAEN_EN                 = 3,     /*!< EN : Enable HW controlled DMA Function to manage DMA to flash
23623                                                      devices. HW will automatically handle issuance of instruction/address
23624                                                      bytes based on settings in the FLASH register.                            */
23625 } MSPI_DMACFG_DMAEN_Enum;
23626 
23627 /* ========================================================  DMASTAT  ======================================================== */
23628 /* ======================================================  DMATARGADDR  ====================================================== */
23629 /* ======================================================  DMADEVADDR  ======================================================= */
23630 /* ======================================================  DMATOTCOUNT  ====================================================== */
23631 /* =======================================================  DMABCOUNT  ======================================================= */
23632 /* =======================================================  DMATHRESH  ======================================================= */
23633 /* =========================================================  CQCFG  ========================================================= */
23634 /* ================================================  MSPI CQCFG CQPRI [1..1]  ================================================ */
23635 typedef enum {                                  /*!< MSPI_CQCFG_CQPRI                                                          */
23636   MSPI_CQCFG_CQPRI_LOW                 = 0,     /*!< LOW : Low Priority (service as best effort)                               */
23637   MSPI_CQCFG_CQPRI_HIGH                = 1,     /*!< HIGH : High Priority (service immediately)                                */
23638 } MSPI_CQCFG_CQPRI_Enum;
23639 
23640 /* ================================================  MSPI CQCFG CQEN [0..0]  ================================================= */
23641 typedef enum {                                  /*!< MSPI_CQCFG_CQEN                                                           */
23642   MSPI_CQCFG_CQEN_DIS                  = 0,     /*!< DIS : Disable CQ Function                                                 */
23643   MSPI_CQCFG_CQEN_EN                   = 1,     /*!< EN : Enable CQ Function                                                   */
23644 } MSPI_CQCFG_CQEN_Enum;
23645 
23646 /* ========================================================  CQADDR  ========================================================= */
23647 /* ========================================================  CQSTAT  ========================================================= */
23648 /* ========================================================  CQFLAGS  ======================================================== */
23649 /* =============================================  MSPI CQFLAGS CQFLAGS [0..15]  ============================================== */
23650 typedef enum {                                  /*!< MSPI_CQFLAGS_CQFLAGS                                                      */
23651   MSPI_CQFLAGS_CQFLAGS_STOP            = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
23652   MSPI_CQFLAGS_CQFLAGS_CQIDX           = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
23653   MSPI_CQFLAGS_CQFLAGS_DMACPL          = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
23654   MSPI_CQFLAGS_CQFLAGS_CMDCPL          = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
23655   MSPI_CQFLAGS_CQFLAGS_IOM1READY       = 512,   /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
23656                                                      status is the result of XNOR'ing the IOM0START with the
23657                                                      incoming status from the IOM. When high, MSPI can send
23658                                                      to the buffer.                                                            */
23659   MSPI_CQFLAGS_CQFLAGS_IOM0READY       = 256,   /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
23660                                                      status is the result of XNOR'ing the IOM0START with the
23661                                                      incoming status from the IOM. When high, MSPI can send
23662                                                      to the buffer.                                                            */
23663   MSPI_CQFLAGS_CQFLAGS_SWFLAG7         = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
23664                                                      operations.                                                               */
23665   MSPI_CQFLAGS_CQFLAGS_SWFLAG6         = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
23666                                                      operations.                                                               */
23667   MSPI_CQFLAGS_CQFLAGS_SWFLAG5         = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
23668                                                      operations.                                                               */
23669   MSPI_CQFLAGS_CQFLAGS_SWFLAG4         = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
23670                                                      operations.                                                               */
23671   MSPI_CQFLAGS_CQFLAGS_SWFLAG3         = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
23672                                                      operations.                                                               */
23673   MSPI_CQFLAGS_CQFLAGS_SWFLAG2         = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
23674                                                      operations.                                                               */
23675   MSPI_CQFLAGS_CQFLAGS_SWFLAG1         = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
23676                                                      operations.                                                               */
23677   MSPI_CQFLAGS_CQFLAGS_SWFLAG0         = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
23678                                                      operations.                                                               */
23679 } MSPI_CQFLAGS_CQFLAGS_Enum;
23680 
23681 /* ======================================================  CQSETCLEAR  ======================================================= */
23682 /* ========================================================  CQPAUSE  ======================================================== */
23683 /* ==============================================  MSPI CQPAUSE CQMASK [0..15]  ============================================== */
23684 typedef enum {                                  /*!< MSPI_CQPAUSE_CQMASK                                                       */
23685   MSPI_CQPAUSE_CQMASK_STOP             = 32768, /*!< STOP : CQ Stop Flag. When set, CQ processing will complete.               */
23686   MSPI_CQPAUSE_CQMASK_CQIDX            = 16384, /*!< CQIDX : CQ Index Pointers (CURIDX/ENDIDX) match.                          */
23687   MSPI_CQPAUSE_CQMASK_DMACPL           = 2048,  /*!< DMACPL : DMA Complete Status (hardwired DMACPL bit in DMASTAT)            */
23688   MSPI_CQPAUSE_CQMASK_CMDCPL           = 1024,  /*!< CMDCPL : PIO Operation completed (STATUS bit in CTRL register)            */
23689   MSPI_CQPAUSE_CQMASK_IOM1READY        = 512,   /*!< IOM1READY : IOM Buffer 1 Ready Status (from selected IOM). This
23690                                                      status is the result of XNOR'ing the IOM0START with the
23691                                                      incoming status from the IOM. When high, MSPI can send
23692                                                      to the buffer.                                                            */
23693   MSPI_CQPAUSE_CQMASK_IOM0READY        = 256,   /*!< IOM0READY : IOM Buffer 0 Ready Status (from selected IOM). This
23694                                                      status is the result of XNOR'ing the IOM0START with the
23695                                                      incoming status from the IOM. When high, MSPI can send
23696                                                      to the buffer.                                                            */
23697   MSPI_CQPAUSE_CQMASK_SWFLAG7          = 128,   /*!< SWFLAG7 : Software flag 7. Can be used by software to start/pause
23698                                                      operations.                                                               */
23699   MSPI_CQPAUSE_CQMASK_SWFLAG6          = 64,    /*!< SWFLAG6 : Software flag 6. Can be used by software to start/pause
23700                                                      operations.                                                               */
23701   MSPI_CQPAUSE_CQMASK_SWFLAG5          = 32,    /*!< SWFLAG5 : Software flag 5. Can be used by software to start/pause
23702                                                      operations.                                                               */
23703   MSPI_CQPAUSE_CQMASK_SWFLAG4          = 16,    /*!< SWFLAG4 : Software flag 4. Can be used by software to start/pause
23704                                                      operations.                                                               */
23705   MSPI_CQPAUSE_CQMASK_SWFLAG3          = 8,     /*!< SWFLAG3 : Software flag 3. Can be used by software to start/pause
23706                                                      operations.                                                               */
23707   MSPI_CQPAUSE_CQMASK_SWFLAG2          = 4,     /*!< SWFLAG2 : Software flag 2. Can be used by software to start/pause
23708                                                      operations.                                                               */
23709   MSPI_CQPAUSE_CQMASK_SWFLAG1          = 2,     /*!< SWFLAG1 : Software flag 1. Can be used by software to start/pause
23710                                                      operations.                                                               */
23711   MSPI_CQPAUSE_CQMASK_SWFLAG0          = 1,     /*!< SWFLAG0 : Software flag 0. Can be used by software to start/pause
23712                                                      operations.                                                               */
23713 } MSPI_CQPAUSE_CQMASK_Enum;
23714 
23715 /* =======================================================  CQCURIDX  ======================================================== */
23716 /* =======================================================  CQENDIDX  ======================================================== */
23717 
23718 
23719 /* =========================================================================================================================== */
23720 /* ================                                            PDM                                            ================ */
23721 /* =========================================================================================================================== */
23722 
23723 /* =========================================================  PCFG  ========================================================== */
23724 /* ===============================================  PDM PCFG LRSWAP [31..31]  ================================================ */
23725 typedef enum {                                  /*!< PDM_PCFG_LRSWAP                                                           */
23726   PDM_PCFG_LRSWAP_EN                   = 1,     /*!< EN : Swap left and right channels (FIFO Read RIGHT_LEFT).                 */
23727   PDM_PCFG_LRSWAP_NOSWAP               = 0,     /*!< NOSWAP : No channel swapping (IFO Read LEFT_RIGHT).                       */
23728 } PDM_PCFG_LRSWAP_Enum;
23729 
23730 /* ==============================================  PDM PCFG PGARIGHT [26..30]  =============================================== */
23731 typedef enum {                                  /*!< PDM_PCFG_PGARIGHT                                                         */
23732   PDM_PCFG_PGARIGHT_P405DB             = 31,    /*!< P405DB : 40.5 db gain.                                                    */
23733   PDM_PCFG_PGARIGHT_P390DB             = 30,    /*!< P390DB : 39.0 db gain.                                                    */
23734   PDM_PCFG_PGARIGHT_P375DB             = 29,    /*!< P375DB : 37.5 db gain.                                                    */
23735   PDM_PCFG_PGARIGHT_P360DB             = 28,    /*!< P360DB : 36.0 db gain.                                                    */
23736   PDM_PCFG_PGARIGHT_P345DB             = 27,    /*!< P345DB : 34.5 db gain.                                                    */
23737   PDM_PCFG_PGARIGHT_P330DB             = 26,    /*!< P330DB : 33.0 db gain.                                                    */
23738   PDM_PCFG_PGARIGHT_P315DB             = 25,    /*!< P315DB : 31.5 db gain.                                                    */
23739   PDM_PCFG_PGARIGHT_P300DB             = 24,    /*!< P300DB : 30.0 db gain.                                                    */
23740   PDM_PCFG_PGARIGHT_P285DB             = 23,    /*!< P285DB : 28.5 db gain.                                                    */
23741   PDM_PCFG_PGARIGHT_P270DB             = 22,    /*!< P270DB : 27.0 db gain.                                                    */
23742   PDM_PCFG_PGARIGHT_P255DB             = 21,    /*!< P255DB : 25.5 db gain.                                                    */
23743   PDM_PCFG_PGARIGHT_P240DB             = 20,    /*!< P240DB : 24.0 db gain.                                                    */
23744   PDM_PCFG_PGARIGHT_P225DB             = 19,    /*!< P225DB : 22.5 db gain.                                                    */
23745   PDM_PCFG_PGARIGHT_P210DB             = 18,    /*!< P210DB : 21.0 db gain.                                                    */
23746   PDM_PCFG_PGARIGHT_P195DB             = 17,    /*!< P195DB : 19.5 db gain.                                                    */
23747   PDM_PCFG_PGARIGHT_P180DB             = 16,    /*!< P180DB : 18.0 db gain.                                                    */
23748   PDM_PCFG_PGARIGHT_P165DB             = 15,    /*!< P165DB : 16.5 db gain.                                                    */
23749   PDM_PCFG_PGARIGHT_P150DB             = 14,    /*!< P150DB : 15.0 db gain.                                                    */
23750   PDM_PCFG_PGARIGHT_P135DB             = 13,    /*!< P135DB : 13.5 db gain.                                                    */
23751   PDM_PCFG_PGARIGHT_P120DB             = 12,    /*!< P120DB : 12.0 db gain.                                                    */
23752   PDM_PCFG_PGARIGHT_P105DB             = 11,    /*!< P105DB : 10.5 db gain.                                                    */
23753   PDM_PCFG_PGARIGHT_P90DB              = 10,    /*!< P90DB : 9.0 db gain.                                                      */
23754   PDM_PCFG_PGARIGHT_P75DB              = 9,     /*!< P75DB : 7.5 db gain.                                                      */
23755   PDM_PCFG_PGARIGHT_P60DB              = 8,     /*!< P60DB : 6.0 db gain.                                                      */
23756   PDM_PCFG_PGARIGHT_P45DB              = 7,     /*!< P45DB : 4.5 db gain.                                                      */
23757   PDM_PCFG_PGARIGHT_P30DB              = 6,     /*!< P30DB : 3.0 db gain.                                                      */
23758   PDM_PCFG_PGARIGHT_P15DB              = 5,     /*!< P15DB : 1.5 db gain.                                                      */
23759   PDM_PCFG_PGARIGHT_0DB                = 4,     /*!< 0DB : 0.0 db gain.                                                        */
23760   PDM_PCFG_PGARIGHT_M15DB              = 3,     /*!< M15DB : -1.5 db gain.                                                     */
23761   PDM_PCFG_PGARIGHT_M300DB             = 2,     /*!< M300DB : -3.0 db gain.                                                    */
23762   PDM_PCFG_PGARIGHT_M45DB              = 1,     /*!< M45DB : -4.5 db gain.                                                     */
23763   PDM_PCFG_PGARIGHT_M60DB              = 0,     /*!< M60DB : -6.0 db gain.                                                     */
23764 } PDM_PCFG_PGARIGHT_Enum;
23765 
23766 /* ===============================================  PDM PCFG PGALEFT [21..25]  =============================================== */
23767 typedef enum {                                  /*!< PDM_PCFG_PGALEFT                                                          */
23768   PDM_PCFG_PGALEFT_P405DB              = 31,    /*!< P405DB : 40.5 db gain.                                                    */
23769   PDM_PCFG_PGALEFT_P390DB              = 30,    /*!< P390DB : 39.0 db gain.                                                    */
23770   PDM_PCFG_PGALEFT_P375DB              = 29,    /*!< P375DB : 37.5 db gain.                                                    */
23771   PDM_PCFG_PGALEFT_P360DB              = 28,    /*!< P360DB : 36.0 db gain.                                                    */
23772   PDM_PCFG_PGALEFT_P345DB              = 27,    /*!< P345DB : 34.5 db gain.                                                    */
23773   PDM_PCFG_PGALEFT_P330DB              = 26,    /*!< P330DB : 33.0 db gain.                                                    */
23774   PDM_PCFG_PGALEFT_P315DB              = 25,    /*!< P315DB : 31.5 db gain.                                                    */
23775   PDM_PCFG_PGALEFT_P300DB              = 24,    /*!< P300DB : 30.0 db gain.                                                    */
23776   PDM_PCFG_PGALEFT_P285DB              = 23,    /*!< P285DB : 28.5 db gain.                                                    */
23777   PDM_PCFG_PGALEFT_P270DB              = 22,    /*!< P270DB : 27.0 db gain.                                                    */
23778   PDM_PCFG_PGALEFT_P255DB              = 21,    /*!< P255DB : 25.5 db gain.                                                    */
23779   PDM_PCFG_PGALEFT_P240DB              = 20,    /*!< P240DB : 24.0 db gain.                                                    */
23780   PDM_PCFG_PGALEFT_P225DB              = 19,    /*!< P225DB : 22.5 db gain.                                                    */
23781   PDM_PCFG_PGALEFT_P210DB              = 18,    /*!< P210DB : 21.0 db gain.                                                    */
23782   PDM_PCFG_PGALEFT_P195DB              = 17,    /*!< P195DB : 19.5 db gain.                                                    */
23783   PDM_PCFG_PGALEFT_P180DB              = 16,    /*!< P180DB : 18.0 db gain.                                                    */
23784   PDM_PCFG_PGALEFT_P165DB              = 15,    /*!< P165DB : 16.5 db gain.                                                    */
23785   PDM_PCFG_PGALEFT_P150DB              = 14,    /*!< P150DB : 15.0 db gain.                                                    */
23786   PDM_PCFG_PGALEFT_P135DB              = 13,    /*!< P135DB : 13.5 db gain.                                                    */
23787   PDM_PCFG_PGALEFT_P120DB              = 12,    /*!< P120DB : 12.0 db gain.                                                    */
23788   PDM_PCFG_PGALEFT_P105DB              = 11,    /*!< P105DB : 10.5 db gain.                                                    */
23789   PDM_PCFG_PGALEFT_P90DB               = 10,    /*!< P90DB : 9.0 db gain.                                                      */
23790   PDM_PCFG_PGALEFT_P75DB               = 9,     /*!< P75DB : 7.5 db gain.                                                      */
23791   PDM_PCFG_PGALEFT_P60DB               = 8,     /*!< P60DB : 6.0 db gain.                                                      */
23792   PDM_PCFG_PGALEFT_P45DB               = 7,     /*!< P45DB : 4.5 db gain.                                                      */
23793   PDM_PCFG_PGALEFT_P30DB               = 6,     /*!< P30DB : 3.0 db gain.                                                      */
23794   PDM_PCFG_PGALEFT_P15DB               = 5,     /*!< P15DB : 1.5 db gain.                                                      */
23795   PDM_PCFG_PGALEFT_0DB                 = 4,     /*!< 0DB : 0.0 db gain.                                                        */
23796   PDM_PCFG_PGALEFT_M15DB               = 3,     /*!< M15DB : -1.5 db gain.                                                     */
23797   PDM_PCFG_PGALEFT_M300DB              = 2,     /*!< M300DB : -3.0 db gain.                                                    */
23798   PDM_PCFG_PGALEFT_M45DB               = 1,     /*!< M45DB : -4.5 db gain.                                                     */
23799   PDM_PCFG_PGALEFT_M60DB               = 0,     /*!< M60DB : -6.0 db gain.                                                     */
23800 } PDM_PCFG_PGALEFT_Enum;
23801 
23802 /* ===============================================  PDM PCFG MCLKDIV [17..18]  =============================================== */
23803 typedef enum {                                  /*!< PDM_PCFG_MCLKDIV                                                          */
23804   PDM_PCFG_MCLKDIV_MCKDIV4             = 3,     /*!< MCKDIV4 : Divide input clock by 4                                         */
23805   PDM_PCFG_MCLKDIV_MCKDIV3             = 2,     /*!< MCKDIV3 : Divide input clock by 3                                         */
23806   PDM_PCFG_MCLKDIV_MCKDIV2             = 1,     /*!< MCKDIV2 : Divide input clock by 2                                         */
23807   PDM_PCFG_MCLKDIV_MCKDIV1             = 0,     /*!< MCKDIV1 : Divide input clock by 1                                         */
23808 } PDM_PCFG_MCLKDIV_Enum;
23809 
23810 /* ================================================  PDM PCFG ADCHPD [9..9]  ================================================= */
23811 typedef enum {                                  /*!< PDM_PCFG_ADCHPD                                                           */
23812   PDM_PCFG_ADCHPD_EN                   = 0,     /*!< EN : Enable high pass filter.                                             */
23813   PDM_PCFG_ADCHPD_DIS                  = 1,     /*!< DIS : Disable high pass filter.                                           */
23814 } PDM_PCFG_ADCHPD_Enum;
23815 
23816 /* ===============================================  PDM PCFG SOFTMUTE [1..1]  ================================================ */
23817 typedef enum {                                  /*!< PDM_PCFG_SOFTMUTE                                                         */
23818   PDM_PCFG_SOFTMUTE_EN                 = 1,     /*!< EN : Enable Soft Mute.                                                    */
23819   PDM_PCFG_SOFTMUTE_DIS                = 0,     /*!< DIS : Disable Soft Mute.                                                  */
23820 } PDM_PCFG_SOFTMUTE_Enum;
23821 
23822 /* ===============================================  PDM PCFG PDMCOREEN [0..0]  =============================================== */
23823 typedef enum {                                  /*!< PDM_PCFG_PDMCOREEN                                                        */
23824   PDM_PCFG_PDMCOREEN_EN                = 1,     /*!< EN : Enable Data Streaming.                                               */
23825   PDM_PCFG_PDMCOREEN_DIS               = 0,     /*!< DIS : Disable Data Streaming.                                             */
23826 } PDM_PCFG_PDMCOREEN_Enum;
23827 
23828 /* =========================================================  VCFG  ========================================================== */
23829 /* ===============================================  PDM VCFG IOCLKEN [31..31]  =============================================== */
23830 typedef enum {                                  /*!< PDM_VCFG_IOCLKEN                                                          */
23831   PDM_VCFG_IOCLKEN_DIS                 = 0,     /*!< DIS : Disable FIFO read.                                                  */
23832   PDM_VCFG_IOCLKEN_EN                  = 1,     /*!< EN : Enable FIFO read.                                                    */
23833 } PDM_VCFG_IOCLKEN_Enum;
23834 
23835 /* ================================================  PDM VCFG RSTB [30..30]  ================================================= */
23836 typedef enum {                                  /*!< PDM_VCFG_RSTB                                                             */
23837   PDM_VCFG_RSTB_RESET                  = 0,     /*!< RESET : Reset the core.                                                   */
23838   PDM_VCFG_RSTB_NORM                   = 1,     /*!< NORM : Enable the core.                                                   */
23839 } PDM_VCFG_RSTB_Enum;
23840 
23841 /* ==============================================  PDM VCFG PDMCLKSEL [27..29]  ============================================== */
23842 typedef enum {                                  /*!< PDM_VCFG_PDMCLKSEL                                                        */
23843   PDM_VCFG_PDMCLKSEL_DISABLE           = 0,     /*!< DISABLE : Static value.                                                   */
23844   PDM_VCFG_PDMCLKSEL_12MHz             = 1,     /*!< 12MHz : PDM clock is 12 MHz.                                              */
23845   PDM_VCFG_PDMCLKSEL_6MHz              = 2,     /*!< 6MHz : PDM clock is 6 MHz.                                                */
23846   PDM_VCFG_PDMCLKSEL_3MHz              = 3,     /*!< 3MHz : PDM clock is 3 MHz.                                                */
23847   PDM_VCFG_PDMCLKSEL_1_5MHz            = 4,     /*!< 1_5MHz : PDM clock is 1.5 MHz.                                            */
23848   PDM_VCFG_PDMCLKSEL_750KHz            = 5,     /*!< 750KHz : PDM clock is 750 KHz.                                            */
23849   PDM_VCFG_PDMCLKSEL_375KHz            = 6,     /*!< 375KHz : PDM clock is 375 KHz.                                            */
23850   PDM_VCFG_PDMCLKSEL_187KHz            = 7,     /*!< 187KHz : PDM clock is 187.5 KHz.                                          */
23851 } PDM_VCFG_PDMCLKSEL_Enum;
23852 
23853 /* ==============================================  PDM VCFG PDMCLKEN [26..26]  =============================================== */
23854 typedef enum {                                  /*!< PDM_VCFG_PDMCLKEN                                                         */
23855   PDM_VCFG_PDMCLKEN_DIS                = 0,     /*!< DIS : Disable serial clock.                                               */
23856   PDM_VCFG_PDMCLKEN_EN                 = 1,     /*!< EN : Enable serial clock.                                                 */
23857 } PDM_VCFG_PDMCLKEN_Enum;
23858 
23859 /* ================================================  PDM VCFG I2SEN [20..20]  ================================================ */
23860 typedef enum {                                  /*!< PDM_VCFG_I2SEN                                                            */
23861   PDM_VCFG_I2SEN_DIS                   = 0,     /*!< DIS : Disable I2S interface.                                              */
23862   PDM_VCFG_I2SEN_EN                    = 1,     /*!< EN : Enable I2S interface.                                                */
23863 } PDM_VCFG_I2SEN_Enum;
23864 
23865 /* ===============================================  PDM VCFG BCLKINV [19..19]  =============================================== */
23866 typedef enum {                                  /*!< PDM_VCFG_BCLKINV                                                          */
23867   PDM_VCFG_BCLKINV_INV                 = 0,     /*!< INV : BCLK inverted.                                                      */
23868   PDM_VCFG_BCLKINV_NORM                = 1,     /*!< NORM : BCLK not inverted.                                                 */
23869 } PDM_VCFG_BCLKINV_Enum;
23870 
23871 /* ==============================================  PDM VCFG DMICKDEL [17..17]  =============================================== */
23872 typedef enum {                                  /*!< PDM_VCFG_DMICKDEL                                                         */
23873   PDM_VCFG_DMICKDEL_0CYC               = 0,     /*!< 0CYC : No delay.                                                          */
23874   PDM_VCFG_DMICKDEL_1CYC               = 1,     /*!< 1CYC : 1 cycle delay.                                                     */
23875 } PDM_VCFG_DMICKDEL_Enum;
23876 
23877 /* ================================================  PDM VCFG SELAP [16..16]  ================================================ */
23878 typedef enum {                                  /*!< PDM_VCFG_SELAP                                                            */
23879   PDM_VCFG_SELAP_I2S                   = 1,     /*!< I2S : Clock source from I2S BCLK.                                         */
23880   PDM_VCFG_SELAP_INTERNAL              = 0,     /*!< INTERNAL : Clock source from internal clock generator.                    */
23881 } PDM_VCFG_SELAP_Enum;
23882 
23883 /* ================================================  PDM VCFG PCMPACK [8..8]  ================================================ */
23884 typedef enum {                                  /*!< PDM_VCFG_PCMPACK                                                          */
23885   PDM_VCFG_PCMPACK_DIS                 = 0,     /*!< DIS : Disable PCM packing.                                                */
23886   PDM_VCFG_PCMPACK_EN                  = 1,     /*!< EN : Enable PCM packing.                                                  */
23887 } PDM_VCFG_PCMPACK_Enum;
23888 
23889 /* =================================================  PDM VCFG CHSET [3..4]  ================================================= */
23890 typedef enum {                                  /*!< PDM_VCFG_CHSET                                                            */
23891   PDM_VCFG_CHSET_DIS                   = 0,     /*!< DIS : Channel disabled.                                                   */
23892   PDM_VCFG_CHSET_LEFT                  = 1,     /*!< LEFT : Mono left channel.                                                 */
23893   PDM_VCFG_CHSET_RIGHT                 = 2,     /*!< RIGHT : Mono right channel.                                               */
23894   PDM_VCFG_CHSET_STEREO                = 3,     /*!< STEREO : Stereo channels.                                                 */
23895 } PDM_VCFG_CHSET_Enum;
23896 
23897 /* =======================================================  VOICESTAT  ======================================================= */
23898 /* =======================================================  FIFOREAD  ======================================================== */
23899 /* =======================================================  FIFOFLUSH  ======================================================= */
23900 /* ========================================================  FIFOTHR  ======================================================== */
23901 /* =========================================================  INTEN  ========================================================= */
23902 /* ========================================================  INTSTAT  ======================================================== */
23903 /* ========================================================  INTCLR  ========================================================= */
23904 /* ========================================================  INTSET  ========================================================= */
23905 /* =======================================================  DMATRIGEN  ======================================================= */
23906 /* ======================================================  DMATRIGSTAT  ====================================================== */
23907 /* ========================================================  DMACFG  ========================================================= */
23908 /* ===============================================  PDM DMACFG DMAPRI [8..8]  ================================================ */
23909 typedef enum {                                  /*!< PDM_DMACFG_DMAPRI                                                         */
23910   PDM_DMACFG_DMAPRI_LOW                = 0,     /*!< LOW : Low Priority (service as best effort)                               */
23911   PDM_DMACFG_DMAPRI_HIGH               = 1,     /*!< HIGH : High Priority (service immediately)                                */
23912 } PDM_DMACFG_DMAPRI_Enum;
23913 
23914 /* ===============================================  PDM DMACFG DMADIR [2..2]  ================================================ */
23915 typedef enum {                                  /*!< PDM_DMACFG_DMADIR                                                         */
23916   PDM_DMACFG_DMADIR_P2M                = 0,     /*!< P2M : Peripheral to Memory (SRAM) transaction. THe PDM module
23917                                                      will only DMA to memory.                                                  */
23918   PDM_DMACFG_DMADIR_M2P                = 1,     /*!< M2P : Memory to Peripheral transaction. Not available for PDM
23919                                                      module                                                                    */
23920 } PDM_DMACFG_DMADIR_Enum;
23921 
23922 /* ================================================  PDM DMACFG DMAEN [0..0]  ================================================ */
23923 typedef enum {                                  /*!< PDM_DMACFG_DMAEN                                                          */
23924   PDM_DMACFG_DMAEN_DIS                 = 0,     /*!< DIS : Disable DMA Function                                                */
23925   PDM_DMACFG_DMAEN_EN                  = 1,     /*!< EN : Enable DMA Function                                                  */
23926 } PDM_DMACFG_DMAEN_Enum;
23927 
23928 /* ======================================================  DMATOTCOUNT  ====================================================== */
23929 /* ======================================================  DMATARGADDR  ====================================================== */
23930 /* ========================================================  DMASTAT  ======================================================== */
23931 
23932 
23933 /* =========================================================================================================================== */
23934 /* ================                                          PWRCTRL                                          ================ */
23935 /* =========================================================================================================================== */
23936 
23937 /* =======================================================  SUPPLYSRC  ======================================================= */
23938 /* ==========================================  PWRCTRL SUPPLYSRC BLEBUCKEN [0..0]  =========================================== */
23939 typedef enum {                                  /*!< PWRCTRL_SUPPLYSRC_BLEBUCKEN                                               */
23940   PWRCTRL_SUPPLYSRC_BLEBUCKEN_EN       = 1,     /*!< EN : Enable the BLE Buck.                                                 */
23941   PWRCTRL_SUPPLYSRC_BLEBUCKEN_DIS      = 0,     /*!< DIS : Disable the BLE Buck.                                               */
23942 } PWRCTRL_SUPPLYSRC_BLEBUCKEN_Enum;
23943 
23944 /* =====================================================  SUPPLYSTATUS  ====================================================== */
23945 /* =========================================  PWRCTRL SUPPLYSTATUS BLEBUCKON [1..1]  ========================================= */
23946 typedef enum {                                  /*!< PWRCTRL_SUPPLYSTATUS_BLEBUCKON                                            */
23947   PWRCTRL_SUPPLYSTATUS_BLEBUCKON_LDO   = 0,     /*!< LDO : Indicates the the LDO is supplying the BLE/Burst power
23948                                                      domain                                                                    */
23949   PWRCTRL_SUPPLYSTATUS_BLEBUCKON_BUCK  = 1,     /*!< BUCK : Indicates the the Buck is supplying the BLE/Burst power
23950                                                      domain                                                                    */
23951 } PWRCTRL_SUPPLYSTATUS_BLEBUCKON_Enum;
23952 
23953 /* ========================================  PWRCTRL SUPPLYSTATUS SIMOBUCKON [0..0]  ========================================= */
23954 typedef enum {                                  /*!< PWRCTRL_SUPPLYSTATUS_SIMOBUCKON                                           */
23955   PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_OFF  = 0,     /*!< OFF : Indicates the the SIMO Buck is OFF.                                 */
23956   PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_ON   = 1,     /*!< ON : Indicates the the SIMO Buck is ON.                                   */
23957 } PWRCTRL_SUPPLYSTATUS_SIMOBUCKON_Enum;
23958 
23959 /* =======================================================  DEVPWREN  ======================================================== */
23960 /* ===========================================  PWRCTRL DEVPWREN PWRBLEL [13..13]  =========================================== */
23961 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRBLEL                                                  */
23962   PWRCTRL_DEVPWREN_PWRBLEL_EN          = 1,     /*!< EN : Power up BLE controller                                              */
23963   PWRCTRL_DEVPWREN_PWRBLEL_DIS         = 0,     /*!< DIS : Power down BLE controller                                           */
23964 } PWRCTRL_DEVPWREN_PWRBLEL_Enum;
23965 
23966 /* ===========================================  PWRCTRL DEVPWREN PWRPDM [12..12]  ============================================ */
23967 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRPDM                                                   */
23968   PWRCTRL_DEVPWREN_PWRPDM_EN           = 1,     /*!< EN : Power up PDM                                                         */
23969   PWRCTRL_DEVPWREN_PWRPDM_DIS          = 0,     /*!< DIS : Power down PDM                                                      */
23970 } PWRCTRL_DEVPWREN_PWRPDM_Enum;
23971 
23972 /* ===========================================  PWRCTRL DEVPWREN PWRMSPI [11..11]  =========================================== */
23973 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRMSPI                                                  */
23974   PWRCTRL_DEVPWREN_PWRMSPI_EN          = 1,     /*!< EN : Power up MSPI                                                        */
23975   PWRCTRL_DEVPWREN_PWRMSPI_DIS         = 0,     /*!< DIS : Power down MSPI                                                     */
23976 } PWRCTRL_DEVPWREN_PWRMSPI_Enum;
23977 
23978 /* ==========================================  PWRCTRL DEVPWREN PWRSCARD [10..10]  =========================================== */
23979 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRSCARD                                                 */
23980   PWRCTRL_DEVPWREN_PWRSCARD_EN         = 1,     /*!< EN : Power up SCARD                                                       */
23981   PWRCTRL_DEVPWREN_PWRSCARD_DIS        = 0,     /*!< DIS : Power down SCARD                                                    */
23982 } PWRCTRL_DEVPWREN_PWRSCARD_Enum;
23983 
23984 /* ============================================  PWRCTRL DEVPWREN PWRADC [9..9]  ============================================= */
23985 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRADC                                                   */
23986   PWRCTRL_DEVPWREN_PWRADC_EN           = 1,     /*!< EN : Power up ADC                                                         */
23987   PWRCTRL_DEVPWREN_PWRADC_DIS          = 0,     /*!< DIS : Power Down ADC                                                      */
23988 } PWRCTRL_DEVPWREN_PWRADC_Enum;
23989 
23990 /* ===========================================  PWRCTRL DEVPWREN PWRUART1 [8..8]  ============================================ */
23991 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRUART1                                                 */
23992   PWRCTRL_DEVPWREN_PWRUART1_EN         = 1,     /*!< EN : Power up UART 1                                                      */
23993   PWRCTRL_DEVPWREN_PWRUART1_DIS        = 0,     /*!< DIS : Power down UART 1                                                   */
23994 } PWRCTRL_DEVPWREN_PWRUART1_Enum;
23995 
23996 /* ===========================================  PWRCTRL DEVPWREN PWRUART0 [7..7]  ============================================ */
23997 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRUART0                                                 */
23998   PWRCTRL_DEVPWREN_PWRUART0_EN         = 1,     /*!< EN : Power up UART 0                                                      */
23999   PWRCTRL_DEVPWREN_PWRUART0_DIS        = 0,     /*!< DIS : Power down UART 0                                                   */
24000 } PWRCTRL_DEVPWREN_PWRUART0_Enum;
24001 
24002 /* ============================================  PWRCTRL DEVPWREN PWRIOM5 [6..6]  ============================================ */
24003 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM5                                                  */
24004   PWRCTRL_DEVPWREN_PWRIOM5_EN          = 1,     /*!< EN : Power up IO Master 5                                                 */
24005   PWRCTRL_DEVPWREN_PWRIOM5_DIS         = 0,     /*!< DIS : Power down IO Master 5                                              */
24006 } PWRCTRL_DEVPWREN_PWRIOM5_Enum;
24007 
24008 /* ============================================  PWRCTRL DEVPWREN PWRIOM4 [5..5]  ============================================ */
24009 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM4                                                  */
24010   PWRCTRL_DEVPWREN_PWRIOM4_EN          = 1,     /*!< EN : Power up IO Master 4                                                 */
24011   PWRCTRL_DEVPWREN_PWRIOM4_DIS         = 0,     /*!< DIS : Power down IO Master 4                                              */
24012 } PWRCTRL_DEVPWREN_PWRIOM4_Enum;
24013 
24014 /* ============================================  PWRCTRL DEVPWREN PWRIOM3 [4..4]  ============================================ */
24015 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM3                                                  */
24016   PWRCTRL_DEVPWREN_PWRIOM3_EN          = 1,     /*!< EN : Power up IO Master 3                                                 */
24017   PWRCTRL_DEVPWREN_PWRIOM3_DIS         = 0,     /*!< DIS : Power down IO Master 3                                              */
24018 } PWRCTRL_DEVPWREN_PWRIOM3_Enum;
24019 
24020 /* ============================================  PWRCTRL DEVPWREN PWRIOM2 [3..3]  ============================================ */
24021 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM2                                                  */
24022   PWRCTRL_DEVPWREN_PWRIOM2_EN          = 1,     /*!< EN : Power up IO Master 2                                                 */
24023   PWRCTRL_DEVPWREN_PWRIOM2_DIS         = 0,     /*!< DIS : Power down IO Master 2                                              */
24024 } PWRCTRL_DEVPWREN_PWRIOM2_Enum;
24025 
24026 /* ============================================  PWRCTRL DEVPWREN PWRIOM1 [2..2]  ============================================ */
24027 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM1                                                  */
24028   PWRCTRL_DEVPWREN_PWRIOM1_EN          = 1,     /*!< EN : Power up IO Master 1                                                 */
24029   PWRCTRL_DEVPWREN_PWRIOM1_DIS         = 0,     /*!< DIS : Power down IO Master 1                                              */
24030 } PWRCTRL_DEVPWREN_PWRIOM1_Enum;
24031 
24032 /* ============================================  PWRCTRL DEVPWREN PWRIOM0 [1..1]  ============================================ */
24033 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOM0                                                  */
24034   PWRCTRL_DEVPWREN_PWRIOM0_EN          = 1,     /*!< EN : Power up IO Master 0                                                 */
24035   PWRCTRL_DEVPWREN_PWRIOM0_DIS         = 0,     /*!< DIS : Power down IO Master 0                                              */
24036 } PWRCTRL_DEVPWREN_PWRIOM0_Enum;
24037 
24038 /* ============================================  PWRCTRL DEVPWREN PWRIOS [0..0]  ============================================= */
24039 typedef enum {                                  /*!< PWRCTRL_DEVPWREN_PWRIOS                                                   */
24040   PWRCTRL_DEVPWREN_PWRIOS_EN           = 1,     /*!< EN : Power up IO slave                                                    */
24041   PWRCTRL_DEVPWREN_PWRIOS_DIS          = 0,     /*!< DIS : Power down IO slave                                                 */
24042 } PWRCTRL_DEVPWREN_PWRIOS_Enum;
24043 
24044 /* =====================================================  MEMPWDINSLEEP  ===================================================== */
24045 /* ======================================  PWRCTRL MEMPWDINSLEEP CACHEPWDSLP [31..31]  ======================================= */
24046 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP                                         */
24047   PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_EN = 1,     /*!< EN : Power down cache in deep sleep                                       */
24048   PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_DIS = 0,    /*!< DIS : Retain cache in deep sleep                                          */
24049 } PWRCTRL_MEMPWDINSLEEP_CACHEPWDSLP_Enum;
24050 
24051 /* ======================================  PWRCTRL MEMPWDINSLEEP FLASH1PWDSLP [14..14]  ====================================== */
24052 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP                                        */
24053   PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_EN = 1,    /*!< EN : FLASH1 is powered down during deep sleep                             */
24054   PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_DIS = 0,   /*!< DIS : FLASH1 is kept powered on during deep sleep                         */
24055 } PWRCTRL_MEMPWDINSLEEP_FLASH1PWDSLP_Enum;
24056 
24057 /* ======================================  PWRCTRL MEMPWDINSLEEP FLASH0PWDSLP [13..13]  ====================================== */
24058 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP                                        */
24059   PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_EN = 1,    /*!< EN : FLASH0 is powered down during deep sleep                             */
24060   PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_DIS = 0,   /*!< DIS : FLASH0 is kept powered on during deep sleep                         */
24061 } PWRCTRL_MEMPWDINSLEEP_FLASH0PWDSLP_Enum;
24062 
24063 /* =======================================  PWRCTRL MEMPWDINSLEEP SRAMPWDSLP [3..12]  ======================================== */
24064 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP                                          */
24065   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_NONE = 0,    /*!< NONE : All banks retained                                                 */
24066   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP0 = 1,  /*!< GROUP0 : SRAM GROUP0 powered down (64KB-96KB)                             */
24067   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP1 = 2,  /*!< GROUP1 : SRAM GROUP1 powered down (96KB-128KB)                            */
24068   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP2 = 4,  /*!< GROUP2 : SRAM GROUP2 powered down (128KB-160KB)                           */
24069   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP3 = 8,  /*!< GROUP3 : SRAM GROUP3 powered down (160KB-192KB)                           */
24070   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP4 = 16, /*!< GROUP4 : SRAM GROUP4 powered down (192KB-224KB)                           */
24071   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP5 = 32, /*!< GROUP5 : SRAM GROUP5 powered down (224KB-256KB)                           */
24072   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP6 = 64, /*!< GROUP6 : SRAM GROUP6 powered down (256KB-288KB)                           */
24073   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP7 = 128,/*!< GROUP7 : SRAM GROUP7 powered down (288KB-320KB)                           */
24074   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP8 = 256,/*!< GROUP8 : SRAM GROUP8 powered down (320KB-352KB)                           */
24075   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_GROUP9 = 512,/*!< GROUP9 : SRAM GROUP9 powered down (352KB-384KB)                           */
24076   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM64K = 3, /*!< SRAM64K : Power-down lower 64k SRAM (64KB-128KB)                          */
24077   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_SRAM128K = 15,/*!< SRAM128K : Power-down lower 128k SRAM (64KB-192KB)                       */
24078   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER32K = 1022,/*!< ALLBUTLOWER32K : All SRAM banks but lower 32k powered down (96KB-384KB). */
24079   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER64K = 1020,/*!< ALLBUTLOWER64K : All banks but lower 64k powered down.           */
24080   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALLBUTLOWER128K = 1008,/*!< ALLBUTLOWER128K : All banks but lower 128k powered down.        */
24081   PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_ALL = 1023,  /*!< ALL : All banks powered down.                                             */
24082 } PWRCTRL_MEMPWDINSLEEP_SRAMPWDSLP_Enum;
24083 
24084 /* ========================================  PWRCTRL MEMPWDINSLEEP DTCMPWDSLP [0..2]  ======================================== */
24085 typedef enum {                                  /*!< PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP                                          */
24086   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_NONE = 0,    /*!< NONE : All DTCM retained                                                  */
24087   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM0 = 1,/*!< GROUP0DTCM0 : Group0_DTCM0 powered down in deep sleep (0KB-8KB)        */
24088   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0DTCM1 = 2,/*!< GROUP0DTCM1 : Group0_DTCM1 powered down in deep sleep (8KB-32KB)       */
24089   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP0 = 3,  /*!< GROUP0 : Both DTCMs in group0 are powered down in deep sleep
24090                                                      (0KB-32KB)                                                                */
24091   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALLBUTGROUP0DTCM0 = 6,/*!< ALLBUTGROUP0DTCM0 : Group1 and Group0_DTCM1 are powered down
24092                                                      in deep sleep (8KB-64KB)                                                  */
24093   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_GROUP1 = 4,  /*!< GROUP1 : Group1 DTCM powered down in deep sleep (32KB-64KB)               */
24094   PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_ALL = 7,     /*!< ALL : All DTCMs powered down in deep sleep (0KB-64KB)                     */
24095 } PWRCTRL_MEMPWDINSLEEP_DTCMPWDSLP_Enum;
24096 
24097 /* =======================================================  MEMPWREN  ======================================================== */
24098 /* ===========================================  PWRCTRL MEMPWREN CACHEB2 [31..31]  =========================================== */
24099 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_CACHEB2                                                  */
24100   PWRCTRL_MEMPWREN_CACHEB2_EN          = 1,     /*!< EN : Power up Cache Bank 2                                                */
24101   PWRCTRL_MEMPWREN_CACHEB2_DIS         = 0,     /*!< DIS : Power down Cache Bank 2                                             */
24102 } PWRCTRL_MEMPWREN_CACHEB2_Enum;
24103 
24104 /* ===========================================  PWRCTRL MEMPWREN CACHEB0 [30..30]  =========================================== */
24105 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_CACHEB0                                                  */
24106   PWRCTRL_MEMPWREN_CACHEB0_EN          = 1,     /*!< EN : Power up Cache Bank 0                                                */
24107   PWRCTRL_MEMPWREN_CACHEB0_DIS         = 0,     /*!< DIS : Power down Cache Bank 0                                             */
24108 } PWRCTRL_MEMPWREN_CACHEB0_Enum;
24109 
24110 /* ===========================================  PWRCTRL MEMPWREN FLASH1 [14..14]  ============================================ */
24111 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_FLASH1                                                   */
24112   PWRCTRL_MEMPWREN_FLASH1_EN           = 1,     /*!< EN : Power up FLASH1                                                      */
24113   PWRCTRL_MEMPWREN_FLASH1_DIS          = 0,     /*!< DIS : Power down FLASH1                                                   */
24114 } PWRCTRL_MEMPWREN_FLASH1_Enum;
24115 
24116 /* ===========================================  PWRCTRL MEMPWREN FLASH0 [13..13]  ============================================ */
24117 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_FLASH0                                                   */
24118   PWRCTRL_MEMPWREN_FLASH0_EN           = 1,     /*!< EN : Power up FLASH0                                                      */
24119   PWRCTRL_MEMPWREN_FLASH0_DIS          = 0,     /*!< DIS : Power down FLASH0                                                   */
24120 } PWRCTRL_MEMPWREN_FLASH0_Enum;
24121 
24122 /* =============================================  PWRCTRL MEMPWREN SRAM [3..12]  ============================================= */
24123 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_SRAM                                                     */
24124   PWRCTRL_MEMPWREN_SRAM_NONE           = 0,     /*!< NONE : Do not power ON any of the SRAM banks                              */
24125   PWRCTRL_MEMPWREN_SRAM_GROUP0         = 1,     /*!< GROUP0 : Power ON only SRAM group0 (0KB-32KB)                             */
24126   PWRCTRL_MEMPWREN_SRAM_GROUP1         = 2,     /*!< GROUP1 : Power ON only SRAM group1 (32KB-64KB)                            */
24127   PWRCTRL_MEMPWREN_SRAM_GROUP2         = 4,     /*!< GROUP2 : Power ON only SRAM group2 (64KB-96KB)                            */
24128   PWRCTRL_MEMPWREN_SRAM_GROUP3         = 8,     /*!< GROUP3 : Power ON only SRAM group3 (96KB-128KB)                           */
24129   PWRCTRL_MEMPWREN_SRAM_GROUP4         = 16,    /*!< GROUP4 : Power ON only SRAM group4 (128KB-160KB)                          */
24130   PWRCTRL_MEMPWREN_SRAM_GROUP5         = 32,    /*!< GROUP5 : Power ON only SRAM group5 (160KB-192KB)                          */
24131   PWRCTRL_MEMPWREN_SRAM_GROUP6         = 64,    /*!< GROUP6 : Power ON only SRAM group6 (192KB-224KB)                          */
24132   PWRCTRL_MEMPWREN_SRAM_GROUP7         = 128,   /*!< GROUP7 : Power ON only SRAM group7 (224KB-256KB)                          */
24133   PWRCTRL_MEMPWREN_SRAM_GROUP8         = 256,   /*!< GROUP8 : Power ON only SRAM group8 (256KB-288KB)                          */
24134   PWRCTRL_MEMPWREN_SRAM_GROUP9         = 512,   /*!< GROUP9 : Power ON only SRAM group9 (288KB-320KB)                          */
24135   PWRCTRL_MEMPWREN_SRAM_SRAM64K        = 3,     /*!< SRAM64K : Power ON only lower 64k                                         */
24136   PWRCTRL_MEMPWREN_SRAM_SRAM128K       = 15,    /*!< SRAM128K : Power ON only lower 128k                                       */
24137   PWRCTRL_MEMPWREN_SRAM_SRAM256K       = 255,   /*!< SRAM256K : Power ON only lower 256k                                       */
24138   PWRCTRL_MEMPWREN_SRAM_ALL            = 1023,  /*!< ALL : All SRAM banks (320K) powered ON                                    */
24139 } PWRCTRL_MEMPWREN_SRAM_Enum;
24140 
24141 /* =============================================  PWRCTRL MEMPWREN DTCM [0..2]  ============================================== */
24142 typedef enum {                                  /*!< PWRCTRL_MEMPWREN_DTCM                                                     */
24143   PWRCTRL_MEMPWREN_DTCM_NONE           = 0,     /*!< NONE : Do not enable power to any DTCMs                                   */
24144   PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM0    = 1,     /*!< GROUP0DTCM0 : Power ON only GROUP0_DTCM0                                  */
24145   PWRCTRL_MEMPWREN_DTCM_GROUP0DTCM1    = 2,     /*!< GROUP0DTCM1 : Power ON only GROUP0_DTCM1                                  */
24146   PWRCTRL_MEMPWREN_DTCM_GROUP0         = 3,     /*!< GROUP0 : Power ON only DTCMs in group0                                    */
24147   PWRCTRL_MEMPWREN_DTCM_GROUP1         = 4,     /*!< GROUP1 : Power ON only DTCMs in group1                                    */
24148   PWRCTRL_MEMPWREN_DTCM_ALL            = 7,     /*!< ALL : Power ON all DTCMs                                                  */
24149 } PWRCTRL_MEMPWREN_DTCM_Enum;
24150 
24151 /* =====================================================  MEMPWRSTATUS  ====================================================== */
24152 /* =====================================================  DEVPWRSTATUS  ====================================================== */
24153 /* =======================================================  SRAMCTRL  ======================================================== */
24154 /* ========================================  PWRCTRL SRAMCTRL SRAMLIGHTSLEEP [8..19]  ======================================== */
24155 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP                                           */
24156   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_ALL  = 255,   /*!< ALL : Enable LIGHT SLEEP for ALL SRAMs                                    */
24157   PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_DIS  = 0,     /*!< DIS : Disables LIGHT SLEEP for ALL SRAMs                                  */
24158 } PWRCTRL_SRAMCTRL_SRAMLIGHTSLEEP_Enum;
24159 
24160 /* =======================================  PWRCTRL SRAMCTRL SRAMMASTERCLKGATE [2..2]  ======================================= */
24161 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE                                        */
24162   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_EN = 1,    /*!< EN : Enable Master SRAM Clock Gate                                        */
24163   PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_DIS = 0,   /*!< DIS : Disables Master SRAM Clock Gating                                   */
24164 } PWRCTRL_SRAMCTRL_SRAMMASTERCLKGATE_Enum;
24165 
24166 /* ==========================================  PWRCTRL SRAMCTRL SRAMCLKGATE [1..1]  ========================================== */
24167 typedef enum {                                  /*!< PWRCTRL_SRAMCTRL_SRAMCLKGATE                                              */
24168   PWRCTRL_SRAMCTRL_SRAMCLKGATE_EN      = 1,     /*!< EN : Enable Individual SRAM Clock Gating                                  */
24169   PWRCTRL_SRAMCTRL_SRAMCLKGATE_DIS     = 0,     /*!< DIS : Disables Individual SRAM Clock Gating                               */
24170 } PWRCTRL_SRAMCTRL_SRAMCLKGATE_Enum;
24171 
24172 /* =======================================================  ADCSTATUS  ======================================================= */
24173 /* =========================================================  MISC  ========================================================== */
24174 /* ============================================  PWRCTRL MISC MEMVRLPBLE [6..6]  ============================================= */
24175 typedef enum {                                  /*!< PWRCTRL_MISC_MEMVRLPBLE                                                   */
24176   PWRCTRL_MISC_MEMVRLPBLE_EN           = 1,     /*!< EN : Mem VR can go to lp mode even when BLE is powered on.                */
24177   PWRCTRL_MISC_MEMVRLPBLE_DIS          = 0,     /*!< DIS : Mem VR will stay in active mode when BLE is powered on.             */
24178 } PWRCTRL_MISC_MEMVRLPBLE_Enum;
24179 
24180 /* =====================================================  DEVPWREVENTEN  ===================================================== */
24181 /* =======================================  PWRCTRL DEVPWREVENTEN BURSTEVEN [31..31]  ======================================== */
24182 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BURSTEVEN                                           */
24183   PWRCTRL_DEVPWREVENTEN_BURSTEVEN_EN   = 1,     /*!< EN : Enable BURST status event                                            */
24184   PWRCTRL_DEVPWREVENTEN_BURSTEVEN_DIS  = 0,     /*!< DIS : Disable BURST status event                                          */
24185 } PWRCTRL_DEVPWREVENTEN_BURSTEVEN_Enum;
24186 
24187 /* ====================================  PWRCTRL DEVPWREVENTEN BURSTFEATUREEVEN [30..30]  ==================================== */
24188 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN                                    */
24189   PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_EN = 1,/*!< EN : Enable BURSTFEATURE status event                                     */
24190   PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_DIS = 0,/*!< DIS : Disable BURSTFEATURE status event                                  */
24191 } PWRCTRL_DEVPWREVENTEN_BURSTFEATUREEVEN_Enum;
24192 
24193 /* =====================================  PWRCTRL DEVPWREVENTEN BLEFEATUREEVEN [29..29]  ===================================== */
24194 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN                                      */
24195   PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_EN = 1,  /*!< EN : Enable BLEFEATURE status event                                       */
24196   PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_DIS = 0, /*!< DIS : Disable BLEFEATURE status event                                     */
24197 } PWRCTRL_DEVPWREVENTEN_BLEFEATUREEVEN_Enum;
24198 
24199 /* =========================================  PWRCTRL DEVPWREVENTEN BLELEVEN [8..8]  ========================================= */
24200 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_BLELEVEN                                            */
24201   PWRCTRL_DEVPWREVENTEN_BLELEVEN_EN    = 1,     /*!< EN : Enable BLE power-on status event                                     */
24202   PWRCTRL_DEVPWREVENTEN_BLELEVEN_DIS   = 0,     /*!< DIS : Disable BLE power-on status event                                   */
24203 } PWRCTRL_DEVPWREVENTEN_BLELEVEN_Enum;
24204 
24205 /* =========================================  PWRCTRL DEVPWREVENTEN PDMEVEN [7..7]  ========================================== */
24206 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_PDMEVEN                                             */
24207   PWRCTRL_DEVPWREVENTEN_PDMEVEN_EN     = 1,     /*!< EN : Enable PDM power-on status event                                     */
24208   PWRCTRL_DEVPWREVENTEN_PDMEVEN_DIS    = 0,     /*!< DIS : Disable PDM power-on status event                                   */
24209 } PWRCTRL_DEVPWREVENTEN_PDMEVEN_Enum;
24210 
24211 /* =========================================  PWRCTRL DEVPWREVENTEN MSPIEVEN [6..6]  ========================================= */
24212 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MSPIEVEN                                            */
24213   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_EN    = 1,     /*!< EN : Enable MSPI power-on status event                                    */
24214   PWRCTRL_DEVPWREVENTEN_MSPIEVEN_DIS   = 0,     /*!< DIS : Disable MSPI power-on status event                                  */
24215 } PWRCTRL_DEVPWREVENTEN_MSPIEVEN_Enum;
24216 
24217 /* =========================================  PWRCTRL DEVPWREVENTEN ADCEVEN [5..5]  ========================================== */
24218 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_ADCEVEN                                             */
24219   PWRCTRL_DEVPWREVENTEN_ADCEVEN_EN     = 1,     /*!< EN : Enable ADC power-on status event                                     */
24220   PWRCTRL_DEVPWREVENTEN_ADCEVEN_DIS    = 0,     /*!< DIS : Disable ADC power-on status event                                   */
24221 } PWRCTRL_DEVPWREVENTEN_ADCEVEN_Enum;
24222 
24223 /* =========================================  PWRCTRL DEVPWREVENTEN HCPCEVEN [4..4]  ========================================= */
24224 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPCEVEN                                            */
24225   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_EN    = 1,     /*!< EN : Enable HCPC power-on status event                                    */
24226   PWRCTRL_DEVPWREVENTEN_HCPCEVEN_DIS   = 0,     /*!< DIS : Disable HCPC power-on status event                                  */
24227 } PWRCTRL_DEVPWREVENTEN_HCPCEVEN_Enum;
24228 
24229 /* =========================================  PWRCTRL DEVPWREVENTEN HCPBEVEN [3..3]  ========================================= */
24230 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPBEVEN                                            */
24231   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_EN    = 1,     /*!< EN : Enable HCPB power-on status event                                    */
24232   PWRCTRL_DEVPWREVENTEN_HCPBEVEN_DIS   = 0,     /*!< DIS : Disable HCPB power-on status event                                  */
24233 } PWRCTRL_DEVPWREVENTEN_HCPBEVEN_Enum;
24234 
24235 /* =========================================  PWRCTRL DEVPWREVENTEN HCPAEVEN [2..2]  ========================================= */
24236 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_HCPAEVEN                                            */
24237   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_EN    = 1,     /*!< EN : Enable HCPA power-on status event                                    */
24238   PWRCTRL_DEVPWREVENTEN_HCPAEVEN_DIS   = 0,     /*!< DIS : Disable HCPA power-on status event                                  */
24239 } PWRCTRL_DEVPWREVENTEN_HCPAEVEN_Enum;
24240 
24241 /* =========================================  PWRCTRL DEVPWREVENTEN MCUHEVEN [1..1]  ========================================= */
24242 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCUHEVEN                                            */
24243   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_EN    = 1,     /*!< EN : Enable MCHU power-on status event                                    */
24244   PWRCTRL_DEVPWREVENTEN_MCUHEVEN_DIS   = 0,     /*!< DIS : Disable MCUH power-on status event                                  */
24245 } PWRCTRL_DEVPWREVENTEN_MCUHEVEN_Enum;
24246 
24247 /* =========================================  PWRCTRL DEVPWREVENTEN MCULEVEN [0..0]  ========================================= */
24248 typedef enum {                                  /*!< PWRCTRL_DEVPWREVENTEN_MCULEVEN                                            */
24249   PWRCTRL_DEVPWREVENTEN_MCULEVEN_EN    = 1,     /*!< EN : Enable MCUL power-on status event                                    */
24250   PWRCTRL_DEVPWREVENTEN_MCULEVEN_DIS   = 0,     /*!< DIS : Disable MCUL power-on status event                                  */
24251 } PWRCTRL_DEVPWREVENTEN_MCULEVEN_Enum;
24252 
24253 /* =====================================================  MEMPWREVENTEN  ===================================================== */
24254 /* =======================================  PWRCTRL MEMPWREVENTEN CACHEB2EN [31..31]  ======================================== */
24255 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB2EN                                           */
24256   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_EN   = 1,     /*!< EN : Enable CACHE BANK 2 status event                                     */
24257   PWRCTRL_MEMPWREVENTEN_CACHEB2EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 2 status event                                   */
24258 } PWRCTRL_MEMPWREVENTEN_CACHEB2EN_Enum;
24259 
24260 /* =======================================  PWRCTRL MEMPWREVENTEN CACHEB0EN [30..30]  ======================================== */
24261 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_CACHEB0EN                                           */
24262   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_EN   = 1,     /*!< EN : Enable CACHE BANK 0 status event                                     */
24263   PWRCTRL_MEMPWREVENTEN_CACHEB0EN_DIS  = 0,     /*!< DIS : Disable CACHE BANK 0 status event                                   */
24264 } PWRCTRL_MEMPWREVENTEN_CACHEB0EN_Enum;
24265 
24266 /* ========================================  PWRCTRL MEMPWREVENTEN FLASH1EN [14..14]  ======================================== */
24267 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_FLASH1EN                                            */
24268   PWRCTRL_MEMPWREVENTEN_FLASH1EN_EN    = 1,     /*!< EN : Enable FLASH status event                                            */
24269   PWRCTRL_MEMPWREVENTEN_FLASH1EN_DIS   = 0,     /*!< DIS : Disables FLASH status event                                         */
24270 } PWRCTRL_MEMPWREVENTEN_FLASH1EN_Enum;
24271 
24272 /* ========================================  PWRCTRL MEMPWREVENTEN FLASH0EN [13..13]  ======================================== */
24273 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_FLASH0EN                                            */
24274   PWRCTRL_MEMPWREVENTEN_FLASH0EN_EN    = 1,     /*!< EN : Enable FLASH status event                                            */
24275   PWRCTRL_MEMPWREVENTEN_FLASH0EN_DIS   = 0,     /*!< DIS : Disables FLASH status event                                         */
24276 } PWRCTRL_MEMPWREVENTEN_FLASH0EN_Enum;
24277 
24278 /* =========================================  PWRCTRL MEMPWREVENTEN SRAMEN [3..12]  ========================================== */
24279 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_SRAMEN                                              */
24280   PWRCTRL_MEMPWREVENTEN_SRAMEN_NONE    = 0,     /*!< NONE : Disable SRAM power-on status event                                 */
24281   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP0EN = 1,    /*!< GROUP0EN : Enable SRAM group0 (0KB-32KB) power on status event            */
24282   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP1EN = 2,    /*!< GROUP1EN : Enable SRAM group1 (32KB-64KB) power on status event           */
24283   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP2EN = 4,    /*!< GROUP2EN : Enable SRAM group2 (64KB-96KB) power on status event           */
24284   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP3EN = 8,    /*!< GROUP3EN : Enable SRAM group3 (96KB-128KB) power on status event          */
24285   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP4EN = 16,   /*!< GROUP4EN : Enable SRAM group4 (128KB-160KB) power on status
24286                                                      event                                                                     */
24287   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP5EN = 32,   /*!< GROUP5EN : Enable SRAM group5 (160KB-192KB) power on status
24288                                                      event                                                                     */
24289   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP6EN = 64,   /*!< GROUP6EN : Enable SRAM group6 (192KB-224KB) power on status
24290                                                      event                                                                     */
24291   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP7EN = 128,  /*!< GROUP7EN : Enable SRAM group7 (224KB-256KB) power on status
24292                                                      event                                                                     */
24293   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP8EN = 256,  /*!< GROUP8EN : Enable SRAM group8 (256KB-288KB) power on status
24294                                                      event                                                                     */
24295   PWRCTRL_MEMPWREVENTEN_SRAMEN_GROUP9EN = 512,  /*!< GROUP9EN : Enable SRAM group9 (288KB-320KB) power on status
24296                                                      event                                                                     */
24297 } PWRCTRL_MEMPWREVENTEN_SRAMEN_Enum;
24298 
24299 /* ==========================================  PWRCTRL MEMPWREVENTEN DTCMEN [0..2]  ========================================== */
24300 typedef enum {                                  /*!< PWRCTRL_MEMPWREVENTEN_DTCMEN                                              */
24301   PWRCTRL_MEMPWREVENTEN_DTCMEN_NONE    = 0,     /*!< NONE : Do not enable DTCM power-on status event                           */
24302   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM0EN = 1,/*!< GROUP0DTCM0EN : Enable GROUP0_DTCM0 power on status event                */
24303   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0DTCM1EN = 2,/*!< GROUP0DTCM1EN : Enable GROUP0_DTCM1 power on status event                */
24304   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP0EN = 3,    /*!< GROUP0EN : Enable DTCMs in group0 power on status event                   */
24305   PWRCTRL_MEMPWREVENTEN_DTCMEN_GROUP1EN = 4,    /*!< GROUP1EN : Enable DTCMs in group1 power on status event                   */
24306   PWRCTRL_MEMPWREVENTEN_DTCMEN_ALL     = 7,     /*!< ALL : Enable all DTCM power on status event                               */
24307 } PWRCTRL_MEMPWREVENTEN_DTCMEN_Enum;
24308 
24309 
24310 
24311 /* =========================================================================================================================== */
24312 /* ================                                          RSTGEN                                           ================ */
24313 /* =========================================================================================================================== */
24314 
24315 /* ==========================================================  CFG  ========================================================== */
24316 /* =========================================================  SWPOI  ========================================================= */
24317 /* =============================================  RSTGEN SWPOI SWPOIKEY [0..7]  ============================================== */
24318 typedef enum {                                  /*!< RSTGEN_SWPOI_SWPOIKEY                                                     */
24319   RSTGEN_SWPOI_SWPOIKEY_KEYVALUE       = 27,    /*!< KEYVALUE : Writing 0x1B key value generates a software POI reset.         */
24320 } RSTGEN_SWPOI_SWPOIKEY_Enum;
24321 
24322 /* =========================================================  SWPOR  ========================================================= */
24323 /* =============================================  RSTGEN SWPOR SWPORKEY [0..7]  ============================================== */
24324 typedef enum {                                  /*!< RSTGEN_SWPOR_SWPORKEY                                                     */
24325   RSTGEN_SWPOR_SWPORKEY_KEYVALUE       = 212,   /*!< KEYVALUE : Writing 0xD4 key value generates a software POR reset.         */
24326 } RSTGEN_SWPOR_SWPORKEY_Enum;
24327 
24328 /* ========================================================  TPIURST  ======================================================== */
24329 /* =========================================================  INTEN  ========================================================= */
24330 /* ========================================================  INTSTAT  ======================================================== */
24331 /* ========================================================  INTCLR  ========================================================= */
24332 /* ========================================================  INTSET  ========================================================= */
24333 /* =========================================================  STAT  ========================================================== */
24334 
24335 
24336 /* =========================================================================================================================== */
24337 /* ================                                            RTC                                            ================ */
24338 /* =========================================================================================================================== */
24339 
24340 /* ========================================================  CTRLOW  ========================================================= */
24341 /* =========================================================  CTRUP  ========================================================= */
24342 /* ===============================================  RTC CTRUP CTERR [31..31]  ================================================ */
24343 typedef enum {                                  /*!< RTC_CTRUP_CTERR                                                           */
24344   RTC_CTRUP_CTERR_NOERR                = 0,     /*!< NOERR : No read error occurred                                            */
24345   RTC_CTRUP_CTERR_RDERR                = 1,     /*!< RDERR : Read error occurred                                               */
24346 } RTC_CTRUP_CTERR_Enum;
24347 
24348 /* ================================================  RTC CTRUP CEB [28..28]  ================================================= */
24349 typedef enum {                                  /*!< RTC_CTRUP_CEB                                                             */
24350   RTC_CTRUP_CEB_DIS                    = 0,     /*!< DIS : Disable the Century bit from changing                               */
24351   RTC_CTRUP_CEB_EN                     = 1,     /*!< EN : Enable the Century bit to change                                     */
24352 } RTC_CTRUP_CEB_Enum;
24353 
24354 /* =================================================  RTC CTRUP CB [27..27]  ================================================= */
24355 typedef enum {                                  /*!< RTC_CTRUP_CB                                                              */
24356   RTC_CTRUP_CB_2000                    = 0,     /*!< 2000 : Century is 2000s                                                   */
24357   RTC_CTRUP_CB_1900_2100               = 1,     /*!< 1900_2100 : Century is 1900s/2100s                                        */
24358 } RTC_CTRUP_CB_Enum;
24359 
24360 /* ========================================================  ALMLOW  ========================================================= */
24361 /* =========================================================  ALMUP  ========================================================= */
24362 /* ========================================================  RTCCTL  ========================================================= */
24363 /* ===============================================  RTC RTCCTL HR1224 [5..5]  ================================================ */
24364 typedef enum {                                  /*!< RTC_RTCCTL_HR1224                                                         */
24365   RTC_RTCCTL_HR1224_24HR               = 0,     /*!< 24HR : Hours in 24 hour mode                                              */
24366   RTC_RTCCTL_HR1224_12HR               = 1,     /*!< 12HR : Hours in 12 hour mode                                              */
24367 } RTC_RTCCTL_HR1224_Enum;
24368 
24369 /* ================================================  RTC RTCCTL RSTOP [4..4]  ================================================ */
24370 typedef enum {                                  /*!< RTC_RTCCTL_RSTOP                                                          */
24371   RTC_RTCCTL_RSTOP_RUN                 = 0,     /*!< RUN : Allow the RTC input clock to run                                    */
24372   RTC_RTCCTL_RSTOP_STOP                = 1,     /*!< STOP : Stop the RTC input clock                                           */
24373 } RTC_RTCCTL_RSTOP_Enum;
24374 
24375 /* =================================================  RTC RTCCTL RPT [1..3]  ================================================= */
24376 typedef enum {                                  /*!< RTC_RTCCTL_RPT                                                            */
24377   RTC_RTCCTL_RPT_DIS                   = 0,     /*!< DIS : Alarm interrupt disabled                                            */
24378   RTC_RTCCTL_RPT_YEAR                  = 1,     /*!< YEAR : Interrupt every year                                               */
24379   RTC_RTCCTL_RPT_MONTH                 = 2,     /*!< MONTH : Interrupt every month                                             */
24380   RTC_RTCCTL_RPT_WEEK                  = 3,     /*!< WEEK : Interrupt every week                                               */
24381   RTC_RTCCTL_RPT_DAY                   = 4,     /*!< DAY : Interrupt every day                                                 */
24382   RTC_RTCCTL_RPT_HR                    = 5,     /*!< HR : Interrupt every hour                                                 */
24383   RTC_RTCCTL_RPT_MIN                   = 6,     /*!< MIN : Interrupt every minute                                              */
24384   RTC_RTCCTL_RPT_SEC                   = 7,     /*!< SEC : Interrupt every second/10th/100th                                   */
24385 } RTC_RTCCTL_RPT_Enum;
24386 
24387 /* ================================================  RTC RTCCTL WRTC [0..0]  ================================================= */
24388 typedef enum {                                  /*!< RTC_RTCCTL_WRTC                                                           */
24389   RTC_RTCCTL_WRTC_DIS                  = 0,     /*!< DIS : Counter writes are disabled                                         */
24390   RTC_RTCCTL_WRTC_EN                   = 1,     /*!< EN : Counter writes are enabled                                           */
24391 } RTC_RTCCTL_WRTC_Enum;
24392 
24393 /* =========================================================  INTEN  ========================================================= */
24394 /* ========================================================  INTSTAT  ======================================================== */
24395 /* ========================================================  INTCLR  ========================================================= */
24396 /* ========================================================  INTSET  ========================================================= */
24397 
24398 
24399 /* =========================================================================================================================== */
24400 /* ================                                           SCARD                                           ================ */
24401 /* =========================================================================================================================== */
24402 
24403 /* ==========================================================  SR  =========================================================== */
24404 /* ==================================================  SCARD SR FHF [6..6]  ================================================== */
24405 typedef enum {                                  /*!< SCARD_SR_FHF                                                              */
24406   SCARD_SR_FHF_HALFFULL                = 1,     /*!< HALFFULL : FIFO is half full.                                             */
24407 } SCARD_SR_FHF_Enum;
24408 
24409 /* ================================================  SCARD SR FT2REND [5..5]  ================================================ */
24410 typedef enum {                                  /*!< SCARD_SR_FT2REND                                                          */
24411   SCARD_SR_FT2REND_CMPL                = 1,     /*!< CMPL : TX to RX completed.                                                */
24412   SCARD_SR_FT2REND_NOTCMPL             = 0,     /*!< NOTCMPL : TX to RX not completed.                                         */
24413 } SCARD_SR_FT2REND_Enum;
24414 
24415 /* ==================================================  SCARD SR PE [4..4]  =================================================== */
24416 typedef enum {                                  /*!< SCARD_SR_PE                                                               */
24417   SCARD_SR_PE_PEERR                    = 1,     /*!< PEERR : Parity error.                                                     */
24418   SCARD_SR_PE_PENONE                   = 0,     /*!< PENONE : No parity error.                                                 */
24419 } SCARD_SR_PE_Enum;
24420 
24421 /* ==================================================  SCARD SR OVR [3..3]  ================================================== */
24422 typedef enum {                                  /*!< SCARD_SR_OVR                                                              */
24423   SCARD_SR_OVR_RXOVR                   = 1,     /*!< RXOVR : RX FIFO overflow.                                                 */
24424   SCARD_SR_OVR_RXOVRNONE               = 0,     /*!< RXOVRNONE : RX FIFO no overflow.                                          */
24425 } SCARD_SR_OVR_Enum;
24426 
24427 /* ==================================================  SCARD SR FER [2..2]  ================================================== */
24428 typedef enum {                                  /*!< SCARD_SR_FER                                                              */
24429   SCARD_SR_FER_FRAMINGERR              = 1,     /*!< FRAMINGERR : Framing error.                                               */
24430   SCARD_SR_FER_NOFRAMINGERR            = 0,     /*!< NOFRAMINGERR : No framing error detected.                                 */
24431 } SCARD_SR_FER_Enum;
24432 
24433 /* ================================================  SCARD SR TBERBF [1..1]  ================================================= */
24434 typedef enum {                                  /*!< SCARD_SR_TBERBF                                                           */
24435   SCARD_SR_TBERBF_TXFIFOEMPTY          = 1,     /*!< TXFIFOEMPTY : Transmit: FIFO empty.                                       */
24436   SCARD_SR_TBERBF_TXFIFONOTEMPTY       = 0,     /*!< TXFIFONOTEMPTY : Transmit: FIFO not empty.                                */
24437 } SCARD_SR_TBERBF_Enum;
24438 
24439 /* ==================================================  SCARD SR FNE [0..0]  ================================================== */
24440 typedef enum {                                  /*!< SCARD_SR_FNE                                                              */
24441   SCARD_SR_FNE_NOTEMPTY                = 1,     /*!< NOTEMPTY : RX FIFO not empty.                                             */
24442   SCARD_SR_FNE_EMPTY                   = 0,     /*!< EMPTY : RX FIFO empty.                                                    */
24443 } SCARD_SR_FNE_Enum;
24444 
24445 /* ==========================================================  IER  ========================================================== */
24446 /* ==========================================================  TCR  ========================================================== */
24447 /* ==========================================================  UCR  ========================================================== */
24448 /* ==========================================================  DR  =========================================================== */
24449 /* =========================================================  BPRL  ========================================================== */
24450 /* =========================================================  BPRH  ========================================================== */
24451 /* =========================================================  UCR1  ========================================================== */
24452 /* ==========================================================  SR1  ========================================================== */
24453 /* =================================================  SCARD SR1 IDLE [3..3]  ================================================= */
24454 typedef enum {                                  /*!< SCARD_SR1_IDLE                                                            */
24455   SCARD_SR1_IDLE_IDLE                  = 1,     /*!< IDLE : ISO7816 idle.                                                      */
24456   SCARD_SR1_IDLE_ACTIVE                = 0,     /*!< ACTIVE : ISO7816 active.                                                  */
24457 } SCARD_SR1_IDLE_Enum;
24458 
24459 /* ===============================================  SCARD SR1 SYNCEND [2..2]  ================================================ */
24460 typedef enum {                                  /*!< SCARD_SR1_SYNCEND                                                         */
24461   SCARD_SR1_SYNCEND_CMPL               = 1,     /*!< CMPL : Synchronization complete.                                          */
24462   SCARD_SR1_SYNCEND_INCMPL             = 0,     /*!< INCMPL : Incomplete.                                                      */
24463 } SCARD_SR1_SYNCEND_Enum;
24464 
24465 /* =================================================  SCARD SR1 PRL [1..1]  ================================================== */
24466 typedef enum {                                  /*!< SCARD_SR1_PRL                                                             */
24467   SCARD_SR1_PRL_INSREM                 = 1,     /*!< INSREM : Card inserted/removed.                                           */
24468 } SCARD_SR1_PRL_Enum;
24469 
24470 /* ===============================================  SCARD SR1 ECNTOVER [0..0]  =============================================== */
24471 typedef enum {                                  /*!< SCARD_SR1_ECNTOVER                                                        */
24472   SCARD_SR1_ECNTOVER_OVR               = 1,     /*!< OVR : ETU overflow.                                                       */
24473 } SCARD_SR1_ECNTOVER_Enum;
24474 
24475 /* =========================================================  IER1  ========================================================== */
24476 /* =========================================================  ECNTL  ========================================================= */
24477 /* =========================================================  ECNTH  ========================================================= */
24478 /* ==========================================================  GTR  ========================================================== */
24479 /* ========================================================  RETXCNT  ======================================================== */
24480 /* ======================================================  RETXCNTRMI  ======================================================= */
24481 /* ========================================================  CLKCTRL  ======================================================== */
24482 
24483 
24484 /* =========================================================================================================================== */
24485 /* ================                                         SECURITY                                          ================ */
24486 /* =========================================================================================================================== */
24487 
24488 /* =========================================================  CTRL  ========================================================== */
24489 /* =============================================  SECURITY CTRL FUNCTION [4..7]  ============================================= */
24490 typedef enum {                                  /*!< SECURITY_CTRL_FUNCTION                                                    */
24491   SECURITY_CTRL_FUNCTION_CRC32         = 0,     /*!< CRC32 : Perform CRC32 operation                                           */
24492 } SECURITY_CTRL_FUNCTION_Enum;
24493 
24494 /* ========================================================  SRCADDR  ======================================================== */
24495 /* ==========================================================  LEN  ========================================================== */
24496 /* ========================================================  RESULT  ========================================================= */
24497 /* =======================================================  LOCKCTRL  ======================================================== */
24498 /* ============================================  SECURITY LOCKCTRL SELECT [0..7]  ============================================ */
24499 typedef enum {                                  /*!< SECURITY_LOCKCTRL_SELECT                                                  */
24500   SECURITY_LOCKCTRL_SELECT_CUSTOMER_KEY = 1,    /*!< CUSTOMER_KEY : Unlock Customer Key (access to top half of INFO0)          */
24501   SECURITY_LOCKCTRL_SELECT_NONE        = 0,     /*!< NONE : Lock Control should be set to NONE when not in use.                */
24502 } SECURITY_LOCKCTRL_SELECT_Enum;
24503 
24504 /* =======================================================  LOCKSTAT  ======================================================== */
24505 /* ===========================================  SECURITY LOCKSTAT STATUS [0..31]  ============================================ */
24506 typedef enum {                                  /*!< SECURITY_LOCKSTAT_STATUS                                                  */
24507   SECURITY_LOCKSTAT_STATUS_CUSTOMER_KEY = 1,    /*!< CUSTOMER_KEY : Customer Key is unlocked (access is granted to
24508                                                      top half of INFO0)                                                        */
24509   SECURITY_LOCKSTAT_STATUS_NONE        = 0,     /*!< NONE : No resources are unlocked                                          */
24510 } SECURITY_LOCKSTAT_STATUS_Enum;
24511 
24512 /* =========================================================  KEY0  ========================================================== */
24513 /* =========================================================  KEY1  ========================================================== */
24514 /* =========================================================  KEY2  ========================================================== */
24515 /* =========================================================  KEY3  ========================================================== */
24516 
24517 
24518 /* =========================================================================================================================== */
24519 /* ================                                           UART0                                           ================ */
24520 /* =========================================================================================================================== */
24521 
24522 /* ==========================================================  DR  =========================================================== */
24523 /* ===============================================  UART0 DR OEDATA [11..11]  ================================================ */
24524 typedef enum {                                  /*!< UART0_DR_OEDATA                                                           */
24525   UART0_DR_OEDATA_NOERR                = 0,     /*!< NOERR : No error on UART OEDATA, overrun error indicator.                 */
24526   UART0_DR_OEDATA_ERR                  = 1,     /*!< ERR : Error on UART OEDATA, overrun error indicator.                      */
24527 } UART0_DR_OEDATA_Enum;
24528 
24529 /* ===============================================  UART0 DR BEDATA [10..10]  ================================================ */
24530 typedef enum {                                  /*!< UART0_DR_BEDATA                                                           */
24531   UART0_DR_BEDATA_NOERR                = 0,     /*!< NOERR : No error on UART BEDATA, break error indicator.                   */
24532   UART0_DR_BEDATA_ERR                  = 1,     /*!< ERR : Error on UART BEDATA, break error indicator.                        */
24533 } UART0_DR_BEDATA_Enum;
24534 
24535 /* ================================================  UART0 DR PEDATA [9..9]  ================================================= */
24536 typedef enum {                                  /*!< UART0_DR_PEDATA                                                           */
24537   UART0_DR_PEDATA_NOERR                = 0,     /*!< NOERR : No error on UART PEDATA, parity error indicator.                  */
24538   UART0_DR_PEDATA_ERR                  = 1,     /*!< ERR : Error on UART PEDATA, parity error indicator.                       */
24539 } UART0_DR_PEDATA_Enum;
24540 
24541 /* ================================================  UART0 DR FEDATA [8..8]  ================================================= */
24542 typedef enum {                                  /*!< UART0_DR_FEDATA                                                           */
24543   UART0_DR_FEDATA_NOERR                = 0,     /*!< NOERR : No error on UART FEDATA, framing error indicator.                 */
24544   UART0_DR_FEDATA_ERR                  = 1,     /*!< ERR : Error on UART FEDATA, framing error indicator.                      */
24545 } UART0_DR_FEDATA_Enum;
24546 
24547 /* ==========================================================  RSR  ========================================================== */
24548 /* ================================================  UART0 RSR OESTAT [3..3]  ================================================ */
24549 typedef enum {                                  /*!< UART0_RSR_OESTAT                                                          */
24550   UART0_RSR_OESTAT_NOERR               = 0,     /*!< NOERR : No error on UART OESTAT, overrun error indicator.                 */
24551   UART0_RSR_OESTAT_ERR                 = 1,     /*!< ERR : Error on UART OESTAT, overrun error indicator.                      */
24552 } UART0_RSR_OESTAT_Enum;
24553 
24554 /* ================================================  UART0 RSR BESTAT [2..2]  ================================================ */
24555 typedef enum {                                  /*!< UART0_RSR_BESTAT                                                          */
24556   UART0_RSR_BESTAT_NOERR               = 0,     /*!< NOERR : No error on UART BESTAT, break error indicator.                   */
24557   UART0_RSR_BESTAT_ERR                 = 1,     /*!< ERR : Error on UART BESTAT, break error indicator.                        */
24558 } UART0_RSR_BESTAT_Enum;
24559 
24560 /* ================================================  UART0 RSR PESTAT [1..1]  ================================================ */
24561 typedef enum {                                  /*!< UART0_RSR_PESTAT                                                          */
24562   UART0_RSR_PESTAT_NOERR               = 0,     /*!< NOERR : No error on UART PESTAT, parity error indicator.                  */
24563   UART0_RSR_PESTAT_ERR                 = 1,     /*!< ERR : Error on UART PESTAT, parity error indicator.                       */
24564 } UART0_RSR_PESTAT_Enum;
24565 
24566 /* ================================================  UART0 RSR FESTAT [0..0]  ================================================ */
24567 typedef enum {                                  /*!< UART0_RSR_FESTAT                                                          */
24568   UART0_RSR_FESTAT_NOERR               = 0,     /*!< NOERR : No error on UART FESTAT, framing error indicator.                 */
24569   UART0_RSR_FESTAT_ERR                 = 1,     /*!< ERR : Error on UART FESTAT, framing error indicator.                      */
24570 } UART0_RSR_FESTAT_Enum;
24571 
24572 /* ==========================================================  FR  =========================================================== */
24573 /* =================================================  UART0 FR TXFE [7..7]  ================================================== */
24574 typedef enum {                                  /*!< UART0_FR_TXFE                                                             */
24575   UART0_FR_TXFE_XMTFIFO_EMPTY          = 1,     /*!< XMTFIFO_EMPTY : Transmit FIFO is empty.                                   */
24576 } UART0_FR_TXFE_Enum;
24577 
24578 /* =================================================  UART0 FR RXFF [6..6]  ================================================== */
24579 typedef enum {                                  /*!< UART0_FR_RXFF                                                             */
24580   UART0_FR_RXFF_RCVFIFO_FULL           = 1,     /*!< RCVFIFO_FULL : Receive FIFO is full.                                      */
24581 } UART0_FR_RXFF_Enum;
24582 
24583 /* =================================================  UART0 FR TXFF [5..5]  ================================================== */
24584 typedef enum {                                  /*!< UART0_FR_TXFF                                                             */
24585   UART0_FR_TXFF_XMTFIFO_FULL           = 1,     /*!< XMTFIFO_FULL : Transmit FIFO is full.                                     */
24586 } UART0_FR_TXFF_Enum;
24587 
24588 /* =================================================  UART0 FR RXFE [4..4]  ================================================== */
24589 typedef enum {                                  /*!< UART0_FR_RXFE                                                             */
24590   UART0_FR_RXFE_RCVFIFO_EMPTY          = 1,     /*!< RCVFIFO_EMPTY : Receive FIFO is empty.                                    */
24591 } UART0_FR_RXFE_Enum;
24592 
24593 /* =================================================  UART0 FR BUSY [3..3]  ================================================== */
24594 typedef enum {                                  /*!< UART0_FR_BUSY                                                             */
24595   UART0_FR_BUSY_BUSY                   = 1,     /*!< BUSY : UART busy indicator.                                               */
24596 } UART0_FR_BUSY_Enum;
24597 
24598 /* ==================================================  UART0 FR DCD [2..2]  ================================================== */
24599 typedef enum {                                  /*!< UART0_FR_DCD                                                              */
24600   UART0_FR_DCD_DETECTED                = 1,     /*!< DETECTED : Data carrier detect detected.                                  */
24601 } UART0_FR_DCD_Enum;
24602 
24603 /* ==================================================  UART0 FR DSR [1..1]  ================================================== */
24604 typedef enum {                                  /*!< UART0_FR_DSR                                                              */
24605   UART0_FR_DSR_READY                   = 1,     /*!< READY : Data set ready.                                                   */
24606 } UART0_FR_DSR_Enum;
24607 
24608 /* ==================================================  UART0 FR CTS [0..0]  ================================================== */
24609 typedef enum {                                  /*!< UART0_FR_CTS                                                              */
24610   UART0_FR_CTS_CLEARTOSEND             = 1,     /*!< CLEARTOSEND : Clear to send is indicated.                                 */
24611 } UART0_FR_CTS_Enum;
24612 
24613 /* =========================================================  ILPR  ========================================================== */
24614 /* =========================================================  IBRD  ========================================================== */
24615 /* =========================================================  FBRD  ========================================================== */
24616 /* =========================================================  LCRH  ========================================================== */
24617 /* ==========================================================  CR  =========================================================== */
24618 /* ================================================  UART0 CR CLKSEL [4..6]  ================================================= */
24619 typedef enum {                                  /*!< UART0_CR_CLKSEL                                                           */
24620   UART0_CR_CLKSEL_NOCLK                = 0,     /*!< NOCLK : No UART clock. This is the low power default.                     */
24621   UART0_CR_CLKSEL_24MHZ                = 1,     /*!< 24MHZ : 24 MHz clock.                                                     */
24622   UART0_CR_CLKSEL_12MHZ                = 2,     /*!< 12MHZ : 12 MHz clock.                                                     */
24623   UART0_CR_CLKSEL_6MHZ                 = 3,     /*!< 6MHZ : 6 MHz clock.                                                       */
24624   UART0_CR_CLKSEL_3MHZ                 = 4,     /*!< 3MHZ : 3 MHz clock.                                                       */
24625 } UART0_CR_CLKSEL_Enum;
24626 
24627 /* =========================================================  IFLS  ========================================================== */
24628 /* ==========================================================  IER  ========================================================== */
24629 /* ==========================================================  IES  ========================================================== */
24630 /* ==========================================================  MIS  ========================================================== */
24631 /* ==========================================================  IEC  ========================================================== */
24632 
24633 
24634 /* =========================================================================================================================== */
24635 /* ================                                           VCOMP                                           ================ */
24636 /* =========================================================================================================================== */
24637 
24638 /* ==========================================================  CFG  ========================================================== */
24639 /* ===============================================  VCOMP CFG LVLSEL [16..19]  =============================================== */
24640 typedef enum {                                  /*!< VCOMP_CFG_LVLSEL                                                          */
24641   VCOMP_CFG_LVLSEL_0P58V               = 0,     /*!< 0P58V : Set Reference input to 0.58 Volts.                                */
24642   VCOMP_CFG_LVLSEL_0P77V               = 1,     /*!< 0P77V : Set Reference input to 0.77 Volts.                                */
24643   VCOMP_CFG_LVLSEL_0P97V               = 2,     /*!< 0P97V : Set Reference input to 0.97 Volts.                                */
24644   VCOMP_CFG_LVLSEL_1P16V               = 3,     /*!< 1P16V : Set Reference input to 1.16 Volts.                                */
24645   VCOMP_CFG_LVLSEL_1P35V               = 4,     /*!< 1P35V : Set Reference input to 1.35 Volts.                                */
24646   VCOMP_CFG_LVLSEL_1P55V               = 5,     /*!< 1P55V : Set Reference input to 1.55 Volts.                                */
24647   VCOMP_CFG_LVLSEL_1P74V               = 6,     /*!< 1P74V : Set Reference input to 1.74 Volts.                                */
24648   VCOMP_CFG_LVLSEL_1P93V               = 7,     /*!< 1P93V : Set Reference input to 1.93 Volts.                                */
24649   VCOMP_CFG_LVLSEL_2P13V               = 8,     /*!< 2P13V : Set Reference input to 2.13 Volts.                                */
24650   VCOMP_CFG_LVLSEL_2P32V               = 9,     /*!< 2P32V : Set Reference input to 2.32 Volts.                                */
24651   VCOMP_CFG_LVLSEL_2P51V               = 10,    /*!< 2P51V : Set Reference input to 2.51 Volts.                                */
24652   VCOMP_CFG_LVLSEL_2P71V               = 11,    /*!< 2P71V : Set Reference input to 2.71 Volts.                                */
24653   VCOMP_CFG_LVLSEL_2P90V               = 12,    /*!< 2P90V : Set Reference input to 2.90 Volts.                                */
24654   VCOMP_CFG_LVLSEL_3P09V               = 13,    /*!< 3P09V : Set Reference input to 3.09 Volts.                                */
24655   VCOMP_CFG_LVLSEL_3P29V               = 14,    /*!< 3P29V : Set Reference input to 3.29 Volts.                                */
24656   VCOMP_CFG_LVLSEL_3P48V               = 15,    /*!< 3P48V : Set Reference input to 3.48 Volts.                                */
24657 } VCOMP_CFG_LVLSEL_Enum;
24658 
24659 /* =================================================  VCOMP CFG NSEL [8..9]  ================================================= */
24660 typedef enum {                                  /*!< VCOMP_CFG_NSEL                                                            */
24661   VCOMP_CFG_NSEL_VREFEXT1              = 0,     /*!< VREFEXT1 : Use external reference 1 for reference input.                  */
24662   VCOMP_CFG_NSEL_VREFEXT2              = 1,     /*!< VREFEXT2 : Use external reference 2 for reference input.                  */
24663   VCOMP_CFG_NSEL_VREFEXT3              = 2,     /*!< VREFEXT3 : Use external reference 3 for reference input.                  */
24664   VCOMP_CFG_NSEL_DAC                   = 3,     /*!< DAC : Use DAC output selected by LVLSEL for reference input.              */
24665 } VCOMP_CFG_NSEL_Enum;
24666 
24667 /* =================================================  VCOMP CFG PSEL [0..1]  ================================================= */
24668 typedef enum {                                  /*!< VCOMP_CFG_PSEL                                                            */
24669   VCOMP_CFG_PSEL_VDDADJ                = 0,     /*!< VDDADJ : Use VDDADJ for the positive input.                               */
24670   VCOMP_CFG_PSEL_VTEMP                 = 1,     /*!< VTEMP : Use the temperature sensor output for the positive input.
24671                                                      Note: If this channel is selected for PSEL, the bandgap
24672                                                      circuit required for temperature comparisons will automatically
24673                                                      turn on. The bandgap circuit requires 11 us to stabilize.                 */
24674   VCOMP_CFG_PSEL_VEXT1                 = 2,     /*!< VEXT1 : Use external voltage 0 for positive input.                        */
24675   VCOMP_CFG_PSEL_VEXT2                 = 3,     /*!< VEXT2 : Use external voltage 1 for positive input.                        */
24676 } VCOMP_CFG_PSEL_Enum;
24677 
24678 /* =========================================================  STAT  ========================================================== */
24679 /* ===============================================  VCOMP STAT PWDSTAT [1..1]  =============================================== */
24680 typedef enum {                                  /*!< VCOMP_STAT_PWDSTAT                                                        */
24681   VCOMP_STAT_PWDSTAT_POWERED_DOWN      = 1,     /*!< POWERED_DOWN : The voltage comparator is powered down.                    */
24682 } VCOMP_STAT_PWDSTAT_Enum;
24683 
24684 /* ===============================================  VCOMP STAT CMPOUT [0..0]  ================================================ */
24685 typedef enum {                                  /*!< VCOMP_STAT_CMPOUT                                                         */
24686   VCOMP_STAT_CMPOUT_VOUT_LOW           = 0,     /*!< VOUT_LOW : The negative input of the comparator is greater than
24687                                                      the positive input.                                                       */
24688   VCOMP_STAT_CMPOUT_VOUT_HIGH          = 1,     /*!< VOUT_HIGH : The positive input of the comparator is greater
24689                                                      than the negative input.                                                  */
24690 } VCOMP_STAT_CMPOUT_Enum;
24691 
24692 /* ========================================================  PWDKEY  ========================================================= */
24693 /* ==============================================  VCOMP PWDKEY PWDKEY [0..31]  ============================================== */
24694 typedef enum {                                  /*!< VCOMP_PWDKEY_PWDKEY                                                       */
24695   VCOMP_PWDKEY_PWDKEY_Key              = 55,    /*!< Key : Key value to unlock the register.                                   */
24696 } VCOMP_PWDKEY_PWDKEY_Enum;
24697 
24698 /* =========================================================  INTEN  ========================================================= */
24699 /* ========================================================  INTSTAT  ======================================================== */
24700 /* ========================================================  INTCLR  ========================================================= */
24701 /* ========================================================  INTSET  ========================================================= */
24702 
24703 
24704 /* =========================================================================================================================== */
24705 /* ================                                            WDT                                            ================ */
24706 /* =========================================================================================================================== */
24707 
24708 /* ==========================================================  CFG  ========================================================== */
24709 /* ================================================  WDT CFG CLKSEL [24..26]  ================================================ */
24710 typedef enum {                                  /*!< WDT_CFG_CLKSEL                                                            */
24711   WDT_CFG_CLKSEL_OFF                   = 0,     /*!< OFF : Low Power Mode. This setting disables the watch dog timer.          */
24712   WDT_CFG_CLKSEL_128HZ                 = 1,     /*!< 128HZ : 128 Hz LFRC clock.                                                */
24713   WDT_CFG_CLKSEL_16HZ                  = 2,     /*!< 16HZ : 16 Hz LFRC clock.                                                  */
24714   WDT_CFG_CLKSEL_1HZ                   = 3,     /*!< 1HZ : 1 Hz LFRC clock.                                                    */
24715   WDT_CFG_CLKSEL_1_16HZ                = 4,     /*!< 1_16HZ : 1/16th Hz LFRC clock.                                            */
24716 } WDT_CFG_CLKSEL_Enum;
24717 
24718 /* =========================================================  RSTRT  ========================================================= */
24719 /* ================================================  WDT RSTRT RSTRT [0..7]  ================================================= */
24720 typedef enum {                                  /*!< WDT_RSTRT_RSTRT                                                           */
24721   WDT_RSTRT_RSTRT_KEYVALUE             = 178,   /*!< KEYVALUE : This is the key value to write to WDTRSTRT to restart
24722                                                      the WDT. This is a write only register.                                   */
24723 } WDT_RSTRT_RSTRT_Enum;
24724 
24725 /* =========================================================  LOCK  ========================================================== */
24726 /* =================================================  WDT LOCK LOCK [0..7]  ================================================== */
24727 typedef enum {                                  /*!< WDT_LOCK_LOCK                                                             */
24728   WDT_LOCK_LOCK_KEYVALUE               = 58,    /*!< KEYVALUE : This is the key value to write to WDTLOCK to lock
24729                                                      the WDT.                                                                  */
24730 } WDT_LOCK_LOCK_Enum;
24731 
24732 /* =========================================================  COUNT  ========================================================= */
24733 /* =========================================================  INTEN  ========================================================= */
24734 /* ========================================================  INTSTAT  ======================================================== */
24735 /* ========================================================  INTCLR  ========================================================= */
24736 /* ========================================================  INTSET  ========================================================= */
24737 
24738 /** @} */ /* End of group EnumValue_peripherals */
24739 
24740 
24741 #ifdef __cplusplus
24742 }
24743 #endif
24744 
24745 #endif /* APOLLO3_H */
24746 
24747 
24748 /** @} */ /* End of group apollo3 */
24749 
24750 /** @} */ /* End of group Ambiq Micro */
24751