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Searched refs:CQADDR (Results 1 – 13 of 13) sorted by relevance

/hal_ambiq-latest/mcu/apollo4p/hal/mcu/
Dam_hal_cmdq.c123 &IOM0->CQCFG, &IOM0->CQADDR,
131 &IOM1->CQCFG, &IOM1->CQADDR,
139 &IOM2->CQCFG, &IOM2->CQADDR,
147 &IOM3->CQCFG, &IOM3->CQADDR,
155 &IOM4->CQCFG, &IOM4->CQADDR,
163 &IOM5->CQCFG, &IOM5->CQADDR,
171 &IOM6->CQCFG, &IOM6->CQADDR,
179 &IOM7->CQCFG, &IOM7->CQADDR,
187 &MSPI0->CQCFG, &MSPI0->CQADDR,
195 &MSPI1->CQCFG, &MSPI1->CQADDR,
[all …]
Dam_hal_iom.c1051 uint32_t *pCqAddr = (uint32_t *)IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_CQEnable()
1054 *pCqAddr = (uint32_t) &IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_CQEnable()
2043 IOMn(pIOMState->ui32Module)->CQADDR = pIOMState->registerState.regCQADDR; in am_hal_iom_power_ctrl()
2085 pIOMState->registerState.regCQADDR = IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_power_ctrl()
Dam_hal_mspi.c3619 MSPIn(pMSPIState->ui32Module)->CQADDR = pMSPIState->registerState.regCQADDR; in am_hal_mspi_power_control()
3669 … pMSPIState->registerState.regCQADDR = MSPIn(pMSPIState->ui32Module)->CQADDR; in am_hal_mspi_power_control()
/hal_ambiq-latest/mcu/apollo3p/hal/
Dam_hal_cmdq.c121 &IOM0->CQCFG, &IOM0->CQADDR,
129 &IOM1->CQCFG, &IOM1->CQADDR,
137 &IOM2->CQCFG, &IOM2->CQADDR,
145 &IOM3->CQCFG, &IOM3->CQADDR,
153 &IOM4->CQCFG, &IOM4->CQADDR,
161 &IOM5->CQCFG, &IOM5->CQADDR,
169 &MSPI0->CQCFG, &MSPI0->CQADDR,
177 &MSPI1->CQCFG, &MSPI1->CQADDR,
185 &MSPI2->CQCFG, &MSPI2->CQADDR,
193 &BLEIF->CQCFG, &BLEIF->CQADDR,
Dam_hal_iom.c996 uint32_t *pCqAddr = (uint32_t *)IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_CQEnable()
999 *pCqAddr = (uint32_t) &IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_CQEnable()
1984 IOMn(pIOMState->ui32Module)->CQADDR = pIOMState->registerState.regCQADDR; in am_hal_iom_power_ctrl()
2025 pIOMState->registerState.regCQADDR = IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_power_ctrl()
Dam_hal_mspi.c3230 MSPIn(pMSPIState->ui32Module)->CQADDR = pMSPIState->registerState.regCQADDR; in am_hal_mspi_power_control()
3280 pMSPIState->registerState.regCQADDR = MSPIn(pMSPIState->ui32Module)->CQADDR; in am_hal_mspi_power_control()
/hal_ambiq-latest/mcu/apollo3/hal/
Dam_hal_cmdq.c121 &IOM0->CQCFG, &IOM0->CQADDR,
129 &IOM1->CQCFG, &IOM1->CQADDR,
137 &IOM2->CQCFG, &IOM2->CQADDR,
145 &IOM3->CQCFG, &IOM3->CQADDR,
153 &IOM4->CQCFG, &IOM4->CQADDR,
161 &IOM5->CQCFG, &IOM5->CQADDR,
169 &MSPI->CQCFG, &MSPI->CQADDR,
177 &BLEIF->CQCFG, &BLEIF->CQADDR,
Dam_hal_iom.c1011 uint32_t *pCqAddr = (uint32_t *)IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_CQEnable()
1014 *pCqAddr = (uint32_t) &IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_CQEnable()
2169 IOMn(pIOMState->ui32Module)->CQADDR = pIOMState->registerState.regCQADDR; in am_hal_iom_power_ctrl()
2210 pIOMState->registerState.regCQADDR = IOMn(pIOMState->ui32Module)->CQADDR; in am_hal_iom_power_ctrl()
Dam_hal_mspi.c3173 MSPIn(pMSPIState->ui32Module)->CQADDR = pMSPIState->registerState.regCQADDR; in am_hal_mspi_power_control()
3222 pMSPIState->registerState.regCQADDR = MSPIn(pMSPIState->ui32Module)->CQADDR; in am_hal_mspi_power_control()
/hal_ambiq-latest/CMSIS/AmbiqMicro/Include/
Dapollo3.h1379 …__IOM uint32_t CQADDR; /*!< (@ 0x0000024C) The SRAM address which will be fet… member
1391 …__IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source… member
5953 …__IOM uint32_t CQADDR; /*!< (@ 0x00000298) The SRAM address which will be fet… member
5965 …__IOM uint32_t CQADDR : 18; /*!< [19..2] Bits 19:2 of target byte address for source… member
7597 …__IOM uint32_t CQADDR; /*!< (@ 0x000002A8) Location of the command queue in S… member
7607 …__IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or … member
Dapollo3p.h1377 …__IOM uint32_t CQADDR; /*!< (@ 0x0000024C) The SRAM address which will be fet… member
1389 …__IOM uint32_t CQADDR : 19; /*!< [20..2] Bits 19:2 of target byte address for source… member
6661 …__IOM uint32_t CQADDR; /*!< (@ 0x00000298) The SRAM address which will be fet… member
6673 …__IOM uint32_t CQADDR : 19; /*!< [20..2] Bits 19:2 of target byte address for source… member
8502 …__IOM uint32_t CQADDR; /*!< (@ 0x000002A8) Location of the command queue in S… member
8512 …__IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or … member
Dapollo4b_generic.h17404 …__IOM uint32_t CQADDR; /*!< (@ 0x0000022C) The SRAM address which will be fet… member
17416 …__IOM uint32_t CQADDR : 27; /*!< [28..2] Bits 28:2 of target byte address for source… member
19662 …__IOM uint32_t CQADDR; /*!< (@ 0x000002A8) Location of the command queue in S… member
19672 …__IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or … member
Dapollo4p.h17503 …__IOM uint32_t CQADDR; /*!< (@ 0x0000022C) The SRAM address which will be fet… member
17515 …__IOM uint32_t CQADDR : 27; /*!< [28..2] Bits 28:2 of target byte address for source… member
19895 …__IOM uint32_t CQADDR; /*!< (@ 0x000002A8) Location of the command queue in S… member
19905 …__IOM uint32_t CQADDR : 29; /*!< [28..0] Address of command queue buffer in SRAM or … member