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Searched refs:CPU_CACHECFG_IENABLE_Pos (Results 1 – 3 of 3) sorted by relevance

/hal_ambiq-latest/mcu/apollo4p/hal/mcu/
Dam_hal_cachectrl.c179 ((psConfig->eMode << CPU_CACHECFG_IENABLE_Pos) & in am_hal_cachectrl_config()
/hal_ambiq-latest/CMSIS/AmbiqMicro/Include/
Dapollo4b_generic.h28136 #define CPU_CACHECFG_IENABLE_Pos (8UL) /*!< IENABLE (Bit 8) … macro
Dapollo4p.h28730 #define CPU_CACHECFG_IENABLE_Pos (8UL) /*!< IENABLE (Bit 8) … macro