Searched refs:CMDCMP (Results 1 – 10 of 10) sorted by relevance
1817 BLEIFn(ui32Module)->INTEN_b.CMDCMP = 0; in am_hal_ble_blocking_transfer()1819 BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; in am_hal_ble_blocking_transfer()1987 bCmdCmp = BLEIFn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_ble_blocking_transfer()2022 WHILE_TIMEOUT_MS_BREAK ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 2, in am_hal_ble_blocking_transfer()2043 WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 10, in am_hal_ble_blocking_transfer()2045 BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; in am_hal_ble_blocking_transfer()
2444 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_blocking_transfer()2518 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_blocking_transfer()2939 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_spi_blocking_fullduplex()
1924 BLEIFn(ui32Module)->INTEN_b.CMDCMP = 0; in am_hal_ble_blocking_transfer()1926 BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; in am_hal_ble_blocking_transfer()2094 bCmdCmp = BLEIFn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_ble_blocking_transfer()2129 WHILE_TIMEOUT_MS_BREAK ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 2, in am_hal_ble_blocking_transfer()2150 WHILE_TIMEOUT_MS ( BLEIFn(ui32Module)->INTSTAT_b.CMDCMP == 0, 10, in am_hal_ble_blocking_transfer()2152 BLEIFn(ui32Module)->INTCLR_b.CMDCMP = 1; in am_hal_ble_blocking_transfer()
2627 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_blocking_transfer()2701 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_blocking_transfer()3161 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_spi_blocking_fullduplex()
2863 while (!MSPIn(ui32Module)->INTSTAT_b.CMDCMP); in am_hal_mspi_interrupt_service()3052 while (!MSPIn(ui32Module)->INTSTAT_b.CMDCMP); in am_hal_mspi_interrupt_service()
2516 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_blocking_transfer()2590 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_blocking_transfer()2995 bCmdCmp = IOMn(ui32Module)->INTSTAT_b.CMDCMP; in am_hal_iom_spi_blocking_fullduplex()
975 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member1038 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member1102 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member1166 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member5471 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member5521 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member5572 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member5623 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member7373 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member7402 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member[all …]
977 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member1040 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member1104 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member1168 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member6190 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt … member6238 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt … member6287 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt … member6336 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command complete interrupt … member8256 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member8285 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member[all …]
17042 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member17096 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member17151 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member17206 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member19531 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member19560 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member19590 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member19620 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member
17157 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member17207 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member17258 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member17309 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Command Complete interrupt. Asserted when th… member19755 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member19786 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member19818 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member19850 …__IOM uint32_t CMDCMP : 1; /*!< [0..0] Transfer complete. Note that DMA and CQ oper… member
