1/* SPDX-License-Identifier: Apache-2.0 */
2
3#include <arm/armv7-m.dtsi>
4#include <mem.h>
5#include <freq.h>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/gpio/gpio.h>
8
9/ {
10	clocks {
11		uartclk: apb-pclk {
12			compatible = "fixed-clock";
13			clock-frequency = <DT_FREQ_M(24)>;
14			#clock-cells = <0>;
15		};
16		xo32m: xo32m {
17			compatible = "ambiq,clkctrl";
18			clock-frequency = <DT_FREQ_M(32)>;
19			#clock-cells = <1>;
20		};
21		xo32k: xo32k {
22			compatible = "ambiq,clkctrl";
23			clock-frequency = <DT_FREQ_K(32)>;
24			#clock-cells = <1>;
25		};
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			compatible = "arm,cortex-m4f";
34			reg = <0>;
35			#address-cells = <1>;
36			#size-cells = <1>;
37
38			itm: itm@e0000000 {
39				compatible = "arm,armv7m-itm";
40				reg = <0xe0000000 0x1000>;
41				swo-ref-frequency = <DT_FREQ_M(48)>;
42			};
43		};
44	};
45
46	/* TCM */
47	tcm: tcm@10000000 {
48		compatible = "zephyr,memory-region";
49		reg = <0x10000000 0x10000>;
50		zephyr,memory-region = "ITCM";
51	};
52
53	/* SRAM */
54	sram0: memory@10010000 {
55		compatible = "mmio-sram";
56		reg = <0x10010000 0x2B0000>;
57	};
58
59	soc {
60		compatible = "ambiq,apollo4p-blue", "ambiq,apollo4x", "simple-bus";
61
62		flash: flash-controller@18000 {
63			compatible = "ambiq,flash-controller";
64			reg = <0x00018000 0x1e8000>;
65
66			#address-cells = <1>;
67			#size-cells = <1>;
68
69			/* MRAM region */
70			flash0: flash@18000 {
71				compatible = "soc-nv-flash";
72				reg = <0x00018000 0x1e8000>;
73			};
74		};
75
76		pwrcfg: pwrcfg@40021000 {
77			compatible = "ambiq,pwrctrl";
78			reg = <0x40021000 0x400>;
79			#pwrcfg-cells = <2>;
80		};
81
82		stimer0: stimer@40008800 {
83			compatible = "ambiq,stimer";
84			reg = <0x40008800 0x80>;
85			interrupts = <32 0>;
86			status = "okay";
87		};
88
89		counter0: counter@40008200 {
90			compatible = "ambiq,counter";
91			reg = <0x40008200 0x20>;
92			interrupts = <67 0>;
93			clock-frequency = <DT_FREQ_M(6)>;
94			clk-source = <1>;
95			status = "disabled";
96		};
97
98		uart0: uart@4001c000 {
99			compatible = "ambiq,uart", "arm,pl011";
100			reg = <0x4001c000 0x1000>;
101			interrupts = <15 0>;
102			interrupt-names = "UART0";
103			status = "disabled";
104			clocks = <&uartclk>;
105			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
106		};
107		uart1: uart@4001d000 {
108			compatible = "ambiq,uart", "arm,pl011";
109			reg = <0x4001d000 0x1000>;
110			interrupts = <16 0>;
111			interrupt-names = "UART1";
112			status = "disabled";
113			clocks = <&uartclk>;
114			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
115		};
116
117		uart2: uart@4001e000 {
118			compatible = "ambiq,uart", "arm,pl011";
119			reg = <0x4001e000 0x1000>;
120			interrupts = <17 0>;
121			interrupt-names = "UART2";
122			status = "disabled";
123			clocks = <&uartclk>;
124			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
125		};
126
127		uart3: uart@4001f000 {
128			compatible = "ambiq,uart", "arm,pl011";
129			reg = <0x4001f000 0x1000>;
130			interrupts = <18 0>;
131			interrupt-names = "UART3";
132			status = "disabled";
133			clocks = <&uartclk>;
134			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
135		};
136
137		spi0: spi@40050000 {
138			compatible = "ambiq,spi";
139			reg = <0x40050000 0x1000>;
140			#address-cells = <1>;
141			#size-cells = <0>;
142			interrupts = <6 0>;
143			status = "disabled";
144			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
145		};
146
147		spi1: spi@40051000 {
148			compatible = "ambiq,spi";
149			reg = <0x40051000 0x1000>;
150			#address-cells = <1>;
151			#size-cells = <0>;
152			interrupts = <7 0>;
153			status = "disabled";
154			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
155		};
156
157		spi2: spi@40052000 {
158			compatible = "ambiq,spi";
159			reg = <0x40052000 0x1000>;
160			#address-cells = <1>;
161			#size-cells = <0>;
162			interrupts = <8 0>;
163			status = "disabled";
164			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
165		};
166
167		spi3: spi@40053000 {
168			compatible = "ambiq,spi";
169			reg = <0x40053000 0x1000>;
170			#address-cells = <1>;
171			#size-cells = <0>;
172			interrupts = <9 0>;
173			status = "disabled";
174			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
175		};
176
177		spi4: spi@40054000 {
178			/* IOM4 works as SPI and is wired internally for BLE HCI. */
179			compatible = "ambiq,spi";
180			reg = <0x40054000 0x1000>;
181			#address-cells = <1>;
182			#size-cells = <0>;
183			interrupts = <10 0>;
184			cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
185			clock-frequency = <DT_FREQ_M(24)>;
186			status = "disabled";
187			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
188
189			bt_hci_apollo: bt-hci@0 {
190				compatible = "ambiq,bt-hci-spi";
191				reg = <0>;
192				spi-max-frequency = <DT_FREQ_M(24)>;
193				irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>;
194				reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>;
195				clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>;
196			};
197		};
198
199		spi5: spi@40055000 {
200			compatible = "ambiq,spi";
201			reg = <0x40055000 0x1000>;
202			#address-cells = <1>;
203			#size-cells = <0>;
204			interrupts = <11 0>;
205			status = "disabled";
206			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
207		};
208
209		spi6: spi@40056000 {
210			compatible = "ambiq,spi";
211			reg = <0x40056000 0x1000>;
212			#address-cells = <1>;
213			#size-cells = <0>;
214			interrupts = <12 0>;
215			status = "disabled";
216			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
217		};
218
219		spi7: spi@40057000 {
220			compatible = "ambiq,spi";
221			reg = <0x40057000 0x1000>;
222			#address-cells = <1>;
223			#size-cells = <0>;
224			interrupts = <13 0>;
225			status = "disabled";
226			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
227		};
228
229		i2c0: i2c@40050000 {
230			compatible = "ambiq,i2c";
231			reg = <0x40050000 0x1000>;
232			#address-cells = <1>;
233			#size-cells = <0>;
234			interrupts = <6 0>;
235			status = "disabled";
236			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
237		};
238
239		i2c1: i2c@40051000 {
240			compatible = "ambiq,i2c";
241			reg = <0x40051000 0x1000>;
242			#address-cells = <1>;
243			#size-cells = <0>;
244			interrupts = <7 0>;
245			status = "disabled";
246			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
247		};
248
249		i2c2: i2c@40052000 {
250			compatible = "ambiq,i2c";
251			reg = <0x40052000 0x1000>;
252			#address-cells = <1>;
253			#size-cells = <0>;
254			interrupts = <8 0>;
255			status = "disabled";
256			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
257		};
258
259		i2c3: i2c@40053000 {
260			compatible = "ambiq,i2c";
261			reg = <0x40053000 0x1000>;
262			#address-cells = <1>;
263			#size-cells = <0>;
264			interrupts = <9 0>;
265			status = "disabled";
266			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
267		};
268
269		i2c4: i2c@40054000 {
270			compatible = "ambiq,i2c";
271			reg = <0x40054000 0x1000>;
272			#address-cells = <1>;
273			#size-cells = <0>;
274			interrupts = <10 0>;
275			status = "disabled";
276			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
277		};
278
279		i2c5: i2c@40055000 {
280			compatible = "ambiq,i2c";
281			reg = <0x40055000 0x1000>;
282			#address-cells = <1>;
283			#size-cells = <0>;
284			interrupts = <11 0>;
285			status = "disabled";
286			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
287		};
288
289		i2c6: i2c@40056000 {
290			compatible = "ambiq,i2c";
291			reg = <0x40056000 0x1000>;
292			#address-cells = <1>;
293			#size-cells = <0>;
294			interrupts = <12 0>;
295			status = "disabled";
296			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
297		};
298
299		i2c7: i2c@40057000 {
300			compatible = "ambiq,i2c";
301			reg = <0x40057000 0x1000>;
302			#address-cells = <1>;
303			#size-cells = <0>;
304			interrupts = <13 0>;
305			status = "disabled";
306			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
307		};
308
309		mspi0: spi@40060000 {
310			compatible = "ambiq,mspi";
311			reg = <0x40060000 0x400>;
312			interrupts = <20 0>;
313			#address-cells = <1>;
314			#size-cells = <0>;
315			status = "disabled";
316			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
317		};
318
319		mspi1: spi@40061000 {
320			compatible = "ambiq,mspi";
321			reg = <0x40061000 0x400>;
322			interrupts = <21 0>;
323			#address-cells = <1>;
324			#size-cells = <0>;
325			status = "disabled";
326			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
327		};
328
329		mspi2: spi@40062000 {
330			compatible = "ambiq,mspi";
331			reg = <0x40062000 0x400>;
332			interrupts = <22 0>;
333			#address-cells = <1>;
334			#size-cells = <0>;
335			status = "disabled";
336			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
337		};
338
339		usb: usb@400b0000 {
340			compatible = "ambiq,usb";
341			reg = <0x400B0000 0x4100>;
342			interrupts = <27 0>;
343			num-bidir-endpoints = <6>;
344			maximum-speed = "full-speed";
345			status = "disabled";
346			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
347		};
348
349		rtc0: rtc@40004800 {
350			compatible = "ambiq,rtc";
351			reg = <0x40004800 0x210>;
352			interrupts = <2 0>;
353			alarms-count = <1>;
354			status = "disabled";
355		};
356
357		pinctrl: pin-controller@40010000 {
358			compatible = "ambiq,apollo4-pinctrl";
359			reg = <0x40010000 0x800>;
360			#address-cells = <1>;
361			#size-cells = <0>;
362
363			gpio: gpio@40010000 {
364				compatible = "ambiq,gpio";
365				gpio-map-mask = <0xffffffe0 0xffffffc0>;
366				gpio-map-pass-thru = <0x1f 0x3f>;
367				gpio-map = <
368					0x00 0x0 &gpio0_31 0x0 0x0
369					0x20 0x0 &gpio32_63 0x0 0x0
370					0x40 0x0 &gpio64_95 0x0 0x0
371					0x60 0x0 &gpio96_127 0x0 0x0
372				>;
373				reg = <0x40010000>;
374				#gpio-cells = <2>;
375				#address-cells = <1>;
376				#size-cells = <0>;
377				ranges;
378
379				gpio0_31: gpio0_31@0 {
380					compatible = "ambiq,gpio-bank";
381					gpio-controller;
382					#gpio-cells = <2>;
383					reg = <0>;
384					interrupts = <56 0>;
385					status = "disabled";
386				};
387
388				gpio32_63: gpio32_63@80 {
389					compatible = "ambiq,gpio-bank";
390					gpio-controller;
391					#gpio-cells = <2>;
392					reg = <0x80>;
393					interrupts = <57 0>;
394					status = "disabled";
395				};
396
397				gpio64_95: gpio64_95@100 {
398					compatible = "ambiq,gpio-bank";
399					gpio-controller;
400					#gpio-cells = <2>;
401					reg = <0x100>;
402					interrupts = <58 0>;
403					status = "disabled";
404				};
405
406				gpio96_127: gpio96_127@180 {
407					compatible = "ambiq,gpio-bank";
408					gpio-controller;
409					#gpio-cells = <2>;
410					reg = <0x180>;
411					interrupts = <59 0>;
412					status = "disabled";
413				};
414			};
415		};
416
417		wdt0: watchdog@40024000 {
418			compatible = "ambiq,watchdog";
419			reg = <0x40024000 0x400>;
420			interrupts = <1 0>;
421			clock-frequency = <16>;
422			status = "disabled";
423		};
424
425	};
426};
427
428&nvic {
429	arm,num-irq-priority-bits = <3>;
430};
431