1 //*****************************************************************************
2 //
3 //! @file am_hal_gpio.h
4 //!
5 //! @brief General Purpose Input Output Functionality
6 //!
7 //! @addtogroup gpio_4p GPIO - General Purpose Input Output
8 //! @ingroup apollo4p_hal
9 //! @{
10 //
11 //*****************************************************************************
12 
13 //*****************************************************************************
14 //
15 // Copyright (c) 2023, Ambiq Micro, Inc.
16 // All rights reserved.
17 //
18 // Redistribution and use in source and binary forms, with or without
19 // modification, are permitted provided that the following conditions are met:
20 //
21 // 1. Redistributions of source code must retain the above copyright notice,
22 // this list of conditions and the following disclaimer.
23 //
24 // 2. Redistributions in binary form must reproduce the above copyright
25 // notice, this list of conditions and the following disclaimer in the
26 // documentation and/or other materials provided with the distribution.
27 //
28 // 3. Neither the name of the copyright holder nor the names of its
29 // contributors may be used to endorse or promote products derived from this
30 // software without specific prior written permission.
31 //
32 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
36 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 // POSSIBILITY OF SUCH DAMAGE.
43 //
44 // This is part of revision release_sdk_4_4_0-3c5977e664 of the AmbiqSuite Development Package.
45 //
46 //*****************************************************************************
47 #ifndef AM_HAL_GPIO_H
48 #define AM_HAL_GPIO_H
49 
50 #ifdef __cplusplus
51 extern "C"
52 {
53 #endif
54 
55 //
56 //! Maximum number of GPIOs on this device.
57 //
58 #define AM_HAL_GPIO_MAX_PADS        AM_HAL_PIN_TOTAL_GPIOS
59 #define AM_HAL_GPIO_NUMWORDS        ((AM_HAL_GPIO_MAX_PADS + 31) / 32)
60 
61 //*****************************************************************************
62 //
63 // Macros
64 //
65 //*****************************************************************************
66 
67 //*****************************************************************************
68 //
69 //! @name Compute some relative offsets needed in the HAL.
70 //! GPIO_INTX_DELTA:   The number of bytes between successive interrupt registers
71 //!                    (i.e. INTEN0, INTEN1, INTEN2, ...).
72 //! GPIO_NXINT_DELTA:  The number of bytes between MCUN0INTxx and MCUN1INTxx regs.
73 //! @{
74 //
75 //*****************************************************************************
76 #define GPIO_INTX_DELTA         (offsetof(GPIO_Type, MCUN0INT1EN)   - offsetof(GPIO_Type, MCUN0INT0EN))
77 #define GPIO_NXINT_DELTA        (offsetof(GPIO_Type, MCUN1INT0EN)   - offsetof(GPIO_Type, MCUN0INT0EN))
78 //! @}
79 
80 //*****************************************************************************
81 //
82 //! @name The interrupt register order is: EN, STAT, CLR, SET.
83 //! GPIO_INTCLR_DELTA:  The number of bytes between EN and CLR registers.
84 //! GPIO_INTSTAT_DELTA: The number of bytes between EN and STAT registers.
85 //! GPIO_INTSET_DELTA: The number of bytes between EN and SET registers.
86 //! @{
87 //
88 //*****************************************************************************
89 #define GPIO_INTSTAT_DELTA      (offsetof(GPIO_Type, MCUN1INT0STAT) - offsetof(GPIO_Type, MCUN0INT0EN))
90 #define GPIO_INTCLR_DELTA       (offsetof(GPIO_Type, MCUN1INT0CLR)  - offsetof(GPIO_Type, MCUN0INT0EN))
91 #define GPIO_INTSET_DELTA       (offsetof(GPIO_Type, MCUN1INT0SET)  - offsetof(GPIO_Type, MCUN0INT0EN))
92 //! @}
93 
94 //*****************************************************************************
95 //
96 //! @name Other GPIO helper macros.
97 //! GPIO_IRQ2N()     Given an IRQ, determine N (0 or 1).
98 //! GPIO_IRQ2IDX()   Given a GPIO number, determine the interrupt reg index
99 //!                  relative to N (0-3).
100 //! GPIO_NUM2IDX()   Given a GPIO number, compute the 32-bit index
101 //!                  (e.g. 31=0, 32=1, 63=1, 64=2)
102 //! GPIO_NUM2MSK()   Given a GPIO number, determine the interrupt mask for
103 //!                  that bit.
104 //! GPIO_NUM_IRQS    The total number of GPIO IRQs.
105 //! @{
106 //
107 //*****************************************************************************
108 #define GPIO_IRQ2N(irq)     ( (irq - GPIO0_001F_IRQn) / (GPIO0_607F_IRQn - GPIO0_001F_IRQn + 1) )
109 #define GPIO_IRQ2IDX(irq)   ( (irq - GPIO0_001F_IRQn) % (GPIO0_607F_IRQn - GPIO0_001F_IRQn + 1) )
110 #define GPIO_NUM2IDX(num)   ( num / 32 )
111 #define GPIO_NUM2MSK(num)   ( 1 << (num & 0x1F) )
112 
113 #define GPIO_NUM_IRQS       (GPIO1_607F_IRQn - GPIO0_001F_IRQn + 1)
114 //! @}
115 
116 //*****************************************************************************
117 //
118 // Global definitions
119 //
120 //*****************************************************************************
121 
122 //*****************************************************************************
123 //
124 //! GPIO Interrupt Channels
125 //! The GPIO module generates interrupts through two "channels". l
126 //
127 //*****************************************************************************
128 typedef enum
129 {
130     AM_HAL_GPIO_INT_CHANNEL_0,
131     AM_HAL_GPIO_INT_CHANNEL_1,
132     AM_HAL_GPIO_INT_CHANNEL_BOTH
133 } am_hal_gpio_int_channel_e;
134 
135 //*****************************************************************************
136 //
137 //! GPIO Interrupt Control definitions.
138 //! These include Enable, Disable, and Clear functions.
139 //
140 //*****************************************************************************
141 typedef enum
142 {
143     //
144     // GPIO Interrupt Enable controls
145     //
146     AM_HAL_GPIO_INT_CTRL_INDV_DISABLE,
147     AM_HAL_GPIO_INT_CTRL_INDV_ENABLE,
148     AM_HAL_GPIO_INT_CTRL_MASK_DISABLE,
149     AM_HAL_GPIO_INT_CTRL_MASK_ENABLE,
150     AM_HAL_GPIO_INT_CTRL_LAST = AM_HAL_GPIO_INT_CTRL_MASK_ENABLE
151 } am_hal_gpio_int_ctrl_e;
152 
153 //*****************************************************************************
154 //
155 //! Pin configuration
156 //
157 //*****************************************************************************
158 typedef enum
159 {
160     AM_HAL_GPIO_PIN_FUNCTION_DOES_NOT_EXIST = AM_HAL_STATUS_MODULE_SPECIFIC_START,
161 } am_hal_gpio_status_e;
162 
163 //
164 //! Configuration structure for GPIOs.
165 //
166 typedef struct
167 {
168     union
169     {
170         volatile uint32_t cfg;
171 
172         struct
173         {
174             uint32_t uFuncSel        : 4;   // [3:0]
175             uint32_t eGPInput        : 1;   // [4:4]
176             uint32_t eGPRdZero       : 1;   // [5:5]
177             uint32_t eIntDir         : 2;   // [7:6]
178             uint32_t eGPOutCfg       : 2;   // [9:8]
179             uint32_t eDriveStrength  : 2;   // [11:10]
180             uint32_t uSlewRate       : 1;   // [12:12]
181             uint32_t ePullup         : 3;   // [15:13]
182             uint32_t uNCE            : 6;   // [21:16]
183             uint32_t eCEpol          : 1;   // [22:22]
184             uint32_t uRsvd_0         : 2;   // [24:23]
185             uint32_t ePowerSw        : 1;   // [25:25]  // Select pads only, otherwise reserved
186             uint32_t eForceInputEn   : 1;   // [26:26]
187             uint32_t eForceOutputEn  : 1;   // [27:27]
188             uint32_t uRsvd_1         : 4;   // [31:28]
189         } cfg_b;
190     } GP;
191 } am_hal_gpio_pincfg_t;
192 
193 //
194 //! Drive strengths.
195 // Designated as relative full-driver strength.
196 // All physical (non-virtual) pads support 0P1X and 0P5X.
197 // Only select pads support OP75X and 1P0X.
198 //
199 typedef enum
200 {
201     AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X  = 0x0,  // 0.1x  output driver selected
202     AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P5X  = 0x1,  // 0.5x  output driver selected
203     AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P75X = 0x2,  // 0.75x output driver selected
204     AM_HAL_GPIO_PIN_DRIVESTRENGTH_1P0X  = 0x3   // 1.0x  output driver selected
205 } am_hal_gpio_drivestrength_e;
206 
207 //
208 // Deprecated. Please use the above enums instead.
209 //
210 #define AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA  AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X
211 #define AM_HAL_GPIO_PIN_DRIVESTRENGTH_16MA  AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P5X
212 
213 //
214 //! Power switch configuration.
215 //
216 typedef enum
217 {
218     AM_HAL_GPIO_PIN_POWERSW_NONE,
219     AM_HAL_GPIO_PIN_POWERSW_VDD,
220     AM_HAL_GPIO_PIN_POWERSW_VSS,
221     AM_HAL_GPIO_PIN_POWERSW_INVALID,
222 } am_hal_gpio_powersw_e;
223 
224 //
225 //! Pull-up values.
226 //
227 typedef enum
228 {
229     AM_HAL_GPIO_PIN_PULLUP_NONE         = 0x00,
230     AM_HAL_GPIO_PIN_PULLDOWN_50K,
231     AM_HAL_GPIO_PIN_PULLUP_1_5K,
232     AM_HAL_GPIO_PIN_PULLUP_6K,
233     AM_HAL_GPIO_PIN_PULLUP_12K,
234     AM_HAL_GPIO_PIN_PULLUP_24K,
235     AM_HAL_GPIO_PIN_PULLUP_50K,
236     AM_HAL_GPIO_PIN_PULLUP_100K,    // Weak pullup
237 } am_hal_gpio_pullup_e;
238 
239 //
240 //! GPIO Input configuration.
241 //
242 typedef enum
243 {
244     AM_HAL_GPIO_PIN_INPUT_AUTO          = 0x0,
245     AM_HAL_GPIO_PIN_INPUT_NONE          = 0x0,
246     AM_HAL_GPIO_PIN_INPUT_ENABLE        = 0x1
247 } am_hal_gpio_input_e;
248 
249 //
250 //! Output configurations.
251 //
252 typedef enum
253 {
254     AM_HAL_GPIO_PIN_OUTCFG_DISABLE     = 0x0,
255     AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL    = 0x1,
256     AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN   = 0x2,
257     AM_HAL_GPIO_PIN_OUTCFG_TRISTATE    = 0x3
258 } am_hal_gpio_outcfg_e;
259 
260 //
261 //! GPIO "read zero" configuration.
262 //
263 typedef enum
264 {
265     AM_HAL_GPIO_PIN_RDZERO_READPIN      = 0x0,
266     AM_HAL_GPIO_PIN_RDZERO_ZERO         = 0x1
267 } am_hal_gpio_readen_e;
268 
269 //
270 //! GPIO interrupt configuration.
271 //
272 typedef enum
273 {
274     AM_HAL_GPIO_PIN_INTDIR_NONE         = 0x0,
275     AM_HAL_GPIO_PIN_INTDIR_HI2LO        = 0x1,
276     AM_HAL_GPIO_PIN_INTDIR_LO2HI        = 0x2,
277     AM_HAL_GPIO_PIN_INTDIR_BOTH         = 0x3
278 } am_hal_gpio_intdir_e;
279 
280 //
281 //! GPIO NCE module selection.
282 //
283 typedef enum
284 {
285     AM_HAL_GPIO_NCE_IOM0CE0    =  GPIO_PINCFG0_NCESRC0_IOM0CE0,         // IOM 0 NCE 0 module
286     AM_HAL_GPIO_NCE_IOM0CE1    =  GPIO_PINCFG0_NCESRC0_IOM0CE1,         // IOM 0 NCE 1 module
287     AM_HAL_GPIO_NCE_IOM0CE2    =  GPIO_PINCFG0_NCESRC0_IOM0CE2,         // IOM 0 NCE 2 module
288     AM_HAL_GPIO_NCE_IOM0CE3    =  GPIO_PINCFG0_NCESRC0_IOM0CE3,         // IOM 0 NCE 3 module
289     AM_HAL_GPIO_NCE_IOM1CE0    =  GPIO_PINCFG0_NCESRC0_IOM1CE0,         // IOM 1 NCE 0 module
290     AM_HAL_GPIO_NCE_IOM1CE1    =  GPIO_PINCFG0_NCESRC0_IOM1CE1,         // IOM 1 NCE 1 module
291     AM_HAL_GPIO_NCE_IOM1CE2    =  GPIO_PINCFG0_NCESRC0_IOM1CE2,         // IOM 1 NCE 2 module
292     AM_HAL_GPIO_NCE_IOM1CE3    =  GPIO_PINCFG0_NCESRC0_IOM1CE3,         // IOM 1 NCE 3 module
293     AM_HAL_GPIO_NCE_IOM2CE0    =  GPIO_PINCFG0_NCESRC0_IOM2CE0,         // IOM 2 NCE 0 module
294     AM_HAL_GPIO_NCE_IOM2CE1    =  GPIO_PINCFG0_NCESRC0_IOM2CE1,         // IOM 2 NCE 1 module
295     AM_HAL_GPIO_NCE_IOM2CE2    =  GPIO_PINCFG0_NCESRC0_IOM2CE2,         // IOM 2 NCE 2 module
296     AM_HAL_GPIO_NCE_IOM2CE3    =  GPIO_PINCFG0_NCESRC0_IOM2CE3,         // IOM 2 NCE 3 module
297     AM_HAL_GPIO_NCE_IOM3CE0    =  GPIO_PINCFG0_NCESRC0_IOM3CE0,         // IOM 3 NCE 0 module
298     AM_HAL_GPIO_NCE_IOM3CE1    =  GPIO_PINCFG0_NCESRC0_IOM3CE1,         // IOM 3 NCE 1 module
299     AM_HAL_GPIO_NCE_IOM3CE2    =  GPIO_PINCFG0_NCESRC0_IOM3CE2,         // IOM 3 NCE 2 module
300     AM_HAL_GPIO_NCE_IOM3CE3    =  GPIO_PINCFG0_NCESRC0_IOM3CE3,         // IOM 3 NCE 3 module
301     AM_HAL_GPIO_NCE_IOM4CE0    =  GPIO_PINCFG0_NCESRC0_IOM4CE0,         // IOM 4 NCE 0 module
302     AM_HAL_GPIO_NCE_IOM4CE1    =  GPIO_PINCFG0_NCESRC0_IOM4CE1,         // IOM 4 NCE 1 module
303     AM_HAL_GPIO_NCE_IOM4CE2    =  GPIO_PINCFG0_NCESRC0_IOM4CE2,         // IOM 4 NCE 2 module
304     AM_HAL_GPIO_NCE_IOM4CE3    =  GPIO_PINCFG0_NCESRC0_IOM4CE3,         // IOM 4 NCE 3 module
305     AM_HAL_GPIO_NCE_IOM5CE0    =  GPIO_PINCFG0_NCESRC0_IOM5CE0,         // IOM 5 NCE 0 module
306     AM_HAL_GPIO_NCE_IOM5CE1    =  GPIO_PINCFG0_NCESRC0_IOM5CE1,         // IOM 5 NCE 1 module
307     AM_HAL_GPIO_NCE_IOM5CE2    =  GPIO_PINCFG0_NCESRC0_IOM5CE2,         // IOM 5 NCE 2 module
308     AM_HAL_GPIO_NCE_IOM5CE3    =  GPIO_PINCFG0_NCESRC0_IOM5CE3,         // IOM 5 NCE 3 module
309     AM_HAL_GPIO_NCE_IOM6CE0    =  GPIO_PINCFG0_NCESRC0_IOM6CE0,         // IOM 6 NCE 0 module
310     AM_HAL_GPIO_NCE_IOM6CE1    =  GPIO_PINCFG0_NCESRC0_IOM6CE1,         // IOM 6 NCE 1 module
311     AM_HAL_GPIO_NCE_IOM6CE2    =  GPIO_PINCFG0_NCESRC0_IOM6CE2,         // IOM 6 NCE 2 module
312     AM_HAL_GPIO_NCE_IOM6CE3    =  GPIO_PINCFG0_NCESRC0_IOM6CE3,         // IOM 6 NCE 3 module
313     AM_HAL_GPIO_NCE_IOM7CE0    =  GPIO_PINCFG0_NCESRC0_IOM7CE0,         // IOM 7 NCE 0 module
314     AM_HAL_GPIO_NCE_IOM7CE1    =  GPIO_PINCFG0_NCESRC0_IOM7CE1,         // IOM 7 NCE 1 module
315     AM_HAL_GPIO_NCE_IOM7CE2    =  GPIO_PINCFG0_NCESRC0_IOM7CE2,         // IOM 7 NCE 2 module
316     AM_HAL_GPIO_NCE_IOM7CE3    =  GPIO_PINCFG0_NCESRC0_IOM7CE3,         // IOM 7 NCE 3 module
317     AM_HAL_GPIO_NCE_MSPI0CEN0  =  GPIO_PINCFG0_NCESRC0_MSPI0CEN0,       // MSPI 0 NCE 0 module
318     AM_HAL_GPIO_NCE_MSPI0CEN1  =  GPIO_PINCFG0_NCESRC0_MSPI0CEN1,       // MSPI 0 NCE 1 module
319     AM_HAL_GPIO_NCE_MSPI1CEN0  =  GPIO_PINCFG0_NCESRC0_MSPI1CEN0,       // MSPI 1 NCE 0 module
320     AM_HAL_GPIO_NCE_MSPI1CEN1  =  GPIO_PINCFG0_NCESRC0_MSPI1CEN1,       // MSPI 1 NCE 1 module
321     AM_HAL_GPIO_NCE_MSPI2CEN0  =  GPIO_PINCFG0_NCESRC0_MSPI2CEN0,       // MSPI 2 NCE 0 module
322     AM_HAL_GPIO_NCE_MSPI2CEN1  =  GPIO_PINCFG0_NCESRC0_MSPI2CEN1,       // MSPI 2 NCE 1 module
323     AM_HAL_GPIO_NCE_DCDPIDE    =  GPIO_PINCFG0_NCESRC0_DC_DPI_DE,       // DC DPI DE module
324     AM_HAL_GPIO_NCE_DCCSX      =  GPIO_PINCFG0_NCESRC0_DISP_CONT_CSX,   // DC CSX module
325     AM_HAL_GPIO_NCE_DCSPICSN   =  GPIO_PINCFG0_NCESRC0_DC_SPI_CS_N,     // DC SPI CS_N module
326     AM_HAL_GPIO_NCE_QSPICSN    =  GPIO_PINCFG0_NCESRC0_DC_QSPI_CS_N,    // DC QSPI CS_N module
327 } am_hal_gpio_nce_sel_e;
328 
329 //
330 //! GPIO NCE polarity.
331 //
332 typedef enum
333 {
334     AM_HAL_GPIO_PIN_CEPOL_ACTIVELOW     = 0x0,
335     AM_HAL_GPIO_PIN_CEPOL_ACTIVEHIGH    = 0x1
336 } am_hal_gpio_cepol_e;
337 
338 //
339 //! Force output or input enable.
340 //
341 typedef enum
342 {
343     AM_HAL_GPIO_PIN_FORCEEN_NONE       = 0x0,
344     AM_HAL_GPIO_PIN_FORCEEN_FORCE      = 0x1
345 } am_hal_gpio_forceen_e;
346 
347 //*****************************************************************************
348 //
349 //! Read types for am_hal_gpio_state_read().
350 //
351 //*****************************************************************************
352 typedef enum
353 {
354     AM_HAL_GPIO_INPUT_READ,
355     AM_HAL_GPIO_OUTPUT_READ,
356     AM_HAL_GPIO_ENABLE_READ
357 } am_hal_gpio_read_type_e;
358 
359 //*****************************************************************************
360 //
361 //! Write types for am_hal_gpio_state_write().
362 //!
363 //! It's important to note that types:
364 //! AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_EN and AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_DIS
365 //! operate on the output enable of the pin.
366 //! Therefore
367 //!     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_EN enables the output,
368 //!     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_DIS puts the pin into hi-impedance.
369 //!
370 //! Given this behavior, perhaps more appropriate names might have been:
371 //!     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUTEN
372 //!     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUTDIS
373 //
374 //*****************************************************************************
375 typedef enum
376 {
377     AM_HAL_GPIO_OUTPUT_CLEAR,
378     AM_HAL_GPIO_OUTPUT_SET,
379     AM_HAL_GPIO_OUTPUT_TOGGLE,
380     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_DIS,    // Disable output, i.e. Hi-Z
381     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_EN,     // Enable output
382     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_TOG
383 } am_hal_gpio_write_type_e;
384 
385 //*****************************************************************************
386 //
387 // These enums have been deprecated due to improper naming conventions.
388 //
389 //*****************************************************************************
390 #define AM_HAL_GPIO_OUTPUT_TRISTATE_DISABLE    AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_DIS
391 #define AM_HAL_GPIO_OUTPUT_TRISTATE_ENABLE     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_EN
392 #define AM_HAL_GPIO_OUTPUT_TRISTATE_TOGGLE     AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_TOG
393 
394 //
395 //! The handler type includes a void* parameter.
396 //
397 typedef void (*am_hal_gpio_handler_t)(void *pArg);
398 
399 //*****************************************************************************
400 //
401 //!
402 //! @name Common configurations.
403 //! @{
404 //
405 //*****************************************************************************
406 #define AM_HAL_GPIO_PINCFG_DEFAULT                                            \
407     {                                                                         \
408         .GP.cfg_b.uFuncSel         = 3,                                       \
409         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_DISABLE,          \
410         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
411         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
412         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_NONE,              \
413         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
414         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_NONE,             \
415         .GP.cfg_b.uSlewRate        = 0,                                       \
416         .GP.cfg_b.uNCE             = 0,                                       \
417         .GP.cfg_b.eCEpol           = 0,                                       \
418         .GP.cfg_b.ePowerSw         = 0,                                       \
419         .GP.cfg_b.eForceInputEn    = 0,                                       \
420         .GP.cfg_b.eForceOutputEn   = 0,                                       \
421         .GP.cfg_b.uRsvd_0          = 0,                                       \
422         .GP.cfg_b.uRsvd_1          = 0,                                       \
423     }
424 
425 #define AM_HAL_GPIO_PINCFG_OUTPUT                                             \
426     {                                                                         \
427         .GP.cfg_b.uFuncSel         = 3,                                       \
428         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,         \
429         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
430         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
431         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_NONE,              \
432         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
433         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_LO2HI,            \
434         .GP.cfg_b.uSlewRate        = 0,                                       \
435         .GP.cfg_b.uNCE             = 0,                                       \
436         .GP.cfg_b.eCEpol           = 0,                                       \
437         .GP.cfg_b.ePowerSw         = 0,                                       \
438         .GP.cfg_b.eForceInputEn    = 0,                                       \
439         .GP.cfg_b.eForceOutputEn   = 0,                                       \
440         .GP.cfg_b.uRsvd_0          = 0,                                       \
441         .GP.cfg_b.uRsvd_1          = 0,                                       \
442     }
443 
444 #define AM_HAL_GPIO_PINCFG_OUTPUT_WITH_READ                                   \
445     {                                                                         \
446         .GP.cfg_b.uFuncSel         = 3,                                       \
447         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL,         \
448         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
449         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
450         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_ENABLE,            \
451         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
452         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_LO2HI,            \
453         .GP.cfg_b.uSlewRate        = 0,                                       \
454         .GP.cfg_b.uNCE             = 0,                                       \
455         .GP.cfg_b.eCEpol           = 0,                                       \
456         .GP.cfg_b.ePowerSw         = 0,                                       \
457         .GP.cfg_b.eForceInputEn    = 0,                                       \
458         .GP.cfg_b.eForceOutputEn   = 0,                                       \
459         .GP.cfg_b.uRsvd_0          = 0,                                       \
460         .GP.cfg_b.uRsvd_1          = 0,                                       \
461     }
462 
463 #define AM_HAL_GPIO_PINCFG_INPUT                                              \
464     {                                                                         \
465         .GP.cfg_b.uFuncSel         = 3,                                       \
466         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_DISABLE,          \
467         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
468         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
469         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_ENABLE,            \
470         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
471         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_LO2HI,            \
472         .GP.cfg_b.uSlewRate        = 0,                                       \
473         .GP.cfg_b.uNCE             = 0,                                       \
474         .GP.cfg_b.eCEpol           = 0,                                       \
475         .GP.cfg_b.ePowerSw         = 0,                                       \
476         .GP.cfg_b.eForceInputEn    = 0,                                       \
477         .GP.cfg_b.eForceOutputEn   = 0,                                       \
478         .GP.cfg_b.uRsvd_0          = 0,                                       \
479         .GP.cfg_b.uRsvd_1          = 0,                                       \
480     }
481 
482 #define AM_HAL_GPIO_PINCFG_TRISTATE                                           \
483     {                                                                         \
484         .GP.cfg_b.uFuncSel         = 3,                                       \
485         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_TRISTATE,         \
486         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
487         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
488         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_NONE,              \
489         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
490         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_LO2HI,            \
491         .GP.cfg_b.uSlewRate        = 0,                                       \
492         .GP.cfg_b.uNCE             = 0,                                       \
493         .GP.cfg_b.eCEpol           = 0,                                       \
494         .GP.cfg_b.ePowerSw         = 0,                                       \
495         .GP.cfg_b.eForceInputEn    = 0,                                       \
496         .GP.cfg_b.eForceOutputEn   = 0,                                       \
497         .GP.cfg_b.uRsvd_0          = 0,                                       \
498         .GP.cfg_b.uRsvd_1          = 0,                                       \
499     }
500 
501 #define AM_HAL_GPIO_PINCFG_OPENDRAIN                                          \
502     {                                                                         \
503         .GP.cfg_b.uFuncSel         = 3,                                       \
504         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN,        \
505         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
506         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
507         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_NONE,              \
508         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
509         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_LO2HI,            \
510         .GP.cfg_b.uSlewRate        = 0,                                       \
511         .GP.cfg_b.uNCE             = 0,                                       \
512         .GP.cfg_b.eCEpol           = 0,                                       \
513         .GP.cfg_b.ePowerSw         = 0,                                       \
514         .GP.cfg_b.eForceInputEn    = 0,                                       \
515         .GP.cfg_b.eForceOutputEn   = 0,                                       \
516         .GP.cfg_b.uRsvd_0          = 0,                                       \
517         .GP.cfg_b.uRsvd_1          = 0,                                       \
518     }
519 
520 #define AM_HAL_GPIO_PINCFG_DISABLED                                           \
521     {                                                                         \
522         .GP.cfg_b.uFuncSel         = 3,                                       \
523         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_DISABLE,          \
524         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_0P1X,      \
525         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_NONE,             \
526         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_NONE,              \
527         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
528         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_NONE,             \
529         .GP.cfg_b.uSlewRate        = 0,                                       \
530         .GP.cfg_b.uNCE             = 0,                                       \
531         .GP.cfg_b.eCEpol           = 0,                                       \
532         .GP.cfg_b.ePowerSw         = 0,                                       \
533         .GP.cfg_b.eForceInputEn    = 0,                                       \
534         .GP.cfg_b.eForceOutputEn   = 0,                                       \
535         .GP.cfg_b.uRsvd_0          = 0,                                       \
536         .GP.cfg_b.uRsvd_1          = 0,                                       \
537     }
538 
539 #define AM_HAL_GPIO_PINCFG_PULLEDUP_DISABLED                                  \
540     {                                                                         \
541         .GP.cfg_b.uFuncSel         = 3,                                       \
542         .GP.cfg_b.eGPOutCfg        = AM_HAL_GPIO_PIN_OUTCFG_DISABLE,          \
543         .GP.cfg_b.eDriveStrength   = AM_HAL_GPIO_PIN_DRIVESTRENGTH_12MA,      \
544         .GP.cfg_b.ePullup          = AM_HAL_GPIO_PIN_PULLUP_100K,             \
545         .GP.cfg_b.eGPInput         = AM_HAL_GPIO_PIN_INPUT_NONE,              \
546         .GP.cfg_b.eGPRdZero        = AM_HAL_GPIO_PIN_RDZERO_READPIN,          \
547         .GP.cfg_b.eIntDir          = AM_HAL_GPIO_PIN_INTDIR_LO2HI,            \
548         .GP.cfg_b.uSlewRate        = 0,                                       \
549         .GP.cfg_b.uNCE             = 0,                                       \
550         .GP.cfg_b.eCEpol           = 0,                                       \
551         .GP.cfg_b.ePowerSw         = 0,                                       \
552         .GP.cfg_b.eForceInputEn    = 0,                                       \
553         .GP.cfg_b.eForceOutputEn   = 0,                                       \
554         .GP.cfg_b.uRsvd_0          = 0,                                       \
555         .GP.cfg_b.uRsvd_1          = 0,                                       \
556     }
557 //! @}
558 
559 //*****************************************************************************
560 //
561 //! @name Structures where default configurations can be accessed.
562 //! @{
563 //
564 //*****************************************************************************
565 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_default;
566 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_disabled;
567 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_pulledup_disabled;
568 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_output;
569 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_output_with_read;
570 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_input;
571 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_tristate;
572 extern const am_hal_gpio_pincfg_t am_hal_gpio_pincfg_opendrain;
573 //! @}
574 
575 //*****************************************************************************
576 //
577 //! Structure for defining bitmasks used in the interrupt functions.
578 //
579 //*****************************************************************************
580 typedef struct
581 {
582     union
583     {
584         volatile uint32_t Msk[AM_HAL_GPIO_NUMWORDS];
585 
586         struct
587         {
588             volatile uint32_t b0 :   1;
589             volatile uint32_t b1 :   1;
590             volatile uint32_t b2 :   1;
591             volatile uint32_t b3 :   1;
592             volatile uint32_t b4 :   1;
593             volatile uint32_t b5 :   1;
594             volatile uint32_t b6 :   1;
595             volatile uint32_t b7 :   1;
596             volatile uint32_t b8 :   1;
597             volatile uint32_t b9 :   1;
598             volatile uint32_t b10 :  1;
599             volatile uint32_t b11 :  1;
600             volatile uint32_t b12 :  1;
601             volatile uint32_t b13 :  1;
602             volatile uint32_t b14 :  1;
603             volatile uint32_t b15 :  1;
604             volatile uint32_t b16 :  1;
605             volatile uint32_t b17 :  1;
606             volatile uint32_t b18 :  1;
607             volatile uint32_t b19 :  1;
608             volatile uint32_t b20 :  1;
609             volatile uint32_t b21 :  1;
610             volatile uint32_t b22 :  1;
611             volatile uint32_t b23 :  1;
612             volatile uint32_t b24 :  1;
613             volatile uint32_t b25 :  1;
614             volatile uint32_t b26 :  1;
615             volatile uint32_t b27 :  1;
616             volatile uint32_t b28 :  1;
617             volatile uint32_t b29 :  1;
618             volatile uint32_t b30 :  1;
619             volatile uint32_t b31 :  1;
620             volatile uint32_t b32 :  1;
621             volatile uint32_t b33 :  1;
622             volatile uint32_t b34 :  1;
623             volatile uint32_t b35 :  1;
624             volatile uint32_t b36 :  1;
625             volatile uint32_t b37 :  1;
626             volatile uint32_t b38 :  1;
627             volatile uint32_t b39 :  1;
628             volatile uint32_t b40 :  1;
629             volatile uint32_t b41 :  1;
630             volatile uint32_t b42 :  1;
631             volatile uint32_t b43 :  1;
632             volatile uint32_t b44 :  1;
633             volatile uint32_t b45 :  1;
634             volatile uint32_t b46 :  1;
635             volatile uint32_t b47 :  1;
636             volatile uint32_t b48 :  1;
637             volatile uint32_t b49 :  1;
638             volatile uint32_t b50 :  1;
639             volatile uint32_t b51 :  1;
640             volatile uint32_t b52 :  1;
641             volatile uint32_t b53 :  1;
642             volatile uint32_t b54 :  1;
643             volatile uint32_t b55 :  1;
644             volatile uint32_t b56 :  1;
645             volatile uint32_t b57 :  1;
646             volatile uint32_t b58 :  1;
647             volatile uint32_t b59 :  1;
648             volatile uint32_t b60 :  1;
649             volatile uint32_t b61 :  1;
650             volatile uint32_t b62 :  1;
651             volatile uint32_t b63 :  1;
652             volatile uint32_t b64 :  1;
653             volatile uint32_t b65 :  1;
654             volatile uint32_t b66 :  1;
655             volatile uint32_t b67 :  1;
656             volatile uint32_t b68 :  1;
657             volatile uint32_t b69 :  1;
658             volatile uint32_t b70 :  1;
659             volatile uint32_t b71 :  1;
660             volatile uint32_t b72 :  1;
661             volatile uint32_t b73 :  1;
662             volatile uint32_t b74 :  1;
663             volatile uint32_t b75 :  1;
664             volatile uint32_t b76 :  1;
665             volatile uint32_t b77 :  1;
666             volatile uint32_t b78 :  1;
667             volatile uint32_t b79 :  1;
668             volatile uint32_t b80 :  1;
669             volatile uint32_t b81 :  1;
670             volatile uint32_t b82 :  1;
671             volatile uint32_t b83 :  1;
672             volatile uint32_t b84 :  1;
673             volatile uint32_t b85 :  1;
674             volatile uint32_t b86 :  1;
675             volatile uint32_t b87 :  1;
676             volatile uint32_t b88 :  1;
677             volatile uint32_t b89 :  1;
678             volatile uint32_t b90 :  1;
679             volatile uint32_t b91 :  1;
680             volatile uint32_t b92 :  1;
681             volatile uint32_t b93 :  1;
682             volatile uint32_t b94 :  1;
683             volatile uint32_t b95 :  1;
684             volatile uint32_t b96 :  1;
685             volatile uint32_t b97 :  1;
686             volatile uint32_t b98 :  1;
687             volatile uint32_t b99 :  1;
688             volatile uint32_t b100 : 1;
689             volatile uint32_t b101 : 1;
690             volatile uint32_t b102 : 1;
691             volatile uint32_t b103 : 1;
692             volatile uint32_t b104 : 1;
693             volatile uint32_t b105 : 1;
694             volatile uint32_t b106 : 1;
695             volatile uint32_t b107 : 1;
696             volatile uint32_t b108 : 1;
697             volatile uint32_t b109 : 1;
698             volatile uint32_t b110 : 1;
699             volatile uint32_t b111 : 1;
700             volatile uint32_t b112 : 1;
701             volatile uint32_t b113 : 1;
702             volatile uint32_t b114 : 1;
703             volatile uint32_t b115 : 1;
704             volatile uint32_t b116 : 1;
705             volatile uint32_t b117 : 1;
706             volatile uint32_t b118 : 1;
707             volatile uint32_t b119 : 1;
708             volatile uint32_t b120 : 1;
709             volatile uint32_t b121 : 1;
710             volatile uint32_t b122 : 1;
711             volatile uint32_t b123 : 1;
712             volatile uint32_t b124 : 1;
713             volatile uint32_t b125 : 1;
714             volatile uint32_t b126 : 1;
715             volatile uint32_t b127 : 1;
716         } Msk_b;
717     } U;
718 } am_hal_gpio_mask_t;
719 
720 //
721 //! Use AM_HAL_GPIO_MASK_ZERO to initialize a am_hal_gpio_mask_t union/structure
722 //! to all zeros at declaration time. e.g.
723 //!  am_hal_gpio_mask_t gpionewmask = AM_HAL_GPIO_MASK_DECLARE_ZERO;
724 //
725 #define AM_HAL_GPIO_MASK_DECLARE_ZERO   \
726 {                                       \
727     .U.Msk[0] = 0,                      \
728     .U.Msk[1] = 0,                      \
729     .U.Msk[2] = 0,                      \
730     .U.Msk[3] = 0                       \
731 }
732 
733 //
734 //! Initialize a mask to a given value (typically 0 or 0xFFFFFFFF).
735 //
736 #define AM_HAL_GPIO_MASK_INIT(msk, val)     \
737 {                                           \
738     msk.U.Msk[0] = val;                     \
739     msk.U.Msk[1] = val;                     \
740     msk.U.Msk[2] = val;                     \
741     msk.U.Msk[3] = val;                     \
742 }
743 
744 //
745 //! Given a pointer to am_hal_gpio_mask_t, use this macro to initialize
746 //! all members to the given value (typically 0 or 0xFFFFFFFF).
747 //
748 #define AM_HAL_GPIO_PMASK_INIT(pmsk, val)   \
749 {                                           \
750     pmsk->U.Msk[0] = val;                   \
751     pmsk->U.Msk[1] = val;                   \
752     pmsk->U.Msk[2] = val;                   \
753     pmsk->U.Msk[3] = val;                   \
754 }
755 
756 //*****************************************************************************
757 //
758 //! @name Helper macros
759 //! @{
760 //
761 //*****************************************************************************
762 #define AM_HAL_MASK32(n)        ((uint32_t)1 << ((n) & 0x1F))
763 
764 #define AM_HAL_GPIO_RDn(pin)    ((volatile uint32_t *)&GPIO->RD0  + (((pin) >> 5) & 0x3))
765 #define AM_HAL_GPIO_WTn(pin)    ((volatile uint32_t *)&GPIO->WT0  + (((pin) >> 5) & 0x3))
766 #define AM_HAL_GPIO_WTCn(pin)   ((volatile uint32_t *)&GPIO->WTC0 + (((pin) >> 5) & 0x3))
767 #define AM_HAL_GPIO_WTSn(pin)   ((volatile uint32_t *)&GPIO->WTS0 + (((pin) >> 5) & 0x3))
768 #define AM_HAL_GPIO_ENn(pin)    ((volatile uint32_t *)&GPIO->EN0  + (((pin) >> 5) & 0x3))
769 #define AM_HAL_GPIO_ENCn(pin)   ((volatile uint32_t *)&GPIO->ENC0 + (((pin) >> 5) & 0x3))
770 #define AM_HAL_GPIO_ENSn(pin)   ((volatile uint32_t *)&GPIO->ENS0 + (((pin) >> 5) & 0x3))
771 //! @}
772 
773 //*****************************************************************************
774 //
775 //! @brief Macros to read GPIO values in an optimized manner.
776 //!
777 //! @param n - The GPIO number to be read.
778 //!
779 //! In almost all cases, it is reasonable to use am_hal_gpio_state_read() to
780 //! read GPIO values with all of the inherent error checking, critical
781 //! sectioning, and general safety.
782 //!
783 //! However, occasionally there is a need to read a GPIO value in an optimized
784 //! manner.  These 3 macros will accomplish that.  Each macro will return a
785 //! value of 1 or 0.
786 //!
787 //! Note that the macros are named as lower-case counterparts to the
788 //! enumerations for the am_hal_gpio_state_read() function.  That is:
789 //!
790 //!     AM_HAL_GPIO_INPUT_READ  -> am_hal_gpio_input_read(n)
791 //!     AM_HAL_GPIO_OUTPUT_READ -> am_hal_gpio_output_read(n)
792 //!     AM_HAL_GPIO_ENABLE_READ -> am_hal_gpio_enable_read(n)
793 //!
794 //! @return Each macro will return a 1 or 0 per the value of the requested GPIO.
795 //!
796 //
797 //*****************************************************************************
798 #define am_hal_gpio_input_read(n)   ((*AM_HAL_GPIO_RDn((n)) >> ((n) % 32)) & 1)
799 #define am_hal_gpio_output_read(n)  ((*AM_HAL_GPIO_WTn((n)) >> ((n) % 32)) & 1)
800 #define am_hal_gpio_enable_read(n)  ((*AM_HAL_GPIO_ENn((n)) >> ((n) % 32)) & 1)
801 
802 //*****************************************************************************
803 //
804 //! @brief Macros to write GPIO values in an optimized manner.
805 //!
806 //! @param n - The GPIO number to be written.
807 //!
808 //! In almost all cases, it is reasonable to use am_hal_gpio_state_write() to
809 //! write GPIO values with all of the inherent error checking, critical
810 //! sectioning, and general safety.
811 //!
812 //! However, occasionally there is a need to write a GPIO value in an optimized
813 //! manner.  These 3 macros will accomplish that.
814 //!
815 //! Note that the macros are named as lower-case counterparts to the
816 //! enumerations for the am_hal_gpio_state_read() function.  That is:
817 //!
818 //!    AM_HAL_GPIO_OUTPUT_CLEAR                -> am_hal_gpio_output_clear(n)
819 //!    AM_HAL_GPIO_OUTPUT_SET                  -> am_hal_gpio_output_set(n)
820 //!    AM_HAL_GPIO_OUTPUT_TOGGLE               -> am_hal_gpio_output_toggle(n)
821 //!    AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_DIS  -> am_hal_gpio_output_tristate_output_dis(n)
822 //!    AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_EN   -> am_hal_gpio_output_tristate_output_en(n)
823 //!    AM_HAL_GPIO_OUTPUT_TRISTATE_OUTPUT_TOG  -> am_hal_gpio_output_toggle(n).
824 //!
825 //! It's important to note that the macros:
826 //!     am_hal_gpio_output_tristate_output_en()
827 //!     am_hal_gpio_output_tristate_output_dis()
828 //! operate on the output enable of the pin. Therefore,
829 //!     am_hal_gpio_output_tristate_output_en() enables the output,
830 //!     am_hal_gpio_output_tristate_output_dis() puts the pin into hi-impedance.
831 //! Given this behavior, perhaps more appropriate names might have been:
832 //!     am_hal_gpio_output_tristate_outputen()
833 //!     am_hal_gpio_output_tristate_outputdis()
834 //!
835 //*****************************************************************************
836 #define am_hal_gpio_output_clear(n)             (*AM_HAL_GPIO_WTCn((n)) = AM_HAL_MASK32(n))
837 #define am_hal_gpio_output_set(n)               (*AM_HAL_GPIO_WTSn((n)) = AM_HAL_MASK32(n))
838 #define am_hal_gpio_output_toggle(n)                                            \
839     if ( 1 )                                                                    \
840     {                                                                           \
841         AM_CRITICAL_BEGIN                                                       \
842         (*AM_HAL_GPIO_WTn((n)) ^= AM_HAL_MASK32(n));                            \
843         AM_CRITICAL_END                                                         \
844     }
845 
846 #define am_hal_gpio_output_tristate_output_dis(n)  (*AM_HAL_GPIO_ENCn((n)) = AM_HAL_MASK32(n))
847 #define am_hal_gpio_output_tristate_output_en(n)   (*AM_HAL_GPIO_ENSn((n)) = AM_HAL_MASK32(n))
848 #define am_hal_gpio_output_tristate_output_tog(n)                                   \
849     if ( 1 )                                                                    \
850     {                                                                           \
851         AM_CRITICAL_BEGIN                                                       \
852         (*AM_HAL_GPIO_ENn((n)) ^=  AM_HAL_MASK32(n));                           \
853         AM_CRITICAL_END                                                         \
854     }
855 
856 //*****************************************************************************
857 //
858 // These macros have been deprecated due to improper naming conventions.
859 //
860 //*****************************************************************************
861 #define am_hal_gpio_output_tristate_disable(n)   am_hal_gpio_output_tristate_output_dis(n)
862 #define am_hal_gpio_output_tristate_enable(n)    am_hal_gpio_output_tristate_output_en(n)
863 #define am_hal_gpio_output_tristate_toggle(n)    am_hal_gpio_output_tristate_output_tog(n)
864 
865 //*****************************************************************************
866 //
867 //*****************************************************************************
868 #define am_hal_gpio_intdir_toggle(n)                                            \
869     if ( 1 )                                                                    \
870     {                                                                           \
871         volatile uint32_t *pui32Config = &GPIO->PINCFG0;                        \
872         AM_CRITICAL_BEGIN                                                       \
873         GPIO->PADKEY = GPIO_PADKEY_PADKEY_Key;                                  \
874         pui32Config[n] ^= ((uint32_t)0x3 << GPIO_PINCFG0_IRPTEN0_Pos);          \
875         AM_CRITICAL_END                                                         \
876     }
877 
878 //*****************************************************************************
879 //
880 // External functions.
881 //
882 //*****************************************************************************
883 
884 //*****************************************************************************
885 //
886 //! @brief Return the current configuration of a pin.
887 //!
888 //! @param ui32GpioNum is the GPIO pin number to configure.
889 //! @param psGpioCfg - Ptr for the return value of the current configuration.
890 //!
891 //! This function returns the current configuration of a GPIO.
892 //!
893 //! @return Standard HAL status code.
894 //
895 //*****************************************************************************
896 extern uint32_t
897 am_hal_gpio_pinconfig_get(uint32_t ui32GpioNum, am_hal_gpio_pincfg_t* psGpioCfg);
898 
899 //*****************************************************************************
900 //
901 //! @brief Configure the function of a single pin.
902 //!
903 //! @param ui32GpioNum is the GPIO pin number to configure.
904 //! @param sGpioCfg Structure corresponding to the desired configuration.
905 //!
906 //! This function sets the configuration of a GPIO.
907 //!
908 //! @return Standard HAL status code.
909 //
910 //*****************************************************************************
911 extern uint32_t am_hal_gpio_pinconfig(uint32_t ui32GpioNum,
912                                       const am_hal_gpio_pincfg_t sGpioCfg);
913 
914 //*****************************************************************************
915 //
916 //! @brief Configure the function of a single pin.
917 //!
918 //! @param ui32GpioNum is the GPIO pin number to configure.
919 //! @param sGpioCfg Structure corresponding to the desired configuration.
920 //! @param eFunction Function Select type
921 //!
922 //! This function sets the configuration of a GPIO.
923 //!
924 //! @return Standard HAL status code.
925 //
926 //*****************************************************************************
927 extern uint32_t am_hal_gpio_pinconfig_override(uint32_t ui32GpioNum,
928                                                am_hal_gpio_pincfg_t sGpioCfg,
929                                                am_hal_pin_function_e eFunction);
930 
931 //*****************************************************************************
932 //
933 //! @brief Read GPIO state values
934 //!
935 //! @param ui32GpioNum is the pin to read.
936 //! @param eReadType is the type of read to perform.
937 //! @param pui32ReadState returns the requested value.
938 //!
939 //! This function allows the caller to read any of the following values
940 //! associated with a GPIO:
941 //! - Input value
942 //! - Output value
943 //! - Output enable value
944 //!
945 //! @return Standard HAL status code.
946 //
947 //*****************************************************************************
948 extern uint32_t am_hal_gpio_state_read(uint32_t ui32GpioNum,
949                                        am_hal_gpio_read_type_e eReadType,
950                                        uint32_t *pui32ReadState);
951 
952 //*****************************************************************************
953 //
954 //! @brief Write GPIO state values
955 //!
956 //! @param ui32GpioNum is the pin to write to
957 //! @param eWriteType is the type of write to perform.
958 //!
959 //! This function allows the caller to write any of the following values
960 //! associated with a GPIO:
961 //! - Ouput drive value
962 //! - Output enable value
963 //!
964 //! @return Standard HAL status code.
965 //
966 //*****************************************************************************
967 extern uint32_t am_hal_gpio_state_write(uint32_t ui32GpioNum,
968                                         am_hal_gpio_write_type_e eWriteType);
969 
970 //*****************************************************************************
971 //
972 //! @brief Enable one or more GPIO interrupts.
973 //!
974 //! @param eChannel:  Selects the GPIO channel to operate on, must be one of:
975 //!     AM_HAL_GPIO_INT_CHANNEL_0,
976 //!     AM_HAL_GPIO_INT_CHANNEL_1,
977 //!     AM_HAL_GPIO_INT_CHANNEL_BOTH
978 //!
979 //! @param eControl: Specify the control operation on an individual or multiple
980 //! GPIO interrupts. The control operation is one of:
981 //!     AM_HAL_GPIO_INT_CTRL_INDV_DISABLE
982 //!     AM_HAL_GPIO_INT_CTRL_INDV_ENABLE
983 //!     AM_HAL_GPIO_INT_CTRL_MASK_DISABLE
984 //!     AM_HAL_GPIO_INT_CTRL_MASK_ENABLE
985 //!
986 //! @param pGpioIntMaskOrNumber allows specifying either an individual GPIO or
987 //! multiple GPIOs via a mask.  Its actual usage is determined based on the
988 //! eControl parameter as follows:
989 //!     AM_HAL_GPIO_INT_CTRL_INDV_DISABLE or AM_HAL_GPIO_INT_CTRL_INDV_ENABLE:
990 //!       gGpioIntMaskOrNumber points to a uint32_t which specifies the single
991 //!       GPIO interrupt number to operate on.
992 //!     AM_HAL_GPIO_INT_CTRL_MASK_DISABLE or AM_HAL_GPIO_INT_CTRL_MASK_ENABLE:
993 //!       gGpioIntMaskOrNumber points to a am_hal_gpio_mask_t structure which
994 //!       specifies a mask of interrupts to operate on (similar to the way that
995 //!       previous Apollo devices were handled in the HAL).
996 //!
997 //! This function enables an individual interrupt or multiple interrupts for
998 //! the GPIO module.
999 //!
1000 //! @return Standard HAL status code.
1001 //
1002 //*****************************************************************************
1003 extern uint32_t am_hal_gpio_interrupt_control(am_hal_gpio_int_channel_e eChannel,
1004                                               am_hal_gpio_int_ctrl_e eControl,
1005                                               void *pGpioIntMaskOrNumber);
1006 
1007 //*****************************************************************************
1008 //
1009 //! @brief Read the GPIO interrupt status.
1010 //!
1011 //! @param eChannel:  Selects the GPIO channel to operate on, must be one of:
1012 //!     AM_HAL_GPIO_INT_CHANNEL_0,
1013 //!     AM_HAL_GPIO_INT_CHANNEL_1,
1014 //!     AM_HAL_GPIO_INT_CHANNEL_BOTH
1015 //! @param bEnabledOnly determines whether disabled interrupts are included in
1016 //! the status.
1017 //! @param pGpioIntMask - Mask of GPIO interrupts to be cleared.
1018 //!
1019 //! This function reads the current interrupt status for the GPIO module. If the
1020 //! \e bEnabledOnly parameter is set, then only interrupt bits associated with
1021 //! active interrupts will be set.
1022 //!
1023 //! @return Standard HAL status code.
1024 //
1025 //*****************************************************************************
1026 extern uint32_t am_hal_gpio_interrupt_status_get(am_hal_gpio_int_channel_e eChannel,
1027                                                  bool bEnabledOnly,
1028                                                  am_hal_gpio_mask_t *pGpioIntMask);
1029 
1030 //*****************************************************************************
1031 //
1032 //! @brief Clear GPIO interrupts.
1033 //!
1034 //! @param eChannel - One of:
1035 //!     AM_HAL_GPIO_INT_CHANNEL_0,
1036 //!     AM_HAL_GPIO_INT_CHANNEL_1,
1037 //!     AM_HAL_GPIO_INT_CHANNEL_BOTH
1038 //! @param pGpioIntMask - Mask of GPIO interrupts to be cleared.
1039 //! This mask is typically returned from am_hal_gpio_interrupt_status_get().
1040 //!
1041 //! @return Status.
1042 //!         Fails if any invalid bits are set in pGpioIntMask.
1043 //
1044 //*****************************************************************************
1045 extern uint32_t am_hal_gpio_interrupt_clear(am_hal_gpio_int_channel_e eChannel,
1046                                             am_hal_gpio_mask_t *pGpioIntMask);
1047 
1048 //*****************************************************************************
1049 //
1050 //! @brief Read the GPIO interrupt status of a given GPIO IRQ.
1051 //!
1052 //! @param ui32GpioIrq is the desired GPIO IRQ number.  It is one of:
1053 //!     GPIO0_001F_IRQn, GPIO0_203F_IRQn, GPIO0_405F_IRQn, GPIO0_607F_IRQn
1054 //!     GPIO1_001F_IRQn, GPIO1_203F_IRQn, GPIO1_405F_IRQn, GPIO1_607F_IRQn
1055 //! @param bEnabledOnly determines whether disabled interrupts are included in
1056 //! the status.
1057 //! @param pui32IntStatus returns the GPIO interrupt status.  The value that
1058 //! is returned is the mod 32 value of the register containing the GPIO.
1059 //!
1060 //! This function reads the current interrupt status for the given GPIO IRQ.
1061 //! The IRQ number covers up to 32 GPIOs.  If the bEnabledOnly parameter is set,
1062 //! then only interrupt bits associated with active interrupts for that IRQ
1063 //! will be returned.
1064 //!
1065 //! @return Standard HAL status code.
1066 //
1067 //*****************************************************************************
1068 extern uint32_t am_hal_gpio_interrupt_irq_status_get(uint32_t ui32GpioIrq,
1069                                                      bool bEnabledOnly,
1070                                                      uint32_t *pui32IntStatus);
1071 
1072 //*****************************************************************************
1073 //
1074 //! @brief Clear the interrupts(s) for specified GPIO IRQ.
1075 //!
1076 //! @param ui32GpioIrq - The GPIO IRQ group to clear.  It is one of:
1077 //!     GPIO0_001F_IRQn, GPIO0_203F_IRQn, GPIO0_405F_IRQn, GPIO0_607F_IRQn
1078 //!     GPIO1_001F_IRQn, GPIO1_203F_IRQn, GPIO1_405F_IRQn, GPIO1_607F_IRQn
1079 //! @param ui32GpioIntMaskStatus - The bitmask for the interrupts to be cleared for the
1080 //!     given GPIO IRQ. This value is usually obtained from a call to
1081 //!     am_hal_gpio_interrupt_irq_status_get().
1082 //!
1083 //! @return Status.
1084 //
1085 //*****************************************************************************
1086 extern uint32_t am_hal_gpio_interrupt_irq_clear(uint32_t ui32GpioIrq,
1087                                                 uint32_t ui32GpioIntMaskStatus);
1088 
1089 //*****************************************************************************
1090 //
1091 //! @brief Register an interrupt handler for a specific GPIO.
1092 //!
1093 //! @param eChannel:  Selects the GPIO channel to operate on, must be one of:
1094 //!     AM_HAL_GPIO_INT_CHANNEL_0,
1095 //!     AM_HAL_GPIO_INT_CHANNEL_1,
1096 //!     AM_HAL_GPIO_INT_CHANNEL_BOTH
1097 //! @param ui32GpioNum GPIO pin number to register an interrupt for.
1098 //! @param pfnHandler is a function pointer for an interrupt handler for this
1099 //! pin.
1100 //! @param pArg
1101 //!
1102 //! This routine was designed to work with \e am_hal_gpio_interrupt_service().
1103 //! Together, the two routines can be used to call pin-specific interrupt
1104 //! handler. This function adds the \e pfnHandler argument to a table of
1105 //! interrupt handlers so that \e am_hal_gpio_interrupt_service() can call it in
1106 //! response to interrupts from the associated GPIO pin.
1107 
1108 //! @note Usage of this function is entirely optional. It is always possible to
1109 //! use if-statements (or a similar construct) to check the GPIO interrupt
1110 //! status and call the correct routine from within the main GPIO interrupt
1111 //! handler.
1112 //!
1113 //! @return Standard HAL status code.
1114 //
1115 //*****************************************************************************
1116 extern uint32_t am_hal_gpio_interrupt_register(am_hal_gpio_int_channel_e eChannel,
1117                                                uint32_t ui32GpioNum,
1118                                                am_hal_gpio_handler_t pfnHandler,
1119                                                void *pArg);
1120 
1121 //*****************************************************************************
1122 //
1123 //! @brief Relay interrupts from the main GPIO module to individual handlers.
1124 //!
1125 //! @param ui32GpioIrq - Interrupt to read
1126 //! @param ui32GpioIntMaskStatus - recently read GPIO interrupt status.
1127 //!
1128 //! This routine was designed to work with \e am_hal_gpio_interrupt_register().
1129 //! Together, the two routines can be used to call pin-specific interrupt
1130 //! handler. Once an interrupt handler has been registered with \e
1131 //! am_hal_gpio_interrupt_register(), this function will call it in response to
1132 //! interrupt signals from the associated pin.
1133 
1134 //! @note Usage of this function is entirely optional. It is always possible to
1135 //! use if-statements (or a similar construct) to check the GPIO interrupt
1136 //! status and call the correct routine from within the main GPIO interrupt
1137 //! handler.
1138 //!
1139 //! @return Standard HAL status code.
1140 //
1141 //*****************************************************************************
1142 extern uint32_t am_hal_gpio_interrupt_service(uint32_t ui32GpioIrq,
1143                                               uint32_t ui32GpioIntMaskStatus);
1144 
1145 #ifdef __cplusplus
1146 }
1147 #endif
1148 
1149 #endif // AM_HAL_GPIO_H
1150 
1151 //*****************************************************************************
1152 //
1153 // End Doxygen group.
1154 //! @}
1155 //
1156 //*****************************************************************************
1157