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Searched refs:TCM_MAX_SIZE (Results 1 – 7 of 7) sorted by relevance

/hal_ambiq-3.5.0/mcu/apollo4p/regs/
Dam_reg_base_addresses.h103 #define TCM_MAX_SIZE (384UL * 1024UL) macro
109 #define SSRAM0_BASEADDR (SRAM_BASEADDR + TCM_MAX_SIZE)
137 #define RAM_TOTAL_SIZE (TCM_MAX_SIZE + NONTCM_MAX_SIZE)
/hal_ambiq-3.5.0/mcu/apollo4p/hal/mcu/
Dam_hal_cmdq.c376 if (pCmdQ->cmdQBufEnd >= (SRAM_BASEADDR + TCM_MAX_SIZE)) in am_hal_cmdq_enable()
561 if (pCmdQ->cmdQBufEnd >= (SRAM_BASEADDR + TCM_MAX_SIZE)) in am_hal_cmdq_post_block()
909 if (pCmdQ->cmdQBufEnd >= (SRAM_BASEADDR + TCM_MAX_SIZE)) in am_hal_cmdq_post_loop_block()
Dam_hal_sysctrl.c85 … if (((uint32_t)&pDummy < SRAM_BASEADDR) || ((uint32_t)&pDummy >= (SRAM_BASEADDR + TCM_MAX_SIZE))) in am_hal_sysctrl_sleep()
Dam_hal_mcuctrl.c204 psDevice->ui32DTCMSize = TCM_MAX_SIZE; in device_info_get()
Dam_hal_iom.c2305 …te->pNBTxnBuf + pIOMState->ui32NBTxnBufLength * 4) < (SRAM_BASEADDR + TCM_MAX_SIZE)) ? true: false; in am_hal_iom_configure()
Dam_hal_mspi.c1377 …_t)pMSPIState->pTCB + pMSPIState->ui32TCBSize * 4) < (SRAM_BASEADDR + TCM_MAX_SIZE)) ? true: false; in am_hal_mspi_configure()
/hal_ambiq-3.5.0/mcu/apollo4p/hal/
Dam_hal_security.c237 if ((ui32StartAddr + ui32SizeBytes) >= (SRAM_BASEADDR + TCM_MAX_SIZE)) in am_hal_crc32()